/* BEGIN INCLUDE FILE ... history_regs_l68.incl.pl1 ... last modified 10/80 */ dcl (ouhrp, cuhrp, aphrp, duhrp, hr_data_ptr) ptr; dcl ou_offset fixed bin init (0), /* offsets to hr data within the hr data block */ cu_offset fixed bin init (32), du_offset fixed bin init (64), au_offset fixed bin init (96); dcl 1 cuhra (16) based (cuhrp) aligned, (2 pia bit (1), /* preparing instruction address */ 2 poa bit (1), /* preparing operand address */ 2 riw bit (1), /* requesting indirect word */ 2 siw bit (1), /* restoring indirect word */ 2 pot bit (1), /* preparing operand tally */ 2 pon bit (1), /* preparing operand address */ 2 raw bit (1), /* requesting alter-rewrite word */ 2 saw bit (1), /* restoring alter-rewrite word */ 2 trgo bit (1), /* transfer go - condition met */ 2 xde bit (1), /* XED from even location */ 2 xdo bit (1), /* XED from odd location */ 2 ic bit (1), /* even/odd inst. pair */ 2 rpts bit (1), /* repeat operation */ 2 wi bit (1), /* wait for instruction fetch */ 2 ar bit (1), /* address reg valid */ 2 nxip bit (1), /* not an xip address */ 2 nflt bit (1), /* not an FLT address */ 2 np bit (1), /* not in privilaged mode */ 2 op_code bit (10), /* op code of inst */ 2 inhib bit (1), /* inhibit int bit */ 2 its_flag bit (1), /* ar reg mod flag */ 2 tag bit (6), /* tag field of instr */ 2 ca_value bit (18), /* address field of inst */ 2 pcmd bit (5), /* processor command register */ 2 psl bit (4), /* port select lines */ 2 xint bit (1), /* execute interrupt */ 2 ins_fetch bit (1), /* inst fetch */ 2 cus bit (1), /* control unit store */ 2 ous bit (1), /* operations unit store */ 2 cul bit (1), /* control unit load */ 2 oul bit (1), /* operations unit load */ 2 dir bit (1), /* direct cycle */ 2 npcb bit (1), /* port logic not busy */ 2 pib bit (1)) unaligned; /* port interface busy */ dcl 1 ouhra (16) based (ouhrp) aligned, (2 nopc bit (9), /* next inst. op code */ 2 itw bit (1), /* IT tally word 6/9 bit data */ 2 ntg bit (3), /* next inst tag field */ 2 cmod bit (1), /* character modification */ 2 dir bit (1), /* direct modification */ 2 efad bit (2), /* LREG/SREG effective addr */ 2 pad0 bit (1), 2 rp bit (9), /* copy of RP reg */ 2 opbf bit (1), /* OU op code buffer full */ 2 frpf bit (1), /* primary register full */ 2 srf bit (1), /* secondary register full */ 2 gin bit (1), /* first cycle for all OU */ 2 gos bit (1), /* second cycle for OU - multiple OP */ 2 gd1 bit (1), /* first divide cycle */ 2 gd2 bit (1), /* second divide cycle */ 2 goe bit (1), /* exponent compare cycle */ 2 goa bit (1), /* mamtissa alignment cycle */ 2 gom bit (1), /* general OU cycle */ 2 gon bit (1), /* normalize cycle */ 2 gof bit (1), /* final cycle */ 2 fstr bit (1), /* OU store data available */ 2 dn bit (1), /* data not available */ 2 an bit (1), /* A reg not in use */ 2 qn bit (1), /* Q reg not used */ 2 x0n bit (1), /* X0 not in use */ 2 x1n bit (1), /* X1 not in use */ 2 x2n bit (1), /* X2 not in use */ 2 x3n bit (1), /* X3 not in use */ 2 x4n bit (1), /* X4 not in use */ 2 x5n bit (1), /* X5 not in use */ 2 x6n bit (1), /* X6 not in use */ 2 x7n bit (1), /* X7 not in use */ 2 pad1 bit (3), 2 ict bit (18)) unaligned; /* address of OU inst */ dcl 1 apuhra (16) based (aphrp), (2 esn bit (15), /* effective segment number for this cycle */ 2 bsy bit (2), /* source of ESN above */ 2 fdsptw bit (1), /* fetch of dseg PTW */ 2 mdsptw bit (1), /* mod of dseg PTW */ 2 dfsdw bit (1), /* xxxxxx */ 2 fptw bit (1), /* fetch PTW */ 2 fptw2 bit (1), /* fetch PTW + 1 */ 2 mptw bit (1), /* modify PTW */ 2 fanp bit (1), /* fetch final add from non-paged seg */ 2 fap bit (1), /* xxxxx */ 2 sdwmf bit (1), /* SDW match in AM */ 2 sdwamr bit (4), /* AM register that holds SDW */ 2 ptwmf bit (1), /* PTW match in AM */ 2 ptwamr bit (4), /* AM register that holds PTW */ 2 flt bit (1), /* ACV or DF flt caused by this cycle */ 2 finadd bit (24), /* absolute address of this cycle */ 2 trr bit (3), /* value of tpr.trr for this cycle */ 2 apu_pad1 bit (7), 2 flthld bit (1), /* an ACV or DF flt is waiting to be processed */ 2 apu_pad2 bit (1))unaligned; dcl 1 duhra (16) based (duhrp) aligned, (2 pol bit (1), /* preparing operand length */ 2 pop bit (1), /* preparing pointer */ 2 ndesc bit (1), /* need descriptor */ 2 seladr bit (1), /* select address register */ 2 dlendr bit (1), /* length = direct */ 2 dfrst bit (1), /* processing desc. for first time */ 2 exr bit (1), /* extended register modification */ 2 ldfrst bit (1), /* last cycle of dfrst above */ 2 dulea bit (1), /* DU load and effective add. */ 2 dusea bit (1), /* DU store and effective add. */ 2 redo bit (1), /* redo - no update of ptrs. and lngh. */ 2 wcws bit (1), /* load word count < word size */ 2 exh bit (1), /* exhaust */ 2 eseq bit (1), /* end of sequence */ 2 einst bit (1), /* end of instruction */ 2 durw bit (1), /* DU read or write */ 2 ptra bit (2), /* PR address bits 0 and 1 */ 2 fai1 bit (1), /* active/inactive desc. 1 */ 2 fai2 bit (1), /* active/inactive desc. 2 */ 2 fai3 bit (1), /* active/inactive desc. 3 */ 2 du_wrd bit (1), /* word type inst. */ 2 nine bit (1), /* nine bit type inst. */ 2 six bit (1), /* six bit type inst. */ 2 four bit (1), /* four bit type inst. */ 2 one bit (1), /* one bit type inst */ 2 du_pad1 bit (4), 2 samplint bit (1), /* sample for mid inst. intrp. */ 2 sfcsq bit (1), /* specific first count of sequence */ 2 adjlen bit (1), /* adjust length */ 2 mif bit (1), /* mid inst. intrp. indicator */ 2 inhibstc1 bit (1), /* inhibit sct1 inst. */ 2 du_pad2 bit (1), 2 duidl bit (1), /* DU idle */ 2 dcldgta bit (1), /* desc. load gates A */ 2 dcldgtb bit (1), /* desc. load gates B */ 2 dcldgtc bit (1), /* desc. load gates C */ 2 nopl1 bit (1), /* alignment cnt. for 1st numeric op. ld. */ 2 nopgl1 bit (1), /* numeric op. 1 gate load */ 2 nopl2 bit (1), /* alignment cnt. for 2nd numeric op. ld. */ 2 nopgl2 bit (1), /* numeric op. 2 gate load */ 2 aoplg1 bit (1), /* alphanum. op. 1 gate load */ 2 aoplg2 bit (1), /* alphanum. op. 2 gate load */ 2 lrwrg1 bit (1), /* load rewrite reg. gate 1 */ 2 lrwrg2 bit (1), /* load rewrite reg. gate 2 */ 2 dataav_du bit (1), /* data available */ 2 rw1rl bit (1), /* rewrite one reg. loaded */ 2 numstg bit (1), /* numeric store gate */ 2 anstg bit (1), /* alpha-numeric store gate */ 2 opav bit (1), /* operand available */ 2 endseq_du bit (1), /* end sequence */ 2 len128 bit (1), /* length < 128 */ 2 charop bit (1), /* character operation */ 2 anpk bit (1), /* alphanumeric packing cycle */ 2 exmop bit (1), /* execute MOP */ 2 blnk bit (1), /* blanking ind. */ 2 du_pad3 bit (1), 2 bde bit (1), /* binary to decimal ind. */ 2 dbe bit (1), /* decimal to binary ind. */ 2 shft bit (1), /* shift ind. */ 2 flt bit (1), /* floating ind. */ 2 rnd bit (1), /* round ind. */ 2 addsub bit (1), /* add-subtract ind. */ 2 multdiv bit (1), /* multiply-divide ind. */ 2 expon bit (1), /* exponent ind. */ 2 du_pad4 bit (4))unaligned; /* END INCLUDE FILE ... history_regs.incl.pl1 */ */ ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull and Bull HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by Bull HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved */