/* BEGIN INCLUDE ............imp_dcm_data ................ */ /* For imp_dcm */ dcl imp_data$dcm external; dcl 1 dcm based aligned, 2 initialized bit (36) aligned, /* If non-zero IMP DCM has been initialized */ 2 int_lock bit (36) aligned, /* Lock for interupts */ 2 finish_status_lock bit (36) aligned, /* If unsuccesful to lock "imp_status" returns. "imp_finish" waits until the lock is cleared. */ 2 interrupt_sequence_number fixed bin (35), 2 last_ready_line_drop_time fixed bin (71), /* Time at which the last ready-line-drop happenned. It is needed to take care of the burst of interrupts generated by the new Interface when the ready line comes up */ 2 state char (8) aligned, /* State of IMP and last I/O operation */ 2 data_transfer_sw bit (1) aligned, /* If off no read writes permitted. */ 2 multi_cpu_int_lock bit (36) aligned, /* Lock to make sure only one cpu gets in the interrupt handler */ 2 filler1 (6) fixed bin (35), 2 interrupt_times_histogram (1:6), /* CPU time spent in processing interrupts */ 3 max_value fixed bin (35), 3 count fixed bin (34), 3 total fixed bin (71), /* Following variables used to store data about IMP read and write channels */ 2 channel (1:2), /* Data blocks for read and write channels */ 3 mode char (4) aligned, /* Mode of current operation on this channel */ 3 assigned bit (1), /* ="1"b if the channel has been assigned */ 3 devx fixed bin (35), /* IOM manager index of the channel */ 3 current_io_counter fixed bin, /* Number of attempts */ 3 reset_status_needed bit (1), 3 alarm_set bit (1), 3 alarm_time fixed bin (71), 3 last_io_time fixed bin (71), 3 buffer_address pointer, /* Address of buffer area */ 3 buffer_absolute_address fixed bin (24), /* Absolute address of buffer area */ 3 idcw bit (36), /* IDCW for reset */ 3 status_ptr pointer, /* points to status word */ /* Following variables used for read operations */ 2 rin fixed bin, /* Number of words traversed in read buffer on input. */ 2 rout fixed bin, /* Number of words traversed in read buffer while emptying it. */ 2 read_buffer_full bit (1) aligned, /* When read buffers are full this bit is turned on by the interrupt side. Call side turns this bit off after removing something from the read buffer. */ 2 filler2 fixed bin (35), /* Following variables used for write operations */ 2 win fixed bin, /* Number of words traversed in write buffer while filling the buffers. (Copying messages into the buffer.) */ 2 wout fixed bin, /* Number of words traversed in write buffer while emptying the buffers. (Sending the messages to the IMP. ) */ 2 wakeup_ncp_on_write_buf_empty fixed bin, /* It also contains the length in words */ 2 filler3 fixed bin (35), 2 write_times_histogram (1:4), 3 max_value fixed bin (35), /* Maximum number of micro seconds for this entry */ 3 count fixed bin (34), /* Number of write in this entry */ 3 total fixed bin (71), /* Total time for this entry in microseconds */ /* Following variables used for non-read-write operations */ 2 polling_on bit (1), /* If on, IMP polling is on. */ 2 polling_needed bit (1), /* If on polling operation is perforemed at the first oppertunity. */ 2 filler3_2 (6) fixed bin (35), /* Following variables are used by imp_dcm_init */ 2 misc_bits aligned, 3 (imp_status_wired, /* On if imp_status has been wired down */ data_seg_wired) bit (1) unaligned, /* On if necessary data pages are wired */ 2 imp_dcm_init_progress fixed bin, 2 imp_dcm_first_call_time fixed bin (71), /* This is the time imp_dcm_init was first called. Used for statistics gathering. */ /* Bits for various debugging aids to become operational */ 2 misc_switches aligned, 3 print_status bit (1) unaligned, /* If on status is printed on typewriter for every call to imp_status */ 3 stop_status bit (1) unaligned, /* If on and a connect can not be issued then imp_status will call BOS */ 3 trace_wakeups bit (1) unaligned, /* If this bit is on and if memory tracing is on then wakeup_ncp calls in imp_status are traced. */ 3 tracing bit (1) unaligned, /* If this bit is on and one of the processor switches is on too, then "trace" is called to write either on tape or printer. */ 2 filler6 (3) fixed bin (35), /* Following variables are used for memory trace operations. */ 2 mtrace_lock bit (36) aligned, /* Tracing tries to lock it. If succesful tracing is done. Ofcourse tracing switch should be on. If unsuccesful no tracing */ 2 mtrace_routine_lock bit (36) aligned, /* Routines that manipulate tracing use this lock. */ 2 mtrace_sequence fixed bin (34), 2 mtrace_current fixed bin, /* Index to entry available. */ 2 mtrace aligned, 3 mtdummy bit (2) unaligned, 3 mtswitch bit (1) unaligned, 2 filler7 (3) fixed bin, /* Following variables used to gather information about cpu time wasted in looping on data base in case of multiple-processor system */ 2 (loop_interrupt, /* Number of times the stac function looped. */ loop_call) fixed bin (71); /* CONSTANTS */ dcl interrupt_times_histogram_values (1:6) fixed bin (35) static options (constant) initial (2000, /* two mili-seconds */ 4000, /* four millseconds */ 8000, /* eight miliseconds */ 16000, /* sixteen miliseconds */ 32000, /* thirtytwo milliseconds */ 64000); /* sixtyfour milliseconds */ dcl write_times_histogram_values (1:4) fixed bin (34) static options (constant) initial (1000000, /* One second */ 5000000, /* Five seconds */ 10000000, /* Ten Seconds */ 50000000); /* Fifty seconds. This value is not used any way */ /* definition of I/O modes on IMP read and write channels */ dcl (inactive_mode init (""), read_mode init ("read"), write_mode init ("writ"), reset_status_mode init ("rese"), host_down_mode init ("hsdn"), host_up_mode init ("hsup"), abort_mode init ("abrt")) char (4) aligned static options (constant); /* Indices for referecencing channel data */ dcl (read_channel init (1), write_channel init (2)) fixed binary static options (constant); /* ASCII channel names */ dcl channel_name (1:2) char (4) aligned static options (constant) init ("impr", "impw"); /* END INCLUDE...............imp_dcm_data ................ */ */ ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull and Bull HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by Bull HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved */