/* BEGIN INCLUDE FILE ... mcs_memory_map.incl.pl1 */ /* This include file descibes MCS memory layout. Created 6/2/76 by Mike Grady Modified 1979 June 1 by Art Beattie to add new cells in comm_reg. Modified June 1982 by Robert Coren to add some more new cells in comm_reg and change some of them to fixed bin (18) unsigned. */ dcl 1 mem_array aligned based (memp), /* as an array of 18 bit words */ 2 mem (0:65535) bit (18) unaligned; dcl 1 low_mem aligned based (memp), /* detail of low memory */ 2 interrupt_vectors (0:255) bit (18) unal, /* loc 0-377 octal */ 2 interrupt_cells (16) bit (18) unal, /* loc 400-417 octal */ 2 iom_fault_status (16) bit (18) unal, /* loc 420-437 octal */ 2 processor_fault_vectors (8) bit (18) unal, /* loc 440-447 octal */ 2 chan_mailbox (24) bit (18) unal, /* loc 450-477 octal */ 2 lsla_mailbox (0:5) like hwcm, /* LSLA hardware comm regions, loc 500-637 octal */ 2 comm_reg unal, /* software communications region for MCS system */ 3 crldt fixed bin (71) aligned, /* date and time binder produced this image */ 3 crbdt fixed bin (71) aligned, /* date and time image was booted into FNP */ 3 crbuf fixed bin (17) unal, /* base of free buffer pool */ 3 crmem fixed bin (18) unsigned unal, /* last loc of mem configured */ 3 crnbf fixed bin (17) unal, /* free buffers in pool now */ 3 criom fixed bin (17) unal, /* pointer to iom table */ 3 crnhs fixed bin (17) unal, /* number of HSLAs */ 3 crnls fixed bin (17) unal, /* number of LSLAs */ 3 crcon bit (18) unal, /* console enable switch */ 3 crmod fixed bin (17) unal, /* base of module chain */ 3 crnxa fixed bin (17) unal, /* pointer to head of free space chain */ 3 crtra bit (18) unal, /* trace entry enable mask */ 3 crtrb fixed bin (18) unsigned unal, /* base of trace table */ 3 crtrc fixed bin (18) unsigned unal, /* next trace table entry pointer */ 3 crreg fixed bin (17) unal, /* pointer to fault reg storage area */ 3 crttb fixed bin (17) unal, /* pointer to tib table base */ 3 crtte fixed bin (17) unal, /* last addr in tib table */ 3 crdly fixed bin (17) unal, /* pointer to delay table chain */ 3 crver char (4) unal, /* mcs version number */ 3 crbrk fixed bin (17) unal, /* pointer to breakpoint control table */ 3 crtsw bit (18) unal, /* trace switch (zero=trace on) */ 3 crnxs fixed bin (17) unal, /* pointer to next free small block */ 3 crnbs fixed bin (17) unal, /* number of buffers devoted to small space */ 3 crcct fixed bin (17) unal, /* pointer to first cct descriptor */ 3 crskd fixed bin (17) unal, /* pointer to scheduler data block */ 3 cretb fixed bin (17) unal, /* pointer to list of echo-negotiation bit tables */ 3 crcpt fixed bin (17) unal, /* pointer to cpu page table */ 3 crpte fixed bin (17) unal, /* pointer to variable cpu page table entry */ 3 crtsz fixed bin (17) unal, /* size of trace data buffer */ 3 crmet bit (18) unal, /* metering enabled */ 3 crtdt bit (18) unal, /* 0 if no COLTS channel; set to TIB address if it exists */ 3 crbtm bit (18) unal, /* address of time meters for buffer allocation/freeing */ 3 crnxe fixed bin (18) unsigned unal, /* next available space in extended memory */ 3 crbpe fixed bin (17) unal, /* buffer paging window table entry */ 3 pad (39) bit (18) unal, 3 crcpr char (28) unal, /* image copyright notice */ 3 crash_location bit (18) unal, /* offset used for unresolved REF's */ 3 crash_opcode bit (18) unal, /* crash instruction */ 2 hsla_mailbox (0:2), /* loc 1000-3777 octal */ 3 subchannel (0:31) like hwcm; /* HSLA hardware comm regions */ dcl 1 icw aligned based, /* Standard FNP Indirect Control Word */ 2 xfer_mode bit (3) unal, /* transfer mode, bit-36 for dia */ 2 fnp_addr bit (15) unal, /* address in fnp */ 2 pad bit (6) unal, /* padding, exhaust bit */ 2 tally bit (12) unal; dcl 1 hwcm aligned based (hwcmp), /* Standard hardware comm region */ 2 ricw0 like icw, /* primary receive icw */ 2 ricw1 like icw, /* secondary receive icw */ 2 sicw0 like icw, /* primary send icw */ 2 sicw1 like icw, /* secondary send icw */ 2 baw bit (18) unal, /* base address word */ 2 sfcmp bit (18) unal, /* pointer to sfcm for this channel */ 2 mask_reg bit (36) unal, /* maskregister, subch 0 only */ 2 stat_icw like icw, /* status icw */ 2 config_pcw bit (36) unal; /* subchannel configuration */ /* Tables used to describe the configuration of the FNP */ dcl 1 iom_table (0: 15) unaligned based (itblp), /* FNP IOM table */ 2 flags, 3 mpx_chan bit (1) unal, /* multiplexed channel */ 3 pad bit (6) unal, 3 char_len bit (2) unal, 3 dev_type bit (5) unal, /* device type on this channel */ 3 dev_speed bit (4) unal, /* for those devices with speed (LSLA) */ 2 table bit (18) unal; /* pointer to secondary table for mpx_chan */ dcl 1 lsla_table (0:52) based (tblp) unal, /* LSLA table, entry one per slot */ 2 flags, 3 pad1 bit (11) unal, 3 ibm_code bit (1) unal, /* if 6-bit odd parity */ 3 pad2 bit (3) unal, 3 slot_id bit (3) unal, /* slot type this slot */ 2 tib_addr fixed bin (17) unal; /* pointer to tib */ dcl 1 hsla_table (0:31) based (tblp) unal, /* HSLA table, entry one per subchannel */ 2 flags, 3 conc_chan bit (1) unal, /* concentrator attached to this channnel */ 3 private_line bit (1) unal, /* indicates direct connect or pl modem for sync chan */ 3 async bit (1) unal, /* on if async channel */ 3 option1 bit (1) unal, /* three option specification bits */ 3 option2 bit (1) unal, 3 modem_type bit (4) unal, /* indicator of type of modem on this channel */ 3 line_type bit (5) unal, /* line type of this channel */ 3 dev_speed bit (4) unal, /* speed of this subchannel */ 2 tib_addr fixed bin (17) unal; /* addr of tib for this subchannel */ dcl (memp, itblp, tblp, hwcmp) ptr; dcl (DIA init ("00010"b), /* dev_type definitions */ HSLA init ("00011"b), LSLA init ("00100"b), CONSOLE init ("00101"b), PRINTER init ("00110"b)) bit (5) int static options (constant); /* END INCLUDE FILE mcs_memory_map.incl.pl1 */ */ ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull and Bull HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by Bull HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved */