/* *********************************************************** * * * Copyright, (C) Honeywell Information Systems Inc., 1982 * * * *********************************************************** */ /* Begin include file ...... rsw.incl.pl1 Modified 3/26/77 by Noel I. Morris Modified 9/03/80 by J. A. Bush for the DPS8/70M CPU Modified 3/24/82 by J. A. Bush to allow the L68 CPU to address 4MW/port */ dcl rswp ptr; dcl 1 dps_rsw_2 aligned based (rswp), /* rsw 2 template for DPS and L68 CPUs */ (2 pad1 bit (4), 2 cpu_type fixed bin (2) unsigned, /* 0 = L68 or DPS, 1 = DPS8 */ 2 fault_base bit (7), /* high order bits of fault vector */ 2 pad2 bit (6), 2 dps_option bit (1), /* "1"b => DPS CPU, "0"b => L68 CPU */ 2 pad3 bit (7), 2 cache2 bit (1), /* "1"b => 2k cache installed, "0"b => no cache */ 2 ext_gcos bit (1), /* "1"b => ext gcos option installed */ 2 id bit (4), /* CPU ID - "1110"b => L68 */ 2 cpu_num fixed bin (3) unsigned) unaligned; /* processor number */ dcl 1 dps8_rsw_2 aligned based (rswp), /* rsw 2 template for DPS8 CPUs */ (2 interlace_info (0:3) bit (1), /* if interlace enabled; "0"b => 4-word, "1"b => 2-word */ 2 cpu_type fixed bin (2) unsigned, /* 0 = L68 or DPS, 1 = DPS8 */ 2 fault_base bit (7), /* high order bits of fault vector */ 2 id_prom bit (1), /* "1"b => id_prom present */ 2 pad1 bit (5), 2 dps_option bit (1), /* always "1"b for DPS8 CPU */ 2 cache8 bit (1), /* "1"b => 8k cache installed, "0"b => no cache */ 2 pad2 bit (2), 2 multics_cpu bit (1), /* always "1"b for Multics cpu */ 2 pad3 bit (5), 2 cpu_speed bit (4), /* cpu speed options */ 2 cpu_num fixed bin (3) unsigned) unaligned; /* processor number */ dcl 1 rsw_1_3 aligned based (rswp), /* rsw 3 only valid on DPS and L68 CPUs */ (2 port_info (0:3), /* controller port information */ 3 port_assignment bit (3), /* port address assignment */ 3 port_enable bit (1), /* "1"b => port enabled */ 3 initialize_enable bit (1), /* "1"b => system initialize enabled */ 3 interlace_enable bit (1), /* "1"b => port is interlaced with neighbor */ 3 mem_size fixed bin (3) unsigned) unaligned; /* encoded memory size on port */ dcl 1 rsw_4 aligned based (rswp), /* rsw 4 only valid on DPS and L68 CPUs */ (2 pad1 bit (13), 2 port_info (0:7), /* additional controller port information */ 3 four bit (1), /* "0"b => 4-word interlace - "1"b => 2-word interlace */ 3 half bit (1), /* "1"b => only half of memory on controller in use */ 2 pad2 bit (7)) unaligned; dcl dps_mem_size_table (0:7) fixed bin (24) static options (constant) init /* DPS and L68 memory sizes */ (32768, 65536, 4194304, 131072, 524288, 1048576, 2097152, 262144); /* Note that the third array element above, is changed incompatibly in MR10.0. In previous releases, this array element was used to decode a port size of 98304 (96K). With MR10.0 it is now possible to address 4MW per CPU port, by installing FCO # PHAF183 and using a group 10 patch plug, on L68 and DPS CPUs. */ dcl dps8_mem_size_table (0:7) fixed bin (24) static options (constant) init /* DPS8 memory sizes */ (32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304); dcl rsw_valid (0:1) fixed bin static options (constant) init (5, 3); /* # of rsw valid per cpu type */ /* End of include file ...... rsw.incl.pl1 */ */ ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull and Bull HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by Bull HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved */