/* Begin include file ...... scr.incl.pl1 modified 5/75 by Noel I. Morris modified 10/81 by M.R. Jordan for 64K chip, M64 memory modified '83 to make values constant */ /* This include file is to be used in conjunction with pmut$rscr and pmut$sscr. Wherever possible the terms in the processor manual are used in the declaration. */ dcl (SC_MR init (0), /* SC Mode Register */ SC_CFG init (1), /* SC Configuration Switches */ SC_MSK init (2), /* SC Interrupt Mask */ SC_IC init (3), /* SC Interrupt Cells */ SC_ETC init (4), /* SC Elapsed Time Clock */ SC_SU init (6)) fixed bin (6) static options (constant); /* SU Mode Register */ dcl scrp ptr; /* pointer to SC data */ dcl 1 scr_cfg1 based (scrp) aligned, /* configuration data for 6000 SC */ (2 mode_a bit (3), /* 000 => on-line 001 => test mode 010 => off-line */ 2 bdry_a bit (3), /* 000 => 32K, 001 => 64K, etc */ 2 mode_b bit (3), /* see mode_a */ 2 bdry_b bit (3), /* see bdry_a */ 2 int bit (1), /* 1 => stores are internally interlaced */ 2 lwr bit (1), /* 1 => store B is low */ 2 addr_offset bit (2), /* 00 => no offset, 01 => 32K offset, etc. */ 2 port_no bit (4), /* requester's port number */ 2 port_enable (0:7) bit (2), /* 00 => port disabled 01 => port under program control 11 => port enabled */ 2 pima (4) bit (9)) unaligned; /* program interrupt mask assignments 000 => unassigned 400 => assigned to port 0 200 => assigned to port 1 . . . 002 => assigned to port 7 001 => assigned to maint. panel */ dcl 1 scr_cfg2 based (scrp) aligned, /* configuration data for 4MW SCU */ (2 mask_a_assign bit (9), /* interrupt mask "A" port assignment 400 => assigned to port 0 . . 002 => assigned to port 7 001 => mask off */ 2 size bit (3), /* size of lower store */ 2 a_online bit (1), /* 1 => store A online */ 2 a1_online bit (1), /* 1 => store A1 online */ 2 b_online bit (1), /* 1 => store B online */ 2 b1_online bit (1), /* 1 => store B1 online */ 2 port_no bit (4), /* requester's port number */ 2 pad1 bit (1), 2 mode bit (1), /* 1 => programmable mode */ 2 nea_enabled bit (1), /* 1 => non-existent address logic enabled */ 2 nea bit (7), /* 001 => 32K, 002 => 64K, 003 => 96K, etc. */ 2 int bit (1), /* 1 => stores are internally interlaced */ 2 lwr bit (1), /* 1 => store B is low */ 2 port_mask_0_3 bit (4), /* 1 => corresponding port enabled */ 2 mask_b_assign bit (9), /* interrupt mask "B" port assignment */ 2 pad2 bit (12), 2 cyclic_prior bit (7), /* cyclic port priority switches */ 2 pad3 bit (4), 2 port_mask_4_7 bit (4)) unal; /* 1 => corresponding port enabled */ dcl 1 scr_mr based (scrp) aligned, /* SC mode register */ (2 pad1 bit (50), 2 identification bit (4), /* 0000 => 8034, 8035 0001 => 6000 SC 0010 => 4MW SCU */ 2 TS_strobe_margin bit (2), /* 00 => normal timing 01 => slow timing 10 => inhibit strobe 11 => fast timing */ 2 G0_strobe_margin bit (2), 2 ANSWER_strobe_margin bit (2), 2 DA_strobe_margin bit (2), 2 EOC_strobe_margin bit (2), 2 PLUS_5_VOLT_margin bit (2), /* 00 => normal voltage 01 => -5% 10 => normal voltage 11 => +5% */ 2 parity_override bit (1), /* 1 => SU forced to accept data with incorrect parity */ 2 parity_disable bit (1), /* 1 => disable data and ZAC parity checking */ 2 store_IA_disable bit (1), /* 1 => disable illegal action indication */ 2 ZAC_parity_error bit (1), /* 1 => cause ZAC parity error */ 2 SGR_accepted bit (1), /* 1 => SGR command accepted by SC */ 2 pad2 bit (1)) unal; dcl 1 scr_msk based (scrp) aligned, /* SC mask register */ (2 interrupt_mask_1 bit (16), /* mask bits for interrupts 0 thru 15 */ 2 pad1 bit (16), 2 port_mask_1 bit (4), /* mask bits for ports 0 thru 3 */ 2 interrupt_mask_2 bit (16), /* mask bits for interrupts 16 thru 31 */ 2 pad2 bit (16), 2 port_mask_2 bit (4)) unal; /* mask bits for ports 4 thru 7 */ dcl 1 scr_su based (scrp) aligned, /* store unit mode register */ (2 pad1 bit (36), 2 ZAC_line bit (6), /* EDAC mode only - address field */ 2 syndrome bit (8), /* EDAC mode only - failure syndrome */ 2 identification bit (4), /* 0000 => High Speed Core Model AA1 0001 => High Speed Core Model AA3 0011 => 4K, 16 pin chip, MOS memory, M32 boards 0100 => 1K chip MOS memory with EDAC enabled 1010 => 64K, 16 pin chip, MOS memory, M64 boards 1011 => 16K, 16 pin chip, MOS memory, M264 boards 1100 => 1K chip MOS memory with EDAC disabled 1110 => 16K, 16 pin chip, MOS memory, M128 boards 1111 => 4K, 22 pin chip MOS memory, M16 boards */ 2 EDAC_disabled bit (1), /* 1 => correction disabled but detection still enabled */ 2 pad2 bit (4), 2 MINUS_5_VOLT_margin bit (2), 2 PLUS_5_VOLT_margin bit (2), 2 spare_margin bit (2), 2 PLUS_19_VOLT_margin bit (2), 2 pad3 bit (1), 2 SENSE_strobe_margin bit (2), /* core only */ 2 pad4 bit (1), 2 maint_functions_enabled bit (1)) unal; /* 1 => maintenance functions enabled */ /* End of include file ...... scr.incl.pl1 */ */ ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull and Bull HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by Bull HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved */