/* BEGIN INCLUDE FILE scs.incl.pl1 ... March 1983 */ /* format: style4 */ /* Information about system controllers */ dcl 1 scs$controller_data (0:7) aligned ext, /* per-controller info */ 2 size fixed bin (17) unaligned, /* size (in 1024 word blocks) of this controller */ 2 base fixed bin (17) unaligned, /* abs address (0 mod 1024) for base of this controller */ 2 eima_data (4) unaligned, /* EIMA information for this controller */ 3 mask_available bit (1) unaligned, /* ON if corresponding mask exists */ 3 mask_assigned bit (1) unaligned, /* ON if mask assigned to a port */ 3 mbz bit (3) unaligned, 3 mask_assignment fixed bin (3) unaligned, /* port to which mask is assigned */ 2 info aligned, 3 online bit (1) unaligned, /* ON if controller is online */ 3 offline bit (1) unaligned, /* ON if controller is offline but can be added */ 3 store_a_online bit (1) unaligned, /* ON if store A is online */ 3 store_a1_online bit (1) unaligned, /* ON if store A1 is online */ 3 store_b_online bit (1) unaligned, /* ON if store B is online */ 3 store_b1_online bit (1) unaligned, /* ON if store B1 is online */ 3 store_b_is_lower bit (1) unaligned, /* ON if store B is lower */ 3 ext_interlaced bit (1) unaligned, /* ON if this SCU is interlaced with other SCU */ 3 int_interlaced bit (1) unaligned, /* ON if this SCU is internally interlaced */ 3 four_word bit (1) unaligned, /* ON if external interlace is 4-word */ 3 cyclic_priority (7) bit (1) unaligned, /* Cyclic priority for adjacent ports */ 3 type bit (4) unaligned, /* Model number for this controller */ 3 abs_wired bit (1) unaligned, /* ON if controller can have abs_wired pages */ 3 program bit (1) unaligned, /* PROGRAM/MANUAL switch setting */ 3 mbz bit (13) unaligned, 2 lower_store_size fixed bin (17) unaligned, /* size (in 1024 word blocks) of lower store */ 2 upper_store_size fixed bin (17) unaligned; /* size (in 1024 word blocks) of upper store */ /* Information about CPUs */ dcl 1 scs$processor_data (0:7) aligned ext, /* information about CPUs in the system */ ( 2 online bit (1), /* "1"b if CPU is online */ 2 offline bit (1), /* "1"b if CPU is offline but can be added */ 2 release_mask bit (1), /* "1"b is this CPU is to give up its mask */ 2 accept_mask bit (1), /* "1"b if this CPU is to grap mask in idle loop */ 2 delete_cpu bit (1), /* "1"b if this CPU is to delete itself */ 2 interrupt_cpu bit (1), /* "1"b if this CPU takes hardware interrupts */ 2 halted_cpu bit (1), /* "1"b if this CPU has stopped itself (going to BOS) */ 2 cpu_type fixed bin (2) unsigned, /* 0 => DPS or L68, 1 => DPS8 */ 2 mbz1 bit (6), 2 cache_size fixed bin (3) unsigned, /* 0 = No cache; 1 = L68 2K cache; 2 = DPS8 8K cache; 3 = DPS8 VS&SC 8K cache; 4 = DPS8 VS&SC 16K cache; 5 = DPS8 VS&SC 32K cache 7 = ignore cache size (set by ISOLTS reconfig) */ 2 mbz2 bit (12), 2 expanded_port bit (1), /* "1"b = on expanded port */ 2 expander_port fixed bin (2) unsigned, /* The actual expander port */ 2 controller_port fixed bin (3) unsigned ) unaligned; /* Port on controller */ dcl 1 scs$port_data (0:7) aligned external static, /* Info about what is connected to each SCU port */ 2 assigned fixed bin (4) unsigned unaligned, /* Type of device on this port */ 2 expander_port bit (1) unaligned, /* "1"b => this port has a port expander */ 2 expanded_cpu (0:3) bit (1) unaligned, /* "1"b => this expander port has a CPU attached */ 2 iom_number fixed bin (3) unsigned unaligned, /* IOM number of IOM attached to this port */ 2 cpu_number (0:3) fixed bin (3) unsigned unaligned, /* CPU number of CPU(s) attached to this port */ /* cpu_number (0) is only one if expander_port is "0"b */ 2 pad bit (12) unaligned; dcl 1 scs$cow (0:7) aligned external, /* Actual connect words */ 2 pad bit (36) aligned, /* Expander COW's must be odd-word */ 2 cow, 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 3 mbz1 bit (13) unaligned, 3 expander_command bit (3) unaligned, /* Expander command. */ 3 mbz2 bit (2) unaligned, 3 expanded_port bit (1) unaligned, /* "1"b = on expanded port */ 3 expander_port fixed bin (3) unsigned unaligned, /* Port on expander for cioc */ 3 mbz3 bit (3) unaligned, 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ dcl 1 scs$cow_ptrs (0:7) external aligned, /* Pointers to COW's */ 2 rel_cow_ptr bit (18) unal, /* Relative pointer to COW */ 2 pad bit (12) unal, 2 tag bit (6) unal; /* Better be zero. */ dcl 1 scs$reconfig_general_cow aligned external, /* Used during reconfig ops. */ 2 pad bit (36) aligned, 2 cow, /* Connect operand word, in odd location. */ 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 3 mbz1 bit (13) unaligned, 3 expander_command bit (3) unaligned, /* Expander command. */ 3 mbz2 bit (9) unaligned, 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ /* MASKS and PATTERNS */ dcl scs$sys_level bit (72) aligned ext; /* mask used while handling I/O interrupts */ dcl scs$open_level bit (72) aligned ext; /* mask used during normal operation */ dcl scs$processor_start_mask bit (72) aligned ext; /* mask used when starting up a CPU */ dcl scs$cpu_test_mask bit (72) aligned ext; /* mask used for ISOLTS CPU testing */ dcl scs$number_of_masks fixed bin ext; /* number of masks (starting at sys_level) */ dcl scs$processor_start_pattern bit (36) aligned ext; /* SMIC pattern used to send processor start interrupt */ dcl scs$cpu_test_pattern bit (36) aligned ext; /* SMIC pattern used for ISOLTS processor testing */ /* CAM and CACHE clear info */ dcl scs$cam_pair fixed bin (71) ext; /* instructions XEDd when CAMing and clearing CACHE */ dcl scs$cam_wait bit (8) aligned ext; /* Used when evicting pages from main memory */ /* MASKING INSTRUCTIONS & POINTERS */ dcl scs$set_mask (0:7) bit (36) aligned ext; /* instructions to set mask (STAQ or SMCM) */ dcl scs$read_mask (0:7) bit (36) aligned ext; /* instructions to read mask (LDAQ or RMCM) */ dcl scs$mask_ptr (0:7) ptr unaligned ext; /* pointers for real or simulated masks */ /* MISCELLANEOUS */ dcl 1 scs$processor_test_data aligned ext, /* info used for cpu testing */ ( 2 active bit (1), /* = "1"b if cpu currently under test */ 2 scu_state bit (2), /* state of scu being used for testing (see definition below) */ 2 pad1 bit (4), 2 req_mem fixed bin (10), /* dedicated memory required to test this cpu */ 2 cpu_tag fixed bin (5), /* tag of cpu under test */ 2 scu_tag fixed bin (5), /* tag of scu being used for cpu testing */ 2 mask_cpu fixed bin (5) ) unaligned; /* tag of active cpu that has mask asigned to above scu */ /* scu_state = "00"b => SCU defined by scs$processor_test_data.scu_tag not yet effected */ /* scu_state = "01"b => all core removed from SCU, port mask not yet changed */ /* scu_state = "10"b => all core removed from SCU, port mask changed */ /* scu_state = "11"b => only 64k at base of SCU being used for testing, original port mask restored */ dcl scs$idle_aptep (0:7) ptr unaligned ext; /* pointer to idle process APTE for each processor */ dcl scs$connect_lock bit (36) aligned ext; /* lock for sending connects */ dcl scs$reconfig_lock bit (36) aligned ext; /* Lock used during reconfiguration */ dcl scs$trouble_flags bit (8) aligned ext; /* checkoff flags for sys_trouble stopping */ dcl scs$bos_restart_flags bit (8) aligned ext; /* checkoff flags for restarting after sys_trouble */ dcl scs$nprocessors fixed bin ext; /* number of runnung processors */ dcl scs$bos_processor_tag fixed bin (3) ext; /* CPU tag of processor running BOS */ dcl scs$faults_initialized bit (1) aligned ext; /* ON after faults have been enabled */ dcl scs$sys_trouble_pending bit (1) aligned ext; /* sys_trouble event is pending in the system */ dcl scs$fast_cam_pending (0:7) bit (36) aligned ext; /* checkoff cells for cam connect */ dcl scs$interrupt_controller fixed bin (3) ext; /* port number of low order controller */ dcl scs$processor_start_int_no fixed bin (5) ext; /* interrupt cell for starting a processor */ dcl scs$processor bit (8) aligned ext; /* bits ON for online CPUs */ dcl scs$processor_start_wait bit (8) aligned ext; /* checkoff flags for waiting for new processor */ dcl scs$trouble_dbrs (0:7) fixed bin (71); /* DBR values at system crash time */ dcl scs$port_addressing_word (0:7) bit (3) aligned ext; /* active module port number for each controller */ dcl scs$cfg_data (0:7) fixed bin (71) aligned ext; /* RSCR-CFG data from each controller */ dcl scs$cfg_data_save fixed bin (71) aligned ext; /* RSCR-CFG save area for ISOLTS CPU testing */ dcl scs$expanded_ports bit (1) unaligned dim (0:7) external; /* Which ports have expanders */ dcl scs$processor_switch_data (0:4) bit (36) aligned ext; /* raw data from RSW 0 thru 4 */ dcl scs$processor_switch_template (0:4) bit (36) aligned ext; /* expected data from RSW 0 thru 4 */ dcl scs$processor_switch_compare (0:4) bit (36) aligned ext; /* discrepancies from expected data */ dcl scs$processor_switch_mask (0:4) bit (36) aligned ext; /* masks for comparing switch data */ dcl scs$processor_data_switch_value bit (36) aligned ext; /* Correct value for CPU data switches */ dcl scs$controller_config_size (0:7) fixed bin (14) aligned ext; /* Controller size on config card */ dcl scs$reconfig_locker_id char (32) aligned ext; /* process group ID of process doing reconfiguration */ dcl scs$scas_page_table (0:31) bit (36) aligned external static; /* PTWs for SCAS pages */ dcl scs$cycle_priority_template bit (7) aligned ext; /* template for setting anti-hog switches */ dcl scs$set_cycle_switches bit (1) aligned ext; /* flag to set ant-hog switches */ dcl ( IOM_PORT init (1), CPU_PORT init (2), BULK_PORT init (3) ) fixed bin int static options (constant); /* values for scs$port_data.assigned */ /* END INCLUDE FILE scs.incl.pl1 */ */ ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull and Bull HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by Bull HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved */