



		    cache_priv.alm                  11/11/89  1109.6rew 11/11/89  0827.3       63477



" ***********************************************************
" *                                                         *
" * Copyright, (C) Honeywell Bull Inc., 1987                *
" *                                                         *
" * Copyright, (C) Honeywell Information Systems Inc., 1984 *
" *                                                         *
" * Copyright, (C) Honeywell Information Systems Inc., 1982 *
" *                                                         *
" * Copyright (c) 1972 by Massachusetts Institute of        *
" * Technology and Honeywell Information Systems, Inc.      *
" *                                                         *
" ***********************************************************

"  
"  cache_priv - privileged subroutine to perform static test of cache memory.
"  Called from pl1 procedure cache_tester.
"  
"  Entry description:
"  
"  dcl  cache_priv$csh1 (csh2) entry (ptr, fixed bin, ptr, fixed bin (35));
"  call cache_priv$csh1 (csh2) (wired_buf_ptr, buf_size, info_ptr, code);
"  
"  where:
"  
"  1. wired_buf_ptr - is a ptr to a wired encachable buffer. It is assumed that the
"  wired buffer has been filled with the desired test data pattern, by the caller.
"  
"  2. buf_size - is the buffer size in words. It should be one half the cache size.
"  
"  3. info_ptr - is a ptr to a wired info structure which is a 3 element array of
"  error/diagnostic info. The structure array elements are defined below. The data
"  from the first 3 errors encountered is stored in the info structure.
"  
"  4. code - is an indication of the existance of a cache error, and is also the
"  count of the number of errors encounterd.
"  
"  The cache_priv$csh1 entry is to test the lower half of cache memory defined by
"  the program settable switch "csh1" in the cache mode register. The
"  cache_priv$csh2 entry is to test the upper half of cache memory defined by the
"  program settable switch "csh2" in the cache mode register.
"  
"  Original coding by J. A. Bush 1/15/80
"  Modified by J. A. Bush 6/20/80 to not inhibit so long
"  
"  Modified  by R. A. Fawcett June 1984 to handle:
"   1. Original type of DPS8M 8K cache
"   2. VSSC cache for 8K 16K and 32K configs
"   3. And do the same things for all types of CACHE including L68 2K.
"      After the above changes Bush would not recognize this program.
"
	name	cache_priv
	entry	csh1
	entry	csh2

	tempd	maskwd,ptwp,arglist(7) arguments for calls
	tempd	temp_fault_reg	temp storage for fault reg
	tempd	cam_wait
	temp	buf_length	storage for cache buffer length
	temp	temp_ind_reg	temp storage for ind reg
	temp	timer		temp storage for the timer register
	temp	not_me
" The next equs are for the cpriv_info.err_data array in cache_tester.
" They are based on the bb indexed by x4 and there are 3 possible error sets.

	equ	cache_data,0	error data in cache
	equ	ex_or_data,2	exclusive or of error data in memory and cache
	equ	fault_reg,4	storage for fault register
	equ	cache_addr,6	storage for error address in cache
	equ	ind_reg,7		storage for indicator register


	bool	par_err,1000	parity indicator
	bool	par_mask,400	parity mask indicator


csh1:
"**** entry to test lower half of cache  ***
	push
	eax3	0		set cache on constant to csh1
	tra	c_com


csh2:
"**** entry to test upper half of cache  ***
	push
	eax3	1		set cache on constant to csh2

c_com:
	eppbp	ap|2,*		get cache buf ptr
	eppbp	bp|0,*
	eppbb	ap|6,*		get com region address
	eppbb	bb|0,*

	lxl7	ap|4,*		get buffer size in words
	stx7	buf_length	and save for comparisons
	eaa	0,x7		calc clear time based on cache size
	arl	3		
	eax4	0,au		initialize csh_on wait count
	eax6	0		start at address 0 of buffer


	epplb	page$cam_wait
	sprilb	cam_wait

	epplb	maskwd		" mask so that no interups are taken
	sprilb	arglist+2
	epplb	ptwp
	sprilb	arglist+4
	ldaq	TWO_ARGS_ND
	staq	arglist
	call      pmut$wire_and_mask(arglist)

	ldi	par_mask,dl	don't take parity fault

	stt	timer		save the current timer
	ldt	TIMER		set timer for 4min + (no fault)


prev_connects:
	epplb	ptwp
	sprilb	arglist+2
	ldaq	ONE_ARG_ND
	staq	arglist		cause other cpus to loop unitl
	call	cam_wait,*(arglist)  cache is loaded

clear_cache:

	lcpr	csh_off,02	insure that cache is OFF
	xec	csh_on,3		turn appropriate cache segment on
	eax4	-1,4		wait for cache hardware initialization
	nop	0,du
	tnz	*-2		error counter (x4) is 0 on loop exit

l_loop:
	ldaq	bp|0,6		fill cache by referencing wired buffer
	eax6	4,6		increment to next block address
	eax7	-4,7		decrement block count
	tnz	l_loop		xfer if not full
	lcpr	csh_off,02	now turn cache off

	stz	scs$cam_wait	trun others lose

set_up_check:
	ldi	0,dl		initialize indicator reg
	eax6	0		all done initialize buffer index
	cmpx3	1,du		are we testing upper cache memory?
	tnz	c_loop		xfer if no, x7  has address 0 (start of lower cache)
	ldx7	buf_length	yes set cache read address to upper half

c_loop:
	inhibit	on
	ldi	par_mask,dl	don't take parity fault here!!!
	lcpr	cache_to_reg_mode,02
	ldaq	bp|0,7		load data from cache
	lcpr	csh_off,02	turn reg mode off
	inhibit	off
	sti	temp_ind_reg	save indicator reg
	ldi	0,dl		and initialize

	cmpaq	bp|0,6		data in cache equal to data in mem?
	tze	par_chk		xfer if yes
	cmpaq  	csh_off		data in cache = csh_off constant?
	tnz	cmp_err		xfer if no

par_chk:
	lxl5	temp_ind_reg	but did we have a parity error?
	canx5	par_err,du
	tnz	cmp_err		xfer if yes

err_cont:
	eax7	2,7		increment cache address
	eax6	2,6		increment memory address
	cmpx6	buf_length	last  cache addr looked at
	tmi	c_loop		xfer if no
	ldi	0,dl		yes, reset parity mask
	eaa	0,4		copy error index to a
	arl	18+3		right justify and get real error count
	sta	ap|8,*		and store in error code


	epplb	maskwd		now we can unmask
	sprilb	arglist+2
	epplb	ptwp
	sprilb	arglist+4
	ldaq	TWO_ARGS_ND
	staq	arglist
	call	pmut$unwire_unmask(arglist)   unmask

	ldt	timer		restore_timer
	return			all done this half

cmp_err:

	cmpx4	24,du		do we have 3 errors already?
	tmi	capture		no, go capture error data
	eax4	8,4		yes, just add 1 more to error count
	tra	err_cont		and go loop trough rest of cache

capture:
	scpr	temp_fault_reg,01 compare/parity error, save fault reg
	staq	bb|cache_data,4	save cache data
	eraq	bp|0,6		exclusive or cache and memory data
	staq	bb|ex_or_data,4
	lxl5	temp_ind_reg	but did we have a parity error?
	anx5	par_err,du
	sxl5	bb|ind_reg,4	save indicator reg of error
	lda	temp_fault_reg	save fault reg
	sta	bb|fault_reg,4
	sxl7	bb|cache_addr,4	save cache address in error
	eax4	8,4		add 1 more to error count
	tra	err_cont		and go loop trough rest of cache

	inhibit	on
	even
csh_on:	lcpr	csh1_on,02	turn csh1 on with xec instruction
	lcpr	csh2_on,02	turn csh2 on with xec instruction
	inhibit	off

csh1_on:	oct	500003		csh1 and operands on
csh2_on:	oct	300003		csh2 and operands on

	even
csh_off:	oct	3
	oct	707070707070	pattern to ignore csh_off constant

cache_to_reg_mode:
	oct	10003		cache dump mode

	even
ONE_ARG_ND:
	zero	2,2
	zero	0,0
TWO_ARGS_ND:
	zero	4,4
	zero	0,0

TIMER:    oct	777777777777
	end






		    bull_copyright_notice.txt       08/30/05  1008.4r   08/30/05  1007.3    00020025

                                          -----------------------------------------------------------


Historical Background

This edition of the Multics software materials and documentation is provided and donated
to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. 
as a contribution to computer science knowledge.  
This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology,
Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull
and Bull HN Information Systems Inc. to the development of this operating system. 
Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970),
renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership
of Professor Fernando Jose Corbato.Users consider that Multics provided the best software architecture for 
managing computer hardware properly and for executing programs. Many subsequent operating systems
incorporated Multics principles.
Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., 
as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. .

                                          -----------------------------------------------------------

Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without
fee is hereby granted,provided that the below copyright notice and historical background appear in all copies
and that both the copyright notice and historical background and this permission notice appear in supporting
documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining
to distribution of the programs without specific prior written permission.
    Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc.
    Copyright 2006 by Bull HN Information Systems Inc.
    Copyright 2006 by Bull SAS
    All Rights Reserved
