" *********************************************************** " * * " * Copyright, (C) Honeywell Bull Inc., 1987 * " * * " * Copyright, (C) Honeywell Information Systems Inc., 1982 * " * * " * Copyright (c) 1972 by Massachusetts Institute of * " * Technology and Honeywell Information Systems, Inc. * " * * " *********************************************************** entry init,start_bootload_cpu,return segdef wait_flag flag cleared by new processor segdef controller_data bits for online controllers segdef new_dbr DBR for new processor segdef first_tra TRA instruction to start new processor segdef trouble_tra TRA instruction if trouble starting segdef startup_tra TRA instruction if startup fault segdef lockup_tra TRA instruction if lockup fault segdef onc_tra TRA instruction if op-not-complete fault " include mode_reg include cache_mode_reg " " INIT - Initialization Entry. init: absa first_steps get absolute address als 6 in AU orsa first_tra and set TRA instruction absa trouble_start get absolute address als 6 in AU orsa trouble_tra set for bad startup absa startup_start get absolute address als 6 in AU orsa startup_tra set for bad startup absa lockup_start get absolute address als 6 in AU orsa lockup_tra set for bad lockup absa onc_start get absolute address als 6 in AU orsa onc_tra set for bad onc absa cache_off get absolute address of cache off template als 6 in AU orsa set_cache_off set in y field of cache off lcpr absa scs$processor_switch_data als 6 get absolute address sta switch_data save for checking switches absa scs$processor_switch_template als 6 get absolute address sta switch_test save for checking switches absa scs$processor_switch_compare als 6 get absolute address sta switch_discrep save for checking switches absa scs$processor_switch_mask als 6 get absolute address sta switch_and save for checking switches eppbp second_step bp -> place to enter appending mode spribp continue save for use by new processor short_return " " START_BOOTLOAD_CPU - Entry to Start Idle Process for Bootload CPU. start_bootload_cpu: push spri prs save prs for new CPU sprisp pds$last_sp make sure we get sp set correctly " ldbr new_dbr load new DBR for idle process tra second_step and go to idle process initialization " tc_init has fixed things with pxss so that we will continue running " at the following instruction. " return: return " " The first steps of the initialized processor ... " " The processor reaches this point still in absolute mode. The " DBR must be loaded, and then appending mode ... inhibit on <+><+><+><+><+><+><+><+><+><+><+><+> first_steps: sti indic-*,ic save indicators lda indic-*,ic pick up indicators cana scu.ir.abs,dl in abs mode? tze gcoserr-*,ic if not, CPU is in wrong mode set_cache_off: lcpr 0,02 turn cache off before we get into trouble. eax3 0 eax7 0 read processor switches ldx6 switch_test-*,ic this code executes in ABSOLUTE MODE ldx5 switch_discrep-*,ic .. ldx4 switch_data-*,ic .. swtest1: rsw 0,7 read processor switches sta 0,4 and save era 0,6 generate discrepancy data sta 0,5 and store eax5 1,5 .. eax6 1,6 .. cmpx7 2,du was this an rsw (2)? tnz swtest2-*,ic xfer if no lda 0,4 yes, load rsw (2) data lrl 30 position cpu type in AL ana 3,dl and out all but cpu type tze swtest2-*,ic xfer if L68 or DPS cpu eax3 0,al copy cpu type into x3 tra swtest3-*,ic and go check switches swtest2: cmpx7 4,du was last instuction rsw (4)? tze swtest3-*,ic yes, go check switches eax4 1,4 increment rsw data storage eax7 1,7 loop until finished tra swtest1-*,ic .. swtest3: eax7 0 see if any switches are set wrongly ldx6 switch_discrep-*,ic remember, ABSOLUTE MODE ldx5 switch_and-*,ic .. swtest4: lda 0,6 pick up discrepancy data cana 0,5 any bits on? tnz swerr-*,ic if so, stop now eax5 1,5 check all switches eax6 1,6 .. cmpx7 2,du was this data from an rsw (2)? tnz swtest5-*,ic xfer if no cmpx3 1,du yes, is this a DPS8 CPU? tze swtest6-*,ic xfer if yes swtest5: cmpx7 4,du is this data from an rsw (4)? tze swtest6-*,ic yes, we are all done eax7 1,7 .. tra swtest4-*,ic .. swerr: lda rcerr_addcpu_bad_switches,dl sta wait_flag-*,ic set it for start_cpu swerr_lp: ldt =o77777,du prevent timer runout faults lda wait_flag-*,ic has start_cpu given use a green lite? tmi nogo-*,ic no, bad switches go to DIS cmpa rcerr_addcpu_bad_switches,dl is start_cpu still thinking about it? tze swerr_lp-*,ic yes, go through another loop swtest6: eax7 0 controller port number in X7 ctest1: lda controller_data-*,ic get controllers online tpl 2,ic if this one offline, skip reference rccl 0,7 if controller port not enabled, get onc fault nop 0,du allow possible onc to "take" nop 0,du .. eax7 32768,7 step to next port lda controller_data-*,ic get controllers online als 1 shift to next controller sta controller_data-*,ic replace data tnz ctest1-*,ic loop if more to do scu cudata-*,ic store control unit lda scu.apu.pt_on+scu.apu.sd_on,dl AM's on? cnaa cudata-*+scu.apu_stat_word,ic tnz amerr-*,ic if not, stop ldbr new_dbr-*,ic load the DBR tra continue-*,ic* enter appending mode " trouble_start: lda rcerr_addcpu_trouble,dl tra nogo-*,ic startup_start: lda rcerr_addcpu_startup,dl tra nogo-*,ic lockup_start: lda rcerr_addcpu_lockup,dl tra nogo-*,ic amerr: lda rcerr_addcpu_amoff,dl tra nogo-*,ic onc_start: eaa 0,7 port number in A arl 33 ldx7 switch_discrep-*,ic store for error analysis sta -3,7 .. lda rcerr_addcpu_enable,dl tra nogo-*,ic gcoserr: lda rcerr_addcpu_gcos,dl tried to add CPU in GCOS mode nogo: sta wait_flag-*,ic dis -1 tra -1,ic " bool hist_on,mr.enable_mr+mr.enable_hist bool cache_on,cmr.cache_1_on+cmr.cache_2_on+cmr.operands_from_cache+cmr.inst_from_cache " " All checks have been passed--start running " second_step: lpri prs load the pointer registers with good stuff ldt 1,du set initial value stt prds$last_timer_setting eax6 0 initialize cache size to 0 (no cache) rsw 2 get cpu type in a reg eax7 64 64 hregs on DPS8 CPU cana =o10000,du is it a DPS8 cpu? tnz cpu_dps8 xfer if yes eax7 16 only 16 hregs for L68 or DPS cpus cana =o400,dl L68 with cache? tze init_hregs No, L68 with no cache eax6 1 yes, set cache size for 2K tra init_hregs cpu_dps8: epplb reg_storage get ptr to store funny CMR scpr lb|2,06 Note, must have addr bit 16 on lda lb|3 load cache size word ana =o3400,dl and out all but size tnz ck_vs_sc is it old style 8K? eax6 2 yes, set index tra init_hregs ck_vs_sc: eax6 5 start with 32K size als 24 bit 60 to A0 c_sz_lp: als 1 position indicator bit tmoz init_hregs exit if we got a hit eax6 -1,6 decrement cache size tra c_sz_lp init_hregs: lcpr 0,03 reset history reg eax7 -1,7 tpnz init_hregs lxl1 prds$processor_tag get our CPU tag lda =o77,dl ansa scs$processor_data,1 reset all bits but port number orsx6 scs$processor_data,1 store cache size xec cache_ctr_tab,1 LB => wired_hardcore_data cache err ctrs sxl6 lb|0 save cache size&type there also epplb prds$cache_luf_reg get setting for lockup/cache control lda cache_on+3,dl set lockup fault reg sta lb|0 set bits to allow cache to run "************************************* Cache is enabled for first time here**************** lcpr lb|0,02 load luf/cache register cams 4 clear cache on L68 and DPS (no effect on DPS8) scpr indic,01 store and clear the fault register lda prds$mode_reg start history regs and start cache ora hist_on,dl enable history regs, stop for fault sta prds$mode_reg_enabled epplb prds$mode_reg_enabled lcpr lb|0,04 load mode reg eppbp prds$idle_ptr,* apte for idle process this cpu spribp prds$apt_ptr mark as apte for running process this cpu ldx0 running,du we must tell traffic controller sxl0 bp|apte.state that state is running rccl sys_info$clock_,* read the calendar clock staq pds$cpu_time initialize (cause pxss won't) staq prds$last_recorded_time initialize this, too. " Now that the processor is fully initialized, reflect this in the SCS. lda processor_data.online+processor_data.interrupt_cpu,du orsa scs$processor_data,1 lda =o400000,du turn on high-order bit arl 0,1 shift to correct position sta prds$processor_pattern set correct bit orsa scs$processor indicate CPU now running " " Clear flag that start_cpu is waiting on. Then, wait " for start_cpu to undo the connect lock. stz wait_flag signal that we are running szn scs$connect_lock connect lock cleared? tze *+4 if so, exit loop llr 72 wait for a while llr 72 .. tra *-4 .. eppsp =its(-1,1),* null pointer for sp in idle processors " Send a connect to pre-empt the idle process. " Then open the mask to allow interrupts. ldq apte.pre_empt_pending,du pre_empt the processor orsq bp|apte.flags cioc scs$cow_ptrs,1* ldaq scs$open_level open up the mask xec scs$set_mask,1 " " " Idle with a flashing pattern in the lights. " " This is a convenient place to recompute tc_data$max_timer_register, " which is the product of the number of CPUs and the tuning parameter " tc_data$pre_empt_sample time. Either of these values may have " changed due to reconfiguration or tuning parameter changes, and " we don't have much else to do here, so ... ldaq flash_pattern inhibit off <-><-><-><-><-><-><-><-><-><-><-><-> idle_dis: dis 0 inhibit on <+><+><+><+><+><+><+><+><+><+><+><+> " The following code checks to see if a connect has been delayed. " This is done by seeing if the ring alarm register is nonzero. " If it is, the connect must be reissued now. sznc pds$alarm_ring is ring alarm set? tze *+2 if not, skip connect reissue cioc scs$cow_ptrs,1* staq prds$idle_temp save flash pattern ldq tc_data$pre_empt_sample_time mpy tc_data$ncpu tze reload_flash bogus for some reason staq tc_data$max_timer_register reload_flash: ldaq prds$idle_temp alr 35 qlr 1 eax7 0,au flash pattern in X7 lxl4 tc_data$n_eligible # of eligible processes in X4 ldx5 bp|apte.term_processid idle type in X5 lxl6 tc_data$stat+2 # of ready processes in X6 tra idle_dis inhibit off <-><-><-><-><-><-><-><-><-><-><-><-> " mod 16 prs: bss ,16 cudata: bss ,8 new_dbr: bss ,2 cache_off: oct 3 template for turning cache off even flash_pattern: zero -1,0 zero 0,-1 continue: its -1,1 reg_storage: bss ,4 switch_data: arg 0 switch_test: arg 0 switch_and: arg 0 switch_discrep: arg 0 controller_data: vfd 8/0 inhibit on <+><+><+><+><+><+><+><+><+><+><+><+> first_tra: tra 0 trouble_tra: tra 0 startup_tra: tra 0 lockup_tra: tra 0 onc_tra: tra 0 inhibit off <-><-><-><-><-><-><-><-><-><-><-><-> even indic: bss ,2 wait_flag: oct 0 inhibit on cache_ctr_tab: epplb wired_hardcore_data$cpu_a_cache_err_ctr_array epplb wired_hardcore_data$cpu_b_cache_err_ctr_array epplb wired_hardcore_data$cpu_c_cache_err_ctr_array epplb wired_hardcore_data$cpu_d_cache_err_ctr_array epplb wired_hardcore_data$cpu_e_cache_err_ctr_array epplb wired_hardcore_data$cpu_f_cache_err_ctr_array epplb wired_hardcore_data$cpu_g_cache_err_ctr_array epplb wired_hardcore_data$cpu_h_cache_err_ctr_array inhibit off " include scs include rcerr include mc " include state_equs include apte end " " " ----------------------------------------------------------- " " " " Historical Background " " This edition of the Multics software materials and documentation is provided and donated " to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. " as a contribution to computer science knowledge. " This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, " Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull " and Bull HN Information Systems Inc. to the development of this operating system. " Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), " renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership " of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for " managing computer hardware properly and for executing programs. Many subsequent operating systems " incorporated Multics principles. " Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., " as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . " " ----------------------------------------------------------- " " Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without " fee is hereby granted,provided that the below copyright notice and historical background appear in all copies " and that both the copyright notice and historical background and this permission notice appear in supporting " documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining " to distribution of the programs without specific prior written permission. " Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. " Copyright 2006 by Bull HN Information Systems Inc. " Copyright 2006 by Bull SAS " All Rights Reserved " "