COMPILATION LISTING OF SEGMENT bce_display_scu_ Compiled by: Multics PL/I Compiler, Release 32f, of October 9, 1989 Compiled at: Bull HN, Phoenix AZ, System-M Compiled on: 11/11/89 1019.2 mst Sat Options: optimize map 1 /****^ *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Bull Inc., 1987 * 4* * * 5* * Copyright, (C) Honeywell Information Systems Inc., 1984 * 6* * * 7* *********************************************************** */ 8 bce_display_scu_: proc (scup, a_offset, lg_sw); 9 10 /* Modification History - prtscu_ 11* Initially coded by J. A. Bush - Dec 1975 12* Modified May 1977 by J. A. Bush to be intellegent about group 7 faults and not print out tsr|ca 13* Modified Aug 1980 by R.L. Coppola to be more intelligent about IOM channels greater than 37 (octal). 14* Also added display of the CT Hold reg in CU status. 15* Stolen for bce use, Keith Loepere December 1983. 16**/ 17 18 dcl scup ptr; /* pointer to SCU Data */ 19 dcl a_offset fixed bin (26); /* relative offset of SCU data */ 20 dcl lg_sw bit (1); /* long format switch "1"b => long */ 21 dcl (strp, byptr, refptr) ptr; 22 dcl (lnpos, flt_lng, inst6, i, j) fixed bin; 23 dcl reoffset fixed bin (26); 24 dcl code fixed bin (35); 25 dcl w (0 : 7) fixed bin based; 26 dcl flt_ln char (100); 27 dcl flt_bf char (24) varying; 28 dcl iocbp ptr; 29 dcl (length, fixed, addr, addrel, baseptr, substr, null, hbound, lbound) builtin; 30 dcl (tsrpr, on_line) bit (1); 31 dcl cvbinbuf char (12); 32 dcl fltdtab (0:35) bit (1) based (byptr) unaligned; 33 dcl cpul (0 : 7) char (1) int static options (constant) init ("a", "b", "c", "d", "e", "f", "g", "h"); 34 dcl at_by_wd char (2); 35 dcl (ioa_, ioa_$rsnnl) entry options (variable); 36 dcl bce_display_instruction_ entry (ptr, fixed bin, fixed bin (26)); 37 dcl bce_segptr_to_name_ entry (ptr) returns (char (*)); 38 dcl cv_bin_$oct entry (fixed bin, char (12)); 39 40 dcl 1 scud based (scup) aligned, 41 2 wd0 unaligned, /* :: */ 42 3 prr bit (3), /* Procedure Ring Register */ 43 3 psr bit (15), /* Procedure Segment Register */ 44 3 apust bit (18), /* APU Status */ 45 2 wd1 unaligned, /* :: */ 46 3 fid bit (20), /* fault/interrupt data */ 47 3 ill_act_lns bit (4), /* Illegal Action Lines */ 48 3 ill_act_chan bit (3), /* Illegal Action Channel (Port) */ 49 3 con_chan bit (3), /* Connect Channel (Port) */ 50 3 fi bit (6), /* Fault/Interrupt Vector Address */ 51 2 wd2 unaligned, /* :: */ 52 3 trr bit (3), /* Temporary Ring Register */ 53 3 tsr bit (15), /* Temporary Segment Register */ 54 3 mbz bit (9), /* :: */ 55 3 cpu bit (3), /* Processor Number */ 56 3 tmd bit (6), /* :: */ 57 2 wd3 fixed bin (35), /* :: */ 58 2 wd4 unaligned, /* :: */ 59 3 ict bit (18), /* Instruction Counter */ 60 3 ir bit (18), /* Indicator Register */ 61 2 wd5 unaligned, /* :: */ 62 3 ca bit (18), /* Computed Address */ 63 3 cus bit (12), /* CU Status */ 64 3 ct_hold bit (6), /* remember mod field */ 65 2 wd6 fixed bin (35), /* Even Instruction */ 66 2 wd7 fixed bin (35); /* Odd Instruction */ 67 68 dcl ill_act (0:15) char (37) varying int static options (constant) init 69 ("...", "Unasigned", "Non Existant Address", "Fault on Condition", 70 "Unassigned", "Data Parity (Store -> SCU)", "Data Parity in Store", 71 "Data Parity (Store -> SCU & in Store)", "Not Control", "Port Not Enabled", "Illegal Command", 72 "Store Not Ready", "ZAC Parity (Processor -> SCU)", "Data Parity (Processor -> SCU)", 73 "ZAC parity (SCU -> Store)", "Data Parity (SCU -> Store)"); 74 75 dcl indrs (18:31) char (4) varying int static options (constant) init 76 ("zero", "neg", "cary", "ovfl", "eovf", "eufl", "oflm", "tro", "par", "parm", "^bar", "tru", "mif", "abs"); 77 78 dcl APU (18:32) char (6) varying int static options (constant) init 79 ("priv", "xsf", "sdwamm", "sd-on", "ptwamm", "pt-on", "pi-ap", "dsptw", "sdwnp", 80 "sdwp", "ptw", "ptw2", "fap", "fanp", "fabs"); 81 82 dcl CU (18:29) char (3) varying int static options (constant) init 83 ("rf", "rpt", "rd", "rl", "pot", "pon", "xde", "xdo", "itp", "rfi", "its", "fif"); 84 85 dcl g1and7flts (5) bit (6) int static options (constant) unaligned init 86 ("01"b3, "11"b3, "21"b3, "31"b3, "37"b3); 87 88 dcl grp1flt (0:19) char (24) varying int static options (constant) init 89 ("Illegal Ring Order", "Not in Execute Bracket", "Execute Bit off", 90 "Not In Read Bracket", "Read Bit Off", "Not In Write Bracket", 91 "Write Bit Off", "Not A Gate", "Not In Call Bracket", "Outward Call", 92 "Bad Outward Call", "Inward Return", "Cross Ring Transfer", 93 "Ring Alarm", "Associative Memory", "Out of Segment Bounds", 94 "Processor Parity Upper", "Processor Parity Lower", 95 "SC To Proc. Seq. Error 1", "SC To Proc. Seq. Error 2"); 96 97 dcl grp2flt (0:6) char (24) varying int static options (constant) init 98 ("Illegal Segment Number", "Illegal Op Code", 99 "Illegal Address & Mod", "Illegal Slave Procedure", 100 "Illegal Procedure", "Non Existant Address", "Out Of Bounds"); 101 102 dcl flt_int_typ (0:63) char (24) varying int static options (constant) init 103 ("...", "Shutdown", "...", "Store", "Bulk Store 0 Term", "MME 1", "...", "Fault Tag 1", 104 "IOM 0 Overhead", "Timer Runout", "IOM 1 Overhead", "Command", "IOM 2 Overhead", "Derail", 105 "IOM 3 Overhead", "Lockup", "IOM 0 Terminate Ch 40-77", "Connect", "IOM 1 Terminate Ch 40-77", "Parity", "Bulk Store 1 Term", 106 "Illegal Procedure", "...", "Op Not Complete", "IOM 0 Terminate", "Startup", "IOM 1 Terminate", 107 "Overflow", "IOM 2 Terminate", "Divide Check", "IOM 3 Terminate", "Execute", "IOM 0 Marker Ch 40-77", 108 "(DF0) Segment", "IOM 1 Marker Ch 40-77", "(DF1) Page", "...", "Directed Fault 2", "...", "Directed Fault 3", 109 "IOM 0 Marker", "Access Violation", "IOM 1 Marker", "MME 2", "IOM 2 Marker", "MME 3", 110 "IOM 3 Marker", "MME 4", "...", "(FT2) Linkage", "...", "Fault Tag 3", "...", "...", "...", "...", 111 "IOM 0 Special", "...", "IOM 1 Special", "...", "IOM 2 Special", "...", "IOM 3 Special", "Trouble"); 112 113 dcl TAG_ptr ptr; /* pointer to tag table */ 114 dcl tag_prt bit (1) init ("0"b); 115 dcl tag_ char (4) init (""); 116 dcl TAG_table (8) char (40) init ( /* tag table */ 117 " au qu du ic al ql dl ", 118 "x0 x1 x2 x3 x4 x5 x6 x7 ", 119 "n* aau* aqu* ailtg ic* aal* aql* ailtg ", 120 "0* a1* a2* a3* a4* a5* a6* a7* a", 121 "fi itp iltg its sd scr f2 f3 ", 122 "ci i sc ad di dic aid idc a", 123 "*n *au *qu iltg *ic *al *ql iltg ", 124 "*0 *1 *2 *3 *4 *5 *6 *7 "); 125 126 127 dcl 1 TAG (64) based (TAG_ptr), 128 2 code char (4) unal, 129 2 pad bit (8) unal, 130 2 chain bit (1); 131 132 /* */ 133 134 reoffset = a_offset; /* copy relative offset */ 135 136 if scud.wd0.psr = "0"b then 137 if scud.wd2.tsr = "0"b then do; 138 call ioa_ ("No SCU data stored"); 139 return; 140 end; 141 inst6 = reoffset + 6; 142 if lg_sw then /* user wants octal dump too */ 143 call ioa_ ("^6o^-^4(^w ^)^/^-^4(^w ^)^/", reoffset, scup -> w); 144 flt_ln, flt_bf = ""; 145 tsrpr = "0"b; /* assume for now don't print tsr */ 146 flt_bf = flt_int_typ (fixed (scud.wd1.fi, 6)); 147 if substr (flt_bf, 1, 3) = "..." then 148 call ioa_ ("Fault/Interrupt (^o), Undefined", fixed (scud.wd1.fi, 6)); 149 else do; 150 flt_lng = length (flt_int_typ (fixed (scud.wd1.fi, 6))); 151 substr (flt_ln, 1, flt_lng) = substr (flt_bf, 1, flt_lng); 152 byptr = addrel (scup, 1); 153 if fltdtab (35) = "1"b then do; 154 substr (flt_ln, flt_lng + 2, 5) = "Fault"; 155 lnpos = flt_lng + 8; 156 do i = 1 to hbound (g1and7flts, 1); /* If grp 1 or 7 faults, don't print out tsr|ca */ 157 if scud.wd1.fi = g1and7flts (i) then 158 tsrpr = "1"b; 159 end; 160 end; 161 else do; 162 substr (flt_ln, flt_lng + 2, 9) = "Interrupt"; 163 lnpos = flt_lng + 12; 164 tsrpr = "1"b; /* don't print out tsr|ca for interrupts */ 165 end; 166 flt_lng = fixed (scud.wd1.fi, 6); 167 call cv_bin_$oct (flt_lng, cvbinbuf); 168 substr (flt_ln, lnpos, 4) = "(" || substr (cvbinbuf, 11, 2) || ")"; 169 lnpos = lnpos + 4; 170 j = lnpos; 171 do i = 0 to hbound (grp1flt, 1); 172 if fltdtab (i) then do; 173 if substr (flt_ln, 1, 5) = "Store"|substr (flt_ln, 1, 12) = "Illegal Proc" then 174 if i <= 6 then 175 call ioa_$rsnnl ("^a, ^a", flt_ln, j, flt_ln, grp2flt (i)); 176 else; 177 else call ioa_$rsnnl ("^a, ^a", flt_ln, j, flt_ln, grp1flt (i)); 178 end; 179 end; 180 call ioa_ ("^a", flt_ln); 181 end; 182 if ill_act_lns ^= "0"b then do; /* display illegal action lines if present */ 183 call ioa_ ("Illegal Action Code (^o) - ^a", fixed (scud.wd1.ill_act_lns, 4), 184 ill_act (fixed (scud.wd1.ill_act_lns, 4))); 185 end; 186 if tsrpr then at_by_wd = "At"; /* if not printing tsr */ 187 else at_by_wd = "By"; 188 byptr = addrel (baseptr (fixed (scud.wd0.psr, 18)), fixed (scud.wd4.ict, 18)); 189 if ^tsrpr then 190 refptr = addrel (baseptr (fixed (scud.wd2.tsr, 18)), fixed (scud.wd5.ca, 18)); 191 call ioa_ ("^a: ^p ^a", at_by_wd, byptr, 192 bce_segptr_to_name_ (byptr)); 193 if ^tsrpr then /* if we want to print out tsr|ca */ 194 call ioa_ ("Referencing: ^p ^a", refptr, 195 bce_segptr_to_name_ (refptr)); 196 call ioa_ ("On: cpu ^a (#^o)", cpul (fixed (scud.wd2.cpu, 3)), 197 fixed (scud.wd2.cpu, 3)); 198 flt_ln = ""; 199 byptr = addr (scud.wd4); /* display Indicator register if any bits present */ 200 do i = lbound (indrs, 1) to hbound (indrs, 1); 201 if fltdtab (i) then 202 call ioa_$rsnnl ("^a ^a,", flt_ln, j, flt_ln, indrs (i)); 203 end; 204 if flt_ln ^= "" then do; 205 substr (flt_ln, j, 1) = " "; 206 call ioa_ ("Indicators: ^a", flt_ln); 207 flt_ln = ""; 208 end; 209 byptr = addr (scud.wd0); /* display interpreted APU status if any bits present */ 210 do i = lbound (APU, 1) to hbound (APU, 1); 211 if fltdtab (i) then 212 call ioa_$rsnnl ("^a ^a,", flt_ln, j, flt_ln, APU (i)); 213 end; 214 if flt_ln ^= "" then do; 215 substr (flt_ln, j, 1) = " "; 216 call ioa_ ("APU Status: ^a", flt_ln); 217 flt_ln = ""; 218 end; 219 byptr = addr (scud.wd5); /* display interprted CU status if any bits present */ 220 do i = lbound (CU, 1) to hbound (CU, 1); 221 if fltdtab (i) then 222 call ioa_$rsnnl ("^a ^a,", flt_ln, j, flt_ln, CU (i)); 223 end; 224 225 TAG_ptr = addr (TAG_table); 226 i = fixed (wd5.ct_hold); 227 228 if i ^= 0 then do; 229 tag_ = TAG.code (i+1); 230 tag_prt = "1"b; 231 end; 232 233 if (flt_ln ^= "") | (tag_ ^= "") then do; 234 substr (flt_ln, j, 1) = " "; 235 call ioa_ ("CU Status: ^a ^[^/CT Hold: ^a^]", 236 flt_ln, tag_prt, tag_); 237 end; 238 239 240 call ioa_ ("Instructions: "); /* display Instructions (words 6 & 7) */ 241 call bce_display_instruction_ (addr (scud.wd6), (1), reoffset + 6); 242 call bce_display_instruction_ (addr (scud.wd7), (1), reoffset + 7); 243 244 /* */ 245 246 end bce_display_scu_; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/11/89 0826.6 bce_display_scu_.pl1 >special_ldd>install>MR12.3-1114>bce_display_scu_.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. APU 001226 constant varying char(6) initial array dcl 78 set ref 210 210 211* CU 001176 constant varying char(3) initial array dcl 82 set ref 220 220 221* TAG based structure array level 1 packed packed unaligned dcl 127 TAG_ptr 000160 automatic pointer dcl 113 set ref 225* 229 TAG_table 000164 automatic char(40) initial array packed unaligned dcl 116 set ref 116* 116* 116* 116* 116* 116* 116* 116* 225 a_offset parameter fixed bin(26,0) dcl 19 ref 8 134 addr builtin function dcl 29 ref 199 209 219 225 241 241 242 242 addrel builtin function dcl 29 ref 152 188 189 at_by_wd 000156 automatic char(2) packed unaligned dcl 34 set ref 186* 187* 191* baseptr builtin function dcl 29 ref 188 189 bce_display_instruction_ 000014 constant entry external dcl 36 ref 241 242 bce_segptr_to_name_ 000016 constant entry external dcl 37 ref 191 193 byptr 000100 automatic pointer dcl 21 set ref 152* 153 172 188* 191* 191* 199* 201 209* 211 219* 221 ca 5 based bit(18) level 3 packed packed unaligned dcl 40 set ref 189 code based char(4) array level 2 packed packed unaligned dcl 127 ref 229 cpu 2(27) based bit(3) level 3 packed packed unaligned dcl 40 ref 196 196 196 cpul 001620 constant char(1) initial array packed unaligned dcl 33 set ref 196* ct_hold 5(30) based bit(6) level 3 packed packed unaligned dcl 40 set ref 226 cv_bin_$oct 000020 constant entry external dcl 38 ref 167 cvbinbuf 000153 automatic char(12) packed unaligned dcl 31 set ref 167* 168 fi 1(30) based bit(6) level 3 packed packed unaligned dcl 40 ref 146 147 147 150 157 166 fixed builtin function dcl 29 ref 146 147 147 150 166 183 183 183 188 188 189 189 196 196 196 226 flt_bf 000143 automatic varying char(24) dcl 27 set ref 144* 146* 147 151 flt_int_typ 000000 constant varying char(24) initial array dcl 102 ref 146 150 flt_ln 000112 automatic char(100) packed unaligned dcl 26 set ref 144* 151* 154* 162* 168* 173 173 173* 173* 177* 177* 180* 198* 201* 201* 204 205* 206* 207* 211* 211* 214 215* 216* 217* 221* 221* 233 234* 235* flt_lng 000105 automatic fixed bin(17,0) dcl 22 set ref 150* 151 151 154 155 162 163 166* 167* fltdtab based bit(1) array packed unaligned dcl 32 ref 153 172 201 211 221 g1and7flts 001175 constant bit(6) initial array packed unaligned dcl 85 ref 156 157 grp1flt 000761 constant varying char(24) initial array dcl 88 set ref 171 177* grp2flt 000700 constant varying char(24) initial array dcl 97 set ref 173* hbound builtin function dcl 29 ref 156 171 200 210 220 i 000107 automatic fixed bin(17,0) dcl 22 set ref 156* 157* 171* 172 173 173 177* 200* 201 201* 210* 211 211* 220* 221 221* 226* 228 229 ict 4 based bit(18) level 3 packed packed unaligned dcl 40 set ref 188 ill_act 001337 constant varying char(37) initial array dcl 68 set ref 183* ill_act_lns 1(20) based bit(4) level 3 packed packed unaligned dcl 40 ref 182 183 183 183 indrs 001303 constant varying char(4) initial array dcl 75 set ref 200 200 201* inst6 000106 automatic fixed bin(17,0) dcl 22 set ref 141* ioa_ 000010 constant entry external dcl 35 ref 138 142 147 180 183 191 193 196 206 216 235 240 ioa_$rsnnl 000012 constant entry external dcl 35 ref 173 177 201 211 221 j 000110 automatic fixed bin(17,0) dcl 22 set ref 170* 173* 177* 201* 205 211* 215 221* 234 lbound builtin function dcl 29 ref 200 210 220 length builtin function dcl 29 ref 150 lg_sw parameter bit(1) packed unaligned dcl 20 ref 8 142 lnpos 000104 automatic fixed bin(17,0) dcl 22 set ref 155* 163* 168 169* 169 170 psr 0(03) based bit(15) level 3 packed packed unaligned dcl 40 set ref 136 188 refptr 000102 automatic pointer dcl 21 set ref 189* 193* 193* reoffset 000111 automatic fixed bin(26,0) dcl 23 set ref 134* 141 142* 241 242 scud based structure level 1 dcl 40 scup parameter pointer dcl 18 ref 8 136 136 142 146 147 147 150 152 157 166 182 183 183 183 188 188 189 189 196 196 196 199 209 219 226 241 241 242 242 substr builtin function dcl 29 set ref 147 151* 151 154* 162* 168* 168 173 173 205* 215* 234* tag_ 000163 automatic char(4) initial packed unaligned dcl 115 set ref 115* 229* 233 235* tag_prt 000162 automatic bit(1) initial packed unaligned dcl 114 set ref 114* 230* 235* tsr 2(03) based bit(15) level 3 packed packed unaligned dcl 40 ref 136 189 tsrpr 000152 automatic bit(1) packed unaligned dcl 30 set ref 145* 157* 164* 186 189 193 w based fixed bin(17,0) array dcl 25 set ref 142* wd0 based structure level 2 packed packed unaligned dcl 40 set ref 209 wd1 1 based structure level 2 packed packed unaligned dcl 40 wd2 2 based structure level 2 packed packed unaligned dcl 40 wd4 4 based structure level 2 packed packed unaligned dcl 40 set ref 199 wd5 5 based structure level 2 packed packed unaligned dcl 40 set ref 219 wd6 6 based fixed bin(35,0) level 2 dcl 40 set ref 241 241 wd7 7 based fixed bin(35,0) level 2 dcl 40 set ref 242 242 NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. code automatic fixed bin(35,0) dcl 24 iocbp automatic pointer dcl 28 null builtin function dcl 29 on_line automatic bit(1) packed unaligned dcl 30 strp automatic pointer dcl 21 NAME DECLARED BY EXPLICIT CONTEXT. bce_display_scu_ 002123 constant entry external dcl 8 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 3700 3722 3610 3710 Length 4120 3610 22 161 70 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME bce_display_scu_ 270 external procedure is an external procedure. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME bce_display_scu_ 000100 byptr bce_display_scu_ 000102 refptr bce_display_scu_ 000104 lnpos bce_display_scu_ 000105 flt_lng bce_display_scu_ 000106 inst6 bce_display_scu_ 000107 i bce_display_scu_ 000110 j bce_display_scu_ 000111 reoffset bce_display_scu_ 000112 flt_ln bce_display_scu_ 000143 flt_bf bce_display_scu_ 000152 tsrpr bce_display_scu_ 000153 cvbinbuf bce_display_scu_ 000156 at_by_wd bce_display_scu_ 000160 TAG_ptr bce_display_scu_ 000162 tag_prt bce_display_scu_ 000163 tag_ bce_display_scu_ 000164 TAG_table bce_display_scu_ THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out_desc call_ext_out return_mac shorten_stack ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. bce_display_instruction_ bce_segptr_to_name_ cv_bin_$oct ioa_ ioa_$rsnnl NO EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 8 002117 114 002130 115 002131 116 002133 134 002224 136 002227 138 002237 139 002255 141 002256 142 002260 144 002310 145 002314 146 002315 147 002334 150 002365 151 002367 152 002372 153 002374 154 002400 155 002403 156 002405 157 002413 159 002426 160 002430 162 002431 163 002434 164 002436 166 002440 167 002446 168 002457 169 002473 170 002475 171 002477 172 002503 173 002510 176 002557 177 002560 179 002614 180 002616 182 002635 183 002644 186 002676 187 002703 188 002705 189 002722 191 002742 193 003010 196 003054 198 003121 199 003124 200 003131 201 003137 203 003200 204 003202 205 003206 206 003212 207 003235 209 003240 210 003244 211 003251 213 003312 214 003314 215 003320 216 003324 217 003347 219 003352 220 003357 221 003365 223 003426 225 003430 226 003432 228 003440 229 003442 230 003446 233 003450 234 003461 235 003465 240 003515 241 003534 242 003561 246 003606 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved