COMPILATION LISTING OF SEGMENT bce_esd Compiled by: Multics PL/I Compiler, Release 32f, of October 9, 1989 Compiled at: Bull HN, Phoenix AZ, System-M Compiled on: 11/11/89 1014.9 mst Sat Options: optimize map 1 /****^ *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Bull Inc., 1987 * 4* * * 5* * Copyright, (C) Honeywell Information Systems Inc., 1984 * 6* * * 7* *********************************************************** */ 8 9 10 /****^ HISTORY COMMENTS: 11* 1) change(87-02-26,Farley), approve(87-04-15,MCR7661), 12* audit(87-04-21,Fawcett), install(87-04-28,MR12.1-1028): 13* Added check for fgbx.io_reconfig that is turned on whenever an I/O 14* reconfiguration can cause memory to be corrupted. Thus no emergency 15* shutdown should be attempted, because it would only propagate the 16* corruption. 17* END HISTORY COMMENTS */ 18 19 20 bce_esd: proc (info_ptr); 21 22 /* Routine to modify machine conditions so as to invoke esd. 23*Written August 1983 by Keith Loepere. */ 24 /* format: style4,indattr,ifthenstmt,ifthen,idind33,^indcomtxt */ 25 26 dcl bce_continue entry (ptr); 27 dcl com_err_ entry options (variable); 28 dcl emergency_shutdown$ entry; 29 dcl info_ptr ptr parameter; 30 dcl 1 toehold$ aligned external like toe_hold; 31 dcl (addr, bin, bit, codeptr, segno, string, wordno) builtin; 32 /* BEGIN include file collection_1_phases.incl.pl1 */ 1 2 1 3 /* Symbolic names for the various collection1 phases. 1 4*Keith Loepere, October 1983. */ 1 5 1 6 /* format: style4,indattr,ifthenstmt,ifthen,idind33,^indcomtxt */ 1 7 1 8 dcl sys_info$collection_1_phase fixed bin external static; 1 9 1 10 dcl EARLY_INITIALIZATION fixed bin init (1) static options (constant); /* phase to find the config deck */ 1 11 dcl BOOT_INITIALIZATION fixed bin init (2) static options (constant); /* phase to setup up crash handler, bce */ 1 12 dcl SERVICE_INITIALIZATION fixed bin init (3) static options (constant); /* phase to set up for service */ 1 13 1 14 /* These first 3 (EARLY, BOOT and SERVICE) must be 1, 2, 3 in that order so 1 15*programs can simply tell apart the booting phases from all others (crash or 1 16*recovery type phases). */ 1 17 1 18 dcl CRASH_INITIALIZATION fixed bin init (4) static options (constant); /* phase to set up bce after crash/shut down */ 1 19 dcl RE_EARLY_INITIALIZATION fixed bin init (5) static options (constant); /* retry boot initialization given safe config to a new early level */ 1 20 dcl BCE_CRASH_INITIALIZATION fixed bin init (6) static options (constant); /* retry boot initialization to give a new boot level given a crash of bce */ 1 21 dcl SHUT_INITIALIZATION fixed bin init (7) static options (constant); /* same as boot but don't load new disk mpcs */ 1 22 1 23 dcl COLLECTION_1_PHASE_NAMES (7) char (16) unal static options (constant) init 1 24 ("early", "boot", "service", "crash", "re_early", "bce_crash", "shut"); 1 25 1 26 /* END include file collection_1_phases.incl.pl1 */ 32 33 /* BEGIN INCLUDE FILE ... flagbox.incl.pl1 */ 2 2 2 3 2 4 /****^ HISTORY COMMENTS: 2 5* 1) change(87-02-26,Farley), approve(87-04-15,MCR7661), 2 6* audit(87-04-21,Fawcett), install(87-04-28,MR12.1-1028): 2 7* Added io_reconfig flag to inhibit BCE from attempting an emergency 2 8* shutdown when the data in memory could be corrupted. 2 9* END HISTORY COMMENTS */ 2 10 2 11 2 12 /* last modified 5/3/77 by Noel I. Morris */ 2 13 /* Modified 8/79 by R.J.C. Kissel to add FNP blast message. */ 2 14 /* Modified 7/82 BIM for recognizable sentinel field */ 2 15 /* Modified for bootload Multics flagbox starting in 8/83 by Keith Loepere. */ 2 16 2 17 /* The contents of this segment are data shared by Multics and bce. 2 18* This entity occupies the locations within the toehold starting at 40o 2 19* (not counting the toehold_used spacer at the beginning). */ 2 20 2 21 dcl flagbox$ ext; 2 22 dcl fgbxp ptr; 2 23 2 24 dcl 1 fgbx based (fgbxp) aligned, 2 25 2 toehold_used (32) bit (36) aligned, /* flagbox seg now mapped onto all of first page of toehold - 2 26* This is what was unused before. */ 2 27 2 flags (36) bit (1) unal, /* communications switches */ 2 28 2 slt_segno bit (18), /* segment # of the SLT */ 2 29 2 pad1 fixed bin, 2 30 2 rtb, /* return to bce info */ 2 31 (3 ssenb bit (1), /* "1"b if storage system enabled */ 2 32 3 call_bce bit (1), /* "1"b if bce called by operator */ 2 33 3 shut bit (1), /* "1"b if bce called after shutdown */ 2 34 3 mess bit (1), /* "1"b if message has been provided */ 2 35 3 alert bit (1), /* "1"b if audible alarm to be sounded */ 2 36 3 breakpoint bit (1), /* "1"b is breakpoint caused call to bce */ 2 37 3 manual_crash bit (1), /* either manual entry or execute fault */ 2 38 3 io_reconfig bit (1), /* "1"b if I/O reconfiguration */ 2 39 /* could cause memory corruption */ 2 40 3 pad bit (21), 2 41 3 bce_entry fixed bin (6) uns) unal, /* type of entry into bce 2 42* 00o => Multics entry 2 43* 20o => manual entry 2 44* 40o => esd entry */ 2 45 2 sentinel char (32) aligned, /* set by bce (for now) */ 2 46 2 sst_sdw bit (72), /* set by init_sst */ 2 47 2 hc_dbr bit (72), /* set by start_cpu, idle DBR */ 2 48 2 message char (64), /* message for return to bce */ 2 49 2 return_to_bce_command char (128) unal; /* command to run upon crash/shutdown */ 2 50 2 51 declare FLAGBOX_SENTINEL char (32) init ("Flagbox & Toehold Valid") int static options (constant); 2 52 2 53 /* END INCLUDE FILE ... flagbox.incl.pl1 */ 33 34 /* BEGIN include file toehold.incl.pl1 */ 3 2 3 3 /* Various reserved entrypoints into the bce toehold. 3 4*Also, only those things one really needs to know about the toehold. 3 5*Keith Loepere, October 1983. */ 3 6 3 7 /* Exclude prn, prv and pad when converting to alm version. */ 3 8 3 9 /* format: style4,indattr,ifthenstmt,ifthen,idind33,^indcomtxt */ 3 10 3 11 dcl 1 toe_hold aligned based, /* name so alm likes */ 3 12 2 entry_sequences (0:15) bit (72) aligned, /* described below */ 3 13 2 flagbox (64) bit (36) aligned, 3 14 2 pad1 (48) bit (36) aligned, 3 15 2 paths (4) like io_path, 3 16 2 n_paths_used fixed bin, 3 17 2 memory_state fixed bin, /* of memory/disk swapping, etc. */ 3 18 2 bce_dbr bit (72) aligned, /* of bce */ 3 19 2 pad2 (1355) bit (36) aligned, 3 20 2 multics_state aligned like mc_state; 3 21 3 22 dcl 1 io_path aligned based, 3 23 2 pcw fixed bin (71) aligned, 3 24 3 25 2 port_number fixed bin (3) uns unal, /* these fields form the word that */ 3 26 2 iom_number fixed bin (15) uns unal, /* must be changed upon */ 3 27 2 channel_number fixed bin unal, /* reconfiguration of channels */ 3 28 3 29 2 pad bit (36) aligned; 3 30 3 31 dcl TOE_HOLD_CRASH_ENTRY fixed bin init (0) static options (constant); /* operator causes crash by xed'ind here */ 3 32 dcl TOE_HOLD_ESD_ENTRY fixed bin init (1) static options (constant); 3 33 dcl TOE_HOLD_DUMP_ENTRY fixed bin init (2) static options (constant); /* place that causes an early dump */ 3 34 dcl TOE_HOLD_MULTICS_ENTRY fixed bin init (3) static options (constant); /* Multics crashes by drl'ing here */ 3 35 dcl TOE_HOLD_RESTART_ENTRY fixed bin init (4) static options (constant); /* bce restarts Multics by drl'ing here */ 3 36 dcl TOE_HOLD_BOOT_ENTRY fixed bin init (5) static options (constant); /* bootload_tape_label starts init by tra'ing here */ 3 37 dcl TOE_HOLD_BOS_ENTRY fixed bin init (12) static options (constant); 3 38 dcl TOE_HOLD_BOS_NO_SAVE_ENTRY fixed bin init (13) static options (constant); 3 39 dcl TOE_HOLD_BOS_MULTICS_ENTRY fixed bin init (14) static options (constant); 3 40 3 41 declare mc_state_ptr ptr; /* to toehold$.multics_state */ 3 42 declare 1 mc_state aligned based (mc_state_ptr), 3 43 2 mc_ aligned like mc, 3 44 2 masks (16) bit (36) aligned, 3 45 2 interrupt bit (72) aligned, 3 46 2 mode_reg bit (36) aligned, /* mode_reg and cache_mode_reg form a double word pair */ 3 47 2 cache_mode_reg bit (36) aligned, 3 48 2 dbr bit (72) aligned, 3 49 2 cfg bit (72) aligned, 3 50 2 bar bit (36) aligned, 3 51 2 old_memory_state fixed bin, 3 52 2 pad16 (6) bit (36) aligned, 3 53 2 ou_history_registers (0: 15) bit (72) aligned, 3 54 2 cu_history_registers (0: 15) bit (72) aligned, 3 55 2 du_history_registers (0: 15) bit (72) aligned, 3 56 2 apu_history_registers (0: 15) bit (72) aligned, 3 57 2 ptwam_ptrs (0: 63) bit (36) aligned, /* word alignment (mod 16, 32) of these am's matters */ 3 58 2 ptwam_regs (0: 63) bit (36) aligned, 3 59 2 sdwam_ptrs (0: 63) bit (36) aligned, 3 60 2 sdwam_regs (0: 63) bit (72) aligned; 3 61 3 62 /* values for memory_state */ 3 63 3 64 dcl Initial_undefined fixed bin init (0) static options (constant); /* initial coming to bce */ 3 65 dcl At_bce__early fixed bin init (1) static options (constant); 3 66 dcl At_bce__boot fixed bin init (2) static options (constant); /* at bce during cool boot phase */ 3 67 dcl Multics fixed bin init (3) static options (constant); /* Multics coming up */ 3 68 dcl Undefined_saving_state fixed bin init (4) static options (constant); /* saving state during coming down */ 3 69 dcl Undefined_reading_bce fixed bin init (5) static options (constant); /* reading in bce */ 3 70 dcl At_bce__crash fixed bin init (6) static options (constant); /* disk holds Multics, at bce */ 3 71 dcl At_bce__shutdown fixed bin init (7) static options (constant); /* disk holds (nothing), coming to bce */ 3 72 dcl Undefined_continue fixed bin init (8) static options (constant); /* swapping memory back */ 3 73 dcl Undefined_saving_mem fixed bin init (9) static options (constant); 3 74 3 75 /* */ 4 2 /* BEGIN INCLUDE FILE mc.incl.pl1 Created Dec 72 for 6180 - WSS. */ 4 3 /* Modified 06/07/76 by Greenberg for mc.resignal */ 4 4 /* Modified 07/07/76 by Morris for fault register data */ 4 5 /* Modified 08/28/80 by J. A. Bush for the DPS8/70M CVPU */ 4 6 /* Modified '82 to make values constant */ 4 7 4 8 /* words 0-15 pointer registers */ 4 9 4 10 dcl mcp ptr; 4 11 4 12 dcl 1 mc based (mcp) aligned, 4 13 2 prs (0:7) ptr, /* POINTER REGISTERS */ 4 14 (2 regs, /* registers */ 4 15 3 x (0:7) bit (18), /* index registers */ 4 16 3 a bit (36), /* accumulator */ 4 17 3 q bit (36), /* q-register */ 4 18 3 e bit (8), /* exponent */ 4 19 3 pad1 bit (28), 4 20 3 t bit (27), /* timer register */ 4 21 3 pad2 bit (6), 4 22 3 ralr bit (3), /* ring alarm register */ 4 23 4 24 2 scu (0:7) bit (36), 4 25 4 26 2 mask bit (72), /* mem controller mask at time of fault */ 4 27 2 ips_temp bit (36), /* Temporary storage for IPS info */ 4 28 2 errcode fixed bin (35), /* fault handler's error code */ 4 29 2 fim_temp, 4 30 3 unique_index bit (18) unal, /* unique index for restarting faults */ 4 31 3 resignal bit (1) unal, /* recompute signal name with fcode below */ 4 32 3 fcode bit (17) unal, /* fault code used as index to FIM table and SCT */ 4 33 2 fault_reg bit (36), /* fault register */ 4 34 2 pad2 bit (1), 4 35 2 cpu_type fixed bin (2) unsigned, /* L68 = 0, DPS8/70M = 1 */ 4 36 2 ext_fault_reg bit (15), /* extended fault reg for DPS8/70M CPU */ 4 37 2 fault_time bit (54), /* time of fault */ 4 38 4 39 2 eis_info (0:7) bit (36)) unaligned; 4 40 4 41 4 42 dcl (apx fixed bin init (0), 4 43 abx fixed bin init (1), 4 44 bpx fixed bin init (2), 4 45 bbx fixed bin init (3), 4 46 lpx fixed bin init (4), 4 47 lbx fixed bin init (5), 4 48 spx fixed bin init (6), 4 49 sbx fixed bin init (7)) internal static options (constant); 4 50 4 51 4 52 4 53 4 54 dcl scup ptr; 4 55 4 56 dcl 1 scu based (scup) aligned, /* SCU DATA */ 4 57 4 58 4 59 /* WORD (0) */ 4 60 4 61 (2 ppr, /* PROCEDURE POINTER REGISTER */ 4 62 3 prr bit (3), /* procedure ring register */ 4 63 3 psr bit (15), /* procedure segment register */ 4 64 3 p bit (1), /* procedure privileged bit */ 4 65 4 66 2 apu, /* APPENDING UNIT STATUS */ 4 67 3 xsf bit (1), /* ext seg flag - IT modification */ 4 68 3 sdwm bit (1), /* match in SDW Ass. Mem. */ 4 69 3 sd_on bit (1), /* SDW Ass. Mem. ON */ 4 70 3 ptwm bit (1), /* match in PTW Ass. Mem. */ 4 71 3 pt_on bit (1), /* PTW Ass. Mem. ON */ 4 72 3 pi_ap bit (1), /* Instr Fetch or Append cycle */ 4 73 3 dsptw bit (1), /* Fetch of DSPTW */ 4 74 3 sdwnp bit (1), /* Fetch of SDW non paged */ 4 75 3 sdwp bit (1), /* Fetch of SDW paged */ 4 76 3 ptw bit (1), /* Fetch of PTW */ 4 77 3 ptw2 bit (1), /* Fetch of pre-paged PTW */ 4 78 3 fap bit (1), /* Fetch of final address paged */ 4 79 3 fanp bit (1), /* Fetch of final address non-paged */ 4 80 3 fabs bit (1), /* Fetch of final address absolute */ 4 81 4 82 2 fault_cntr bit (3), /* number of retrys of EIS instructions */ 4 83 4 84 4 85 /* WORD (1) */ 4 86 4 87 2 fd, /* FAULT DATA */ 4 88 3 iro bit (1), /* illegal ring order */ 4 89 3 oeb bit (1), /* out of execute bracket */ 4 90 3 e_off bit (1), /* no execute */ 4 91 3 orb bit (1), /* out of read bracket */ 4 92 3 r_off bit (1), /* no read */ 4 93 3 owb bit (1), /* out of write bracket */ 4 94 3 w_off bit (1), /* no write */ 4 95 3 no_ga bit (1), /* not a gate */ 4 96 3 ocb bit (1), /* out of call bracket */ 4 97 3 ocall bit (1), /* outward call */ 4 98 3 boc bit (1), /* bad outward call */ 4 99 3 inret bit (1), /* inward return */ 4 100 3 crt bit (1), /* cross ring transfer */ 4 101 3 ralr bit (1), /* ring alarm register */ 4 102 3 am_er bit (1), /* associative memory fault */ 4 103 3 oosb bit (1), /* out of segment bounds */ 4 104 3 paru bit (1), /* processor parity upper */ 4 105 3 parl bit (1), /* processor parity lower */ 4 106 3 onc_1 bit (1), /* op not complete type 1 */ 4 107 3 onc_2 bit (1), /* op not complete type 2 */ 4 108 4 109 2 port_stat, /* PORT STATUS */ 4 110 3 ial bit (4), /* illegal action lines */ 4 111 3 iac bit (3), /* illegal action channel */ 4 112 3 con_chan bit (3), /* connect channel */ 4 113 4 114 2 fi_num bit (5), /* (fault/interrupt) number */ 4 115 2 fi_flag bit (1), /* 1 => fault, 0 => interrupt */ 4 116 4 117 4 118 /* WORD (2) */ 4 119 4 120 2 tpr, /* TEMPORARY POINTER REGISTER */ 4 121 3 trr bit (3), /* temporary ring register */ 4 122 3 tsr bit (15), /* temporary segment register */ 4 123 4 124 2 pad2 bit (9), 4 125 4 126 2 cpu_no bit (3), /* CPU number */ 4 127 4 128 2 delta bit (6), /* tally modification DELTA */ 4 129 4 130 4 131 /* WORD (3) */ 4 132 4 133 2 word3 bit (18), 4 134 4 135 2 tsr_stat, /* TSR STATUS for 1,2,&3 word instructions */ 4 136 3 tsna, /* Word 1 status */ 4 137 4 prn bit (3), /* Word 1 PR number */ 4 138 4 prv bit (1), /* Word 1 PR valid bit */ 4 139 3 tsnb, /* Word 2 status */ 4 140 4 prn bit (3), /* Word 2 PR number */ 4 141 4 prv bit (1), /* Word 2 PR valid bit */ 4 142 3 tsnc, /* Word 3 status */ 4 143 4 prn bit (3), /* Word 3 PR number */ 4 144 4 prv bit (1), /* Word 3 PR valid bit */ 4 145 4 146 2 tpr_tbr bit (6), /* TPR.TBR field */ 4 147 4 148 4 149 /* WORD (4) */ 4 150 4 151 2 ilc bit (18), /* INSTRUCTION COUNTER */ 4 152 4 153 2 ir, /* INDICATOR REGISTERS */ 4 154 3 zero bit (1), /* zero indicator */ 4 155 3 neg bit (1), /* negative indicator */ 4 156 3 carry bit (1), /* carryry indicator */ 4 157 3 ovfl bit (1), /* overflow indicator */ 4 158 3 eovf bit (1), /* eponent overflow */ 4 159 3 eufl bit (1), /* exponent underflow */ 4 160 3 oflm bit (1), /* overflow mask */ 4 161 3 tro bit (1), /* tally runout */ 4 162 3 par bit (1), /* parity error */ 4 163 3 parm bit (1), /* parity mask */ 4 164 3 bm bit (1), /* ^bar mode */ 4 165 3 tru bit (1), /* truncation mode */ 4 166 3 mif bit (1), /* multi-word instruction mode */ 4 167 3 abs bit (1), /* absolute mode */ 4 168 3 hex bit (1), /* hexadecimal exponent mode */ 4 169 3 pad bit (3), 4 170 4 171 4 172 /* WORD (5) */ 4 173 4 174 2 ca bit (18), /* COMPUTED ADDRESS */ 4 175 4 176 2 cu, /* CONTROL UNIT STATUS */ 4 177 3 rf bit (1), /* on first cycle of repeat instr */ 4 178 3 rpt bit (1), /* repeat instruction */ 4 179 3 rd bit (1), /* repeat double instruction */ 4 180 3 rl bit (1), /* repeat link instruciton */ 4 181 3 pot bit (1), /* IT modification */ 4 182 3 pon bit (1), /* return type instruction */ 4 183 3 xde bit (1), /* XDE from Even location */ 4 184 3 xdo bit (1), /* XDE from Odd location */ 4 185 3 poa bit (1), /* operation preparation */ 4 186 3 rfi bit (1), /* tells CPU to refetch instruction */ 4 187 3 its bit (1), /* ITS modification */ 4 188 3 if bit (1), /* fault occured during instruction fetch */ 4 189 4 190 2 cpu_tag bit (6)) unaligned, /* computed tag field */ 4 191 4 192 4 193 /* WORDS (6,7) */ 4 194 4 195 2 even_inst bit (36), /* even instruction of faulting pair */ 4 196 4 197 2 odd_inst bit (36); /* odd instruction of faulting pair */ 4 198 4 199 4 200 4 201 4 202 4 203 4 204 /* ALTERNATE SCU DECLARATION */ 4 205 4 206 4 207 dcl 1 scux based (scup) aligned, 4 208 4 209 (2 pad0 bit (36), 4 210 4 211 2 fd, /* GROUP II FAULT DATA */ 4 212 3 isn bit (1), /* illegal segment number */ 4 213 3 ioc bit (1), /* illegal op code */ 4 214 3 ia_am bit (1), /* illegal address - modifier */ 4 215 3 isp bit (1), /* illegal slave procedure */ 4 216 3 ipr bit (1), /* illegal procedure */ 4 217 3 nea bit (1), /* non existent address */ 4 218 3 oobb bit (1), /* out of bounds */ 4 219 3 pad bit (29), 4 220 4 221 2 pad2 bit (36), 4 222 4 223 2 pad3a bit (18), 4 224 4 225 2 tsr_stat (0:2), /* TSR STATUS as an ARRAY */ 4 226 3 prn bit (3), /* PR number */ 4 227 3 prv bit (1), /* PR valid bit */ 4 228 4 229 2 pad3b bit (6)) unaligned, 4 230 4 231 2 pad45 (0:1) bit (36), 4 232 4 233 2 instr (0:1) bit (36); /* Instruction ARRAY */ 4 234 4 235 4 236 4 237 /* END INCLUDE FILE mc.incl.pl1 */ 3 75 3 76 3 77 /* END include file toehold.incl.pl1 */ 34 35 36 fgbxp = addr (flagbox$); 37 if ^fgbx.ssenb then do; 38 call com_err_ (0, "esd", "Storage system not enabled. esd not performed."); 39 return; 40 end; 41 42 if fgbx.io_reconfig then do; 43 call com_err_ (0, "esd", "Emergency shutdown is prohibited due to possible memory corruption."); 44 sys_info$collection_1_phase = BOOT_INITIALIZATION; 45 toehold$.memory_state = At_bce__boot; 46 return; 47 end; 48 49 mc_state_ptr = addr (toehold$.multics_state); 50 mcp = addr (mc_state.mc_); 51 scup = addr (mc.scu); 52 scu.ppr.prr = "000"b; 53 scu.ppr.psr = bit (bin (segno (codeptr (emergency_shutdown$)), 15), 15); 54 scu.ppr.p = "1"b; 55 string (scu.apu) = "0"b; 56 scu.fault_cntr = "0"b; 57 58 scu.ilc = bit (bin (wordno (codeptr (emergency_shutdown$)), 18), 18); 59 string (scu.ir) = "0"b; 60 scu.ir.bm = "1"b; 61 62 mc_state.interrupt = "0"b; 63 mc_state.cfg = "0"b; 64 65 call bce_continue (info_ptr); /* won't return */ 66 end; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/11/89 0839.1 bce_esd.pl1 >special_ldd>install>MR12.3-1114>bce_esd.pl1 32 1 07/11/84 0937.3 collection_1_phases.incl.pl1 >ldd>include>collection_1_phases.incl.pl1 33 2 04/30/87 1513.7 flagbox.incl.pl1 >ldd>include>flagbox.incl.pl1 34 3 07/11/84 0937.3 toe_hold.incl.pl1 >ldd>include>toe_hold.incl.pl1 3-75 4 12/15/83 1100.4 mc.incl.pl1 >ldd>include>mc.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. At_bce__boot constant fixed bin(17,0) initial dcl 3-66 ref 45 BOOT_INITIALIZATION constant fixed bin(17,0) initial dcl 1-11 ref 44 addr builtin function dcl 31 ref 36 49 50 51 apu 0(19) based structure level 2 packed packed unaligned dcl 4-56 set ref 55* bce_continue 000010 constant entry external dcl 26 ref 65 bin builtin function dcl 31 ref 53 58 bit builtin function dcl 31 ref 53 58 bm 4(28) based bit(1) level 3 packed packed unaligned dcl 4-56 set ref 60* cfg 106 based bit(72) level 2 dcl 3-42 set ref 63* codeptr builtin function dcl 31 ref 53 58 com_err_ 000012 constant entry external dcl 27 ref 38 43 emergency_shutdown$ 000014 constant entry external dcl 28 ref 53 58 fault_cntr 0(33) based bit(3) level 2 packed packed unaligned dcl 4-56 set ref 56* fgbx based structure level 1 dcl 2-24 fgbxp 000100 automatic pointer dcl 2-22 set ref 36* 37 42 flagbox$ 000022 external static fixed bin(17,0) dcl 2-21 set ref 36 ilc 4 based bit(18) level 2 packed packed unaligned dcl 4-56 set ref 58* info_ptr parameter pointer dcl 29 set ref 20 65* interrupt 100 based bit(72) level 2 dcl 3-42 set ref 62* io_path based structure level 1 dcl 3-22 io_reconfig 43(07) based bit(1) level 3 packed packed unaligned dcl 2-24 ref 42 ir 4(18) based structure level 2 packed packed unaligned dcl 4-56 set ref 59* mc based structure level 1 dcl 4-12 mc_ based structure level 2 dcl 3-42 set ref 50 mc_state based structure level 1 dcl 3-42 mc_state_ptr 000102 automatic pointer dcl 3-41 set ref 49* 50 62 63 mcp 000104 automatic pointer dcl 4-10 set ref 50* 51 memory_state 241 000016 external static fixed bin(17,0) level 2 dcl 30 set ref 45* multics_state 2760 000016 external static structure level 2 dcl 30 set ref 49 p 0(18) based bit(1) level 3 packed packed unaligned dcl 4-56 set ref 54* ppr based structure level 2 packed packed unaligned dcl 4-56 prr based bit(3) level 3 packed packed unaligned dcl 4-56 set ref 52* psr 0(03) based bit(15) level 3 packed packed unaligned dcl 4-56 set ref 53* rtb 43 based structure level 2 dcl 2-24 scu 30 based bit(36) array level 2 in structure "mc" packed packed unaligned dcl 4-12 in procedure "bce_esd" set ref 51 scu based structure level 1 dcl 4-56 in procedure "bce_esd" scup 000106 automatic pointer dcl 4-54 set ref 51* 52 53 54 55 56 58 59 60 segno builtin function dcl 31 ref 53 ssenb 43 based bit(1) level 3 packed packed unaligned dcl 2-24 ref 37 string builtin function dcl 31 set ref 55* 59* sys_info$collection_1_phase 000020 external static fixed bin(17,0) dcl 1-8 set ref 44* toe_hold based structure level 1 dcl 3-11 toehold$ 000016 external static structure level 1 dcl 30 wordno builtin function dcl 31 ref 58 NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. At_bce__crash internal static fixed bin(17,0) initial dcl 3-70 At_bce__early internal static fixed bin(17,0) initial dcl 3-65 At_bce__shutdown internal static fixed bin(17,0) initial dcl 3-71 BCE_CRASH_INITIALIZATION internal static fixed bin(17,0) initial dcl 1-20 COLLECTION_1_PHASE_NAMES internal static char(16) initial array packed unaligned dcl 1-23 CRASH_INITIALIZATION internal static fixed bin(17,0) initial dcl 1-18 EARLY_INITIALIZATION internal static fixed bin(17,0) initial dcl 1-10 FLAGBOX_SENTINEL internal static char(32) initial packed unaligned dcl 2-51 Initial_undefined internal static fixed bin(17,0) initial dcl 3-64 Multics internal static fixed bin(17,0) initial dcl 3-67 RE_EARLY_INITIALIZATION internal static fixed bin(17,0) initial dcl 1-19 SERVICE_INITIALIZATION internal static fixed bin(17,0) initial dcl 1-12 SHUT_INITIALIZATION internal static fixed bin(17,0) initial dcl 1-21 TOE_HOLD_BOOT_ENTRY internal static fixed bin(17,0) initial dcl 3-36 TOE_HOLD_BOS_ENTRY internal static fixed bin(17,0) initial dcl 3-37 TOE_HOLD_BOS_MULTICS_ENTRY internal static fixed bin(17,0) initial dcl 3-39 TOE_HOLD_BOS_NO_SAVE_ENTRY internal static fixed bin(17,0) initial dcl 3-38 TOE_HOLD_CRASH_ENTRY internal static fixed bin(17,0) initial dcl 3-31 TOE_HOLD_DUMP_ENTRY internal static fixed bin(17,0) initial dcl 3-33 TOE_HOLD_ESD_ENTRY internal static fixed bin(17,0) initial dcl 3-32 TOE_HOLD_MULTICS_ENTRY internal static fixed bin(17,0) initial dcl 3-34 TOE_HOLD_RESTART_ENTRY internal static fixed bin(17,0) initial dcl 3-35 Undefined_continue internal static fixed bin(17,0) initial dcl 3-72 Undefined_reading_bce internal static fixed bin(17,0) initial dcl 3-69 Undefined_saving_mem internal static fixed bin(17,0) initial dcl 3-73 Undefined_saving_state internal static fixed bin(17,0) initial dcl 3-68 abx internal static fixed bin(17,0) initial dcl 4-42 apx internal static fixed bin(17,0) initial dcl 4-42 bbx internal static fixed bin(17,0) initial dcl 4-42 bpx internal static fixed bin(17,0) initial dcl 4-42 lbx internal static fixed bin(17,0) initial dcl 4-42 lpx internal static fixed bin(17,0) initial dcl 4-42 sbx internal static fixed bin(17,0) initial dcl 4-42 scux based structure level 1 dcl 4-207 spx internal static fixed bin(17,0) initial dcl 4-42 NAME DECLARED BY EXPLICIT CONTEXT. bce_esd 000050 constant entry external dcl 20 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 336 362 241 346 Length 616 241 24 217 75 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME bce_esd 117 external procedure is an external procedure. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME bce_esd 000100 fgbxp bce_esd 000102 mc_state_ptr bce_esd 000104 mcp bce_esd 000106 scup bce_esd THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out_desc call_ext_out return_mac ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. bce_continue com_err_ emergency_shutdown$ THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. flagbox$ sys_info$collection_1_phase toehold$ LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 20 000045 36 000055 37 000057 38 000062 39 000110 42 000111 43 000114 44 000142 45 000145 46 000150 49 000151 50 000154 51 000156 52 000160 53 000162 54 000177 55 000201 56 000203 58 000205 59 000215 60 000217 62 000221 63 000224 65 000226 66 000235 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved