ASSEMBLY LISTING OF SEGMENT >spec>install>1112>cache_priv.alm ASSEMBLED ON: 11/11/89 0925.0 mst Sat OPTIONS USED: -target l68 list symbols ASSEMBLED BY: ALM Version 8.14 March 1989 ASSEMBLER CREATED: 06/09/89 1002.3 mst Fri 1 " *********************************************************** 2 " * * 3 " * Copyright, (C) Honeywell Bull Inc., 1987 * 4 " * * 5 " * Copyright, (C) Honeywell Information Systems Inc., 1984 * 6 " * * 7 " * Copyright, (C) Honeywell Information Systems Inc., 1982 * 8 " * * 9 " * Copyright (c) 1972 by Massachusetts Institute of * 10 " * Technology and Honeywell Information Systems, Inc. * 11 " * * 12 " *********************************************************** 13 14 " 15 " cache_priv - privileged subroutine to perform static test of cache memory. 16 " Called from pl1 procedure cache_tester. 17 " 18 " Entry description: 19 " 20 " dcl cache_priv$csh1 (csh2) entry (ptr, fixed bin, ptr, fixed bin (35)); 21 " call cache_priv$csh1 (csh2) (wired_buf_ptr, buf_size, info_ptr, code); 22 " 23 " where: 24 " 25 " 1. wired_buf_ptr - is a ptr to a wired encachable buffer. It is assumed that the 26 " wired buffer has been filled with the desired test data pattern, by the caller. 27 " 28 " 2. buf_size - is the buffer size in words. It should be one half the cache size. 29 " 30 " 3. info_ptr - is a ptr to a wired info structure which is a 3 element array of 31 " error/diagnostic info. The structure array elements are defined below. The data 32 " from the first 3 errors encountered is stored in the info structure. 33 " 34 " 4. code - is an indication of the existance of a cache error, and is also the 35 " count of the number of errors encounterd. 36 " 37 " The cache_priv$csh1 entry is to test the lower half of cache memory defined by 38 " the program settable switch "csh1" in the cache mode register. The 39 " cache_priv$csh2 entry is to test the upper half of cache memory defined by the 40 " program settable switch "csh2" in the cache mode register. 41 " 42 " Original coding by J. A. Bush 1/15/80 43 " Modified by J. A. Bush 6/20/80 to not inhibit so long 44 " 45 " Modified by R. A. Fawcett June 1984 to handle: 46 " 1. Original type of DPS8M 8K cache 47 " 2. VSSC cache for 8K 16K and 32K configs 48 " 3. And do the same things for all types of CACHE including L68 2K. 49 " After the above changes Bush would not recognize this program. 50 " 000000 51 name cache_priv 000000 52 entry csh1 000004 53 entry csh2 54 55 tempd maskwd,ptwp,arglist(7) arguments for calls 56 tempd temp_fault_reg temp storage for fault reg 57 tempd cam_wait 58 temp buf_length storage for cache buffer length 59 temp temp_ind_reg temp storage for ind reg 60 temp timer temp storage for the timer register 61 temp not_me 62 " The next equs are for the cpriv_info.err_data array in cache_tester. 63 " They are based on the bb indexed by x4 and there are 3 possible error sets. 64 000000 65 equ cache_data,0 error data in cache 000002 66 equ ex_or_data,2 exclusive or of error data in memory and cache 000004 67 equ fault_reg,4 storage for fault register 000006 68 equ cache_addr,6 storage for error address in cache 000007 69 equ ind_reg,7 storage for indicator register 70 71 001000 72 bool par_err,1000 parity indicator 000400 73 bool par_mask,400 parity mask indicator 74 75 000000 76 csh1: 77 "**** entry to test lower half of cache *** 000000 aa 000120 6270 00 78 push 000001 aa 7 00040 2721 20 000002 aa 000000 6230 00 79 eax3 0 set cache on constant to csh1 000003 0a 000007 7100 00 80 tra c_com 81 82 000004 83 csh2: 84 "**** entry to test upper half of cache *** 000004 aa 000120 6270 00 85 push 000005 aa 7 00040 2721 20 000006 aa 000001 6230 00 86 eax3 1 set cache on constant to csh2 87 000007 88 c_com: 000007 aa 0 00002 3521 20 89 eppbp ap|2,* get cache buf ptr 000010 aa 2 00000 3521 20 90 eppbp bp|0,* 000011 aa 0 00006 3535 20 91 eppbb ap|6,* get com region address 000012 aa 3 00000 3535 20 92 eppbb bb|0,* 93 000013 aa 0 00004 7271 20 94 lxl7 ap|4,* get buffer size in words 000014 aa 6 00076 7471 00 95 stx7 buf_length and save for comparisons 000015 aa 000000 6350 17 96 eaa 0,x7 calc clear time based on cache size 000016 aa 000003 7710 00 97 arl 3 000017 aa 000000 6240 01 98 eax4 0,au initialize csh_on wait count 000020 aa 000000 6260 00 99 eax6 0 start at address 0 of buffer 100 101 000021 4a 4 00014 3715 20 102 epplb page$cam_wait 000022 aa 6 00074 6515 00 103 sprilb cam_wait 104 000023 aa 6 00050 3715 00 105 epplb maskwd " mask so that no interups are taken 000024 aa 6 00056 6515 00 106 sprilb arglist+2 000025 aa 6 00052 3715 00 107 epplb ptwp 000026 aa 6 00060 6515 00 108 sprilb arglist+4 000027 0a 000174 2370 00 109 ldaq TWO_ARGS_ND 000030 aa 6 00054 7571 00 110 staq arglist 000031 aa 6 00000 2541 00 111 call pmut$wire_and_mask(arglist) 000032 aa 6 00054 3501 00 000033 4a 4 00010 3521 20 000034 aa 6 00040 7531 00 000035 aa 7 00036 6701 20 000036 aa 6 00000 1731 00 000037 aa 6 00040 0731 00 112 000040 aa 000400 6340 07 113 ldi par_mask,dl don't take parity fault 114 000041 aa 6 00100 4541 00 115 stt timer save the current timer 000042 0a 000176 6370 00 116 ldt TIMER set timer for 4min + (no fault) 117 118 000043 119 prev_connects: 000043 aa 6 00052 3715 00 120 epplb ptwp 000044 aa 6 00056 6515 00 121 sprilb arglist+2 000045 0a 000172 2370 00 122 ldaq ONE_ARG_ND 000046 aa 6 00054 7571 00 123 staq arglist cause other cpus to loop unitl 000047 aa 6 00000 2541 00 124 call cam_wait,*(arglist) cache is loaded 000050 aa 6 00054 3501 00 000051 aa 6 00074 3521 20 000052 aa 6 00040 7531 00 000053 aa 7 00036 6701 20 000054 aa 6 00000 1731 00 000055 aa 6 00040 0731 00 125 000056 126 clear_cache: 127 000056 0a 000166 6740 02 128 lcpr csh_off,02 insure that cache is OFF 000057 0a 000162 7160 13 129 xec csh_on,3 turn appropriate cache segment on 000060 aa 777777 6240 14 130 eax4 -1,4 wait for cache hardware initialization 000061 aa 000000 0110 03 131 nop 0,du 000062 0a 000060 6010 00 132 tnz *-2 error counter (x4) is 0 on loop exit 133 000063 134 l_loop: 000063 aa 2 00000 2371 16 135 ldaq bp|0,6 fill cache by referencing wired buffer 000064 aa 000004 6260 16 136 eax6 4,6 increment to next block address 000065 aa 777774 6270 17 137 eax7 -4,7 decrement block count 000066 0a 000063 6010 00 138 tnz l_loop xfer if not full 000067 0a 000166 6740 02 139 lcpr csh_off,02 now turn cache off 140 000070 4a 4 00016 4501 20 141 stz scs$cam_wait trun others lose 142 000071 143 set_up_check: 000071 aa 000000 6340 07 144 ldi 0,dl initialize indicator reg 000072 aa 000000 6260 00 145 eax6 0 all done initialize buffer index 000073 aa 000001 1030 03 146 cmpx3 1,du are we testing upper cache memory? 000074 0a 000076 6010 00 147 tnz c_loop xfer if no, x7 has address 0 (start of lower cache) 000075 aa 6 00076 2271 00 148 ldx7 buf_length yes set cache read address to upper half 149 000076 150 c_loop: 000076 151 inhibit on 000076 aa 000400 6342 07 152 ldi par_mask,dl don't take parity fault here!!! 000077 0a 000170 6742 02 153 lcpr cache_to_reg_mode,02 000100 aa 2 00000 2373 17 154 ldaq bp|0,7 load data from cache 000101 0a 000166 6742 02 155 lcpr csh_off,02 turn reg mode off 000102 156 inhibit off 000102 aa 6 00077 7541 00 157 sti temp_ind_reg save indicator reg 000103 aa 000000 6340 07 158 ldi 0,dl and initialize 159 000104 aa 2 00000 1171 16 160 cmpaq bp|0,6 data in cache equal to data in mem? 000105 0a 000110 6000 00 161 tze par_chk xfer if yes 000106 0a 000166 1170 00 162 cmpaq csh_off data in cache = csh_off constant? 000107 0a 000142 6010 00 163 tnz cmp_err xfer if no 164 000110 165 par_chk: 000110 aa 6 00077 7251 00 166 lxl5 temp_ind_reg but did we have a parity error? 000111 aa 001000 3050 03 167 canx5 par_err,du 000112 0a 000142 6010 00 168 tnz cmp_err xfer if yes 169 000113 170 err_cont: 000113 aa 000002 6270 17 171 eax7 2,7 increment cache address 000114 aa 000002 6260 16 172 eax6 2,6 increment memory address 000115 aa 6 00076 1061 00 173 cmpx6 buf_length last cache addr looked at 000116 0a 000076 6040 00 174 tmi c_loop xfer if no 000117 aa 000000 6340 07 175 ldi 0,dl yes, reset parity mask 000120 aa 000000 6350 14 176 eaa 0,4 copy error index to a 000121 aa 000025 7710 00 177 arl 18+3 right justify and get real error count 000122 aa 0 00010 7551 20 178 sta ap|8,* and store in error code 179 180 000123 aa 6 00050 3715 00 181 epplb maskwd now we can unmask 000124 aa 6 00056 6515 00 182 sprilb arglist+2 000125 aa 6 00052 3715 00 183 epplb ptwp 000126 aa 6 00060 6515 00 184 sprilb arglist+4 000127 0a 000174 2370 00 185 ldaq TWO_ARGS_ND 000130 aa 6 00054 7571 00 186 staq arglist 000131 aa 6 00000 2541 00 187 call pmut$unwire_unmask(arglist) unmask 000132 aa 6 00054 3501 00 000133 4a 4 00012 3521 20 000134 aa 6 00040 7531 00 000135 aa 7 00036 6701 20 000136 aa 6 00000 1731 00 000137 aa 6 00040 0731 00 188 000140 aa 6 00100 6371 00 189 ldt timer restore_timer 000141 aa 7 00042 7101 20 190 return all done this half 191 000142 192 cmp_err: 193 000142 aa 000030 1040 03 194 cmpx4 24,du do we have 3 errors already? 000143 0a 000146 6040 00 195 tmi capture no, go capture error data 000144 aa 000010 6240 14 196 eax4 8,4 yes, just add 1 more to error count 000145 0a 000113 7100 00 197 tra err_cont and go loop trough rest of cache 198 000146 199 capture: 000146 aa 6 00072 4521 01 200 scpr temp_fault_reg,01 compare/parity error, save fault reg 000147 aa 3 00000 7571 14 201 staq bb|cache_data,4 save cache data 000150 aa 2 00000 6771 16 202 eraq bp|0,6 exclusive or cache and memory data 000151 aa 3 00002 7571 14 203 staq bb|ex_or_data,4 000152 aa 6 00077 7251 00 204 lxl5 temp_ind_reg but did we have a parity error? 000153 aa 001000 3650 03 205 anx5 par_err,du 000154 aa 3 00007 4451 14 206 sxl5 bb|ind_reg,4 save indicator reg of error 000155 aa 6 00072 2351 00 207 lda temp_fault_reg save fault reg 000156 aa 3 00004 7551 14 208 sta bb|fault_reg,4 000157 aa 3 00006 4471 14 209 sxl7 bb|cache_addr,4 save cache address in error 000160 aa 000010 6240 14 210 eax4 8,4 add 1 more to error count 000161 0a 000113 7100 00 211 tra err_cont and go loop trough rest of cache 212 000162 213 inhibit on 214 even 000162 0a 000164 6742 02 215 csh_on: lcpr csh1_on,02 turn csh1 on with xec instruction 000163 0a 000165 6742 02 216 lcpr csh2_on,02 turn csh2 on with xec instruction 000164 217 inhibit off 218 000164 aa 000000 500003 219 csh1_on: oct 500003 csh1 and operands on 000165 aa 000000 300003 220 csh2_on: oct 300003 csh2 and operands on 221 222 even 000166 aa 000000 000003 223 csh_off: oct 3 000167 aa 707070 707070 224 oct 707070707070 pattern to ignore csh_off constant 225 000170 226 cache_to_reg_mode: 000170 aa 000000 010003 227 oct 10003 cache dump mode 228 000171 aa 000000 0110 03 229 even 000172 230 ONE_ARG_ND: 000172 aa 000002 000002 231 zero 2,2 000173 aa 000000 000000 232 zero 0,0 000174 233 TWO_ARGS_ND: 000174 aa 000004 000004 234 zero 4,4 000175 aa 000000 000000 235 zero 0,0 236 000176 aa 777777 777777 237 TIMER: oct 777777777777 238 end ENTRY SEQUENCES 000177 5a 000016 0000 00 000200 aa 7 00046 2721 20 000201 0a 000000 7100 00 000202 5a 000011 0000 00 000203 aa 7 00046 2721 20 000204 0a 000004 7100 00 NO LITERALS NAME DEFINITIONS FOR ENTRY POINTS AND SEGDEFS 000206 5a 000003 000000 000207 5a 000032 600000 000210 aa 000000 000000 000211 55 000011 000002 000212 5a 000002 400003 000213 55 000006 000011 000214 aa 012 143 141 143 000215 aa 150 145 137 160 000216 aa 162 151 166 000 000217 55 000016 000003 000220 0a 000203 500000 000221 55 000014 000003 000222 aa 004 143 163 150 csh2 000223 aa 062 000 000 000 000224 55 000023 000011 000225 0a 000200 500000 000226 55 000021 000003 000227 aa 004 143 163 150 csh1 000230 aa 061 000 000 000 000231 55 000002 000016 000232 6a 000000 400002 000233 55 000026 000003 000234 aa 014 163 171 155 symbol_table 000235 aa 142 157 154 137 000236 aa 164 141 142 154 000237 aa 145 000 000 000 DEFINITIONS HASH TABLE 000240 aa 000000 000015 000241 aa 000000 000000 000242 5a 000011 000000 000243 5a 000016 000000 000244 aa 000000 000000 000245 aa 000000 000000 000246 aa 000000 000000 000247 5a 000023 000000 000250 aa 000000 000000 000251 aa 000000 000000 000252 aa 000000 000000 000253 aa 000000 000000 000254 aa 000000 000000 000255 aa 000000 000000 EXTERNAL NAMES 000256 aa 003 163 143 163 scs 000257 aa 010 143 141 155 cam_wait 000260 aa 137 167 141 151 000261 aa 164 000 000 000 000262 aa 004 160 141 147 page 000263 aa 145 000 000 000 000264 aa 015 165 156 167 unwire_unmask 000265 aa 151 162 145 137 000266 aa 165 156 155 141 000267 aa 163 153 000 000 000270 aa 015 167 151 162 wire_and_mask 000271 aa 145 137 141 156 000272 aa 144 137 155 141 000273 aa 163 153 000 000 000274 aa 004 160 155 165 pmut 000275 aa 164 000 000 000 NO TRAP POINTER WORDS TYPE PAIR BLOCKS 000276 aa 000004 000000 000277 55 000050 000051 000300 aa 000004 000000 000301 55 000054 000051 000302 aa 000004 000000 000303 55 000066 000056 000304 aa 000004 000000 000305 55 000066 000062 000306 aa 000001 000000 000307 aa 000000 000000 INTERNAL EXPRESSION WORDS 000310 5a 000070 000000 000311 5a 000072 000000 000312 5a 000074 000000 000313 5a 000076 000000 LINKAGE INFORMATION 000000 aa 000000 000000 000001 0a 000206 000000 000002 aa 000000 000000 000003 aa 000000 000000 000004 aa 000000 000000 000005 aa 000000 000000 000006 22 000010 000020 000007 a2 000000 000000 000010 9a 777770 0000 46 pmut|wire_and_mask 000011 5a 000105 0000 00 000012 9a 777766 0000 46 pmut|unwire_unmask 000013 5a 000104 0000 00 000014 9a 777764 0000 46 page|cam_wait 000015 5a 000103 0000 00 000016 9a 777762 0000 46 scs|cam_wait 000017 5a 000102 0000 00 SYMBOL INFORMATION SYMBOL TABLE HEADER 000000 aa 000000 000001 000001 aa 163171 155142 000002 aa 164162 145145 000003 aa 000000 000010 000004 aa 000000 117244 000005 aa 361023 525721 000006 aa 000000 117547 000007 aa 242436 347562 000010 aa 141154 155040 000011 aa 040040 040040 000012 aa 000024 000040 000013 aa 000034 000040 000014 aa 000044 000100 000015 aa 000002 000002 000016 aa 000064 000000 000017 aa 000000 000145 000020 aa 000000 000103 000021 aa 000125 000120 000022 aa 000137 000103 000023 aa 000064 000000 000024 aa 101114 115040 000025 aa 126145 162163 000026 aa 151157 156040 000027 aa 070056 061064 000030 aa 040115 141162 000031 aa 143150 040061 000032 aa 071070 071040 000033 aa 040040 040040 000034 aa 110151 162156 000035 aa 145151 163145 000036 aa 156056 123171 000037 aa 163115 141151 000040 aa 156164 056141 000041 aa 040040 040040 000042 aa 040040 040040 000043 aa 040040 040040 000044 aa 055164 141162 000045 aa 147145 164040 000046 aa 154066 070040 000047 aa 040040 040040 000050 aa 040040 040040 000051 aa 040040 040040 000052 aa 040040 040040 000053 aa 040040 040040 000054 aa 040040 040040 000055 aa 040040 040040 000056 aa 040154 151163 000057 aa 164040 163171 000060 aa 155142 157154 000061 aa 163040 040040 000062 aa 040040 040040 000063 aa 040040 040040 000064 aa 000000 000001 000065 aa 000000 000001 000066 aa 000072 000041 000067 aa 175453 021163 000070 aa 000000 117547 000071 aa 210577 200000 000072 aa 076163 160145 >spec>install>1112>cache_priv.alm 000073 aa 143076 151156 000074 aa 163164 141154 000075 aa 154076 061061 000076 aa 061062 076143 000077 aa 141143 150145 000100 aa 137160 162151 000101 aa 166056 141154 000102 aa 155040 040040 MULTICS ASSEMBLY CROSS REFERENCE LISTING Value Symbol Source file Line number 54 arglist cache_priv: 55, 106, 108, 110, 111, 121, 123, 124, 182, 184, 186, 187. 76 buf_length cache_priv: 58, 95, 148, 173. 6 cache_addr cache_priv: 68, 209. 0 cache_data cache_priv: 65, 201. 170 cache_to_reg_mode cache_priv: 153, 226. 74 cam_wait cache_priv: 57, 102, 103, 124, 141. 146 capture cache_priv: 195, 199. 56 clear_cache cache_priv: 126. 142 cmp_err cache_priv: 163, 168, 192. 0 csh1 cache_priv: 52, 76. 164 csh1_on cache_priv: 215, 219. 4 csh2 cache_priv: 53, 83. 165 csh2_on cache_priv: 216, 220. 166 csh_off cache_priv: 128, 139, 155, 162, 223. 162 csh_on cache_priv: 129, 215. 7 c_com cache_priv: 80, 88. 76 c_loop cache_priv: 147, 150, 174. 113 err_cont cache_priv: 170, 197, 211. 2 ex_or_data cache_priv: 66, 203. 4 fault_reg cache_priv: 67, 208. 7 ind_reg cache_priv: 69, 206. 63 l_loop cache_priv: 134, 138. 50 maskwd cache_priv: 55, 105, 181. 101 not_me cache_priv: 61. 172 ONE_ARG_ND cache_priv: 122, 230. page cache_priv: 102. 110 par_chk cache_priv: 161, 165. 1000 par_err cache_priv: 72, 167, 205. 400 par_mask cache_priv: 73, 113, 152. pmut cache_priv: 111, 187. 43 prev_connects cache_priv: 119. 52 ptwp cache_priv: 55, 107, 120, 183. scs cache_priv: 141. 71 set_up_check cache_priv: 143. 72 temp_fault_reg cache_priv: 56, 200, 207. 77 temp_ind_reg cache_priv: 59, 157, 166, 204. 176 TIMER cache_priv: 116, 237. 100 timer cache_priv: 60, 115, 189. 174 TWO_ARGS_ND cache_priv: 109, 185, 233. unwire_unmask cache_priv: 187. wire_and_mask cache_priv: 111. NO FATAL ERRORS ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved