COMPILATION LISTING OF SEGMENT freecore Compiled by: Multics PL/I Compiler, Release 32f, of October 9, 1989 Compiled at: Bull HN, Phoenix AZ, System-M Compiled on: 11/11/89 1028.2 mst Sat Options: optimize map 1 /****^ *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Bull Inc., 1987 * 4* * * 5* * Copyright, (C) Honeywell Information Systems Inc., 1984 * 6* * * 7* * Copyright (c) 1972 by Massachusetts Institute of * 8* * Technology and Honeywell Information Systems, Inc. * 9* * * 10* *********************************************************** */ 11 12 /* This is an procedure to add a block of free core to the used list. 13* This is called during initialization and reconfiguration 14* Modified 3/2/76 by Noel I. Morris for new reconfig 15* Modified 6/21/82 by E. N. Kittlitz to move core map. 16* Modified 4/11/84 by Keith Loepere for thread entrypoint. 17* Modified 1985-03-11, BIM: call check_parity_for_add. */ 18 19 freecore: proc (page_no); 20 21 dcl page_no fixed bin, /* number of the page being added */ 22 page fixed bin, /* copy of page number */ 23 code fixed bin (35), 24 saved_mask fixed bin (71), /* saved interrupt mask */ 25 stk_ptwp ptr, /* pointer to wired stack page page table word */ 26 usedptr ptr; /* pointer to first entry on used list */ 27 28 dcl pmut$lock_ptl entry (fixed bin (71), ptr), 29 syserr entry options (variable), 30 pmut$check_parity_for_add entry (fixed bin, fixed bin (35)), 31 pmut$unlock_ptl entry (fixed bin (71), ptr), 32 wire_proc$wire_me entry, 33 wire_proc$unwire_me entry; 34 35 dcl (addr, bin, ptr, rel) builtin; 36 37 dcl sst$cmp ptr ext; 38 dcl sst$first_core_block fixed bin ext; 39 dcl sst$last_core_block fixed bin ext; 40 dcl sst$nused fixed bin ext; 41 dcl sst$usedp bit (18) ext; 42 dcl sst$wusedp bit (18) aligned ext; 43 /* BEGIN INCLUDE FILE scs.incl.pl1 ... March 1983 */ 1 2 /* format: style4 */ 1 3 1 4 /* Information about system controllers */ 1 5 1 6 dcl 1 scs$controller_data (0:7) aligned ext, /* per-controller info */ 1 7 2 size fixed bin (17) unaligned, /* size (in 1024 word blocks) of this controller */ 1 8 2 base fixed bin (17) unaligned, /* abs address (0 mod 1024) for base of this controller */ 1 9 2 eima_data (4) unaligned, /* EIMA information for this controller */ 1 10 3 mask_available bit (1) unaligned, /* ON if corresponding mask exists */ 1 11 3 mask_assigned bit (1) unaligned, /* ON if mask assigned to a port */ 1 12 3 mbz bit (3) unaligned, 1 13 3 mask_assignment fixed bin (3) unaligned, /* port to which mask is assigned */ 1 14 2 info aligned, 1 15 3 online bit (1) unaligned, /* ON if controller is online */ 1 16 3 offline bit (1) unaligned, /* ON if controller is offline but can be added */ 1 17 3 store_a_online bit (1) unaligned, /* ON if store A is online */ 1 18 3 store_a1_online bit (1) unaligned, /* ON if store A1 is online */ 1 19 3 store_b_online bit (1) unaligned, /* ON if store B is online */ 1 20 3 store_b1_online bit (1) unaligned, /* ON if store B1 is online */ 1 21 3 store_b_is_lower bit (1) unaligned, /* ON if store B is lower */ 1 22 3 ext_interlaced bit (1) unaligned, /* ON if this SCU is interlaced with other SCU */ 1 23 3 int_interlaced bit (1) unaligned, /* ON if this SCU is internally interlaced */ 1 24 3 four_word bit (1) unaligned, /* ON if external interlace is 4-word */ 1 25 3 cyclic_priority (7) bit (1) unaligned, /* Cyclic priority for adjacent ports */ 1 26 3 type bit (4) unaligned, /* Model number for this controller */ 1 27 3 abs_wired bit (1) unaligned, /* ON if controller can have abs_wired pages */ 1 28 3 program bit (1) unaligned, /* PROGRAM/MANUAL switch setting */ 1 29 3 mbz bit (13) unaligned, 1 30 2 lower_store_size fixed bin (17) unaligned, /* size (in 1024 word blocks) of lower store */ 1 31 2 upper_store_size fixed bin (17) unaligned; /* size (in 1024 word blocks) of upper store */ 1 32 1 33 /* Information about CPUs */ 1 34 1 35 dcl 1 scs$processor_data (0:7) aligned ext, /* information about CPUs in the system */ 1 36 ( 1 37 2 online bit (1), /* "1"b if CPU is online */ 1 38 2 offline bit (1), /* "1"b if CPU is offline but can be added */ 1 39 2 release_mask bit (1), /* "1"b is this CPU is to give up its mask */ 1 40 2 accept_mask bit (1), /* "1"b if this CPU is to grap mask in idle loop */ 1 41 2 delete_cpu bit (1), /* "1"b if this CPU is to delete itself */ 1 42 2 interrupt_cpu bit (1), /* "1"b if this CPU takes hardware interrupts */ 1 43 2 halted_cpu bit (1), /* "1"b if this CPU has stopped itself (going to BOS) */ 1 44 2 cpu_type fixed bin (2) unsigned, /* 0 => DPS or L68, 1 => DPS8 */ 1 45 2 mbz1 bit (6), 1 46 2 cache_size fixed bin (3) unsigned, /* 0 = No cache; 1 = L68 2K cache; 1 47* 2 = DPS8 8K cache; 3 = DPS8 VS&SC 8K cache; 1 48* 4 = DPS8 VS&SC 16K cache; 5 = DPS8 VS&SC 32K cache 1 49* 7 = ignore cache size (set by ISOLTS reconfig) */ 1 50 2 mbz2 bit (12), 1 51 2 expanded_port bit (1), /* "1"b = on expanded port */ 1 52 2 expander_port fixed bin (2) unsigned, /* The actual expander port */ 1 53 2 controller_port fixed bin (3) unsigned 1 54 ) unaligned; /* Port on controller */ 1 55 1 56 dcl 1 scs$port_data (0:7) aligned external static, /* Info about what is connected to each SCU port */ 1 57 2 assigned fixed bin (4) unsigned unaligned, /* Type of device on this port */ 1 58 2 expander_port bit (1) unaligned, /* "1"b => this port has a port expander */ 1 59 2 expanded_cpu (0:3) bit (1) unaligned, /* "1"b => this expander port has a CPU attached */ 1 60 2 iom_number fixed bin (3) unsigned unaligned, /* IOM number of IOM attached to this port */ 1 61 2 cpu_number (0:3) fixed bin (3) unsigned unaligned, /* CPU number of CPU(s) attached to this port */ 1 62 /* cpu_number (0) is only one if expander_port is "0"b */ 1 63 2 pad bit (12) unaligned; 1 64 1 65 dcl 1 scs$cow (0:7) aligned external, /* Actual connect words */ 1 66 2 pad bit (36) aligned, /* Expander COW's must be odd-word */ 1 67 2 cow, 1 68 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 1 69 3 mbz1 bit (13) unaligned, 1 70 3 expander_command bit (3) unaligned, /* Expander command. */ 1 71 3 mbz2 bit (2) unaligned, 1 72 3 expanded_port bit (1) unaligned, /* "1"b = on expanded port */ 1 73 3 expander_port fixed bin (3) unsigned unaligned, /* Port on expander for cioc */ 1 74 3 mbz3 bit (3) unaligned, 1 75 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 1 76 1 77 dcl 1 scs$cow_ptrs (0:7) external aligned, /* Pointers to COW's */ 1 78 2 rel_cow_ptr bit (18) unal, /* Relative pointer to COW */ 1 79 2 pad bit (12) unal, 1 80 2 tag bit (6) unal; /* Better be zero. */ 1 81 1 82 dcl 1 scs$reconfig_general_cow aligned external, /* Used during reconfig ops. */ 1 83 2 pad bit (36) aligned, 1 84 2 cow, /* Connect operand word, in odd location. */ 1 85 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 1 86 3 mbz1 bit (13) unaligned, 1 87 3 expander_command bit (3) unaligned, /* Expander command. */ 1 88 3 mbz2 bit (9) unaligned, 1 89 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 1 90 1 91 /* MASKS and PATTERNS */ 1 92 1 93 dcl scs$sys_level bit (72) aligned ext; /* mask used while handling I/O interrupts */ 1 94 dcl scs$open_level bit (72) aligned ext; /* mask used during normal operation */ 1 95 dcl scs$processor_start_mask bit (72) aligned ext; /* mask used when starting up a CPU */ 1 96 dcl scs$cpu_test_mask bit (72) aligned ext; /* mask used for ISOLTS CPU testing */ 1 97 dcl scs$number_of_masks fixed bin ext; /* number of masks (starting at sys_level) */ 1 98 dcl scs$processor_start_pattern bit (36) aligned ext; /* SMIC pattern used to send processor start interrupt */ 1 99 dcl scs$cpu_test_pattern bit (36) aligned ext; /* SMIC pattern used for ISOLTS processor testing */ 1 100 1 101 /* CAM and CACHE clear info */ 1 102 1 103 dcl scs$cam_pair fixed bin (71) ext; /* instructions XEDd when CAMing and clearing CACHE */ 1 104 dcl scs$cam_wait bit (8) aligned ext; /* Used when evicting pages from main memory */ 1 105 1 106 /* MASKING INSTRUCTIONS & POINTERS */ 1 107 1 108 dcl scs$set_mask (0:7) bit (36) aligned ext; /* instructions to set mask (STAQ or SMCM) */ 1 109 dcl scs$read_mask (0:7) bit (36) aligned ext; /* instructions to read mask (LDAQ or RMCM) */ 1 110 dcl scs$mask_ptr (0:7) ptr unaligned ext; /* pointers for real or simulated masks */ 1 111 1 112 /* MISCELLANEOUS */ 1 113 1 114 dcl 1 scs$processor_test_data aligned ext, /* info used for cpu testing */ 1 115 ( 1 116 2 active bit (1), /* = "1"b if cpu currently under test */ 1 117 2 scu_state bit (2), /* state of scu being used for testing (see definition below) */ 1 118 2 pad1 bit (4), 1 119 2 req_mem fixed bin (10), /* dedicated memory required to test this cpu */ 1 120 2 cpu_tag fixed bin (5), /* tag of cpu under test */ 1 121 2 scu_tag fixed bin (5), /* tag of scu being used for cpu testing */ 1 122 2 mask_cpu fixed bin (5) 1 123 ) unaligned; /* tag of active cpu that has mask asigned to above scu */ 1 124 1 125 /* scu_state = "00"b => SCU defined by scs$processor_test_data.scu_tag not yet effected */ 1 126 /* scu_state = "01"b => all core removed from SCU, port mask not yet changed */ 1 127 /* scu_state = "10"b => all core removed from SCU, port mask changed */ 1 128 /* scu_state = "11"b => only 64k at base of SCU being used for testing, original port mask restored */ 1 129 1 130 dcl scs$idle_aptep (0:7) ptr unaligned ext; /* pointer to idle process APTE for each processor */ 1 131 1 132 dcl scs$connect_lock bit (36) aligned ext; /* lock for sending connects */ 1 133 dcl scs$reconfig_lock bit (36) aligned ext; /* Lock used during reconfiguration */ 1 134 dcl scs$trouble_flags bit (8) aligned ext; /* checkoff flags for sys_trouble stopping */ 1 135 dcl scs$bos_restart_flags bit (8) aligned ext; /* checkoff flags for restarting after sys_trouble */ 1 136 dcl scs$nprocessors fixed bin ext; /* number of runnung processors */ 1 137 dcl scs$bos_processor_tag fixed bin (3) ext; /* CPU tag of processor running BOS */ 1 138 dcl scs$faults_initialized bit (1) aligned ext; /* ON after faults have been enabled */ 1 139 dcl scs$sys_trouble_pending bit (1) aligned ext; /* sys_trouble event is pending in the system */ 1 140 dcl scs$fast_cam_pending (0:7) bit (36) aligned ext; /* checkoff cells for cam connect */ 1 141 dcl scs$interrupt_controller fixed bin (3) ext; /* port number of low order controller */ 1 142 dcl scs$processor_start_int_no fixed bin (5) ext; /* interrupt cell for starting a processor */ 1 143 dcl scs$processor bit (8) aligned ext; /* bits ON for online CPUs */ 1 144 dcl scs$processor_start_wait bit (8) aligned ext; /* checkoff flags for waiting for new processor */ 1 145 1 146 dcl scs$trouble_dbrs (0:7) fixed bin (71); /* DBR values at system crash time */ 1 147 1 148 dcl scs$port_addressing_word (0:7) bit (3) aligned ext; /* active module port number for each controller */ 1 149 1 150 dcl scs$cfg_data (0:7) fixed bin (71) aligned ext; /* RSCR-CFG data from each controller */ 1 151 1 152 dcl scs$cfg_data_save fixed bin (71) aligned ext; /* RSCR-CFG save area for ISOLTS CPU testing */ 1 153 1 154 dcl scs$expanded_ports bit (1) unaligned dim (0:7) external; 1 155 /* Which ports have expanders */ 1 156 1 157 dcl scs$processor_switch_data (0:4) bit (36) aligned ext; /* raw data from RSW 0 thru 4 */ 1 158 dcl scs$processor_switch_template (0:4) bit (36) aligned ext; /* expected data from RSW 0 thru 4 */ 1 159 dcl scs$processor_switch_compare (0:4) bit (36) aligned ext; /* discrepancies from expected data */ 1 160 dcl scs$processor_switch_mask (0:4) bit (36) aligned ext; /* masks for comparing switch data */ 1 161 1 162 dcl scs$processor_data_switch_value bit (36) aligned ext; /* Correct value for CPU data switches */ 1 163 1 164 dcl scs$controller_config_size (0:7) fixed bin (14) aligned ext; 1 165 /* Controller size on config card */ 1 166 1 167 dcl scs$reconfig_locker_id char (32) aligned ext; /* process group ID of process doing reconfiguration */ 1 168 1 169 dcl scs$scas_page_table (0:31) bit (36) aligned external static; 1 170 /* PTWs for SCAS pages */ 1 171 1 172 dcl scs$cycle_priority_template bit (7) aligned ext; /* template for setting anti-hog switches */ 1 173 dcl scs$set_cycle_switches bit (1) aligned ext; /* flag to set ant-hog switches */ 1 174 1 175 1 176 dcl ( 1 177 IOM_PORT init (1), 1 178 CPU_PORT init (2), 1 179 BULK_PORT init (3) 1 180 ) fixed bin int static options (constant); /* values for scs$port_data.assigned */ 1 181 1 182 1 183 /* END INCLUDE FILE scs.incl.pl1 */ 43 44 /* BEGIN INCLUDE FILE cmp.incl.pl1 --- October 1982 */ 2 2 /* Note: This include file has an ALM counterpart NOT made with cif (for historical reasons). Keep it up to date */ 2 3 2 4 dcl cmep ptr; /* pointer to core map entry */ 2 5 2 6 dcl 1 cme based (cmep) aligned, /* core map entry */ 2 7 2 fp bit (18) unaligned, /* forward pointer to next entry */ 2 8 2 bp bit (18) unaligned, /* backward pointer to previous entry */ 2 9 2 10 2 devadd bit (22) unaligned, /* device address of page in the core block */ 2 11 2 pad5 bit (1) unaligned, 2 12 2 synch_held bit (1) unaligned, /* Page of synchronized seg held in memory */ 2 13 2 io bit (1) unaligned, /* input/output indicator 1=output, 0=input */ 2 14 2 pad2 bit (1) unaligned, 2 15 2 er bit (1) unaligned, /* indicates error in previous IO activity */ 2 16 2 removing bit (1) unaligned, /* core is being removed by reconfiguration */ 2 17 2 abs_w bit (1) unaligned, /* absolute address must not be changed for page */ 2 18 2 abs_usable bit (1) unaligned, /* page may be assigned with fixed absolute address */ 2 19 2 notify_requested bit (1) unaligned, /* notify requested on I/O completion */ 2 20 2 pad3 bit (1) unaligned, 2 21 2 phm_hedge bit (1) unaligned, /* on => pc$flush_core ought write. */ 2 22 2 contr bit (3) unaligned, /* controller in which core block is located */ 2 23 2 24 2 ptwp bit (18) unaligned, /* pointer to page table word for the page */ 2 25 2 astep bit (18) unaligned, /* relative AST entry pointer of page */ 2 26 2 pin_counter fixed bin (17) unaligned, /* number of times to skip eviction */ 2 27 2 synch_page_entryp bit (18) unaligned; /* relp to synch page entry */ 2 28 2 29 2 30 dcl 1 cma (0: 1) based aligned like cme; /* Core map array */ 2 31 2 32 dcl 1 mcme based (cmep) aligned, /* core map entry for extracting DID */ 2 33 2 pad bit (36) unaligned, 2 34 2 record_no bit (18) unaligned, /* record number of device */ 2 35 2 add_type bit (4) unaligned, /* see add_type.incl.pl1 */ 2 36 2 flags bit (14) unal, 2 37 2 pad1 bit (18) unal; 2 38 2 39 2 40 /* END INCLUDE FILE cmp.incl.pl1 */ 44 45 /* BEGIN INCLUDE FILE syserr_constants.incl.pl1 ... 11/11/80 W. Olin Sibert */ 3 2 /* 85-02-12, EJ Sharpe - Added sorting class constants, removed AIM_MESSAGE, added new action code names. */ 3 3 /* 85-04-24, G. Palter - Renamed SYSERR_UNUSED_10 to SYSERR_RING1_ERROR to reflect its actual use. */ 3 4 3 5 /* This include file has an ALM version. Keep 'em in sync! */ 3 6 3 7 dcl ( 3 8 3 9 /* The following constants define the message action codes. This indicates 3 10*how a message is to be handled. */ 3 11 3 12 SYSERR_CRASH_SYSTEM init (1), 3 13 CRASH init (1), /* Crash the system, and bleat plaintively. */ 3 14 3 15 SYSERR_TERMINATE_PROCESS init (2), 3 16 TERMINATE_PROCESS init (2), /* Terminate the process, print the message, and beep. */ 3 17 3 18 SYSERR_PRINT_WITH_ALARM init (3), 3 19 BEEP init (3), /* Beep and print the message on the console. */ 3 20 3 21 SYSERR_PRINT_ON_CONSOLE init (0), 3 22 ANNOUNCE init (0), /* Just print the message on the console. */ 3 23 3 24 SYSERR_LOG_OR_PRINT init (4), 3 25 LOG init (4), /* Log the message, or print it if it can't be logged */ 3 26 3 27 SYSERR_LOG_OR_DISCARD init (5), 3 28 JUST_LOG init (5), /* Just try to log the message, and discard it if it can't be */ 3 29 3 30 3 31 /* The following constants are added to the normal severities to indicate 3 32*different sorting classes of messages. */ 3 33 3 34 SYSERR_SYSTEM_ERROR init (00), /* indicates a standard level system error */ 3 35 SYSERR_RING1_ERROR init (10), /* indicates an error detected in ring 1 (mseg_, RCP) */ 3 36 SYSERR_COVERT_CHANNEL init (20), /* indicates covert channel audit trail message */ 3 37 SYSERR_UNSUCCESSFUL_ACCESS init (30), /* indicates access denial audit trail message */ 3 38 SYSERR_SUCCESSFUL_ACCESS init (40) /* indicates access grant audit trail message */ 3 39 ) fixed bin internal static options (constant); 3 40 3 41 /* END INCLUDE FILE syserr_constants.incl.pl1 */ 45 46 47 page = page_no; /* copy argument to (soon to be wired) stack */ 48 call wire_proc$wire_me; /* wire ourself down before we lock page table */ 49 call pmut$lock_ptl (saved_mask, stk_ptwp); /* lock and mask */ 50 51 cmep = addr (sst$cmp -> cma (page)); /* get pointer to core map entry */ 52 if cme.bp = (18)"1"b then do; /* only free what's not being used */ 53 54 /* Check for any parity errors reading the memory */ 55 56 call pmut$check_parity_for_add (page, code); 57 if code ^= 0 then call syserr (ANNOUNCE, "freecore: parity error in frame ^o of memory.", page); 58 else do; 59 call thread_into_cmes; 60 61 cmep -> cme.ptwp = (18)"0"b; /* mark this entry as free */ 62 63 cmep -> cme.abs_w, cmep -> cme.removing = "0"b; /* clear flags for entry */ 64 if scs$controller_data (bin (cmep -> cme.contr)).abs_wired /* check if pages in this controller are abs_wired */ 65 then cmep -> cme.abs_usable = "1"b; /* mark this page */ 66 67 end; 68 end; 69 call pmut$unlock_ptl (saved_mask, stk_ptwp); /* unlock and unmask */ 70 call wire_proc$unwire_me; /* unwire this procedure */ 71 return; 72 73 thread_into_cmes: proc; 74 75 if sst$usedp /* check if list has any entries */ 76 then do; /* add block to existing list */ 77 usedptr = ptr (sst$cmp, sst$usedp); /* get pointer to first entry */ 78 cmep -> cme.bp = usedptr -> cme.bp; /* thread at end of list */ 79 cmep -> cme.fp = rel (usedptr); 80 ptr (sst$cmp, usedptr -> cme.bp) -> cme.fp, usedptr -> cme.bp = rel (cmep); 81 if page > sst$last_core_block then sst$last_core_block = page; 82 else if page < sst$first_core_block then sst$first_core_block = page; 83 end; 84 else do; /* first entry to go on the list */ 85 cmep -> cme.bp, cmep -> cme.fp = rel (cmep); /* thread first entry to self */ 86 sst$first_core_block, sst$last_core_block = page; /* initialize core bounds */ 87 sst$wusedp = rel (cmep); /* init write pointer */ 88 end; 89 if sst$usedp = sst$wusedp 90 then sst$wusedp = rel (cmep); /* dont let wusedp get out of sync */ 91 sst$usedp = rel (cmep); /* update list pointer to start here */ 92 sst$nused = sst$nused + 1; /* record that one page was added */ 93 return; 94 end; 95 96 thread: entry (page_no); 97 98 /* Don't fiddle with page or cme, just thread into cme list */ 99 100 page = page_no; /* copy argument to (soon to be wired) stack */ 101 call wire_proc$wire_me; /* wire ourself down before we lock page table */ 102 call pmut$lock_ptl (saved_mask, stk_ptwp); /* lock and mask */ 103 104 cmep = addr (sst$cmp -> cma (page)); /* get pointer to core map entry */ 105 106 call thread_into_cmes; 107 108 call pmut$unlock_ptl (saved_mask, stk_ptwp); /* unlock and unmask */ 109 call wire_proc$unwire_me; /* unwire this procedure */ 110 return; 111 112 113 /* BEGIN MESSAGE DOCUMENTATION 114* 115*Message: 116*freecore: parity error in frame XXX of memory. 117* 118*S: $info 119* 120*T: $init 121* 122*M: A memory parity error has been detected in page XXX of memory. 123*The page will not be put in use. 124* 125*A: $ignore 126* 127* 128*END MESSAGE DOCUMENTATION */ 129 130 end freecore; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/11/89 0825.5 freecore.pl1 >special_ldd>install>MR12.3-1114>freecore.pl1 43 1 10/12/83 0943.5 scs.incl.pl1 >ldd>include>scs.incl.pl1 44 2 11/23/82 0953.7 cmp.incl.pl1 >ldd>include>cmp.incl.pl1 45 3 05/17/85 0615.7 syserr_constants.incl.pl1 >ldd>include>syserr_constants.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. ANNOUNCE 000001 constant fixed bin(17,0) initial dcl 3-7 set ref 57* abs_usable 1(29) based bit(1) level 2 packed packed unaligned dcl 2-6 set ref 64* abs_w 1(28) based bit(1) level 2 packed packed unaligned dcl 2-6 set ref 63* abs_wired 2(21) 000040 external static bit(1) array level 3 packed packed unaligned dcl 1-6 ref 64 addr builtin function dcl 35 ref 51 104 bin builtin function dcl 35 ref 64 bp 0(18) based bit(18) level 2 packed packed unaligned dcl 2-6 set ref 52 78* 78 80 80* 85* cma based structure array level 1 dcl 2-30 set ref 51 104 cme based structure level 1 dcl 2-6 cmep 000110 automatic pointer dcl 2-4 set ref 51* 52 61 63 63 64 64 78 79 80 85 85 85 87 89 91 104* code 000101 automatic fixed bin(35,0) dcl 21 set ref 56* 57 contr 1(33) based bit(3) level 2 packed packed unaligned dcl 2-6 ref 64 fp based bit(18) level 2 packed packed unaligned dcl 2-6 set ref 79* 80* 85* info 2 000040 external static structure array level 2 dcl 1-6 page 000100 automatic fixed bin(17,0) dcl 21 set ref 47* 51 56* 57* 81 81 82 82 86 100* 104 page_no parameter fixed bin(17,0) dcl 21 ref 19 47 96 100 pmut$check_parity_for_add 000014 constant entry external dcl 28 ref 56 pmut$lock_ptl 000010 constant entry external dcl 28 ref 49 102 pmut$unlock_ptl 000016 constant entry external dcl 28 ref 69 108 ptr builtin function dcl 35 ref 77 80 ptwp 2 based bit(18) level 2 packed packed unaligned dcl 2-6 set ref 61* rel builtin function dcl 35 ref 79 80 85 87 89 91 removing 1(27) based bit(1) level 2 packed packed unaligned dcl 2-6 set ref 63* saved_mask 000102 automatic fixed bin(71,0) dcl 21 set ref 49* 69* 102* 108* scs$controller_data 000040 external static structure array level 1 dcl 1-6 sst$cmp 000024 external static pointer dcl 37 ref 51 77 80 104 sst$first_core_block 000026 external static fixed bin(17,0) dcl 38 set ref 82 82* 86* sst$last_core_block 000030 external static fixed bin(17,0) dcl 39 set ref 81 81* 86* sst$nused 000032 external static fixed bin(17,0) dcl 40 set ref 92* 92 sst$usedp 000034 external static bit(18) packed unaligned dcl 41 set ref 75 77 89 91* sst$wusedp 000036 external static bit(18) dcl 42 set ref 87* 89 89* stk_ptwp 000104 automatic pointer dcl 21 set ref 49* 69* 102* 108* syserr 000012 constant entry external dcl 28 ref 57 usedptr 000106 automatic pointer dcl 21 set ref 77* 78 79 80 80 wire_proc$unwire_me 000022 constant entry external dcl 28 ref 70 109 wire_proc$wire_me 000020 constant entry external dcl 28 ref 48 101 NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. BEEP internal static fixed bin(17,0) initial dcl 3-7 BULK_PORT internal static fixed bin(17,0) initial dcl 1-176 CPU_PORT internal static fixed bin(17,0) initial dcl 1-176 CRASH internal static fixed bin(17,0) initial dcl 3-7 IOM_PORT internal static fixed bin(17,0) initial dcl 1-176 JUST_LOG internal static fixed bin(17,0) initial dcl 3-7 LOG internal static fixed bin(17,0) initial dcl 3-7 SYSERR_COVERT_CHANNEL internal static fixed bin(17,0) initial dcl 3-7 SYSERR_CRASH_SYSTEM internal static fixed bin(17,0) initial dcl 3-7 SYSERR_LOG_OR_DISCARD internal static fixed bin(17,0) initial dcl 3-7 SYSERR_LOG_OR_PRINT internal static fixed bin(17,0) initial dcl 3-7 SYSERR_PRINT_ON_CONSOLE internal static fixed bin(17,0) initial dcl 3-7 SYSERR_PRINT_WITH_ALARM internal static fixed bin(17,0) initial dcl 3-7 SYSERR_RING1_ERROR internal static fixed bin(17,0) initial dcl 3-7 SYSERR_SUCCESSFUL_ACCESS internal static fixed bin(17,0) initial dcl 3-7 SYSERR_SYSTEM_ERROR internal static fixed bin(17,0) initial dcl 3-7 SYSERR_TERMINATE_PROCESS internal static fixed bin(17,0) initial dcl 3-7 SYSERR_UNSUCCESSFUL_ACCESS internal static fixed bin(17,0) initial dcl 3-7 TERMINATE_PROCESS internal static fixed bin(17,0) initial dcl 3-7 mcme based structure level 1 dcl 2-32 scs$bos_processor_tag external static fixed bin(3,0) dcl 1-137 scs$bos_restart_flags external static bit(8) dcl 1-135 scs$cam_pair external static fixed bin(71,0) dcl 1-103 scs$cam_wait external static bit(8) dcl 1-104 scs$cfg_data external static fixed bin(71,0) array dcl 1-150 scs$cfg_data_save external static fixed bin(71,0) dcl 1-152 scs$connect_lock external static bit(36) dcl 1-132 scs$controller_config_size external static fixed bin(14,0) array dcl 1-164 scs$cow external static structure array level 1 dcl 1-65 scs$cow_ptrs external static structure array level 1 dcl 1-77 scs$cpu_test_mask external static bit(72) dcl 1-96 scs$cpu_test_pattern external static bit(36) dcl 1-99 scs$cycle_priority_template external static bit(7) dcl 1-172 scs$expanded_ports external static bit(1) array packed unaligned dcl 1-154 scs$fast_cam_pending external static bit(36) array dcl 1-140 scs$faults_initialized external static bit(1) dcl 1-138 scs$idle_aptep external static pointer array packed unaligned dcl 1-130 scs$interrupt_controller external static fixed bin(3,0) dcl 1-141 scs$mask_ptr external static pointer array packed unaligned dcl 1-110 scs$nprocessors external static fixed bin(17,0) dcl 1-136 scs$number_of_masks external static fixed bin(17,0) dcl 1-97 scs$open_level external static bit(72) dcl 1-94 scs$port_addressing_word external static bit(3) array dcl 1-148 scs$port_data external static structure array level 1 dcl 1-56 scs$processor external static bit(8) dcl 1-143 scs$processor_data external static structure array level 1 dcl 1-35 scs$processor_data_switch_value external static bit(36) dcl 1-162 scs$processor_start_int_no external static fixed bin(5,0) dcl 1-142 scs$processor_start_mask external static bit(72) dcl 1-95 scs$processor_start_pattern external static bit(36) dcl 1-98 scs$processor_start_wait external static bit(8) dcl 1-144 scs$processor_switch_compare external static bit(36) array dcl 1-159 scs$processor_switch_data external static bit(36) array dcl 1-157 scs$processor_switch_mask external static bit(36) array dcl 1-160 scs$processor_switch_template external static bit(36) array dcl 1-158 scs$processor_test_data external static structure level 1 dcl 1-114 scs$read_mask external static bit(36) array dcl 1-109 scs$reconfig_general_cow external static structure level 1 dcl 1-82 scs$reconfig_lock external static bit(36) dcl 1-133 scs$reconfig_locker_id external static char(32) dcl 1-167 scs$scas_page_table external static bit(36) array dcl 1-169 scs$set_cycle_switches external static bit(1) dcl 1-173 scs$set_mask external static bit(36) array dcl 1-108 scs$sys_level external static bit(72) dcl 1-93 scs$sys_trouble_pending external static bit(1) dcl 1-139 scs$trouble_dbrs automatic fixed bin(71,0) array dcl 1-146 scs$trouble_flags external static bit(8) dcl 1-134 NAMES DECLARED BY EXPLICIT CONTEXT. freecore 000022 constant entry external dcl 19 thread 000165 constant entry external dcl 96 thread_into_cmes 000241 constant entry internal dcl 73 ref 59 106 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 510 552 332 520 Length 1010 332 42 222 156 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME freecore 115 external procedure is an external procedure. thread_into_cmes internal procedure shares stack frame of external procedure freecore. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME freecore 000100 page freecore 000101 code freecore 000102 saved_mask freecore 000104 stk_ptwp freecore 000106 usedptr freecore 000110 cmep freecore THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out_desc call_ext_out return_mac mpfx2 ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. pmut$check_parity_for_add pmut$lock_ptl pmut$unlock_ptl syserr wire_proc$unwire_me wire_proc$wire_me THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. scs$controller_data sst$cmp sst$first_core_block sst$last_core_block sst$nused sst$usedp sst$wusedp LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 19 000017 47 000027 48 000032 49 000036 51 000047 52 000055 56 000061 57 000071 59 000117 61 000120 63 000123 64 000127 69 000144 70 000155 71 000162 96 000163 100 000172 101 000175 102 000202 104 000213 106 000221 108 000222 109 000233 110 000240 73 000241 75 000242 77 000245 78 000251 79 000254 80 000257 81 000272 82 000277 83 000302 85 000303 86 000312 87 000315 89 000317 91 000324 92 000326 93 000327 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved