COMPILATION LISTING OF SEGMENT mos_memory_check Compiled by: Multics PL/I Compiler, Release 32f, of October 9, 1989 Compiled at: Bull HN, Phoenix AZ, System-M Compiled on: 11/11/89 0956.7 mst Sat Options: optimize map 1 /****^ *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Bull Inc., 1987 * 4* * * 5* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 6* * * 7* * Copyright (c) 1972 by Massachusetts Institute of * 8* * Technology and Honeywell Information Systems, Inc. * 9* * * 10* *********************************************************** */ 11 12 /* format: style4 */ 13 14 /* MOS_MEMORY_CHECK: This procedure scans memorys to check for MOS memory EDAC errors to be logged. */ 15 16 /* Written April 1976 by Larry Johnson */ 17 /* The initial version will check only the low order memory on each controller */ 18 /* Modified June 1976 by Larry Johnson to check all memories on a controller */ 19 /* Modified September 1977 by Larry Johnson for new memory board types */ 20 /* Modified October 1981 by M.R. Jordan for new 64K chip memory */ 21 /* Modified February 1985 by EJ Sharpe to not log binary value for polling interval, add format */ 22 23 mos_memory_check: proc (arg_mem, arg_store, arg_data, arg_code); 24 25 dcl arg_mem (0:31) char (1) unal; 26 dcl arg_store (0:31) char (2) unal; 27 dcl arg_data (0:31) fixed bin (71); /* Array of maintenance registers */ 28 dcl arg_code fixed bin (35); 29 dcl arg_time fixed bin; 30 31 dcl port fixed bin; 32 dcl rscr_result fixed bin (71); 33 dcl poll_entry bit (1) init ("0"b); /* Set if called by polling */ 34 dcl time fixed bin; 35 dcl (store_a_index, store_b_index) fixed bin (5); /* Scas indexes for pmut$rscr */ 36 dcl mem char (1); 37 dcl aloud fixed bin; 38 39 dcl spoke (0:31) bit (1) int static init ((32) (1)"0"b); 40 41 dcl never fixed bin (52) int static options (constant) 42 init (1111111111111111111111111111111111111111111111111111b); 43 44 45 dcl letter (0:7) char (1) unal int static options (constant) init ("a", "b", "c", "d", "e", "f", "g", "h"); 46 47 dcl privileged_mode_ut$rscr entry (fixed bin (5), fixed bin (6), fixed bin (71)); 48 dcl clock_ entry returns (fixed bin (71)); 49 dcl syserr entry options (variable); 50 dcl syserr$binary entry options (variable); 51 52 dcl tc_data$mos_polling_time ext fixed bin (52); 53 dcl tc_data$mos_polling_interval ext fixed bin; 54 dcl pds$process_group_id ext char (32) aligned; 55 dcl pds$processid ext bit (36) aligned; 56 dcl error_table_$lock_wait_time_exceeded ext fixed bin (35); 57 58 dcl cleanup condition; 59 60 dcl (addr, stac, stacq) builtin; 61 62 /* First, lock the reconfig lock */ 63 64 arg_code = 0; 65 66 start: 67 68 on cleanup call clean_up; 69 70 if ^stac (addr (scs$reconfig_lock), pds$processid) then do; 71 if poll_entry then tc_data$mos_polling_time = clock_ () + 60000000; /* Try again in 1 minute */ 72 else arg_code = error_table_$lock_wait_time_exceeded; 73 return; 74 end; 75 scs$reconfig_locker_id = pds$process_group_id; 76 77 /* Now scan looking for memorys */ 78 79 scrp = addr (rscr_result); 80 81 do port = 0 to 7; /* Scan all controlers */ 82 83 if scs$controller_data.online (port) then do;/* Found active memory */ 84 if ^scs$controller_data.store_b_is_lower (port) then do; /* Store a lower */ 85 store_a_index = port; /* Set scas indexes */ 86 store_b_index = port + 8; 87 end; 88 else do; /* Memory upside down */ 89 store_a_index = port + 8; 90 store_b_index = port; 91 end; 92 93 mem = letter (port); 94 95 if scs$controller_data.store_a_online (port) then /* Check all stores */ 96 call check_store ("a", store_a_index); 97 if scs$controller_data.store_a1_online (port) then 98 call check_store ("a1", store_a_index + 16); 99 if scs$controller_data.store_b_online (port) then 100 call check_store ("b", store_b_index); 101 if scs$controller_data.store_b1_online (port) then 102 call check_store ("b1", store_b_index + 16); 103 104 end; 105 106 end; 107 108 if poll_entry then call reschedule; /* Must schedule next pass */ 109 if ^stacq (scs$reconfig_lock, "0"b, pds$processid) then 110 call syserr (ANNOUNCE, "mos_memory_check: Lock error."); 111 return; 112 113 /* Enter here from pxss for polling */ 114 115 poll: entry; 116 117 if tc_data$mos_polling_interval = 0 then do; /* Polling was turned off */ 118 tc_data$mos_polling_time = never; 119 return; 120 end; 121 poll_entry = "1"b; 122 go to start; 123 124 125 /* Entry to set the polling interval */ 126 127 set_poll_time: entry (arg_time); 128 129 time = arg_time; 130 if time < 0 then do; /* Request to return time */ 131 arg_time = tc_data$mos_polling_interval; 132 return; 133 end; 134 tc_data$mos_polling_interval = time; 135 call syserr (JUST_LOG, "mos_memory_check: MOS polling ^[disabled^;time ^d minute^[s^]^].", 136 (time = 0), time, (time ^= 1)); 137 call reschedule; 138 return; 139 140 141 /* Procedure that will check one store of one memory */ 142 143 check_store: proc (store_name, scas_index); 144 145 dcl store_name char (2); /* Name of store being tested */ 146 dcl scas_index fixed bin (5); /* Index in scas for pmut$rscr */ 147 dcl id bit (4) aligned; 148 149 call privileged_mode_ut$rscr (scas_index, (SC_SU), rscr_result); /* Read maintence register */ 150 if ^poll_entry then do; /* Called thru gate, so must return data */ 151 arg_mem (scas_index) = mem; 152 arg_store (scas_index) = store_name; 153 arg_data (scas_index) = rscr_result; 154 end; 155 156 id = scr_su.identification; /* copy id for easier access */ 157 if (id = "0011"b) | (id = "0100"b) | (id = "1010"b) 158 | (id = "1011"b) | (id = "1110"b) | (id = "1111"b) then do; /* MOS memory */ 159 if scr_su.syndrome ^= "0"b then do; /* Some error occured */ 160 if spoke (scas_index) then aloud = JUST_LOG; else aloud = ANNOUNCE; /* Mild fuss first time */ 161 spoke (scas_index) = "1"b; 162 call syserr$binary (aloud, scrp, SB_mos_err, SBL_mos_err, 163 "mos_memory_check: EDAC error on mem ^a store ^a.", mem, store_name); 164 end; 165 end; 166 return; 167 168 end check_store; 169 170 /* Procedure to calculate the next time to poll */ 171 172 reschedule: proc; 173 174 if tc_data$mos_polling_interval = 0 then tc_data$mos_polling_time = never; 175 else tc_data$mos_polling_time = clock_ () + 60000000 * tc_data$mos_polling_interval; 176 177 return; 178 179 end reschedule; 180 181 182 clean_up: proc; 183 184 dcl ignore bit (1); 185 186 ignore = stacq (scs$reconfig_lock, "0"b, pds$processid); /* Unlock if I locked it */ 187 return; 188 189 end clean_up; 190 /* format: off */ 191 /* BEGIN INCLUDE FILE syserr_constants.incl.pl1 ... 11/11/80 W. Olin Sibert */ 1 2 /* 85-02-12, EJ Sharpe - Added sorting class constants, removed AIM_MESSAGE, added new action code names. */ 1 3 /* 85-04-24, G. Palter - Renamed SYSERR_UNUSED_10 to SYSERR_RING1_ERROR to reflect its actual use. */ 1 4 1 5 /* This include file has an ALM version. Keep 'em in sync! */ 1 6 1 7 dcl ( 1 8 1 9 /* The following constants define the message action codes. This indicates 1 10*how a message is to be handled. */ 1 11 1 12 SYSERR_CRASH_SYSTEM init (1), 1 13 CRASH init (1), /* Crash the system, and bleat plaintively. */ 1 14 1 15 SYSERR_TERMINATE_PROCESS init (2), 1 16 TERMINATE_PROCESS init (2), /* Terminate the process, print the message, and beep. */ 1 17 1 18 SYSERR_PRINT_WITH_ALARM init (3), 1 19 BEEP init (3), /* Beep and print the message on the console. */ 1 20 1 21 SYSERR_PRINT_ON_CONSOLE init (0), 1 22 ANNOUNCE init (0), /* Just print the message on the console. */ 1 23 1 24 SYSERR_LOG_OR_PRINT init (4), 1 25 LOG init (4), /* Log the message, or print it if it can't be logged */ 1 26 1 27 SYSERR_LOG_OR_DISCARD init (5), 1 28 JUST_LOG init (5), /* Just try to log the message, and discard it if it can't be */ 1 29 1 30 1 31 /* The following constants are added to the normal severities to indicate 1 32*different sorting classes of messages. */ 1 33 1 34 SYSERR_SYSTEM_ERROR init (00), /* indicates a standard level system error */ 1 35 SYSERR_RING1_ERROR init (10), /* indicates an error detected in ring 1 (mseg_, RCP) */ 1 36 SYSERR_COVERT_CHANNEL init (20), /* indicates covert channel audit trail message */ 1 37 SYSERR_UNSUCCESSFUL_ACCESS init (30), /* indicates access denial audit trail message */ 1 38 SYSERR_SUCCESSFUL_ACCESS init (40) /* indicates access grant audit trail message */ 1 39 ) fixed bin internal static options (constant); 1 40 1 41 /* END INCLUDE FILE syserr_constants.incl.pl1 */ 191 192 /* BEGIN INCLUDE FILE .. syserr_binary_def.incl.pl1 */ 2 2 2 3 /* This include file has an ALM version, keep 'em in sync. */ 2 4 2 5 /* format: off */ 2 6 2 7 /* Modified January 1984 by Paul Farley to add an array of entry values 2 8* to be examined by display_cpu_error. */ 2 9 /* Modified October 1984 by EJ Sharpe to include SB_audit_message */ 2 10 /* Modified January 1985 by EJ Sharpe for SB_char_data_classes */ 2 11 /* Modified 1985-01-25, BIM: added ring alarm audit support. */ 2 12 /* Modified 1985-02-20, EJ Sharpe: added SB_ibm3270_mde, syserr_binary_(seg vol)damage_class, 2 13* also changed some codes to "SB_unused_NN" - see line comments */ 2 14 2 15 /* In the future, these will be the only constants needed in this include 2 16*file. They are the binary data class strings for messages in the new format 2 17*syserr logs. The names are all of the form SB_ZZZZZZZ_data_class where 2 18*ZZZZZZZ is the value of the data class string. Message expanders are named 2 19*expand_ZZZZZZZ_msg_ and are referenced by the log perusal tools. */ 2 20 2 21 dcl ( /* include file name */ 2 22 SB_io_status_data_class init ("io_status"), /* io_syserr_msg */ 2 23 SB_hwfault_data_class init ("hwfault"), /* syserr_fault_msg */ 2 24 SB_mos_data_class init ("mos"), /* scr */ 2 25 SB_segdamage_data_class init ("segdamage"), /* segdamage_msg */ 2 26 SB_voldamage_data_class init ("voldamage"), /* segdamage_msg (first two words) */ 2 27 SB_mdc_del_uidpath_data_class init ("mdc_del_uidpath"), /* none - 16 word UID path */ 2 28 SB_mmdam_data_class init ("mmdam"), /* syserr_mmdam_msg */ 2 29 SB_mpc_poll_data_class init ("mpc_poll"), /* poll_mpc_data */ 2 30 SB_fnp_poll_data_class init ("fnp_poll"), /* poll_fnp_data */ 2 31 SB_config_deck_data_class init ("config_deck"), /* config_deck */ 2 32 SB_vtoce_data_class init ("vtoce"), /* vtoce */ 2 33 SB_access_audit_data_class init ("access_audit"), /* access_audit_bin_header */ 2 34 SB_ibm3270_mde_data_class init ("ibm3270_mde") /* ibm3270_mpx_data */ 2 35 ) static internal char (16) varying options (constant); 2 36 2 37 2 38 /************************ 2 39*Once the syserr$binary is replaced with something that takes real data classes 2 40*and all system modules and tools are upgraded to use the new interface, the 2 41*rest of this include file may be discarded. 2 42*************************/ 2 43 2 44 /* The limit of 36 is arbitrary- there is no reason that it can not be 2 45* extended at any time. */ 2 46 2 47 dcl ( 2 48 SB_disk_err init (1), SBL_disk_err init (5), 2 49 SB_hw_fault init (2), SBL_hw_fault init (176), 2 50 SB_io_err init (3), SBL_io_err init (5), 2 51 SB_unused_4 init (4), SBL_unused_4 init (1), /* was "mos_poll" (mos poll time) */ 2 52 SB_mos_err init (5), SBL_mos_err init (2), /* mos memory error data */ 2 53 SB_unused_6 init (6), SBL_unused_6 init (1), /* was "bulk_status" (bulk dcb status) */ 2 54 SB_unused_7 init (7), SBL_unused_7 init (1), /* was "bulk_csb" (bulk csb status) */ 2 55 SB_unused_8 init (8), SBL_unused_8 init (3), /* was "free_st_1" */ 2 56 SB_unused_9 init (9), SBL_unused_9 init (2), /* was "free_st_2" */ 2 57 SB_unused_10 init (10), SBL_unused_10 init (21), /* was "unpr_add" */ 2 58 SB_zerpag init (11), SBL_zerpag init (20), 2 59 SB_unused_12 init (12), SBL_unused_12 init (20), /* was "unpr_add" */ 2 60 SB_vtoc_salv_dam init (13), SBL_vtoc_salv_dam init (20), 2 61 SB_unused_14 init (14), SBL_unused_14 init (20), /* was "page_rw_err" */ 2 62 SB_unused_15 init (15), SBL_unused_15 init (3), /* was "ruad" */ 2 63 SB_random_segdamage init (16), SBL_random_segdamage init (20), 2 64 SB_read_nc init (17), SBL_read_nc init (2), 2 65 SB_unused_18 init (18), SBL_unused_18 init (2), /* was "vtoc_err" */ 2 66 SB_mdc_del_uidpath init (19), SBL_mdc_del_uidpath init (16), 2 67 SB_ocdcm_err init (20), SBL_ocdcm_err init (5), 2 68 SB_mmdam init (21), SBL_mmdam init (2), 2 69 SB_verify_lock init (22), SBL_verify_lock init (176), 2 70 SB_io_err_detail init (23), SBL_io_err_detail init (11), 2 71 SB_mpc_poll init (24), SBL_mpc_poll init (256) /* max */, 2 72 SB_fnp_poll init (25), SBL_fnp_poll init (256) /* max */, 2 73 SB_config_deck init (26), SBL_config_deck init (256) /* 16 cards at 16 words */, 2 74 SB_vtoce init (27), SBL_vtoce init (192), /* 1 VTOCE */ 2 75 SB_access_audit init (28), SBL_access_audit init (256), /* max */ 2 76 SB_ibm3270_mde init (35), SBL_ibm3270_mde init (256), /* max */ 2 77 SB_end_of_table init (36), SBL_end_of_table init (1) 2 78 ) internal static options (constant) fixed bin; 2 79 2 80 2 81 /* The following array is a mapping of the old syserr$binary codes into the 2 82*new data classes for MR11. It is primarily used by syserr_copy to translate 2 83*the binary data codes stored in the wired syserr log (see above) into the data 2 84*classes needed by the ring-0 paged syserr log which is a new format log. It 2 85*is also used by syserr_log_util_ to translate the data classes back into the 2 86*corresponding binary code (for tools not yet upgraded to deal with the new 2 87*format log messages). */ 2 88 2 89 dcl SB_char_data_classes (36) char (16) varying internal static options (constant) 2 90 init ( "io_status", /* 1 */ 2 91 "hwfault", /* 2 */ 2 92 "io_status", /* 3 */ 2 93 "unused_4", /* 4 */ 2 94 "mos", /* 5 */ 2 95 2 96 "unused_6", /* 6 */ 2 97 "unused_7", /* 7 */ 2 98 "unused_8", /* 8 */ 2 99 "unused_9", /* 9 */ 2 100 "unused_10", /* 10 */ 2 101 2 102 "segdamage", /* 11 */ 2 103 "unused_12", /* 12 */ 2 104 "segdamage", /* 13 */ 2 105 "unused_14", /* 14 */ 2 106 "unused_15", /* 15 */ 2 107 2 108 "segdamage", /* 16 */ 2 109 "voldamage", /* 17 */ 2 110 "unused_18", /* 18 */ 2 111 "mdc_del_uidpath", /* 19 */ 2 112 "io_status", /* 20 */ 2 113 2 114 "mmdam", /* 21 */ 2 115 "hwfault", /* 22 */ 2 116 "io_status", /* 23 */ 2 117 "mpc_poll", /* 24 */ 2 118 "fnp_poll", /* 25 */ 2 119 2 120 "config_deck", /* 26 */ 2 121 "vtoce", /* 27 */ 2 122 "access_audit", /* 28 */ 2 123 "unused_29", /* 29 */ 2 124 "unused_30", /* 30 */ 2 125 "unused_31", /* 31 */ 2 126 "unused_32", /* 32 */ 2 127 "unused_33", /* 33 */ 2 128 "unused_34", /* 34 */ 2 129 "ibm3270_mde", /* 35 */ 2 130 "unused_36" /* 36 */ 2 131 ); 2 132 2 133 2 134 /* format: on */ 2 135 2 136 /* These constants are used by various tools which analyze syserr messages and 2 137*still call the old interface "syserr_log_util_". */ 2 138 2 139 dcl syserr_binary_mos_mask init ("060000000000"b3) bit (36) static options (constant); 2 140 dcl syserr_binary_seg_damage_mask init ("000374000000"b3) bit (36) static options (constant); 2 141 dcl syserr_binary_vol_damage_mask init ("003413000000"b3) bit (36) static options (constant); 2 142 dcl syserr_binary_address_damage_mask init ("002010000000"b3) bit (36) static options (constant); 2 143 2 144 dcl display_cpu_error_binary_defs (2) init ( 2 145 2, /** SB_hw_fault */ 2 146 22 /** SB_verify_lock */ 2 147 ) internal static options (constant) fixed bin; 2 148 2 149 /* END INCLUDE FILE syserr_binary_def.incl.pl1 */ 192 193 /* Begin include file ...... scr.incl.pl1 3 2* modified 5/75 by Noel I. Morris 3 3* modified 10/81 by M.R. Jordan for 64K chip, M64 memory 3 4* modified '83 to make values constant */ 3 5 3 6 /* This include file is to be used in conjunction with pmut$rscr and pmut$sscr. 3 7* Wherever possible the terms in the processor manual are used in the declaration. */ 3 8 3 9 dcl (SC_MR init (0), /* SC Mode Register */ 3 10 SC_CFG init (1), /* SC Configuration Switches */ 3 11 SC_MSK init (2), /* SC Interrupt Mask */ 3 12 SC_IC init (3), /* SC Interrupt Cells */ 3 13 SC_ETC init (4), /* SC Elapsed Time Clock */ 3 14 SC_SU init (6)) fixed bin (6) static options (constant); /* SU Mode Register */ 3 15 3 16 3 17 dcl scrp ptr; /* pointer to SC data */ 3 18 3 19 dcl 1 scr_cfg1 based (scrp) aligned, /* configuration data for 6000 SC */ 3 20 3 21 (2 mode_a bit (3), /* 000 => on-line 3 22* 001 => test mode 3 23* 010 => off-line */ 3 24 2 bdry_a bit (3), /* 000 => 32K, 001 => 64K, etc */ 3 25 2 mode_b bit (3), /* see mode_a */ 3 26 2 bdry_b bit (3), /* see bdry_a */ 3 27 2 int bit (1), /* 1 => stores are internally interlaced */ 3 28 2 lwr bit (1), /* 1 => store B is low */ 3 29 2 addr_offset bit (2), /* 00 => no offset, 01 => 32K offset, etc. */ 3 30 2 port_no bit (4), /* requester's port number */ 3 31 2 port_enable (0:7) bit (2), /* 00 => port disabled 3 32* 01 => port under program control 3 33* 11 => port enabled */ 3 34 2 pima (4) bit (9)) unaligned; /* program interrupt mask assignments 3 35* 000 => unassigned 3 36* 400 => assigned to port 0 3 37* 200 => assigned to port 1 3 38* . 3 39* . 3 40* . 3 41* 002 => assigned to port 7 3 42* 001 => assigned to maint. panel */ 3 43 3 44 3 45 dcl 1 scr_cfg2 based (scrp) aligned, /* configuration data for 4MW SCU */ 3 46 3 47 (2 mask_a_assign bit (9), /* interrupt mask "A" port assignment 3 48* 400 => assigned to port 0 3 49* . 3 50* . 3 51* 002 => assigned to port 7 3 52* 001 => mask off */ 3 53 2 size bit (3), /* size of lower store */ 3 54 2 a_online bit (1), /* 1 => store A online */ 3 55 2 a1_online bit (1), /* 1 => store A1 online */ 3 56 2 b_online bit (1), /* 1 => store B online */ 3 57 2 b1_online bit (1), /* 1 => store B1 online */ 3 58 2 port_no bit (4), /* requester's port number */ 3 59 2 pad1 bit (1), 3 60 2 mode bit (1), /* 1 => programmable mode */ 3 61 2 nea_enabled bit (1), /* 1 => non-existent address logic enabled */ 3 62 2 nea bit (7), /* 001 => 32K, 002 => 64K, 003 => 96K, etc. */ 3 63 2 int bit (1), /* 1 => stores are internally interlaced */ 3 64 2 lwr bit (1), /* 1 => store B is low */ 3 65 2 port_mask_0_3 bit (4), /* 1 => corresponding port enabled */ 3 66 3 67 2 mask_b_assign bit (9), /* interrupt mask "B" port assignment */ 3 68 2 pad2 bit (12), 3 69 2 cyclic_prior bit (7), /* cyclic port priority switches */ 3 70 2 pad3 bit (4), 3 71 2 port_mask_4_7 bit (4)) unal; /* 1 => corresponding port enabled */ 3 72 3 73 3 74 dcl 1 scr_mr based (scrp) aligned, /* SC mode register */ 3 75 3 76 (2 pad1 bit (50), 3 77 2 identification bit (4), /* 0000 => 8034, 8035 3 78* 0001 => 6000 SC 3 79* 0010 => 4MW SCU */ 3 80 2 TS_strobe_margin bit (2), /* 00 => normal timing 3 81* 01 => slow timing 3 82* 10 => inhibit strobe 3 83* 11 => fast timing */ 3 84 2 G0_strobe_margin bit (2), 3 85 2 ANSWER_strobe_margin bit (2), 3 86 2 DA_strobe_margin bit (2), 3 87 2 EOC_strobe_margin bit (2), 3 88 2 PLUS_5_VOLT_margin bit (2), /* 00 => normal voltage 3 89* 01 => -5% 3 90* 10 => normal voltage 3 91* 11 => +5% */ 3 92 2 parity_override bit (1), /* 1 => SU forced to accept data with incorrect parity */ 3 93 2 parity_disable bit (1), /* 1 => disable data and ZAC parity checking */ 3 94 2 store_IA_disable bit (1), /* 1 => disable illegal action indication */ 3 95 2 ZAC_parity_error bit (1), /* 1 => cause ZAC parity error */ 3 96 2 SGR_accepted bit (1), /* 1 => SGR command accepted by SC */ 3 97 2 pad2 bit (1)) unal; 3 98 3 99 3 100 dcl 1 scr_msk based (scrp) aligned, /* SC mask register */ 3 101 3 102 (2 interrupt_mask_1 bit (16), /* mask bits for interrupts 0 thru 15 */ 3 103 2 pad1 bit (16), 3 104 2 port_mask_1 bit (4), /* mask bits for ports 0 thru 3 */ 3 105 3 106 2 interrupt_mask_2 bit (16), /* mask bits for interrupts 16 thru 31 */ 3 107 2 pad2 bit (16), 3 108 2 port_mask_2 bit (4)) unal; /* mask bits for ports 4 thru 7 */ 3 109 3 110 3 111 dcl 1 scr_su based (scrp) aligned, /* store unit mode register */ 3 112 3 113 (2 pad1 bit (36), 3 114 2 ZAC_line bit (6), /* EDAC mode only - address field */ 3 115 2 syndrome bit (8), /* EDAC mode only - failure syndrome */ 3 116 2 identification bit (4), /* 0000 => High Speed Core Model AA1 3 117* 0001 => High Speed Core Model AA3 3 118* 0011 => 4K, 16 pin chip, MOS memory, M32 boards 3 119* 0100 => 1K chip MOS memory with EDAC enabled 3 120* 1010 => 64K, 16 pin chip, MOS memory, M64 boards 3 121* 1011 => 16K, 16 pin chip, MOS memory, M264 boards 3 122* 1100 => 1K chip MOS memory with EDAC disabled 3 123* 1110 => 16K, 16 pin chip, MOS memory, M128 boards 3 124* 1111 => 4K, 22 pin chip MOS memory, M16 boards */ 3 125 2 EDAC_disabled bit (1), /* 1 => correction disabled but detection still enabled */ 3 126 2 pad2 bit (4), 3 127 2 MINUS_5_VOLT_margin bit (2), 3 128 2 PLUS_5_VOLT_margin bit (2), 3 129 2 spare_margin bit (2), 3 130 2 PLUS_19_VOLT_margin bit (2), 3 131 2 pad3 bit (1), 3 132 2 SENSE_strobe_margin bit (2), /* core only */ 3 133 2 pad4 bit (1), 3 134 2 maint_functions_enabled bit (1)) unal; /* 1 => maintenance functions enabled */ 3 135 3 136 /* End of include file ...... scr.incl.pl1 */ 3 137 193 194 /* BEGIN INCLUDE FILE scs.incl.pl1 ... March 1983 */ 4 2 /* format: style4 */ 4 3 4 4 /* Information about system controllers */ 4 5 4 6 dcl 1 scs$controller_data (0:7) aligned ext, /* per-controller info */ 4 7 2 size fixed bin (17) unaligned, /* size (in 1024 word blocks) of this controller */ 4 8 2 base fixed bin (17) unaligned, /* abs address (0 mod 1024) for base of this controller */ 4 9 2 eima_data (4) unaligned, /* EIMA information for this controller */ 4 10 3 mask_available bit (1) unaligned, /* ON if corresponding mask exists */ 4 11 3 mask_assigned bit (1) unaligned, /* ON if mask assigned to a port */ 4 12 3 mbz bit (3) unaligned, 4 13 3 mask_assignment fixed bin (3) unaligned, /* port to which mask is assigned */ 4 14 2 info aligned, 4 15 3 online bit (1) unaligned, /* ON if controller is online */ 4 16 3 offline bit (1) unaligned, /* ON if controller is offline but can be added */ 4 17 3 store_a_online bit (1) unaligned, /* ON if store A is online */ 4 18 3 store_a1_online bit (1) unaligned, /* ON if store A1 is online */ 4 19 3 store_b_online bit (1) unaligned, /* ON if store B is online */ 4 20 3 store_b1_online bit (1) unaligned, /* ON if store B1 is online */ 4 21 3 store_b_is_lower bit (1) unaligned, /* ON if store B is lower */ 4 22 3 ext_interlaced bit (1) unaligned, /* ON if this SCU is interlaced with other SCU */ 4 23 3 int_interlaced bit (1) unaligned, /* ON if this SCU is internally interlaced */ 4 24 3 four_word bit (1) unaligned, /* ON if external interlace is 4-word */ 4 25 3 cyclic_priority (7) bit (1) unaligned, /* Cyclic priority for adjacent ports */ 4 26 3 type bit (4) unaligned, /* Model number for this controller */ 4 27 3 abs_wired bit (1) unaligned, /* ON if controller can have abs_wired pages */ 4 28 3 program bit (1) unaligned, /* PROGRAM/MANUAL switch setting */ 4 29 3 mbz bit (13) unaligned, 4 30 2 lower_store_size fixed bin (17) unaligned, /* size (in 1024 word blocks) of lower store */ 4 31 2 upper_store_size fixed bin (17) unaligned; /* size (in 1024 word blocks) of upper store */ 4 32 4 33 /* Information about CPUs */ 4 34 4 35 dcl 1 scs$processor_data (0:7) aligned ext, /* information about CPUs in the system */ 4 36 ( 4 37 2 online bit (1), /* "1"b if CPU is online */ 4 38 2 offline bit (1), /* "1"b if CPU is offline but can be added */ 4 39 2 release_mask bit (1), /* "1"b is this CPU is to give up its mask */ 4 40 2 accept_mask bit (1), /* "1"b if this CPU is to grap mask in idle loop */ 4 41 2 delete_cpu bit (1), /* "1"b if this CPU is to delete itself */ 4 42 2 interrupt_cpu bit (1), /* "1"b if this CPU takes hardware interrupts */ 4 43 2 halted_cpu bit (1), /* "1"b if this CPU has stopped itself (going to BOS) */ 4 44 2 cpu_type fixed bin (2) unsigned, /* 0 => DPS or L68, 1 => DPS8 */ 4 45 2 mbz1 bit (6), 4 46 2 cache_size fixed bin (3) unsigned, /* 0 = No cache; 1 = L68 2K cache; 4 47* 2 = DPS8 8K cache; 3 = DPS8 VS&SC 8K cache; 4 48* 4 = DPS8 VS&SC 16K cache; 5 = DPS8 VS&SC 32K cache 4 49* 7 = ignore cache size (set by ISOLTS reconfig) */ 4 50 2 mbz2 bit (12), 4 51 2 expanded_port bit (1), /* "1"b = on expanded port */ 4 52 2 expander_port fixed bin (2) unsigned, /* The actual expander port */ 4 53 2 controller_port fixed bin (3) unsigned 4 54 ) unaligned; /* Port on controller */ 4 55 4 56 dcl 1 scs$port_data (0:7) aligned external static, /* Info about what is connected to each SCU port */ 4 57 2 assigned fixed bin (4) unsigned unaligned, /* Type of device on this port */ 4 58 2 expander_port bit (1) unaligned, /* "1"b => this port has a port expander */ 4 59 2 expanded_cpu (0:3) bit (1) unaligned, /* "1"b => this expander port has a CPU attached */ 4 60 2 iom_number fixed bin (3) unsigned unaligned, /* IOM number of IOM attached to this port */ 4 61 2 cpu_number (0:3) fixed bin (3) unsigned unaligned, /* CPU number of CPU(s) attached to this port */ 4 62 /* cpu_number (0) is only one if expander_port is "0"b */ 4 63 2 pad bit (12) unaligned; 4 64 4 65 dcl 1 scs$cow (0:7) aligned external, /* Actual connect words */ 4 66 2 pad bit (36) aligned, /* Expander COW's must be odd-word */ 4 67 2 cow, 4 68 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 4 69 3 mbz1 bit (13) unaligned, 4 70 3 expander_command bit (3) unaligned, /* Expander command. */ 4 71 3 mbz2 bit (2) unaligned, 4 72 3 expanded_port bit (1) unaligned, /* "1"b = on expanded port */ 4 73 3 expander_port fixed bin (3) unsigned unaligned, /* Port on expander for cioc */ 4 74 3 mbz3 bit (3) unaligned, 4 75 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 4 76 4 77 dcl 1 scs$cow_ptrs (0:7) external aligned, /* Pointers to COW's */ 4 78 2 rel_cow_ptr bit (18) unal, /* Relative pointer to COW */ 4 79 2 pad bit (12) unal, 4 80 2 tag bit (6) unal; /* Better be zero. */ 4 81 4 82 dcl 1 scs$reconfig_general_cow aligned external, /* Used during reconfig ops. */ 4 83 2 pad bit (36) aligned, 4 84 2 cow, /* Connect operand word, in odd location. */ 4 85 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 4 86 3 mbz1 bit (13) unaligned, 4 87 3 expander_command bit (3) unaligned, /* Expander command. */ 4 88 3 mbz2 bit (9) unaligned, 4 89 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 4 90 4 91 /* MASKS and PATTERNS */ 4 92 4 93 dcl scs$sys_level bit (72) aligned ext; /* mask used while handling I/O interrupts */ 4 94 dcl scs$open_level bit (72) aligned ext; /* mask used during normal operation */ 4 95 dcl scs$processor_start_mask bit (72) aligned ext; /* mask used when starting up a CPU */ 4 96 dcl scs$cpu_test_mask bit (72) aligned ext; /* mask used for ISOLTS CPU testing */ 4 97 dcl scs$number_of_masks fixed bin ext; /* number of masks (starting at sys_level) */ 4 98 dcl scs$processor_start_pattern bit (36) aligned ext; /* SMIC pattern used to send processor start interrupt */ 4 99 dcl scs$cpu_test_pattern bit (36) aligned ext; /* SMIC pattern used for ISOLTS processor testing */ 4 100 4 101 /* CAM and CACHE clear info */ 4 102 4 103 dcl scs$cam_pair fixed bin (71) ext; /* instructions XEDd when CAMing and clearing CACHE */ 4 104 dcl scs$cam_wait bit (8) aligned ext; /* Used when evicting pages from main memory */ 4 105 4 106 /* MASKING INSTRUCTIONS & POINTERS */ 4 107 4 108 dcl scs$set_mask (0:7) bit (36) aligned ext; /* instructions to set mask (STAQ or SMCM) */ 4 109 dcl scs$read_mask (0:7) bit (36) aligned ext; /* instructions to read mask (LDAQ or RMCM) */ 4 110 dcl scs$mask_ptr (0:7) ptr unaligned ext; /* pointers for real or simulated masks */ 4 111 4 112 /* MISCELLANEOUS */ 4 113 4 114 dcl 1 scs$processor_test_data aligned ext, /* info used for cpu testing */ 4 115 ( 4 116 2 active bit (1), /* = "1"b if cpu currently under test */ 4 117 2 scu_state bit (2), /* state of scu being used for testing (see definition below) */ 4 118 2 pad1 bit (4), 4 119 2 req_mem fixed bin (10), /* dedicated memory required to test this cpu */ 4 120 2 cpu_tag fixed bin (5), /* tag of cpu under test */ 4 121 2 scu_tag fixed bin (5), /* tag of scu being used for cpu testing */ 4 122 2 mask_cpu fixed bin (5) 4 123 ) unaligned; /* tag of active cpu that has mask asigned to above scu */ 4 124 4 125 /* scu_state = "00"b => SCU defined by scs$processor_test_data.scu_tag not yet effected */ 4 126 /* scu_state = "01"b => all core removed from SCU, port mask not yet changed */ 4 127 /* scu_state = "10"b => all core removed from SCU, port mask changed */ 4 128 /* scu_state = "11"b => only 64k at base of SCU being used for testing, original port mask restored */ 4 129 4 130 dcl scs$idle_aptep (0:7) ptr unaligned ext; /* pointer to idle process APTE for each processor */ 4 131 4 132 dcl scs$connect_lock bit (36) aligned ext; /* lock for sending connects */ 4 133 dcl scs$reconfig_lock bit (36) aligned ext; /* Lock used during reconfiguration */ 4 134 dcl scs$trouble_flags bit (8) aligned ext; /* checkoff flags for sys_trouble stopping */ 4 135 dcl scs$bos_restart_flags bit (8) aligned ext; /* checkoff flags for restarting after sys_trouble */ 4 136 dcl scs$nprocessors fixed bin ext; /* number of runnung processors */ 4 137 dcl scs$bos_processor_tag fixed bin (3) ext; /* CPU tag of processor running BOS */ 4 138 dcl scs$faults_initialized bit (1) aligned ext; /* ON after faults have been enabled */ 4 139 dcl scs$sys_trouble_pending bit (1) aligned ext; /* sys_trouble event is pending in the system */ 4 140 dcl scs$fast_cam_pending (0:7) bit (36) aligned ext; /* checkoff cells for cam connect */ 4 141 dcl scs$interrupt_controller fixed bin (3) ext; /* port number of low order controller */ 4 142 dcl scs$processor_start_int_no fixed bin (5) ext; /* interrupt cell for starting a processor */ 4 143 dcl scs$processor bit (8) aligned ext; /* bits ON for online CPUs */ 4 144 dcl scs$processor_start_wait bit (8) aligned ext; /* checkoff flags for waiting for new processor */ 4 145 4 146 dcl scs$trouble_dbrs (0:7) fixed bin (71); /* DBR values at system crash time */ 4 147 4 148 dcl scs$port_addressing_word (0:7) bit (3) aligned ext; /* active module port number for each controller */ 4 149 4 150 dcl scs$cfg_data (0:7) fixed bin (71) aligned ext; /* RSCR-CFG data from each controller */ 4 151 4 152 dcl scs$cfg_data_save fixed bin (71) aligned ext; /* RSCR-CFG save area for ISOLTS CPU testing */ 4 153 4 154 dcl scs$expanded_ports bit (1) unaligned dim (0:7) external; 4 155 /* Which ports have expanders */ 4 156 4 157 dcl scs$processor_switch_data (0:4) bit (36) aligned ext; /* raw data from RSW 0 thru 4 */ 4 158 dcl scs$processor_switch_template (0:4) bit (36) aligned ext; /* expected data from RSW 0 thru 4 */ 4 159 dcl scs$processor_switch_compare (0:4) bit (36) aligned ext; /* discrepancies from expected data */ 4 160 dcl scs$processor_switch_mask (0:4) bit (36) aligned ext; /* masks for comparing switch data */ 4 161 4 162 dcl scs$processor_data_switch_value bit (36) aligned ext; /* Correct value for CPU data switches */ 4 163 4 164 dcl scs$controller_config_size (0:7) fixed bin (14) aligned ext; 4 165 /* Controller size on config card */ 4 166 4 167 dcl scs$reconfig_locker_id char (32) aligned ext; /* process group ID of process doing reconfiguration */ 4 168 4 169 dcl scs$scas_page_table (0:31) bit (36) aligned external static; 4 170 /* PTWs for SCAS pages */ 4 171 4 172 dcl scs$cycle_priority_template bit (7) aligned ext; /* template for setting anti-hog switches */ 4 173 dcl scs$set_cycle_switches bit (1) aligned ext; /* flag to set ant-hog switches */ 4 174 4 175 4 176 dcl ( 4 177 IOM_PORT init (1), 4 178 CPU_PORT init (2), 4 179 BULK_PORT init (3) 4 180 ) fixed bin int static options (constant); /* values for scs$port_data.assigned */ 4 181 4 182 4 183 /* END INCLUDE FILE scs.incl.pl1 */ 194 195 196 /* BEGIN MESSAGE DOCUMENTATION 197* 198* Message: 199* mos_memory_check: Lock error. 200* 201* S: $info 202* 203* T: $run 204* 205* M: After checking the memory controllers for errors, 206* the program mos_memory check attempted to unlock the reconfiguration lock 207* and found it unlocked. 208* The system continues to run. 209* 210* A: $ignore 211* 212* 213* Message: 214* mos_memory_check: MOS polling disabled 215* 216* S: $log 217* 218* T: $run 219* 220* M: A system administrator has disabled MOS memory polling. 221* 222* A: $ignore 223* 224* 225* Message: 226* mos_memory_check: MOS polling time NN minutes. 227* 228* S: $log 229* 230* T: $run 231* 232* M: A system administrator has set the MOS memory polling time to NN minutes. 233* 234* A: $ignore 235* 236* 237* Message: 238* mos_memory_check: EDAC error on mem X store Y. 239* 240* S: $warn 241* 242* T: $run 243* 244* M: MOS memory polling has found that 245* the maintenance register in the system controller 246* shows a nonzero syndrome. 247* The data is logged for use by HEALS or mos_edac_summary. 248* Only the first occurrence of this error is printed online for each box. 249* 250* A: $ignore 251* 252* 253* END MESSAGE DOCUMENTATION */ 254 255 end mos_memory_check; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/11/89 0839.1 mos_memory_check.pl1 >special_ldd>install>MR12.3-1114>mos_memory_check.pl1 191 1 05/17/85 0615.7 syserr_constants.incl.pl1 >ldd>include>syserr_constants.incl.pl1 192 2 03/15/85 0953.1 syserr_binary_def.incl.pl1 >ldd>include>syserr_binary_def.incl.pl1 193 3 08/17/83 1135.7 scr.incl.pl1 >ldd>include>scr.incl.pl1 194 4 10/12/83 0943.5 scs.incl.pl1 >ldd>include>scs.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. ANNOUNCE 000015 constant fixed bin(17,0) initial dcl 1-7 set ref 109* 160 JUST_LOG 000016 constant fixed bin(17,0) initial dcl 1-7 set ref 135* 160 SBL_mos_err 000022 constant fixed bin(17,0) initial dcl 2-47 set ref 162* SB_mos_err 000016 constant fixed bin(17,0) initial dcl 2-47 set ref 162* SC_SU constant fixed bin(6,0) initial dcl 3-9 ref 149 addr builtin function dcl 60 ref 70 79 aloud 000111 automatic fixed bin(17,0) dcl 37 set ref 160* 160* 162* arg_code parameter fixed bin(35,0) dcl 28 set ref 23 64* 72* arg_data parameter fixed bin(71,0) array dcl 27 set ref 23 153* arg_mem parameter char(1) array packed unaligned dcl 25 set ref 23 151* arg_store parameter char(2) array packed unaligned dcl 26 set ref 23 152* arg_time parameter fixed bin(17,0) dcl 29 set ref 127 129 131* cleanup 000112 stack reference condition dcl 58 ref 66 clock_ 000014 constant entry external dcl 48 ref 71 175 error_table_$lock_wait_time_exceeded 000032 external static fixed bin(35,0) dcl 56 ref 72 id 000130 automatic bit(4) dcl 147 set ref 156* 157 157 157 157 157 157 identification 1(14) based bit(4) level 2 packed packed unaligned dcl 3-111 ref 156 ignore 000106 automatic bit(1) packed unaligned dcl 184 set ref 186* info 2 000034 external static structure array level 2 dcl 4-6 letter 000000 constant char(1) initial array packed unaligned dcl 45 ref 93 mem 000110 automatic char(1) packed unaligned dcl 36 set ref 93* 151 162* never 000002 constant fixed bin(52,0) initial dcl 41 ref 118 174 online 2 000034 external static bit(1) array level 3 packed packed unaligned dcl 4-6 ref 83 pds$process_group_id 000026 external static char(32) dcl 54 ref 75 pds$processid 000030 external static bit(36) dcl 55 ref 70 109 186 poll_entry 000104 automatic bit(1) initial packed unaligned dcl 33 set ref 33* 71 108 121* 150 port 000100 automatic fixed bin(17,0) dcl 31 set ref 81* 83 84 85 86 89 90 93 95 97 99 101* privileged_mode_ut$rscr 000012 constant entry external dcl 47 ref 149 rscr_result 000102 automatic fixed bin(71,0) dcl 32 set ref 79 149* 153 scas_index parameter fixed bin(5,0) dcl 146 set ref 143 149* 151 152 153 160 161 scr_su based structure level 1 dcl 3-111 scrp 000120 automatic pointer dcl 3-17 set ref 79* 156 159 162* scs$controller_data 000034 external static structure array level 1 dcl 4-6 scs$reconfig_lock 000036 external static bit(36) dcl 4-133 set ref 70 109 186 scs$reconfig_locker_id 000040 external static char(32) dcl 4-167 set ref 75* spoke 000010 internal static bit(1) initial array packed unaligned dcl 39 set ref 160 161* stac builtin function dcl 60 ref 70 stacq builtin function dcl 60 ref 109 186 store_a1_online 2(03) 000034 external static bit(1) array level 3 packed packed unaligned dcl 4-6 ref 97 store_a_index 000106 automatic fixed bin(5,0) dcl 35 set ref 85* 89* 95* 97 store_a_online 2(02) 000034 external static bit(1) array level 3 packed packed unaligned dcl 4-6 ref 95 store_b1_online 2(05) 000034 external static bit(1) array level 3 packed packed unaligned dcl 4-6 ref 101 store_b_index 000107 automatic fixed bin(5,0) dcl 35 set ref 86* 90* 99* 101 store_b_is_lower 2(06) 000034 external static bit(1) array level 3 packed packed unaligned dcl 4-6 ref 84 store_b_online 2(04) 000034 external static bit(1) array level 3 packed packed unaligned dcl 4-6 ref 99 store_name parameter char(2) packed unaligned dcl 145 set ref 143 152 162* syndrome 1(06) based bit(8) level 2 packed packed unaligned dcl 3-111 ref 159 syserr 000016 constant entry external dcl 49 ref 109 135 syserr$binary 000020 constant entry external dcl 50 ref 162 tc_data$mos_polling_interval 000024 external static fixed bin(17,0) dcl 53 set ref 117 131 134* 174 175 tc_data$mos_polling_time 000022 external static fixed bin(52,0) dcl 52 set ref 71* 118* 174* 175* time 000105 automatic fixed bin(17,0) dcl 34 set ref 129* 130 134 135 135* 135 NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. BEEP internal static fixed bin(17,0) initial dcl 1-7 BULK_PORT internal static fixed bin(17,0) initial dcl 4-176 CPU_PORT internal static fixed bin(17,0) initial dcl 4-176 CRASH internal static fixed bin(17,0) initial dcl 1-7 IOM_PORT internal static fixed bin(17,0) initial dcl 4-176 LOG internal static fixed bin(17,0) initial dcl 1-7 SBL_access_audit internal static fixed bin(17,0) initial dcl 2-47 SBL_config_deck internal static fixed bin(17,0) initial dcl 2-47 SBL_disk_err internal static fixed bin(17,0) initial dcl 2-47 SBL_end_of_table internal static fixed bin(17,0) initial dcl 2-47 SBL_fnp_poll internal static fixed bin(17,0) initial dcl 2-47 SBL_hw_fault internal static fixed bin(17,0) initial dcl 2-47 SBL_ibm3270_mde internal static fixed bin(17,0) initial dcl 2-47 SBL_io_err internal static fixed bin(17,0) initial dcl 2-47 SBL_io_err_detail internal static fixed bin(17,0) initial dcl 2-47 SBL_mdc_del_uidpath internal static fixed bin(17,0) initial dcl 2-47 SBL_mmdam internal static fixed bin(17,0) initial dcl 2-47 SBL_mpc_poll internal static fixed bin(17,0) initial dcl 2-47 SBL_ocdcm_err internal static fixed bin(17,0) initial dcl 2-47 SBL_random_segdamage internal static fixed bin(17,0) initial dcl 2-47 SBL_read_nc internal static fixed bin(17,0) initial dcl 2-47 SBL_unused_10 internal static fixed bin(17,0) initial dcl 2-47 SBL_unused_12 internal static fixed bin(17,0) initial dcl 2-47 SBL_unused_14 internal static fixed bin(17,0) initial dcl 2-47 SBL_unused_15 internal static fixed bin(17,0) initial dcl 2-47 SBL_unused_18 internal static fixed bin(17,0) initial dcl 2-47 SBL_unused_4 internal static fixed bin(17,0) initial dcl 2-47 SBL_unused_6 internal static fixed bin(17,0) initial dcl 2-47 SBL_unused_7 internal static fixed bin(17,0) initial dcl 2-47 SBL_unused_8 internal static fixed bin(17,0) initial dcl 2-47 SBL_unused_9 internal static fixed bin(17,0) initial dcl 2-47 SBL_verify_lock internal static fixed bin(17,0) initial dcl 2-47 SBL_vtoc_salv_dam internal static fixed bin(17,0) initial dcl 2-47 SBL_vtoce internal static fixed bin(17,0) initial dcl 2-47 SBL_zerpag internal static fixed bin(17,0) initial dcl 2-47 SB_access_audit internal static fixed bin(17,0) initial dcl 2-47 SB_access_audit_data_class internal static varying char(16) initial dcl 2-21 SB_char_data_classes internal static varying char(16) initial array dcl 2-89 SB_config_deck internal static fixed bin(17,0) initial dcl 2-47 SB_config_deck_data_class internal static varying char(16) initial dcl 2-21 SB_disk_err internal static fixed bin(17,0) initial dcl 2-47 SB_end_of_table internal static fixed bin(17,0) initial dcl 2-47 SB_fnp_poll internal static fixed bin(17,0) initial dcl 2-47 SB_fnp_poll_data_class internal static varying char(16) initial dcl 2-21 SB_hw_fault internal static fixed bin(17,0) initial dcl 2-47 SB_hwfault_data_class internal static varying char(16) initial dcl 2-21 SB_ibm3270_mde internal static fixed bin(17,0) initial dcl 2-47 SB_ibm3270_mde_data_class internal static varying char(16) initial dcl 2-21 SB_io_err internal static fixed bin(17,0) initial dcl 2-47 SB_io_err_detail internal static fixed bin(17,0) initial dcl 2-47 SB_io_status_data_class internal static varying char(16) initial dcl 2-21 SB_mdc_del_uidpath internal static fixed bin(17,0) initial dcl 2-47 SB_mdc_del_uidpath_data_class internal static varying char(16) initial dcl 2-21 SB_mmdam internal static fixed bin(17,0) initial dcl 2-47 SB_mmdam_data_class internal static varying char(16) initial dcl 2-21 SB_mos_data_class internal static varying char(16) initial dcl 2-21 SB_mpc_poll internal static fixed bin(17,0) initial dcl 2-47 SB_mpc_poll_data_class internal static varying char(16) initial dcl 2-21 SB_ocdcm_err internal static fixed bin(17,0) initial dcl 2-47 SB_random_segdamage internal static fixed bin(17,0) initial dcl 2-47 SB_read_nc internal static fixed bin(17,0) initial dcl 2-47 SB_segdamage_data_class internal static varying char(16) initial dcl 2-21 SB_unused_10 internal static fixed bin(17,0) initial dcl 2-47 SB_unused_12 internal static fixed bin(17,0) initial dcl 2-47 SB_unused_14 internal static fixed bin(17,0) initial dcl 2-47 SB_unused_15 internal static fixed bin(17,0) initial dcl 2-47 SB_unused_18 internal static fixed bin(17,0) initial dcl 2-47 SB_unused_4 internal static fixed bin(17,0) initial dcl 2-47 SB_unused_6 internal static fixed bin(17,0) initial dcl 2-47 SB_unused_7 internal static fixed bin(17,0) initial dcl 2-47 SB_unused_8 internal static fixed bin(17,0) initial dcl 2-47 SB_unused_9 internal static fixed bin(17,0) initial dcl 2-47 SB_verify_lock internal static fixed bin(17,0) initial dcl 2-47 SB_voldamage_data_class internal static varying char(16) initial dcl 2-21 SB_vtoc_salv_dam internal static fixed bin(17,0) initial dcl 2-47 SB_vtoce internal static fixed bin(17,0) initial dcl 2-47 SB_vtoce_data_class internal static varying char(16) initial dcl 2-21 SB_zerpag internal static fixed bin(17,0) initial dcl 2-47 SC_CFG internal static fixed bin(6,0) initial dcl 3-9 SC_ETC internal static fixed bin(6,0) initial dcl 3-9 SC_IC internal static fixed bin(6,0) initial dcl 3-9 SC_MR internal static fixed bin(6,0) initial dcl 3-9 SC_MSK internal static fixed bin(6,0) initial dcl 3-9 SYSERR_COVERT_CHANNEL internal static fixed bin(17,0) initial dcl 1-7 SYSERR_CRASH_SYSTEM internal static fixed bin(17,0) initial dcl 1-7 SYSERR_LOG_OR_DISCARD internal static fixed bin(17,0) initial dcl 1-7 SYSERR_LOG_OR_PRINT internal static fixed bin(17,0) initial dcl 1-7 SYSERR_PRINT_ON_CONSOLE internal static fixed bin(17,0) initial dcl 1-7 SYSERR_PRINT_WITH_ALARM internal static fixed bin(17,0) initial dcl 1-7 SYSERR_RING1_ERROR internal static fixed bin(17,0) initial dcl 1-7 SYSERR_SUCCESSFUL_ACCESS internal static fixed bin(17,0) initial dcl 1-7 SYSERR_SYSTEM_ERROR internal static fixed bin(17,0) initial dcl 1-7 SYSERR_TERMINATE_PROCESS internal static fixed bin(17,0) initial dcl 1-7 SYSERR_UNSUCCESSFUL_ACCESS internal static fixed bin(17,0) initial dcl 1-7 TERMINATE_PROCESS internal static fixed bin(17,0) initial dcl 1-7 display_cpu_error_binary_defs internal static fixed bin(17,0) initial array dcl 2-144 scr_cfg1 based structure level 1 dcl 3-19 scr_cfg2 based structure level 1 dcl 3-45 scr_mr based structure level 1 dcl 3-74 scr_msk based structure level 1 dcl 3-100 scs$bos_processor_tag external static fixed bin(3,0) dcl 4-137 scs$bos_restart_flags external static bit(8) dcl 4-135 scs$cam_pair external static fixed bin(71,0) dcl 4-103 scs$cam_wait external static bit(8) dcl 4-104 scs$cfg_data external static fixed bin(71,0) array dcl 4-150 scs$cfg_data_save external static fixed bin(71,0) dcl 4-152 scs$connect_lock external static bit(36) dcl 4-132 scs$controller_config_size external static fixed bin(14,0) array dcl 4-164 scs$cow external static structure array level 1 dcl 4-65 scs$cow_ptrs external static structure array level 1 dcl 4-77 scs$cpu_test_mask external static bit(72) dcl 4-96 scs$cpu_test_pattern external static bit(36) dcl 4-99 scs$cycle_priority_template external static bit(7) dcl 4-172 scs$expanded_ports external static bit(1) array packed unaligned dcl 4-154 scs$fast_cam_pending external static bit(36) array dcl 4-140 scs$faults_initialized external static bit(1) dcl 4-138 scs$idle_aptep external static pointer array packed unaligned dcl 4-130 scs$interrupt_controller external static fixed bin(3,0) dcl 4-141 scs$mask_ptr external static pointer array packed unaligned dcl 4-110 scs$nprocessors external static fixed bin(17,0) dcl 4-136 scs$number_of_masks external static fixed bin(17,0) dcl 4-97 scs$open_level external static bit(72) dcl 4-94 scs$port_addressing_word external static bit(3) array dcl 4-148 scs$port_data external static structure array level 1 dcl 4-56 scs$processor external static bit(8) dcl 4-143 scs$processor_data external static structure array level 1 dcl 4-35 scs$processor_data_switch_value external static bit(36) dcl 4-162 scs$processor_start_int_no external static fixed bin(5,0) dcl 4-142 scs$processor_start_mask external static bit(72) dcl 4-95 scs$processor_start_pattern external static bit(36) dcl 4-98 scs$processor_start_wait external static bit(8) dcl 4-144 scs$processor_switch_compare external static bit(36) array dcl 4-159 scs$processor_switch_data external static bit(36) array dcl 4-157 scs$processor_switch_mask external static bit(36) array dcl 4-160 scs$processor_switch_template external static bit(36) array dcl 4-158 scs$processor_test_data external static structure level 1 dcl 4-114 scs$read_mask external static bit(36) array dcl 4-109 scs$reconfig_general_cow external static structure level 1 dcl 4-82 scs$scas_page_table external static bit(36) array dcl 4-169 scs$set_cycle_switches external static bit(1) dcl 4-173 scs$set_mask external static bit(36) array dcl 4-108 scs$sys_level external static bit(72) dcl 4-93 scs$sys_trouble_pending external static bit(1) dcl 4-139 scs$trouble_dbrs automatic fixed bin(71,0) array dcl 4-146 scs$trouble_flags external static bit(8) dcl 4-134 syserr_binary_address_damage_mask internal static bit(36) initial packed unaligned dcl 2-142 syserr_binary_mos_mask internal static bit(36) initial packed unaligned dcl 2-139 syserr_binary_seg_damage_mask internal static bit(36) initial packed unaligned dcl 2-140 syserr_binary_vol_damage_mask internal static bit(36) initial packed unaligned dcl 2-141 NAMES DECLARED BY EXPLICIT CONTEXT. check_store 000457 constant entry internal dcl 143 ref 95 97 99 101 clean_up 000651 constant entry internal dcl 182 ref 66 mos_memory_check 000117 constant entry external dcl 23 poll 000355 constant entry external dcl 115 reschedule 000626 constant entry internal dcl 172 ref 108 137 set_poll_time 000377 constant entry external dcl 127 start 000127 constant label dcl 66 ref 122 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 1122 1164 712 1132 Length 1452 712 42 252 207 2 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME mos_memory_check 222 external procedure is an external procedure. on unit on line 66 71 on unit check_store internal procedure shares stack frame of external procedure mos_memory_check. reschedule internal procedure shares stack frame of external procedure mos_memory_check. clean_up internal procedure shares stack frame of on unit on line 66. STORAGE FOR INTERNAL STATIC VARIABLES. LOC IDENTIFIER BLOCK NAME 000010 spoke mos_memory_check STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME mos_memory_check 000100 port mos_memory_check 000102 rscr_result mos_memory_check 000104 poll_entry mos_memory_check 000105 time mos_memory_check 000106 store_a_index mos_memory_check 000107 store_b_index mos_memory_check 000110 mem mos_memory_check 000111 aloud mos_memory_check 000120 scrp mos_memory_check 000130 id check_store on unit on line 66 000106 ignore clean_up THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. r_e_as r_ne_as call_ext_out_desc call_ext_out return_mac stac_mac enable_op ext_entry int_entry stacq_mac THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. clock_ privileged_mode_ut$rscr syserr syserr$binary THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. error_table_$lock_wait_time_exceeded pds$process_group_id pds$processid scs$controller_data scs$reconfig_lock scs$reconfig_locker_id tc_data$mos_polling_interval tc_data$mos_polling_time LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 33 000107 23 000112 64 000125 66 000127 70 000145 71 000154 72 000171 73 000174 75 000175 79 000202 81 000204 83 000211 84 000217 85 000223 86 000225 87 000227 89 000230 90 000233 93 000235 95 000242 97 000252 99 000270 101 000303 106 000321 108 000323 109 000326 111 000353 115 000354 117 000363 118 000366 119 000370 121 000371 122 000373 127 000374 129 000405 130 000410 131 000411 132 000414 134 000415 135 000417 137 000455 138 000456 143 000457 149 000461 150 000476 151 000500 152 000507 153 000516 156 000521 157 000526 159 000542 160 000545 160 000557 161 000561 162 000564 166 000625 172 000626 174 000627 175 000635 177 000650 182 000651 186 000652 187 000660 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved