ASSEMBLY LISTING OF SEGMENT >spec>install>1111>parity_check.alm ASSEMBLED ON: 11/11/89 0922.9 mst Sat OPTIONS USED: -target l68 list symbols ASSEMBLED BY: ALM Version 8.14 March 1989 ASSEMBLER CREATED: 06/09/89 1002.3 mst Fri 1 " *********************************************************** 2 " * * 3 " * Copyright, (C) Honeywell Bull Inc., 1987 * 4 " * * 5 " * Copyright, (C) Honeywell Information Systems Inc., 1982 * 6 " * * 7 " * Copyright (c) 1972 by Massachusetts Institute of * 8 " * Technology and Honeywell Information Systems, Inc. * 9 " * * 10 " *********************************************************** 000000 11 name parity_check 12 000000 13 entry parity_check 000010 14 entry set_parity_mask 000015 15 entry reset_parity_mask 16 17 " Last Modified by RBSnyder 02/14/73 for follow-on 18 19 " 20 " call parity_check(loc, word, check) 21 " 22 " loc pointer pointer to parity cell 23 " word bit(36) contents of cell indicating parity 24 " check fixed bin = 0 if no parity 25 " 26 " 27 " This routine is called to validate the existence of a parity error 28 " by re-accessing the word in question. 29 " It is used by the software to verify that the 30 " condition was in fact a memory parity error. 31 " 32 " 33 " 34 " 35 " call set_parity_mask 36 " 37 " This entry is used to set the parity mask indicator in 38 " the caller's indicators. 39 " 40 " 41 " call reset_parity_mask 42 " 43 " This entry is the reverse of the one above 44 " 45 46 include mc 1-1 " 1-2 " BEGIN INCLUDE FILE mc.incl.alm 6/72 SHW 1-3 " Modified 8/80 by J. A. Bush for dps8/70M CPU 1-4 " 1-5 1-6 " General layout of data items. 1-7 000000 1-8 equ mc.prs,0 pointer registers 000020 1-9 equ mc.regs,16 registers 000030 1-10 equ mc.scu,24 SCU data 000050 1-11 equ mc.eis_info,40 pointers and lengths for EIS 1-12 1-13 " Temporary storage for software 1-14 000040 1-15 equ mc.mask,32 system controller mask at time of fault 000042 1-16 equ mc.ips_temp,34 temporary storage for IPS info 000043 1-17 equ mc.errcode,35 error code 000044 1-18 equ mc.fim_temp,36 temporary to hold fault index and unique index 000045 1-19 equ mc.fault_reg,37 fault register 000046 1-20 equ mc.fault_time,38 time of fault 000046 1-21 equ mc.cpu_type_word,38 CPU type from rsw (2). overlays part of time word 300000 1-22 bool mc.cpu_type_mask,300000 DU 000046 1-23 equ mc.ext_fault_reg,38 ext fault reg for dps8. overlays part of time word 077774 1-24 bool mc.ext_fault_reg_mask,77774 DU 000003 1-25 equ mc.cpu_type_shift,3 positions to shift right or left 1-26 1-27 1-28 1-29 " SCU DATA 1-30 1-31 " WORD (0) PROCEDURE POINTER REGISTER 1-32 000030 1-33 equ mc.scu.ppr.prr_word,24 Procedure Ring Register 000000 1-34 equ scu.ppr.prr_word,0 700000 1-35 bool scu.ppr.prr_mask,700000 DU 000041 1-36 equ scu.ppr.prr_shift,33 1-37 000030 1-38 equ mc.scu.ppr.psr_word,24 Procedure Segment Register 000000 1-39 equ scu.ppr.psr_word,0 077777 1-40 bool scu.ppr.psr_mask,077777 DU 000022 1-41 equ scu.ppr.psr_shift,18 1-42 000030 1-43 equ mc.scu.ppr.p_word,24 Procedure Privileged Bit 000000 1-44 equ scu.ppr.p_word,0 400000 1-45 bool scu.ppr.p,400000 DL 1-46 1-47 " APPENDING UNIT STATUS 000030 1-48 equ mc.scu.apu_stat_word,24 APPENDING UNIT STATUS 000000 1-49 equ scu.apu_stat_word,0 1-50 200000 1-51 bool scu.apu.xsf,200000 DL - Ext Seg Flag - IT mod. 100000 1-52 bool scu.apu.sdwm,100000 DL - Match in SDW Ass. Mem. 040000 1-53 bool scu.apu.sd_on,040000 DL - SDW Ass. Mem. ON 020000 1-54 bool scu.apu.ptwm,020000 DL - Match in PTW Ass. Mem. 010000 1-55 bool scu.apu.pt_on,010000 DL - PTW Ass. Mem. ON 004000 1-56 bool scu.apu.pi_ap,004000 DL - Instr fetch or Append cycle 002000 1-57 bool scu.apu.dsptw,002000 DL - Fetch of DSPTW 001000 1-58 bool scu.apu.sdwnp,001000 DL - Fetch of SDW non-paged 000400 1-59 bool scu.apu.sdwp,000400 DL - Fetch of SDW paged 000200 1-60 bool scu.apu.ptw,000200 DL - Fetch of PTW 000100 1-61 bool scu.apu.ptw2,000100 DL - Fetch of pre-paged PTW 000040 1-62 bool scu.apu.fap,000040 DL - Fetch of final address paged 000020 1-63 bool scu.apu.fanp,000020 DL - Fetch final address non-paged 000010 1-64 bool scu.apu.fabs,000010 DL - Fetch of final address absolute 1-65 000030 1-66 equ mc.scu.fault_cntr_word,24 Num of retrys of EIS instructions. 000000 1-67 equ scu.fault_cntr_word,0 1-68 000007 1-69 bool scu.fault_cntr_mask,000007 1-70 1-71 1-72 " WORD (1) FAULT DATA 1-73 000031 1-74 equ mc.scu.fault_data_word,25 FAULT DATA 000001 1-75 equ scu.fault_data_word,1 1-76 400000 1-77 bool scu.fd.iro,400000 DU - Illegal Ring Order 200000 1-78 bool scu.fd.oeb,200000 DU - Not In Execute Bracket 100000 1-79 bool scu.fd.e_off,100000 DU - No Execute 040000 1-80 bool scu.fd.orb,040000 DU - Not In Read Bracket 020000 1-81 bool scu.fd.r_off,020000 DU - No Read 010000 1-82 bool scu.fd.owb,010000 DU - Not In Write Bracket 004000 1-83 bool scu.fd.w_off,004000 DU - No Write 002000 1-84 bool scu.fd.no_ga,002000 DU - Not A Gate 001000 1-85 bool scu.fd.ocb,001000 DU - Not in Call Bracket 000400 1-86 bool scu.fd.ocall,000400 DU - Outward Call 000200 1-87 bool scu.fd.boc,000200 DU - Bad Outward Call 000100 1-88 bool scu.fd.inret,000100 DU - Inward Return 000040 1-89 bool scu.fd.crt,000040 DU - Cross Ring Transfer 000020 1-90 bool scu.fd.ralr,000020 DU - Ring Alarm 000010 1-91 bool scu.fd.am_er,000010 DU - Assoc. Mem. Fault 000004 1-92 bool scu.fd.oosb,000004 DU - Out Of Bounds 000002 1-93 bool scu.fd.paru,000002 DU - Parity Upper 000001 1-94 bool scu.fd.parl,000001 DU - Parity Lower 1-95 400000 1-96 bool scu.fd.onc_1,400000 DL - Op Not Complete 200000 1-97 bool scu.fd.onc_2,200000 DL - Op Not Complete 1-98 1-99 " GROUP II FAULT DATA 400000 1-100 bool scu.fd.isn,400000 DU - Illegal Segment Number 200000 1-101 bool scu.fd.ioc,200000 DU - Illegal Op Code 100000 1-102 bool scu.fd.ia_im,100000 DU - Illegal Addr - Modifier 040000 1-103 bool scu.fd.isp,040000 DU - Illegal Slave Procedure 020000 1-104 bool scu.fd.ipr,020000 DU - Illegal Procedure 010000 1-105 bool scu.fd.nea,010000 DU - Non Existent Address 004000 1-106 bool scu.fd.oobb,004000 DU - Out Of Bounds 1-107 000031 1-108 equ mc.scu.port_stat_word,25 PORT STATUS 000001 1-109 equ scu.port_stat_word,1 1-110 170000 1-111 bool scu.ial_mask,170000 DL - Illegal Action Lines 000014 1-112 equ scu.ial_shift,12 1-113 007000 1-114 bool scu.iac_mask,007000 DL - Illegal Action Channel 000011 1-115 equ scu.iac_shift,9 1-116 000700 1-117 bool scu.con_chan_mask,000700 DL - Connect Channel 000006 1-118 equ scu.con_chan_shift,6 1-119 000076 1-120 bool scu.fi_num_mask,000076 DL - Fault / Interrupt Number 000001 1-121 equ scu.fi_num_shift,1 1-122 000001 1-123 bool scu.fi_flag_mask,000001 DL - Fault / Interrupt Flag 1-124 1-125 1-126 " WORD (2) TEMPORARY POINTER REGISTER 1-127 000032 1-128 equ mc.scu.tpr.trr_word,26 Temporary Ring Register 000002 1-129 equ scu.tpr.trr_word,2 700000 1-130 bool scu.tpr.trr_mask,700000 DU 000041 1-131 equ scu.tpr.trr_shift,33 1-132 000032 1-133 equ mc.scu.tpr.tsr_word,26 Temporary Segment Register 000002 1-134 equ scu.tpr.tsr_word,2 077777 1-135 bool scu.tpr.tsr_mask,077777 DU 000022 1-136 equ scu.tpr.tsr_shift,18 1-137 000032 1-138 equ mc.scu.cpu_no_word,26 CPU Number 000002 1-139 equ scu.cpu_no_word,2 1-140 000700 1-141 bool scu.cpu_no_mask,000700 DL 000006 1-142 equ scu.cpu_shift,6 1-143 000032 1-144 equ mc.scu.delta_word,26 Tally Modification DELTA 000002 1-145 equ scu.delta_word,2 1-146 000077 1-147 bool scu.delta_mask,000077 DL 1-148 1-149 1-150 " WORD (3) TSR STATUS 1-151 000033 1-152 equ mc.scu.tsr_stat_word,27 TSR STATUS for 1,2, and 3 000003 1-153 equ scu.tsr_stat_word,3 Word Instructions 1-154 777700 1-155 bool scu.tsr_stat_mask,777700 DL - All of Status 000006 1-156 equ scu.tsr_stat_shift,6 1-157 740000 1-158 bool scu.tsna_mask,740000 DL - Word 1 Status 700000 1-159 bool scu.tsna.prn_mask,700000 DL - Word 1 PR num 000017 1-160 equ scu.tsna.prn_shift,15 040000 1-161 bool scu.tsna.prv,040000 DL - Word 1 PR valid bit 1-162 036000 1-163 bool scu.tsnb_mask,036000 DL - Word 2 Status 034000 1-164 bool scu.tsnb.prn_mask,034000 DL - Word 2 PR num 000013 1-165 equ scu.tsnb.prn_shift,11 002000 1-166 bool scu.tsnb.prv,002000 DL - Word 2 PR valid bit 1-167 000013 1-168 bool scu.tsnc_mask,0013 DL - Word 3 Status 001600 1-169 bool scu.tsnc.prn_mask,001600 DL - Word 3 PR num 000007 1-170 equ scu.tsnc.prn_shift,7 000100 1-171 bool scu.tsnc.prv,000100 DL - Word 3 PR valid bit 1-172 1-173 000033 1-174 equ mc.scu.tpr.tbr_word,27 TPR.TBR Field 000003 1-175 equ scu.tpr.tbr_word,3 1-176 000077 1-177 bool scu.tpr.tbr_mask,000077 DL 1-178 1-179 1-180 " WORD (4) INSTRUCTION COUNTER 1-181 000034 1-182 equ mc.scu.ilc_word,28 INSTRUCTION COUNTER 000004 1-183 equ scu.ilc_word,4 000022 1-184 equ scu.ilc_shift,18 1-185 000034 1-186 equ mc.scu.indicators_word,28 INDICATOR REGISTERS 000004 1-187 equ scu.indicators_word,4 1-188 400000 1-189 bool scu.ir.zero,400000 DL - Zero Indicator 200000 1-190 bool scu.ir.neg,200000 DL - Negative Indicator 100000 1-191 bool scu.ir.carry,100000 DL - Carry Indicator 040000 1-192 bool scu.ir.ovfl,040000 DL - Overflow Indicator 020000 1-193 bool scu.ir.eovf,020000 DL - Exponent Overflow Ind 010000 1-194 bool scu.ir.eufl,010000 DL - Exponent Underflow Ind 004000 1-195 bool scu.ir.oflm,004000 DL - Overflow Mask Indicator 002000 1-196 bool scu.ir.tro,002000 DL - Tally Runout Indicator 001000 1-197 bool scu.ir.par,001000 DL - Parity Indicator 000400 1-198 bool scu.ir.parm,000400 DL - Parity Mask Indicator 000200 1-199 bool scu.ir.bm,000200 DL - Bar Mode Indicator 000100 1-200 bool scu.ir.tru,000100 DL - Truncation Indicator 000040 1-201 bool scu.ir.mif,000040 DL - Multiword Indicator 000020 1-202 bool scu.ir.abs,000020 DL - Absolute Indicator 000010 1-203 bool scu.ir.hex,000010 DL - Hexadecimal Indicator 1-204 1-205 " WORD (5) COMPUTED ADDRESS 1-206 000035 1-207 equ mc.scu.ca_word,29 COMPUTED ADDRESS 000005 1-208 equ scu.ca_word,5 000022 1-209 equ scu.ca_shift,18 1-210 000035 1-211 equ mc.scu.cu_stat_word,29 CONTROL UNIT STATUS 000005 1-212 equ scu.cu_stat_word,5 1-213 400000 1-214 bool scu.cu.rf,400000 DL - Repeat First 1-215 " On First Cycle of Repeat Inst. 200000 1-216 bool scu.cu.rpt,200000 DL - Repeat Instruction 100000 1-217 bool scu.cu.rd,100000 DL - Repeat Double Instr. 040000 1-218 bool scu.cu.rl,040000 DL - Repeat Link Instr. 1-219 020000 1-220 bool scu.cu.pot,020000 DL - IT Modification 010000 1-221 bool scu.cu.pon,010000 DL - Return Type Instruction 1-222 004000 1-223 bool scu.cu.xde,004000 DL - XDE from Even Location 002000 1-224 bool scu.cu.xdo,002000 DL - XDE from Odd Location 1-225 001000 1-226 bool scu.cu.poa,001000 DL - Operand Preparation 000400 1-227 bool scu.cu.rfi,000400 DL - Tells CPU to refetch instruction 1-228 " This Bit Not Used (000200) 000100 1-229 bool scu.cu.if,000100 DL - Fault occurred during instruction fetch 1-230 000035 1-231 equ mc.scu.cpu_tag_word,29 Computed Tag Field 000005 1-232 equ scu.cpu_tag_word,5 1-233 000007 1-234 bool scu.cpu_tag_mask,000007 DL 1-235 1-236 1-237 " WORDS (6,7) INSTRUCTIONS 1-238 000036 1-239 equ scu.even_inst_word,30 Even Instruction 1-240 000037 1-241 equ scu.odd_inst_word,31 Odd Instruction 1-242 1-243 1-244 " END INCLUDE FILE incl.alm 47 " 48 000000 49 parity_check: 000000 aa 000400 6340 07 50 ldi scu.ir.parm,dl Set mask 000001 aa 0 00002 3521 20 51 eppbp ap|2,* Pick up pointer to cell 000002 aa 2 00000 2351 20 52 lda bp|0,* Read from cell 000003 aa 0 00004 7551 20 53 sta ap|4,* Return contents 000004 aa 0 00006 7541 20 54 sti ap|6,* Store indicators into return arg 000005 aa 001000 2350 07 55 lda scu.ir.par,dl Pick up mask 000006 aa 0 00006 3551 20 56 ansa ap|6,* If error occured, will be non-zero 000007 aa 7 00044 7101 20 57 short_return 58 000010 59 set_parity_mask: 000010 aa 6 00000 7541 00 60 sti sp|0 store the current indicators 000011 aa 000400 2350 07 61 lda scu.ir.parm,dl Pick up masking bit 000012 aa 6 00000 2551 00 62 orsa sp|0 store into stored indicators 000013 aa 6 00000 6341 00 63 ldi sp|0 reload indicators 000014 aa 7 00044 7101 20 64 short_return 65 000015 66 reset_parity_mask: 000015 aa 6 00000 7541 00 67 sti sp|0 save current indicators 000016 aa 000401 3350 07 68 lca scu.ir.parm+1,dl Form 1-s complement of mask 000017 aa 6 00000 3551 00 69 ansa sp|0 and delete the bit 000020 aa 6 00000 6341 00 70 ldi sp|0 get new indicators 000021 aa 7 00044 7101 20 71 short_return 72 73 end parity_check ENTRY SEQUENCES 000022 5a 000031 0000 00 000023 aa 7 00046 2721 20 000024 0a 000000 7100 00 000025 5a 000022 0000 00 000026 aa 7 00046 2721 20 000027 0a 000010 7100 00 000030 5a 000012 0000 00 000031 aa 7 00046 2721 20 000032 0a 000015 7100 00 NO LITERALS NAME DEFINITIONS FOR ENTRY POINTS AND SEGDEFS 000034 5a 000003 000000 000035 5a 000047 600000 000036 aa 000000 000000 000037 55 000012 000002 000040 5a 000002 400003 000041 55 000006 000012 000042 aa 014 160 141 162 000043 aa 151 164 171 137 000044 aa 143 150 145 143 000045 aa 153 000 000 000 000046 55 000022 000003 000047 0a 000031 500000 000050 55 000015 000003 000051 aa 021 162 145 163 reset_parity_mask 000052 aa 145 164 137 160 000053 aa 141 162 151 164 000054 aa 171 137 155 141 000055 aa 163 153 000 000 000056 55 000031 000012 000057 0a 000026 500000 000060 55 000025 000003 000061 aa 017 163 145 164 set_parity_mask 000062 aa 137 160 141 162 000063 aa 151 164 171 137 000064 aa 155 141 163 153 000065 55 000040 000022 000066 0a 000023 500000 000067 55 000034 000003 000070 aa 014 160 141 162 parity_check 000071 aa 151 164 171 137 000072 aa 143 150 145 143 000073 aa 153 000 000 000 000074 55 000002 000031 000075 6a 000000 400002 000076 55 000043 000003 000077 aa 014 163 171 155 symbol_table 000100 aa 142 157 154 137 000101 aa 164 141 142 154 000102 aa 145 000 000 000 DEFINITIONS HASH TABLE 000103 aa 000000 000015 000104 aa 000000 000000 000105 aa 000000 000000 000106 5a 000022 000000 000107 aa 000000 000000 000110 aa 000000 000000 000111 5a 000012 000000 000112 5a 000040 000000 000113 aa 000000 000000 000114 aa 000000 000000 000115 aa 000000 000000 000116 aa 000000 000000 000117 5a 000031 000000 000120 aa 000000 000000 NO EXTERNAL NAMES NO TRAP POINTER WORDS TYPE PAIR BLOCKS 000121 aa 000001 000000 000122 aa 000000 000000 INTERNAL EXPRESSION WORDS 000123 aa 000000 000000 LINKAGE INFORMATION 000000 aa 000000 000000 000001 0a 000034 000000 000002 aa 000000 000000 000003 aa 000000 000000 000004 aa 000000 000000 000005 aa 000000 000000 000006 22 000010 000010 000007 a2 000000 000000 SYMBOL INFORMATION SYMBOL TABLE HEADER 000000 aa 000000 000001 000001 aa 163171 155142 000002 aa 164162 145145 000003 aa 000000 000010 000004 aa 000000 117244 000005 aa 361023 525721 000006 aa 000000 117547 000007 aa 241463 606031 000010 aa 141154 155040 000011 aa 040040 040040 000012 aa 000024 000040 000013 aa 000034 000040 000014 aa 000044 000100 000015 aa 000002 000002 000016 aa 000064 000000 000017 aa 000000 000145 000020 aa 000000 000115 000021 aa 000125 000122 000022 aa 000136 000115 000023 aa 000064 000000 000024 aa 101114 115040 000025 aa 126145 162163 000026 aa 151157 156040 000027 aa 070056 061064 000030 aa 040115 141162 000031 aa 143150 040061 000032 aa 071070 071040 000033 aa 040040 040040 000034 aa 110151 162156 000035 aa 145151 163145 000036 aa 156056 123171 000037 aa 163115 141151 000040 aa 156164 056141 000041 aa 040040 040040 000042 aa 040040 040040 000043 aa 040040 040040 000044 aa 055164 141162 000045 aa 147145 164040 000046 aa 154066 070040 000047 aa 040040 040040 000050 aa 040040 040040 000051 aa 040040 040040 000052 aa 040040 040040 000053 aa 040040 040040 000054 aa 040040 040040 000055 aa 040040 040040 000056 aa 040154 151163 000057 aa 164040 163171 000060 aa 155142 157154 000061 aa 163040 040040 000062 aa 040040 040040 000063 aa 040040 040040 000064 aa 000000 000001 000065 aa 000000 000002 000066 aa 000076 000043 000067 aa 175453 017704 000070 aa 000000 117547 000071 aa 176205 000000 000072 aa 000107 000030 000073 aa 123154 505731 000074 aa 000000 112316 000075 aa 133412 600000 000076 aa 076163 160145 >spec>install>1111>parity_check.alm 000077 aa 143076 151156 000100 aa 163164 141154 000101 aa 154076 061061 000102 aa 061061 076160 000103 aa 141162 151164 000104 aa 171137 143150 000105 aa 145143 153056 000106 aa 141154 155040 000107 aa 076154 144144 >ldd>include>mc.incl.alm 000110 aa 076151 156143 000111 aa 154165 144145 000112 aa 076155 143056 000113 aa 151156 143154 000114 aa 056141 154155 MULTICS ASSEMBLY CROSS REFERENCE LISTING Value Symbol Source file Line number 300000 mc.cpu_type_mask mc: 22. 3 mc.cpu_type_shift mc: 25. 46 mc.cpu_type_word mc: 21. 50 mc.eis_info mc: 11. 43 mc.errcode mc: 17. 46 mc.ext_fault_reg mc: 23. 77774 mc.ext_fault_reg_mask mc: 24. 45 mc.fault_reg mc: 19. 46 mc.fault_time mc: 20. 44 mc.fim_temp mc: 18. 42 mc.ips_temp mc: 16. 40 mc.mask mc: 15. 0 mc.prs mc: 8. 20 mc.regs mc: 9. 30 mc.scu mc: 10. 30 mc.scu.apu_stat_word mc: 48. 35 mc.scu.ca_word mc: 207. 32 mc.scu.cpu_no_word mc: 138. 35 mc.scu.cpu_tag_word mc: 231. 35 mc.scu.cu_stat_word mc: 211. 32 mc.scu.delta_word mc: 144. 30 mc.scu.fault_cntr_word mc: 66. 31 mc.scu.fault_data_word mc: 74. 34 mc.scu.ilc_word mc: 182. 34 mc.scu.indicators_word mc: 186. 31 mc.scu.port_stat_word mc: 108. 30 mc.scu.ppr.prr_word mc: 33. 30 mc.scu.ppr.psr_word mc: 38. 30 mc.scu.ppr.p_word mc: 43. 33 mc.scu.tpr.tbr_word mc: 174. 32 mc.scu.tpr.trr_word mc: 128. 32 mc.scu.tpr.tsr_word mc: 133. 33 mc.scu.tsr_stat_word mc: 152. 0 parity_check parity_check: 13, 49. 15 reset_parity_mask parity_check: 15, 66. 2000 scu.apu.dsptw mc: 57. 10 scu.apu.fabs mc: 64. 20 scu.apu.fanp mc: 63. 40 scu.apu.fap mc: 62. 4000 scu.apu.pi_ap mc: 56. 200 scu.apu.ptw mc: 60. 100 scu.apu.ptw2 mc: 61. 20000 scu.apu.ptwm mc: 54. 10000 scu.apu.pt_on mc: 55. 100000 scu.apu.sdwm mc: 52. 1000 scu.apu.sdwnp mc: 58. 400 scu.apu.sdwp mc: 59. 40000 scu.apu.sd_on mc: 53. 200000 scu.apu.xsf mc: 51. 0 scu.apu_stat_word mc: 49. 22 scu.ca_shift mc: 209. 5 scu.ca_word mc: 208. 700 scu.con_chan_mask mc: 117. 6 scu.con_chan_shift mc: 118. 700 scu.cpu_no_mask mc: 141. 2 scu.cpu_no_word mc: 139. 6 scu.cpu_shift mc: 142. 7 scu.cpu_tag_mask mc: 234. 5 scu.cpu_tag_word mc: 232. 100 scu.cu.if mc: 229. 1000 scu.cu.poa mc: 226. 10000 scu.cu.pon mc: 221. 20000 scu.cu.pot mc: 220. 100000 scu.cu.rd mc: 217. 400000 scu.cu.rf mc: 214. 400 scu.cu.rfi mc: 227. 40000 scu.cu.rl mc: 218. 200000 scu.cu.rpt mc: 216. 4000 scu.cu.xde mc: 223. 2000 scu.cu.xdo mc: 224. 5 scu.cu_stat_word mc: 212. 77 scu.delta_mask mc: 147. 2 scu.delta_word mc: 145. 36 scu.even_inst_word mc: 239. 7 scu.fault_cntr_mask mc: 69. 0 scu.fault_cntr_word mc: 67. 1 scu.fault_data_word mc: 75. 10 scu.fd.am_er mc: 91. 200 scu.fd.boc mc: 87. 40 scu.fd.crt mc: 89. 100000 scu.fd.e_off mc: 79. 100000 scu.fd.ia_im mc: 102. 100 scu.fd.inret mc: 88. 200000 scu.fd.ioc mc: 101. 20000 scu.fd.ipr mc: 104. 400000 scu.fd.iro mc: 77. 400000 scu.fd.isn mc: 100. 40000 scu.fd.isp mc: 103. 10000 scu.fd.nea mc: 105. 2000 scu.fd.no_ga mc: 84. 400 scu.fd.ocall mc: 86. 1000 scu.fd.ocb mc: 85. 200000 scu.fd.oeb mc: 78. 400000 scu.fd.onc_1 mc: 96. 200000 scu.fd.onc_2 mc: 97. 4000 scu.fd.oobb mc: 106. 4 scu.fd.oosb mc: 92. 40000 scu.fd.orb mc: 80. 10000 scu.fd.owb mc: 82. 1 scu.fd.parl mc: 94. 2 scu.fd.paru mc: 93. 20 scu.fd.ralr mc: 90. 20000 scu.fd.r_off mc: 81. 4000 scu.fd.w_off mc: 83. 1 scu.fi_flag_mask mc: 123. 76 scu.fi_num_mask mc: 120. 1 scu.fi_num_shift mc: 121. 7000 scu.iac_mask mc: 114. 11 scu.iac_shift mc: 115. 170000 scu.ial_mask mc: 111. 14 scu.ial_shift mc: 112. 22 scu.ilc_shift mc: 184. 4 scu.ilc_word mc: 183. 4 scu.indicators_word mc: 187. 20 scu.ir.abs mc: 202. 200 scu.ir.bm mc: 199. 100000 scu.ir.carry mc: 191. 20000 scu.ir.eovf mc: 193. 10000 scu.ir.eufl mc: 194. 10 scu.ir.hex mc: 203. 40 scu.ir.mif mc: 201. 200000 scu.ir.neg mc: 190. 4000 scu.ir.oflm mc: 195. 40000 scu.ir.ovfl mc: 192. 1000 scu.ir.par parity_check: 55, mc: 197. 400 scu.ir.parm parity_check: 50, 61, 68, mc: 198. 2000 scu.ir.tro mc: 196. 100 scu.ir.tru mc: 200. 400000 scu.ir.zero mc: 189. 37 scu.odd_inst_word mc: 241. 1 scu.port_stat_word mc: 109. 400000 scu.ppr.p mc: 45. 700000 scu.ppr.prr_mask mc: 35. 41 scu.ppr.prr_shift mc: 36. 0 scu.ppr.prr_word mc: 34. 77777 scu.ppr.psr_mask mc: 40. 22 scu.ppr.psr_shift mc: 41. 0 scu.ppr.psr_word mc: 39. 0 scu.ppr.p_word mc: 44. 77 scu.tpr.tbr_mask mc: 177. 3 scu.tpr.tbr_word mc: 175. 700000 scu.tpr.trr_mask mc: 130. 41 scu.tpr.trr_shift mc: 131. 2 scu.tpr.trr_word mc: 129. 77777 scu.tpr.tsr_mask mc: 135. 22 scu.tpr.tsr_shift mc: 136. 2 scu.tpr.tsr_word mc: 134. 700000 scu.tsna.prn_mask mc: 159. 17 scu.tsna.prn_shift mc: 160. 40000 scu.tsna.prv mc: 161. 740000 scu.tsna_mask mc: 158. 34000 scu.tsnb.prn_mask mc: 164. 13 scu.tsnb.prn_shift mc: 165. 2000 scu.tsnb.prv mc: 166. 36000 scu.tsnb_mask mc: 163. 1600 scu.tsnc.prn_mask mc: 169. 7 scu.tsnc.prn_shift mc: 170. 100 scu.tsnc.prv mc: 171. 13 scu.tsnc_mask mc: 168. 777700 scu.tsr_stat_mask mc: 155. 6 scu.tsr_stat_shift mc: 156. 3 scu.tsr_stat_word mc: 153. 10 set_parity_mask parity_check: 14, 59. NO FATAL ERRORS ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved