COMPILATION LISTING OF SEGMENT !BBBJZjXjgzwffJ Compiled by: Multics PL/I Compiler, Release 32f, of October 9, 1989 Compiled at: Bull HN, Phoenix AZ, System-M Compiled on: 11/11/89 1006.9 mst Sat Options: table map 1 /* *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Bull Inc., 1987 * 4* * * 5* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 6* * * 7* *********************************************************** */ 8 9 /* PRDS - The Processor Data Segment and Processor Stack. 10* /* Last modified (Date and reason): 11* 2/6/76 by S. Webber Initial coding 12* 6/15/77 by M. Weaver to null signal and sct pointers 13* 8/25/80 by J. A. Bush for the dps8/70m cpu 14* 2/22/81 by J. Bongiovanni for fast_connect_code 15* 6/27/81 by J. Bongiovanni for idle_temp 16* 10/11/83 by R. Coppola to adjust for size change of fast connect code 17* and validate that apt_ptr& ignore_pl are on correct mod 18**/ 19 20 21 /* HISTORY COMMENTS: 22* 1) change(88-05-24,Farley), approve(88-06-30,MCR7927), 23* audit(88-07-12,Fawcett), install(88-08-02,MR12.2-1076): 24* Added fault_reg_last_saved and hregs_last_saved time values, to make sure 25* that the associated data is only saved once per fault. 26* END HISTORY COMMENTS */ 27 28 29 /* ****************************************************** 30* * * 31* * * 32* * Copyright (c) 1972 by Massachusetts Institute of * 33* * Technology and Honeywell Information Systems, Inc. * 34* * * 35* * * 36* ****************************************************** */ 37 38 39 prds: proc; 40 41 /* This program creates the prds data base */ 42 43 /* Automatic */ 44 45 dcl 1 cdsa aligned like cds_args; 46 dcl code fixed bin (35); 47 48 /* Static */ 49 50 dcl prdsname char (4) aligned static init ("prds") options (constant); 51 dcl exclude_pad (1) char (32) aligned static options (constant) init ("pad*"); 52 53 /* The following must correspond to the size of the fast connect code in 54* fast_connect_init */ 55 56 dcl FAST_CONNECT_CODE_WORDS init (72) fixed bin int static options (constant); 57 58 /* Builtins */ 59 60 dcl (addr, bin, mod, rel, size, string, unspec) builtin; 61 62 /* Entries */ 63 64 dcl com_err_ entry options (variable); 65 dcl create_data_segment_ entry (ptr, fixed bin (35)); 66 dcl get_temp_segment_ entry (char (*), ptr, fixed bin (35)); 67 dcl release_temp_segment_ entry (char (*), ptr, fixed bin (35)); 68 69 70 71 72 dcl prdsp ptr; 73 74 dcl 1 prds aligned based (prdsp), 75 2 header aligned like stack_header, /* standard stack header */ 76 2 interrupt_data aligned like mc, /* MC for interrupts */ 77 2 fim_data aligned like mc, /* MC for connect faults, timer runouts */ 78 2 sys_trouble_data aligned like mc, /* MC for saved sys trouble data */ 79 2 ignore_data aligned like scu, /* for SCU data to be ignored at certain times */ 80 2 iitemp fixed bin (71), /* temporary used by ii (surprise!) */ 81 2 last_recorded_time fixed bin (71), /* used by traffic control */ 82 2 idle_ptr ptr, /* pointer to idle process APTE for this processor */ 83 2 simulated_mask fixed bin (71), /* simulated system controller mask register */ 84 2 am_data bit (0), /* to get addr of associative memory data block */ 85 2 ptw_am_regs (4*16) fixed bin (35), /* page table regs (4 sets of 16 for dps8/70m) */ 86 2 ptw_am_ptrs (4*16) fixed bin (35), /* page table pointers (4 sets of 16 for dps8/70m) */ 87 2 sdw_am_regs (4*16) fixed bin (71), /* segment desc. regs (4 sets of 16 for dps8/70m) */ 88 2 sdw_am_ptrs (4*16) fixed bin (35), /* segment desc. pointers (4 sets of 16 for dps8/70m) */ 89 2 processor_pattern bit (8) aligned, /* 1 bit ON for this processor */ 90 2 processor_tag fixed bin (3), /* CPU tag from maintenance panel */ 91 2 last_timer_setting bit (27) aligned, /* last timer value loaded for this CPU */ 92 2 depth fixed bin, /* depth in eligible queue for running process */ 93 2 mode_reg bit (36) aligned, /* mode register for this processor */ 94 2 cache_luf_reg bit (36) aligned, /* cache mode register for this CPU */ 95 2 fault_reg bit (72) aligned, /* place to store the fault register */ 96 2 fault_reg_last_saved fixed bin (71), /* time register last saved */ 97 2 hregs_last_saved fixed bin (71), /* time history regs last saved */ 98 2 apt_ptr ptr, /* -> apte running on this cpu */ 99 2 idle_temp fixed bin (71), /* used by idle process */ 100 101 102 /* The following contains code used for handling connect faults for this processor */ 103 104 105 2 fast_connect_code (FAST_CONNECT_CODE_WORDS) bit (36) aligned, 106 2 fast_connect_code_end bit (36) aligned, /* marker for fast_connect_init */ 107 2 mode_reg_enabled bit (36) aligned, /* used to set mode register */ 108 2 pad_mod_8 (6) fixed bin, 109 2 ignore_pl (8) bit (36) aligned, /* used by wired fim to spl/lpl */ 110 2 pad_mod_16 (8) bit (36) aligned, 111 2 processor_stack aligned like stack_frame; /* first stack frame location */ 112 113 114 115 call get_temp_segment_ ("prds", prdsp, code); 116 117 unspec (prds) = ""b; 118 119 120 /* Now make some checks on alignment of certain variables */ 121 122 call check (addr (prds.idle_ptr), "idle_ptr", 2); 123 call check (addr (prds.processor_stack), "processor_stack", 16); 124 call check (addr (prds.ptw_am_regs), "ptw_am_regs", 16); 125 call check (addr (prds.sdw_am_regs), "sdw_am_regs", 32); 126 call check (addr (prds.fast_connect_code), "fast_connect_code", 2); 127 call check (addr (prds.ignore_pl), "ignore_pl",8); 128 call check (addr (prds.apt_ptr), "apt_ptr", 2); 129 130 /* Now set up call to create data base */ 131 132 cdsa.sections (1).p = addr (prds); 133 cdsa.sections (1).len = size (prds); 134 cdsa.sections (1).struct_name = "prds"; 135 136 cdsa.seg_name = "prds"; 137 cdsa.num_exclude_names = 1; 138 cdsa.exclude_array_ptr = addr (exclude_pad); 139 140 string (cdsa.switches) = "0"b; 141 cdsa.switches.have_text = "1"b; 142 143 call create_data_segment_ (addr (cdsa), code); 144 145 call release_temp_segment_ ("prds", prdsp, code); 146 147 148 149 check: proc (where, message, modulo); 150 151 dcl where ptr; 152 dcl message char (*); 153 dcl modulo fixed bin; 154 155 if mod (bin (rel (where), 18), modulo) ^= 0 156 then call com_err_ (0, prdsname, "The variable ^a is not aligned on a ^d-word boundary.", message, modulo); 157 158 end check; 159 160 1 1 /* BEGIN INCLUDE FILE cds_args.incl.pl1 */ 1 2 1 3 dcl 1 cds_args based aligned, 1 4 2 sections (2), 1 5 3 p ptr, /* pointer to data for text/static section */ 1 6 3 len fixed bin (18), /* size of text/static section */ 1 7 3 struct_name char (32), /* name of declared structure for this section */ 1 8 2 seg_name char (32), /* name to create segment by */ 1 9 2 num_exclude_names fixed bin, /* number of names in exclude array */ 1 10 2 exclude_array_ptr ptr, /* pointer to array of exclude names */ 1 11 2 switches, /* control switches */ 1 12 3 defs_in_link bit (1) unal, /* says put defs in linkage */ 1 13 3 separate_static bit (1) unal, /* says separate static section is wanted */ 1 14 3 have_text bit (1) unal, /* ON if text section given */ 1 15 3 have_static bit (1) unal, /* ON if static section given */ 1 16 3 pad bit (32) unal; 1 17 1 18 dcl exclude_names (1) char (32) based; /* pointed to be cds_args.exclude_array_ptr */ 1 19 1 20 /* END INCLUDE FILE cds_args.incl.pl1 */ 161 162 163 2 1 /* BEGIN INCLUDE FILE ... stack_header.incl.pl1 .. 3/72 Bill Silver */ 2 2 /* modified 7/76 by M. Weaver for *system links and more system use of areas */ 2 3 /* modified 3/77 by M. Weaver to add rnt_ptr */ 2 4 /* Modified April 1983 by C. Hornig for tasking */ 2 5 2 6 /****^ HISTORY COMMENTS: 2 7* 1) change(86-06-24,DGHowe), approve(86-06-24,MCR7396), 2 8* audit(86-08-05,Schroth), install(86-11-03,MR12.0-1206): 2 9* added the heap_header_ptr definition. 2 10* 2) change(86-08-12,Kissel), approve(86-08-12,MCR7473), 2 11* audit(86-10-10,Fawcett), install(86-11-03,MR12.0-1206): 2 12* Modified to support control point management. These changes were actually 2 13* made in February 1985 by G. Palter. 2 14* 3) change(86-10-22,Fawcett), approve(86-10-22,MCR7473), 2 15* audit(86-10-22,Farley), install(86-11-03,MR12.0-1206): 2 16* Remove the old_lot pointer and replace it with cpm_data_ptr. Use the 18 2 17* bit pad after cur_lot_size for the cpm_enabled. This was done to save some 2 18* space int the stack header and change the cpd_ptr unal to cpm_data_ptr 2 19* (ITS pair). 2 20* END HISTORY COMMENTS */ 2 21 2 22 /* format: style2 */ 2 23 2 24 dcl sb ptr; /* the main pointer to the stack header */ 2 25 2 26 dcl 1 stack_header based (sb) aligned, 2 27 2 pad1 (4) fixed bin, /* (0) also used as arg list by outward_call_handler */ 2 28 2 cpm_data_ptr ptr, /* (4) pointer to control point which owns this stack */ 2 29 2 combined_stat_ptr ptr, /* (6) pointer to area containing separate static */ 2 30 2 clr_ptr ptr, /* (8) pointer to area containing linkage sections */ 2 31 2 max_lot_size fixed bin (17) unal, /* (10) DU number of words allowed in lot */ 2 32 2 main_proc_invoked fixed bin (11) unal, /* (10) DL nonzero if main procedure invoked in run unit */ 2 33 2 have_static_vlas bit (1) unal, /* (10) DL "1"b if (very) large arrays are being used in static */ 2 34 2 pad4 bit (2) unal, 2 35 2 run_unit_depth fixed bin (2) unal, /* (10) DL number of active run units stacked */ 2 36 2 cur_lot_size fixed bin (17) unal, /* (11) DU number of words (entries) in lot */ 2 37 2 cpm_enabled bit (18) unal, /* (11) DL non-zero if control point management is enabled */ 2 38 2 system_free_ptr ptr, /* (12) pointer to system storage area */ 2 39 2 user_free_ptr ptr, /* (14) pointer to user storage area */ 2 40 2 null_ptr ptr, /* (16) */ 2 41 2 stack_begin_ptr ptr, /* (18) pointer to first stack frame on the stack */ 2 42 2 stack_end_ptr ptr, /* (20) pointer to next useable stack frame */ 2 43 2 lot_ptr ptr, /* (22) pointer to the lot for the current ring */ 2 44 2 signal_ptr ptr, /* (24) pointer to signal procedure for current ring */ 2 45 2 bar_mode_sp ptr, /* (26) value of sp before entering bar mode */ 2 46 2 pl1_operators_ptr ptr, /* (28) pointer to pl1_operators_$operator_table */ 2 47 2 call_op_ptr ptr, /* (30) pointer to standard call operator */ 2 48 2 push_op_ptr ptr, /* (32) pointer to standard push operator */ 2 49 2 return_op_ptr ptr, /* (34) pointer to standard return operator */ 2 50 2 return_no_pop_op_ptr 2 51 ptr, /* (36) pointer to standard return / no pop operator */ 2 52 2 entry_op_ptr ptr, /* (38) pointer to standard entry operator */ 2 53 2 trans_op_tv_ptr ptr, /* (40) pointer to translator operator ptrs */ 2 54 2 isot_ptr ptr, /* (42) pointer to ISOT */ 2 55 2 sct_ptr ptr, /* (44) pointer to System Condition Table */ 2 56 2 unwinder_ptr ptr, /* (46) pointer to unwinder for current ring */ 2 57 2 sys_link_info_ptr ptr, /* (48) pointer to *system link name table */ 2 58 2 rnt_ptr ptr, /* (50) pointer to Reference Name Table */ 2 59 2 ect_ptr ptr, /* (52) pointer to event channel table */ 2 60 2 assign_linkage_ptr ptr, /* (54) pointer to storage for (obsolete) hcs_$assign_linkage */ 2 61 2 heap_header_ptr ptr, /* (56) pointer to the heap header for this ring */ 2 62 2 trace, 2 63 3 frames, 2 64 4 count fixed bin, /* (58) number of trace frames */ 2 65 4 top_ptr ptr unal, /* (59) pointer to last trace frame */ 2 66 3 in_trace bit (36) aligned, /* (60) trace antirecursion flag */ 2 67 2 pad2 bit (36), /* (61) */ 2 68 2 pad5 pointer; /* (62) pointer to future stuff */ 2 69 2 70 /* The following offset refers to a table within the pl1 operator table. */ 2 71 2 72 dcl tv_offset fixed bin init (361) internal static; 2 73 /* (551) octal */ 2 74 2 75 2 76 /* The following constants are offsets within this transfer vector table. */ 2 77 2 78 dcl ( 2 79 call_offset fixed bin init (271), 2 80 push_offset fixed bin init (272), 2 81 return_offset fixed bin init (273), 2 82 return_no_pop_offset fixed bin init (274), 2 83 entry_offset fixed bin init (275) 2 84 ) internal static; 2 85 2 86 2 87 2 88 2 89 2 90 /* The following declaration is an overlay of the whole stack header. Procedures which 2 91* move the whole stack header should use this overlay. 2 92**/ 2 93 2 94 dcl stack_header_overlay (size (stack_header)) fixed bin based (sb); 2 95 2 96 2 97 2 98 /* END INCLUDE FILE ... stack_header.incl.pl1 */ 164 165 166 3 1 /* BEGIN INCLUDE FILE ... stack_frame.incl.pl1 ... */ 3 2 3 3 /* format: off */ 3 4 3 5 /* Modified: 16 Dec 1977, D. Levin - to add fio_ps_ptr and pl1_ps_ptr */ 3 6 /* Modified: 3 Feb 1978, P. Krupp - to add run_unit_manager bit & main_proc bit */ 3 7 /* Modified: 21 March 1978, D. Levin - change fio_ps_ptr to support_ptr */ 3 8 /* Modified: 03/01/84, S. Herbst - Added RETURN_PTR_MASK */ 3 9 3 10 3 11 /****^ HISTORY COMMENTS: 3 12* 1) change(86-09-15,Kissel), approve(86-09-15,MCR7473), 3 13* audit(86-10-01,Fawcett), install(86-11-03,MR12.0-1206): 3 14* Modified to add constants for the translator_id field in the stack_frame 3 15* structure. 3 16* END HISTORY COMMENTS */ 3 17 3 18 3 19 dcl RETURN_PTR_MASK bit (72) int static options (constant) /* mask to be AND'd with stack_frame.return_ptr */ 3 20 init ("777777777777777777000000"b3); /* when copying, to ignore bits that a call fills */ 3 21 /* with indicators (nonzero for Fortran hexfp caller) */ 3 22 /* say: unspec(ptr) = unspec(stack_frame.return_ptr) & RETURN_PTR_MASK; */ 3 23 3 24 dcl TRANSLATOR_ID_PL1V2 bit (18) internal static options (constant) init ("000000"b3); 3 25 dcl TRANSLATOR_ID_ALM bit (18) internal static options (constant) init ("000001"b3); 3 26 dcl TRANSLATOR_ID_PL1V1 bit (18) internal static options (constant) init ("000002"b3); 3 27 dcl TRANSLATOR_ID_SIGNAL_CALLER bit (18) internal static options (constant) init ("000003"b3); 3 28 dcl TRANSLATOR_ID_SIGNALLER bit (18) internal static options (constant) init ("000004"b3); 3 29 3 30 3 31 dcl sp pointer; /* pointer to beginning of stack frame */ 3 32 3 33 dcl stack_frame_min_length fixed bin static init(48); 3 34 3 35 3 36 dcl 1 stack_frame based(sp) aligned, 3 37 2 pointer_registers(0 : 7) ptr, 3 38 2 prev_sp pointer, 3 39 2 next_sp pointer, 3 40 2 return_ptr pointer, 3 41 2 entry_ptr pointer, 3 42 2 operator_and_lp_ptr ptr, /* serves as both */ 3 43 2 arg_ptr pointer, 3 44 2 static_ptr ptr unaligned, 3 45 2 support_ptr ptr unal, /* only used by fortran I/O */ 3 46 2 on_unit_relp1 bit(18) unaligned, 3 47 2 on_unit_relp2 bit(18) unaligned, 3 48 2 translator_id bit(18) unaligned, /* Translator ID (see constants above) 3 49* 0 => PL/I version II 3 50* 1 => ALM 3 51* 2 => PL/I version I 3 52* 3 => signal caller frame 3 53* 4 => signaller frame */ 3 54 2 operator_return_offset bit(18) unaligned, 3 55 2 x(0: 7) bit(18) unaligned, /* index registers */ 3 56 2 a bit(36), /* accumulator */ 3 57 2 q bit(36), /* q-register */ 3 58 2 e bit(36), /* exponent */ 3 59 2 timer bit(27) unaligned, /* timer */ 3 60 2 pad bit(6) unaligned, 3 61 2 ring_alarm_reg bit(3) unaligned; 3 62 3 63 3 64 dcl 1 stack_frame_flags based(sp) aligned, 3 65 2 pad(0 : 7) bit(72), /* skip over prs */ 3 66 2 xx0 bit(22) unal, 3 67 2 main_proc bit(1) unal, /* on if frame belongs to a main procedure */ 3 68 2 run_unit_manager bit(1) unal, /* on if frame belongs to run unit manager */ 3 69 2 signal bit(1) unal, /* on if frame belongs to logical signal_ */ 3 70 2 crawl_out bit(1) unal, /* on if this is a signal caller frame */ 3 71 2 signaller bit(1) unal, /* on if next frame is signaller's */ 3 72 2 link_trap bit(1) unal, /* on if this frame was made by the linker */ 3 73 2 support bit(1) unal, /* on if frame belongs to a support proc */ 3 74 2 condition bit(1) unal, /* on if condition established in this frame */ 3 75 2 xx0a bit(6) unal, 3 76 2 xx1 fixed bin, 3 77 2 xx2 fixed bin, 3 78 2 xx3 bit(25) unal, 3 79 2 old_crawl_out bit (1) unal, /* on if this is a signal caller frame */ 3 80 2 old_signaller bit(1) unal, /* on if next frame is signaller's */ 3 81 2 xx3a bit(9) unaligned, 3 82 2 xx4(9) bit(72) aligned, 3 83 2 v2_pl1_op_ret_base ptr, /* When a V2 PL/I program calls an operator the 3 84* * operator puts a pointer to the base of 3 85* * the calling procedure here. (text base ptr) */ 3 86 2 xx5 bit(72) aligned, 3 87 2 pl1_ps_ptr ptr; /* ptr to ps for this frame; also used by fio. */ 3 88 3 89 /* format: on */ 3 90 3 91 /* END INCLUDE FILE ... stack_frame.incl.pl1 */ 167 168 4 1 /* */ 4 2 /* BEGIN INCLUDE FILE mc.incl.pl1 Created Dec 72 for 6180 - WSS. */ 4 3 /* Modified 06/07/76 by Greenberg for mc.resignal */ 4 4 /* Modified 07/07/76 by Morris for fault register data */ 4 5 /* Modified 08/28/80 by J. A. Bush for the DPS8/70M CVPU */ 4 6 /* Modified '82 to make values constant */ 4 7 4 8 /* words 0-15 pointer registers */ 4 9 4 10 dcl mcp ptr; 4 11 4 12 dcl 1 mc based (mcp) aligned, 4 13 2 prs (0:7) ptr, /* POINTER REGISTERS */ 4 14 (2 regs, /* registers */ 4 15 3 x (0:7) bit (18), /* index registers */ 4 16 3 a bit (36), /* accumulator */ 4 17 3 q bit (36), /* q-register */ 4 18 3 e bit (8), /* exponent */ 4 19 3 pad1 bit (28), 4 20 3 t bit (27), /* timer register */ 4 21 3 pad2 bit (6), 4 22 3 ralr bit (3), /* ring alarm register */ 4 23 4 24 2 scu (0:7) bit (36), 4 25 4 26 2 mask bit (72), /* mem controller mask at time of fault */ 4 27 2 ips_temp bit (36), /* Temporary storage for IPS info */ 4 28 2 errcode fixed bin (35), /* fault handler's error code */ 4 29 2 fim_temp, 4 30 3 unique_index bit (18) unal, /* unique index for restarting faults */ 4 31 3 resignal bit (1) unal, /* recompute signal name with fcode below */ 4 32 3 fcode bit (17) unal, /* fault code used as index to FIM table and SCT */ 4 33 2 fault_reg bit (36), /* fault register */ 4 34 2 pad2 bit (1), 4 35 2 cpu_type fixed bin (2) unsigned, /* L68 = 0, DPS8/70M = 1 */ 4 36 2 ext_fault_reg bit (15), /* extended fault reg for DPS8/70M CPU */ 4 37 2 fault_time bit (54), /* time of fault */ 4 38 4 39 2 eis_info (0:7) bit (36)) unaligned; 4 40 4 41 4 42 dcl (apx fixed bin init (0), 4 43 abx fixed bin init (1), 4 44 bpx fixed bin init (2), 4 45 bbx fixed bin init (3), 4 46 lpx fixed bin init (4), 4 47 lbx fixed bin init (5), 4 48 spx fixed bin init (6), 4 49 sbx fixed bin init (7)) internal static options (constant); 4 50 4 51 4 52 4 53 4 54 dcl scup ptr; 4 55 4 56 dcl 1 scu based (scup) aligned, /* SCU DATA */ 4 57 4 58 4 59 /* WORD (0) */ 4 60 4 61 (2 ppr, /* PROCEDURE POINTER REGISTER */ 4 62 3 prr bit (3), /* procedure ring register */ 4 63 3 psr bit (15), /* procedure segment register */ 4 64 3 p bit (1), /* procedure privileged bit */ 4 65 4 66 2 apu, /* APPENDING UNIT STATUS */ 4 67 3 xsf bit (1), /* ext seg flag - IT modification */ 4 68 3 sdwm bit (1), /* match in SDW Ass. Mem. */ 4 69 3 sd_on bit (1), /* SDW Ass. Mem. ON */ 4 70 3 ptwm bit (1), /* match in PTW Ass. Mem. */ 4 71 3 pt_on bit (1), /* PTW Ass. Mem. ON */ 4 72 3 pi_ap bit (1), /* Instr Fetch or Append cycle */ 4 73 3 dsptw bit (1), /* Fetch of DSPTW */ 4 74 3 sdwnp bit (1), /* Fetch of SDW non paged */ 4 75 3 sdwp bit (1), /* Fetch of SDW paged */ 4 76 3 ptw bit (1), /* Fetch of PTW */ 4 77 3 ptw2 bit (1), /* Fetch of pre-paged PTW */ 4 78 3 fap bit (1), /* Fetch of final address paged */ 4 79 3 fanp bit (1), /* Fetch of final address non-paged */ 4 80 3 fabs bit (1), /* Fetch of final address absolute */ 4 81 4 82 2 fault_cntr bit (3), /* number of retrys of EIS instructions */ 4 83 4 84 4 85 /* WORD (1) */ 4 86 4 87 2 fd, /* FAULT DATA */ 4 88 3 iro bit (1), /* illegal ring order */ 4 89 3 oeb bit (1), /* out of execute bracket */ 4 90 3 e_off bit (1), /* no execute */ 4 91 3 orb bit (1), /* out of read bracket */ 4 92 3 r_off bit (1), /* no read */ 4 93 3 owb bit (1), /* out of write bracket */ 4 94 3 w_off bit (1), /* no write */ 4 95 3 no_ga bit (1), /* not a gate */ 4 96 3 ocb bit (1), /* out of call bracket */ 4 97 3 ocall bit (1), /* outward call */ 4 98 3 boc bit (1), /* bad outward call */ 4 99 3 inret bit (1), /* inward return */ 4 100 3 crt bit (1), /* cross ring transfer */ 4 101 3 ralr bit (1), /* ring alarm register */ 4 102 3 am_er bit (1), /* associative memory fault */ 4 103 3 oosb bit (1), /* out of segment bounds */ 4 104 3 paru bit (1), /* processor parity upper */ 4 105 3 parl bit (1), /* processor parity lower */ 4 106 3 onc_1 bit (1), /* op not complete type 1 */ 4 107 3 onc_2 bit (1), /* op not complete type 2 */ 4 108 4 109 2 port_stat, /* PORT STATUS */ 4 110 3 ial bit (4), /* illegal action lines */ 4 111 3 iac bit (3), /* illegal action channel */ 4 112 3 con_chan bit (3), /* connect channel */ 4 113 4 114 2 fi_num bit (5), /* (fault/interrupt) number */ 4 115 2 fi_flag bit (1), /* 1 => fault, 0 => interrupt */ 4 116 4 117 4 118 /* WORD (2) */ 4 119 4 120 2 tpr, /* TEMPORARY POINTER REGISTER */ 4 121 3 trr bit (3), /* temporary ring register */ 4 122 3 tsr bit (15), /* temporary segment register */ 4 123 4 124 2 pad2 bit (9), 4 125 4 126 2 cpu_no bit (3), /* CPU number */ 4 127 4 128 2 delta bit (6), /* tally modification DELTA */ 4 129 4 130 4 131 /* WORD (3) */ 4 132 4 133 2 word3 bit (18), 4 134 4 135 2 tsr_stat, /* TSR STATUS for 1,2,&3 word instructions */ 4 136 3 tsna, /* Word 1 status */ 4 137 4 prn bit (3), /* Word 1 PR number */ 4 138 4 prv bit (1), /* Word 1 PR valid bit */ 4 139 3 tsnb, /* Word 2 status */ 4 140 4 prn bit (3), /* Word 2 PR number */ 4 141 4 prv bit (1), /* Word 2 PR valid bit */ 4 142 3 tsnc, /* Word 3 status */ 4 143 4 prn bit (3), /* Word 3 PR number */ 4 144 4 prv bit (1), /* Word 3 PR valid bit */ 4 145 4 146 2 tpr_tbr bit (6), /* TPR.TBR field */ 4 147 4 148 4 149 /* WORD (4) */ 4 150 4 151 2 ilc bit (18), /* INSTRUCTION COUNTER */ 4 152 4 153 2 ir, /* INDICATOR REGISTERS */ 4 154 3 zero bit (1), /* zero indicator */ 4 155 3 neg bit (1), /* negative indicator */ 4 156 3 carry bit (1), /* carryry indicator */ 4 157 3 ovfl bit (1), /* overflow indicator */ 4 158 3 eovf bit (1), /* eponent overflow */ 4 159 3 eufl bit (1), /* exponent underflow */ 4 160 3 oflm bit (1), /* overflow mask */ 4 161 3 tro bit (1), /* tally runout */ 4 162 3 par bit (1), /* parity error */ 4 163 3 parm bit (1), /* parity mask */ 4 164 3 bm bit (1), /* ^bar mode */ 4 165 3 tru bit (1), /* truncation mode */ 4 166 3 mif bit (1), /* multi-word instruction mode */ 4 167 3 abs bit (1), /* absolute mode */ 4 168 3 hex bit (1), /* hexadecimal exponent mode */ 4 169 3 pad bit (3), 4 170 4 171 4 172 /* WORD (5) */ 4 173 4 174 2 ca bit (18), /* COMPUTED ADDRESS */ 4 175 4 176 2 cu, /* CONTROL UNIT STATUS */ 4 177 3 rf bit (1), /* on first cycle of repeat instr */ 4 178 3 rpt bit (1), /* repeat instruction */ 4 179 3 rd bit (1), /* repeat double instruction */ 4 180 3 rl bit (1), /* repeat link instruciton */ 4 181 3 pot bit (1), /* IT modification */ 4 182 3 pon bit (1), /* return type instruction */ 4 183 3 xde bit (1), /* XDE from Even location */ 4 184 3 xdo bit (1), /* XDE from Odd location */ 4 185 3 poa bit (1), /* operation preparation */ 4 186 3 rfi bit (1), /* tells CPU to refetch instruction */ 4 187 3 its bit (1), /* ITS modification */ 4 188 3 if bit (1), /* fault occured during instruction fetch */ 4 189 4 190 2 cpu_tag bit (6)) unaligned, /* computed tag field */ 4 191 4 192 4 193 /* WORDS (6,7) */ 4 194 4 195 2 even_inst bit (36), /* even instruction of faulting pair */ 4 196 4 197 2 odd_inst bit (36); /* odd instruction of faulting pair */ 4 198 4 199 4 200 4 201 4 202 4 203 4 204 /* ALTERNATE SCU DECLARATION */ 4 205 4 206 4 207 dcl 1 scux based (scup) aligned, 4 208 4 209 (2 pad0 bit (36), 4 210 4 211 2 fd, /* GROUP II FAULT DATA */ 4 212 3 isn bit (1), /* illegal segment number */ 4 213 3 ioc bit (1), /* illegal op code */ 4 214 3 ia_am bit (1), /* illegal address - modifier */ 4 215 3 isp bit (1), /* illegal slave procedure */ 4 216 3 ipr bit (1), /* illegal procedure */ 4 217 3 nea bit (1), /* non existent address */ 4 218 3 oobb bit (1), /* out of bounds */ 4 219 3 pad bit (29), 4 220 4 221 2 pad2 bit (36), 4 222 4 223 2 pad3a bit (18), 4 224 4 225 2 tsr_stat (0:2), /* TSR STATUS as an ARRAY */ 4 226 3 prn bit (3), /* PR number */ 4 227 3 prv bit (1), /* PR valid bit */ 4 228 4 229 2 pad3b bit (6)) unaligned, 4 230 4 231 2 pad45 (0:1) bit (36), 4 232 4 233 2 instr (0:1) bit (36); /* Instruction ARRAY */ 4 234 4 235 4 236 4 237 /* END INCLUDE FILE mc.incl.pl1 */ 169 170 171 172 end prds; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/11/89 0859.9 !BBBJZjXjgzwffJ.pl1 >spec>install>1115>prds.cds 161 1 04/01/76 2209.5 cds_args.incl.pl1 >ldd>include>cds_args.incl.pl1 164 2 11/07/86 1550.3 stack_header.incl.pl1 >ldd>include>stack_header.incl.pl1 167 3 11/07/86 1550.3 stack_frame.incl.pl1 >ldd>include>stack_frame.incl.pl1 169 4 12/15/83 1100.4 mc.incl.pl1 >ldd>include>mc.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. FAST_CONNECT_CODE_WORDS 000000 constant fixed bin(17,0) initial dcl 56 ref 74 addr builtin function dcl 60 ref 122 122 123 123 124 124 125 125 126 126 127 127 128 128 132 138 143 143 apt_ptr 1054 based pointer level 2 dcl 74 set ref 128 128 bin builtin function dcl 60 ref 155 cds_args based structure level 1 dcl 1-3 cdsa 000100 automatic structure level 1 dcl 45 set ref 143 143 code 000145 automatic fixed bin(35,0) dcl 46 set ref 115* 143* 145* com_err_ 000022 constant entry external dcl 64 ref 155 create_data_segment_ 000024 constant entry external dcl 65 ref 143 exclude_array_ptr 42 000100 automatic pointer level 2 dcl 45 set ref 138* exclude_pad 000001 constant char(32) initial array dcl 51 set ref 138 fast_connect_code 1060 based bit(36) array level 2 dcl 74 set ref 126 126 get_temp_segment_ 000026 constant entry external dcl 66 ref 115 have_text 44(02) 000100 automatic bit(1) level 3 packed packed unaligned dcl 45 set ref 141* idle_ptr 334 based pointer level 2 dcl 74 set ref 122 122 ignore_pl 1200 based bit(36) array level 2 dcl 74 set ref 127 127 len 2 000100 automatic fixed bin(18,0) array level 3 dcl 45 set ref 133* mc based structure level 1 dcl 4-12 mcp 000154 automatic pointer dcl 4-10 ref 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 4-12 message parameter char packed unaligned dcl 152 set ref 149 155* mod builtin function dcl 60 ref 155 modulo parameter fixed bin(17,0) dcl 153 set ref 149 155 155* num_exclude_names 40 000100 automatic fixed bin(17,0) level 2 dcl 45 set ref 137* p 000100 automatic pointer array level 3 dcl 45 set ref 132* prds based structure level 1 dcl 74 set ref 117* 132 133 prdsname 000026 constant char(4) initial dcl 50 set ref 155* prdsp 000146 automatic pointer dcl 72 set ref 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 115* 117 122 122 123 123 124 124 125 125 126 126 127 127 128 128 132 133 145* processor_stack 1220 based structure level 2 dcl 74 set ref 123 123 ptw_am_regs 340 based fixed bin(35,0) array level 2 dcl 74 set ref 124 124 rel builtin function dcl 60 ref 155 release_temp_segment_ 000030 constant entry external dcl 67 ref 145 sb 000150 automatic pointer dcl 2-24 ref 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 scu based structure level 1 dcl 4-56 scup 000156 automatic pointer dcl 4-54 ref 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 4-56 sdw_am_regs 540 based fixed bin(71,0) array level 2 dcl 74 set ref 125 125 sections 000100 automatic structure array level 2 dcl 45 seg_name 30 000100 automatic char(32) level 2 dcl 45 set ref 136* size builtin function dcl 60 ref 133 sp 000152 automatic pointer dcl 3-31 ref 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 3-36 stack_frame based structure level 1 dcl 3-36 stack_header based structure level 1 dcl 2-26 string builtin function dcl 60 set ref 140* struct_name 3 000100 automatic char(32) array level 3 dcl 45 set ref 134* switches 44 000100 automatic structure level 2 dcl 45 set ref 140* unspec builtin function dcl 60 set ref 117* where parameter pointer dcl 151 ref 149 155 NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. RETURN_PTR_MASK constant bit(72) initial packed unaligned dcl 3-19 TRANSLATOR_ID_ALM constant bit(18) initial packed unaligned dcl 3-25 TRANSLATOR_ID_PL1V1 constant bit(18) initial packed unaligned dcl 3-26 TRANSLATOR_ID_PL1V2 constant bit(18) initial packed unaligned dcl 3-24 TRANSLATOR_ID_SIGNALLER constant bit(18) initial packed unaligned dcl 3-28 TRANSLATOR_ID_SIGNAL_CALLER constant bit(18) initial packed unaligned dcl 3-27 abx constant fixed bin(17,0) initial dcl 4-42 apx constant fixed bin(17,0) initial dcl 4-42 bbx constant fixed bin(17,0) initial dcl 4-42 bpx constant fixed bin(17,0) initial dcl 4-42 call_offset 000011 internal static fixed bin(17,0) initial dcl 2-78 entry_offset 000015 internal static fixed bin(17,0) initial dcl 2-78 exclude_names based char(32) array packed unaligned dcl 1-18 lbx constant fixed bin(17,0) initial dcl 4-42 lpx constant fixed bin(17,0) initial dcl 4-42 push_offset 000012 internal static fixed bin(17,0) initial dcl 2-78 return_no_pop_offset 000014 internal static fixed bin(17,0) initial dcl 2-78 return_offset 000013 internal static fixed bin(17,0) initial dcl 2-78 sbx constant fixed bin(17,0) initial dcl 4-42 scux based structure level 1 dcl 4-207 spx constant fixed bin(17,0) initial dcl 4-42 stack_frame_flags based structure level 1 dcl 3-64 stack_frame_min_length 000016 internal static fixed bin(17,0) initial dcl 3-33 stack_header_overlay based fixed bin(17,0) array dcl 2-94 tv_offset 000010 internal static fixed bin(17,0) initial dcl 2-72 NAMES DECLARED BY EXPLICIT CONTEXT. check 000331 constant entry internal dcl 149 ref 122 123 124 125 126 127 128 prds 000075 constant entry external dcl 39 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 630 662 536 640 Length 10776 536 32 10077 72 10 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME prds 176 external procedure is an external procedure. check internal procedure shares stack frame of external procedure prds. STORAGE FOR INTERNAL STATIC VARIABLES. LOC IDENTIFIER BLOCK NAME 000010 tv_offset prds 000011 call_offset prds 000012 push_offset prds 000013 return_offset prds 000014 return_no_pop_offset prds 000015 entry_offset prds 000016 stack_frame_min_length prds STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME prds 000100 cdsa prds 000145 code prds 000146 prdsp prds 000150 sb prds 000152 sp prds 000154 mcp prds 000156 scup prds THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out_desc call_ext_out return_mac mdfx1 ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. com_err_ create_data_segment_ get_temp_segment_ release_temp_segment_ NO EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 39 000074 115 000102 117 000124 122 000130 123 000141 124 000157 125 000173 126 000210 127 000223 128 000237 132 000251 133 000253 134 000255 136 000260 137 000263 138 000265 140 000267 141 000270 143 000272 145 000305 172 000330 149 000331 155 000342 158 000410 Object Segment >spec>install>1115>prds Created on 11/11/89 1007.0 mst Sat by Hirneisen.SysMaint.a using create_data_segment_, Version II of Thursday, November 20, 1986 Object Text Defs Link Symb Static Start 0 0 1270 1620 1630 1630 Length 2140 1270 330 10 274 0 32 Definitions: segname: prds text|340 am_data text|1054 apt_ptr text|1045 cache_luf_reg text|1043 depth text|1060 fast_connect_code text|1170 fast_connect_code_end text|1046 fault_reg text|1050 fault_reg_last_saved text|160 fim_data text|0 header text|1052 hregs_last_saved text|334 idle_ptr text|1056 idle_temp text|320 ignore_data text|1200 ignore_pl text|330 iitemp text|100 interrupt_data text|332 last_recorded_time text|1042 last_timer_setting text|1044 mode_reg text|1171 mode_reg_enabled text|1040 processor_pattern text|1220 processor_stack text|1041 processor_tag text|440 ptw_am_ptrs text|340 ptw_am_regs text|740 sdw_am_ptrs text|540 sdw_am_regs text|336 simulated_mask symb|0 symbol_table text|240 sys_trouble_data No Links. ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved