COMPILATION LISTING OF SEGMENT relocate_instruction_ Compiled by: Multics PL/I Compiler, Release 33e, of October 6, 1992 Compiled at: CGI Compiled on: 2000-04-18_1114.25_Tue_mdt Options: optimize list 1 /****^ *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Bull Inc., 1987 * 4* * * 5* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 6* * * 7* * Copyright (c) 1972 by Massachusetts Institute of * 8* * Technology and Honeywell Information Systems, Inc. * 9* * * 10* *********************************************************** */ 11 12 13 relocate_instruction_: procedure (from, to, code); 14 15 /* Fixed to relocate tsxN and tspN instructions properly 04/25/84 S. Herbst */ 16 /* Removed above fix, since it causes some after breaks after calls to be ignored 12/04/84 Steve Herbst */ 17 /* Modified to move code into hardcore for bce, Keith Loepere, March 1985. */ 18 19 dcl (from pointer, /* to instruction to be relocated */ 20 to pointer, /* location to relocate it to */ 21 p_delta fixed bin (17), /* what to add to instr offset */ 22 p_instruction_len fixed bin, /* length, with eis descr */ 23 p_special fixed bin, /* eis descrs */ 24 code fixed bin (35)) parameter; /* error code */ 25 26 dcl (op_index, tra_index, tra_target) fixed bin; 27 dcl tra_modifier bit (6) unaligned; 28 dcl (op_name, new_op_name) char (6); 29 dcl delta fixed bin (17); /* offset from "from" to "to" */ 30 dcl relocate_sw bit (1); 31 dcl instruction_len fixed bin; 32 dcl special fixed bin; 33 dcl new_operand bit (36) aligned based (addr (operand)); 34 dcl i fixed bin; 35 dcl (high_bound, low_bound) fixed bin; 36 dcl word bit (36) aligned based; 37 38 dcl 1 instruction aligned, /* overlay for normal instruction */ 39 2 address fixed bin (17) unaligned, 40 2 opcode bit (10) unaligned, 41 2 inst_pad bit (2) unaligned, 42 2 modifier bit (6) unaligned; 43 44 dcl 1 eis_mod aligned, /* format of the modifier */ 45 2 mod_pad bit (2) unaligned, 46 2 indirect bit (1) unaligned, 47 2 register bit (4) unaligned; 48 49 dcl 1 operand aligned, /* overlay for descriptor or indirect word */ 50 2 operand_addr fixed bin (17) unaligned, 51 2 op_pad bit (14) unaligned, 52 2 operand_reg bit (4) unaligned; 53 54 dcl mod_offset (3) fixed bin internal static options (constant) init 55 (30, 12, 3); /* offset of modifier fields in an EIS inst */ 56 57 dcl inst_length_ entry (ptr, fixed bin) returns (fixed bin); 58 59 dcl error_table_$action_not_performed fixed bin (35) external static; 60 61 dcl (addr, addrel, bin, bit, fixed, hbound, lbound, rel, string, substr, unspec) builtin; 62 63 delta = fixed (rel (from), 18, 0) - fixed (rel (to), 18, 0); /* compute for later */ 64 instruction_len = inst_length_ (from, special); 65 if instruction_len = 0 then goto arrgh; 66 67 common: unspec (instruction) = from -> word; 68 op_index = fixed (instruction.opcode, 10, 0); 69 op_name = op_mnemonic_$op_mnemonic (op_index).opcode; 70 71 if instruction_len = 1 then do; /* normal instruction, check for ic and ic* modifiers */ 72 relocate_sw = "0"b; 73 if special = 0 then do; 74 if instruction.modifier = "110100"b then /* *ic, cannot relocate target */ 75 goto arrgh; 76 if instruction.modifier = "000100"b | instruction.modifier = "010100"b then do; 77 relocate_sw = "1"b; 78 instruction.address = instruction.address + delta; 79 end; 80 end; 81 82 /* The following code is commented out because it causes breaks after call 83* statements to be ignored. It was originally put here to prevent the 84* following bug: Suppose you - 85* 1. Set a break after a call statement. 86* 2. Execute the call statement and stop in the called program. 87* 3. Reset the break. 88* 4. Return from the call. 89* You return to the instruction in the break code after the instruction in 90* the break code that actually made the call, but the break code is no longer 91* there. This happened in rare cases to users and caused unsightly faults. 92* 93* One way to do a break after a tsxN or tspN instruction is to really set a 94* before break at the next instruction, but mark it with a flag that tells 95* the rest of probe to pretend that it's an after break at the right 96* instruction. I leave this as a future change. Steve Herbst 12/04/84 */ 97 98 /*OUT if substr (op_name, 1, 3) = "tsp" | substr (op_name, 1, 3) = "tsx" then do; 99*/*OUT tra_target = instruction.address; /* save the computed target of transfer */ 100 /*OUT if relocate_sw then tra_target = tra_target - 1; 101*/*OUT tra_modifier = instruction.modifier; 102*/*OUT if substr (op_name, 1, 3) = "tsp" then new_op_name = "epp" || substr (op_name, 4, 1); 103*/*OUT else new_op_name = "eax" || substr (op_name, 4, 1); 104*/*OUT 105*/*OUT low_bound = lbound (op_mnemonic_$op_mnemonic, 1); 106*/*OUT high_bound = hbound (op_mnemonic_$op_mnemonic, 1); 107*/*OUT /* find out what number a "tra" is */ 108 /*OUT do i = low_bound to high_bound while 109*/*OUT (op_mnemonic_$op_mnemonic (i).opcode ^= "tra"); end; 110*/*OUT if i > high_bound then go to NOT_TS; /* should never happen */ 111 /*OUT tra_index = i; 112*/*OUT /* now find out what number opcode we're creating */ 113 /*OUT do i = low_bound to high_bound while 114*/*OUT (op_mnemonic_$op_mnemonic (i).opcode ^= new_op_name); end; 115*/*OUT if i > high_bound then go to NOT_TS; /* tsxN with unrecognized N? */ 116 /*OUT 117*/*OUT unspec (instruction) = "0"b; 118*/*OUT instruction.opcode = bit (bin (i, 10), 10); 119*/*OUT instruction.address = fixed (rel (from), 18) + 1; 120*/*OUT instruction.modifier = "000000"b; 121*/*OUT to -> word = unspec (instruction); 122*/*OUT 123*/*OUT instruction.opcode = bit (bin (tra_index, 10), 10); 124*/*OUT instruction.address = tra_target; 125*/*OUT instruction.modifier = tra_modifier; 126*/*OUT addrel (to, 1) -> word = unspec (instruction); 127*/*OUT end; 128*/*OUT else OUT*/ 129 130 NOT_TS: to -> word = unspec (instruction); /* move it to its new home */ 131 end; 132 133 else do; /* EIS instruction */ 134 to -> word = unspec (instruction); /* first word requires no relocation */ 135 do i = 1 to special; /* process each descriptor */ 136 string (eis_mod) = substr (unspec (instruction), mod_offset (i), 7); 137 string (new_operand) = addrel (from, i) -> word; /* pick up descriptor or indirect word */ 138 if indirect then do; /* indirect word */ 139 if register = "0100"b then /* descriptor will ultimately have an ic mod */ 140 goto arrgh; /* same problem as *ic */ 141 if operand_reg = "0100"b then /* indirect word has an ic modifier */ 142 operand_addr = operand_addr + delta; 143 end; 144 else if register = "0100"b then /* descriptor with ic mod from instruction */ 145 operand_addr = operand_addr + delta; 146 addrel (to, i) -> word = string (new_operand); /* move this operand to new location */ 147 end; 148 149 do i = special + 1 to instruction_len - 1; /* process non-EIS descriptors, eg.: arg 100,ic */ 150 unspec (instruction) = addrel (from, i) -> word; 151 if instruction.modifier = "110100"b then /* relocate like a simple instruction */ 152 goto arrgh; 153 if instruction.modifier = "000100"b | instruction.modifier = "010100"b then 154 instruction.address = instruction.address + delta; 155 addrel (to, i) -> word = unspec (instruction); 156 end; 157 end; 158 159 return; 160 161 arrgh: code = error_table_$action_not_performed; 162 return; 163 164 bce_relocate_instruction_: entry (from, to, p_delta, p_instruction_len, p_special, code); 165 166 delta = p_delta; 167 instruction_len = p_instruction_len; 168 special = p_special; 169 go to common; 170 1 1 /* BEGIN INCLUDE FILE ... op_mnemonic_format.incl.pl1 1 2* 1 3* James R. Davis 20 May 79 */ 1 4 1 5 dcl 1 op_mnemonic_$op_mnemonic (0:1023) external static aligned, 1 6 2 opcode char (6) unal, 1 7 2 dtype fixed bin (2) unal, /* 0 = alpha, 1 = bit, 2 = numeric */ 1 8 2 num_desc fixed bin (5) unal, 1 9 2 num_words fixed bin (8) unal; 1 10 1 11 dcl modifier (0:63) char (3) aligned int static options (constant) init ( 1 12 " ", "au", "qu", "du", "ic", "al", "ql", "dl", 1 13 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 1 14 "*", "au*", "qu*", "...", "ic*", "al*", "ql*", "...", 1 15 "x0*", "x1*", "x2*", "x3*", "x4*", "x5*", "x6*", "x7*", 1 16 "f", "itp", "...", "its", "sd", "scr", "f2", "f3", 1 17 "ci", "i", "sc", "ad", "di", "dic", "id", "idc", 1 18 "*n", "*au", "*qu", "*du", "*ic", "*al", "*ql", "*dl", 1 19 "*x0", "*x1", "*x2", "*x3", "*x4", "*x5", "*x6", "*x7"); 1 20 1 21 /* Note: if num_words = 1, then num_desc is a flag 1 22* if non0, the tag field of the instruction is to be interpreted specially 1 23* for example, stba or stca 1 24**/ 1 25 /* END INCLUDE FILE op_mnemonic_format.incl.pl1 */ 171 172 173 174 end relocate_instruction_; 175 SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 04/18/00 1114.2 relocate_instruction_.pl1 >udd>sm>ds>w>ml>relocate_instruction_.pl1 171 1 11/26/79 1420.6 op_mnemonic_format.incl.pl1 >ldd>incl>op_mnemonic_format.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. addr builtin function dcl 61 ref 137 146 addrel builtin function dcl 61 ref 137 146 150 155 address 000111 automatic fixed bin(17,0) level 2 packed packed unaligned dcl 38 set ref 78* 78 153* 153 code parameter fixed bin(35,0) dcl 19 set ref 13 161* 164 delta 000104 automatic fixed bin(17,0) dcl 29 set ref 63* 78 141 144 153 166* eis_mod 000112 automatic structure level 1 dcl 44 set ref 136* error_table_$action_not_performed 000012 external static fixed bin(35,0) dcl 59 ref 161 fixed builtin function dcl 61 ref 63 63 68 from parameter pointer dcl 19 set ref 13 63 64* 67 137 150 164 i 000110 automatic fixed bin(17,0) dcl 34 set ref 135* 136 137 146* 149* 150 155* indirect 0(02) 000112 automatic bit(1) level 2 packed packed unaligned dcl 44 set ref 138 inst_length_ 000010 constant entry external dcl 57 ref 64 instruction 000111 automatic structure level 1 dcl 38 set ref 67* 130 134 136 150* 155 instruction_len 000106 automatic fixed bin(17,0) dcl 31 set ref 64* 65 71 149 167* mod_offset 000000 constant fixed bin(17,0) initial array dcl 54 ref 136 modifier 0(30) 000111 automatic bit(6) level 2 packed packed unaligned dcl 38 set ref 74 76 76 151 153 153 new_operand based bit(36) dcl 33 set ref 137* 146 op_index 000100 automatic fixed bin(17,0) dcl 26 set ref 68* 69 op_mnemonic_$op_mnemonic 000014 external static structure array level 1 dcl 1-5 op_name 000102 automatic char(6) packed unaligned dcl 28 set ref 69* opcode 000014 external static char(6) array level 2 in structure "op_mnemonic_$op_mnemonic" packed packed unaligned dcl 1-5 in procedure "relocate_instruction_" ref 69 opcode 0(18) 000111 automatic bit(10) level 2 in structure "instruction" packed packed unaligned dcl 38 in procedure "relocate_instruction_" set ref 68 operand 000113 automatic structure level 1 dcl 49 set ref 137 146 operand_addr 000113 automatic fixed bin(17,0) level 2 packed packed unaligned dcl 49 set ref 141* 141 144* 144 operand_reg 0(32) 000113 automatic bit(4) level 2 packed packed unaligned dcl 49 set ref 141 p_delta parameter fixed bin(17,0) dcl 19 ref 164 166 p_instruction_len parameter fixed bin(17,0) dcl 19 ref 164 167 p_special parameter fixed bin(17,0) dcl 19 ref 164 168 register 0(03) 000112 automatic bit(4) level 2 packed packed unaligned dcl 44 set ref 139 144 rel builtin function dcl 61 ref 63 63 relocate_sw 000105 automatic bit(1) packed unaligned dcl 30 set ref 72* 77* special 000107 automatic fixed bin(17,0) dcl 32 set ref 64* 73 135 149 168* string builtin function dcl 61 set ref 136* 137* 146 substr builtin function dcl 61 ref 136 to parameter pointer dcl 19 ref 13 63 130 134 146 155 164 unspec builtin function dcl 61 set ref 67* 130 134 136 150* 155 word based bit(36) dcl 36 set ref 67 130* 134* 137 146* 150 155* NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. bin builtin function dcl 61 bit builtin function dcl 61 hbound builtin function dcl 61 high_bound automatic fixed bin(17,0) dcl 35 lbound builtin function dcl 61 low_bound automatic fixed bin(17,0) dcl 35 modifier internal static char(3) initial array dcl 1-11 new_op_name automatic char(6) packed unaligned dcl 28 tra_index automatic fixed bin(17,0) dcl 26 tra_modifier automatic bit(6) packed unaligned dcl 27 tra_target automatic fixed bin(17,0) dcl 26 NAMES DECLARED BY EXPLICIT CONTEXT. NOT_TS 000116 constant label dcl 130 arrgh 000262 constant label dcl 161 ref 65 74 139 151 bce_relocate_instruction_ 000274 constant entry external dcl 164 common 000051 constant label dcl 67 ref 169 relocate_instruction_ 000012 constant entry external dcl 13 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 414 432 314 424 Length 630 314 16 161 77 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME relocate_instruction_ 90 external procedure is an external procedure. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME relocate_instruction_ 000100 op_index relocate_instruction_ 000102 op_name relocate_instruction_ 000104 delta relocate_instruction_ 000105 relocate_sw relocate_instruction_ 000106 instruction_len relocate_instruction_ 000107 special relocate_instruction_ 000110 i relocate_instruction_ 000111 instruction relocate_instruction_ 000112 eis_mod relocate_instruction_ 000113 operand relocate_instruction_ THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out return_mac ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. inst_length_ THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. error_table_$action_not_performed op_mnemonic_$op_mnemonic CONSTANTS 000000 aa 000000000036 000001 aa 000000000014 000002 aa 000000000003 000003 aa 404000000043 000004 aa 404000000021 000005 aa 464000000000 BEGIN PROCEDURE relocate_instruction_ ENTRY TO relocate_instruction_ STATEMENT 1 ON LINE 13 relocate_instruction_: procedure (from, to, code); 000006 at 000003000005 000007 tt 000005000003 000010 ta 000006000000 000011 da 000061300000 000012 aa 000140 6270 00 eax7 96 000013 aa 7 00034 3521 20 epp2 pr7|28,* 000014 aa 2 01045 2721 00 tsp2 pr2|549 ext_entry 000015 aa 000006000000 000016 aa 000000000000 000017 aa 6 00032 3735 20 epp7 pr6|26,* 000020 aa 7 00006 3715 20 epp5 pr7|6,* 000021 aa 6 00114 6515 00 spri5 pr6|76 STATEMENT 1 ON LINE 63 delta = fixed (rel (from), 18, 0) - fixed (rel (to), 18, 0); 000022 aa 7 00004 3535 20 epp3 pr7|4,* to 000023 aa 3 00000 3535 20 epp3 pr3|0,* to 000024 aa 3 00000 6351 00 eaa pr3|0 to 000025 aa 000066 7730 00 lrl 54 000026 aa 6 00120 7561 00 stq pr6|80 000027 aa 7 00002 3515 20 epp1 pr7|2,* from 000030 aa 1 00000 3515 20 epp1 pr1|0,* from 000031 aa 1 00000 6351 00 eaa pr1|0 from 000032 aa 000066 7730 00 lrl 54 000033 aa 6 00120 1761 00 sbq pr6|80 000034 aa 6 00104 7561 00 stq pr6|68 delta STATEMENT 1 ON LINE 64 instruction_len = inst_length_ (from, special); 000035 aa 7 00002 3521 20 epp2 pr7|2,* from 000036 aa 6 00124 2521 00 spri2 pr6|84 000037 aa 6 00107 3521 00 epp2 pr6|71 special 000040 aa 6 00126 2521 00 spri2 pr6|86 000041 aa 6 00106 3521 00 epp2 pr6|70 instruction_len 000042 aa 6 00130 2521 00 spri2 pr6|88 000043 aa 6 00122 6211 00 eax1 pr6|82 000044 aa 014000 4310 07 fld 6144,dl 000045 la 4 00010 3521 20 epp2 pr4|8,* inst_length_ 000046 aa 0 00623 7001 00 tsx0 pr0|403 call_ext_out STATEMENT 1 ON LINE 65 if instruction_len = 0 then goto arrgh; 000047 aa 6 00106 2361 00 ldq pr6|70 instruction_len 000050 aa 000212 6000 04 tze 138,ic 000262 STATEMENT 1 ON LINE 67 common: unspec (instruction) = from -> word; 000051 aa 6 00032 3735 20 epp7 pr6|26,* 000052 aa 7 00002 3715 20 epp5 pr7|2,* from 000053 aa 5 00000 2351 20 lda pr5|0,* word 000054 aa 6 00111 7551 00 sta pr6|73 STATEMENT 1 ON LINE 68 op_index = fixed (instruction.opcode, 10, 0); 000055 aa 6 00111 2351 00 lda pr6|73 instruction.opcode 000056 aa 000022 7350 00 als 18 000057 aa 000076 7730 00 lrl 62 000060 aa 6 00100 7561 00 stq pr6|64 op_index STATEMENT 1 ON LINE 69 op_name = op_mnemonic_$op_mnemonic (op_index).opcode; 000061 aa 000001 7360 00 qls 1 000062 aa 6 00044 3701 20 epp4 pr6|36,* 000063 la 4 00014 3535 66 epp3 pr4|12,*ql op_mnemonic_$op_mnemonic.opcode 000064 aa 3 00000 2351 00 lda pr3|0 op_mnemonic_$op_mnemonic.opcode 000065 aa 3 00001 2361 00 ldq pr3|1 op_mnemonic_$op_mnemonic.opcode 000066 aa 0 00154 3771 00 anaq pr0|108 = 777777777777 777777000000 000067 aa 6 00102 7571 00 staq pr6|66 op_name STATEMENT 1 ON LINE 71 if instruction_len = 1 then do; 000070 aa 6 00106 2361 00 ldq pr6|70 instruction_len 000071 aa 000001 1160 07 cmpq 1,dl 000072 aa 000030 6010 04 tnz 24,ic 000122 STATEMENT 1 ON LINE 72 relocate_sw = "0"b; 000073 aa 6 00105 4501 00 stz pr6|69 relocate_sw STATEMENT 1 ON LINE 73 if special = 0 then do; 000074 aa 6 00107 2361 00 ldq pr6|71 special 000075 aa 000021 6010 04 tnz 17,ic 000116 STATEMENT 1 ON LINE 74 if instruction.modifier = "110100"b then /* *ic, cannot relocate target */ goto arrgh; 000076 aa 6 00111 2351 00 lda pr6|73 instruction.modifier 000077 aa 000036 7350 00 als 30 000100 aa 640000 1150 03 cmpa 212992,du 000101 aa 000161 6000 04 tze 113,ic 000262 STATEMENT 1 ON LINE 76 if instruction.modifier = "000100"b | instruction.modifier = "010100"b then do; 000102 aa 6 00121 7551 00 sta pr6|81 instruction.modifier 000103 aa 040000 1150 03 cmpa 16384,du 000104 aa 000003 6000 04 tze 3,ic 000107 000105 aa 240000 1150 03 cmpa 81920,du 000106 aa 000010 6010 04 tnz 8,ic 000116 STATEMENT 1 ON LINE 77 relocate_sw = "1"b; 000107 aa 400000 2350 03 lda 131072,du 000110 aa 6 00105 7551 00 sta pr6|69 relocate_sw STATEMENT 1 ON LINE 78 instruction.address = instruction.address + delta; 000111 aa 6 00111 2351 00 lda pr6|73 instruction.address 000112 aa 000066 7330 00 lrs 54 000113 aa 6 00104 0761 00 adq pr6|68 delta 000114 aa 000066 7370 00 lls 54 000115 aa 6 00111 5511 60 stba pr6|73,60 instruction.address STATEMENT 1 ON LINE 79 end; STATEMENT 1 ON LINE 80 end; STATEMENT 1 ON LINE 130 NOT_TS: to -> word = unspec (instruction); 000116 aa 6 00111 2351 00 lda pr6|73 000117 aa 7 00004 3515 20 epp1 pr7|4,* to 000120 aa 1 00000 7551 20 sta pr1|0,* word STATEMENT 1 ON LINE 131 end; 000121 aa 000140 7100 04 tra 96,ic 000261 STATEMENT 1 ON LINE 133 else do; STATEMENT 1 ON LINE 134 to -> word = unspec (instruction); 000122 aa 6 00111 2351 00 lda pr6|73 000123 aa 7 00004 3515 20 epp1 pr7|4,* to 000124 aa 1 00000 7551 20 sta pr1|0,* word STATEMENT 1 ON LINE 135 do i = 1 to special; 000125 aa 6 00107 2361 00 ldq pr6|71 special 000126 aa 6 00116 7561 00 stq pr6|78 000127 aa 000001 2360 07 ldq 1,dl 000130 aa 6 00110 7561 00 stq pr6|72 i 000131 aa 000000 0110 03 nop 0,du 000132 aa 6 00110 2361 00 ldq pr6|72 i 000133 aa 6 00116 1161 00 cmpq pr6|78 000134 aa 000060 6054 04 tpnz 48,ic 000214 STATEMENT 1 ON LINE 136 string (eis_mod) = substr (unspec (instruction), mod_offset (i), 7); 000135 aa 6 00112 4501 00 stz pr6|74 000136 ta 777777 7270 06 lxl7 -1,ql 000137 aa 003 100 060 517 csl (pr,x7),(pr),fill(0),bool(move) 000140 aa 6 00110 70 0007 descb pr6|72(35),7 000141 aa 6 00112 00 0007 descb pr6|74,7 STATEMENT 1 ON LINE 137 string (new_operand) = addrel (from, i) -> word; 000142 aa 6 00032 3735 20 epp7 pr6|26,* 000143 aa 7 00002 3521 20 epp2 pr7|2,* from 000144 aa 2 00000 3521 66 epp2 pr2|0,*ql from 000145 aa 000000 0520 03 adwp2 0,du 000146 aa 2 00000 2351 00 lda pr2|0 word 000147 aa 6 00113 7551 00 sta pr6|75 new_operand STATEMENT 1 ON LINE 138 if indirect then do; 000150 aa 6 00112 2351 00 lda pr6|74 eis_mod.indirect 000151 aa 100000 3150 03 cana 32768,du 000152 aa 000020 6000 04 tze 16,ic 000172 STATEMENT 1 ON LINE 139 if register = "0100"b then /* descriptor will ultimately have an ic mod */ goto arrgh; 000153 aa 6 00112 2351 00 lda pr6|74 eis_mod.register 000154 aa 000003 7350 00 als 3 000155 aa 0 00010 3771 00 anaq pr0|8 = 740000000000 000000000000 000156 aa 200000 1150 03 cmpa 65536,du 000157 aa 000103 6000 04 tze 67,ic 000262 STATEMENT 1 ON LINE 141 if operand_reg = "0100"b then /* indirect word has an ic modifier */ operand_addr = operand_addr + delta; 000160 aa 6 00113 2351 00 lda pr6|75 operand.operand_reg 000161 aa 000040 7350 00 als 32 000162 aa 200000 1150 03 cmpa 65536,du 000163 aa 000021 6010 04 tnz 17,ic 000204 000164 aa 6 00113 2351 00 lda pr6|75 operand.operand_addr 000165 aa 000066 7330 00 lrs 54 000166 aa 6 00104 0761 00 adq pr6|68 delta 000167 aa 000066 7370 00 lls 54 000170 aa 6 00113 5511 60 stba pr6|75,60 operand.operand_addr STATEMENT 1 ON LINE 143 end; 000171 aa 000013 7100 04 tra 11,ic 000204 STATEMENT 1 ON LINE 144 else if register = "0100"b then /* descriptor with ic mod from instruction */ operand_addr = operand_addr + delta; 000172 aa 6 00112 2351 00 lda pr6|74 eis_mod.register 000173 aa 000003 7350 00 als 3 000174 aa 0 00010 3771 00 anaq pr0|8 = 740000000000 000000000000 000175 aa 200000 1150 03 cmpa 65536,du 000176 aa 000006 6010 04 tnz 6,ic 000204 000177 aa 6 00113 2351 00 lda pr6|75 operand.operand_addr 000200 aa 000066 7330 00 lrs 54 000201 aa 6 00104 0761 00 adq pr6|68 delta 000202 aa 000066 7370 00 lls 54 000203 aa 6 00113 5511 60 stba pr6|75,60 operand.operand_addr STATEMENT 1 ON LINE 146 addrel (to, i) -> word = string (new_operand); 000204 aa 6 00110 2361 00 ldq pr6|72 i 000205 aa 7 00004 3521 20 epp2 pr7|4,* to 000206 aa 2 00000 3521 66 epp2 pr2|0,*ql to 000207 aa 000000 0520 03 adwp2 0,du 000210 aa 6 00113 2351 00 lda pr6|75 new_operand 000211 aa 2 00000 7551 00 sta pr2|0 word STATEMENT 1 ON LINE 147 end; 000212 aa 6 00110 0541 00 aos pr6|72 i 000213 aa 777717 7100 04 tra -49,ic 000132 STATEMENT 1 ON LINE 149 do i = special + 1 to instruction_len - 1; 000214 aa 6 00106 2361 00 ldq pr6|70 instruction_len 000215 aa 000001 1760 07 sbq 1,dl 000216 aa 6 00117 7561 00 stq pr6|79 000217 aa 6 00107 2361 00 ldq pr6|71 special 000220 aa 000001 0760 07 adq 1,dl 000221 aa 6 00110 7561 00 stq pr6|72 i 000222 aa 6 00110 2361 00 ldq pr6|72 i 000223 aa 6 00117 1161 00 cmpq pr6|79 000224 aa 000035 6054 04 tpnz 29,ic 000261 STATEMENT 1 ON LINE 150 unspec (instruction) = addrel (from, i) -> word; 000225 aa 6 00032 3735 20 epp7 pr6|26,* 000226 aa 7 00002 3521 20 epp2 pr7|2,* from 000227 aa 2 00000 3521 66 epp2 pr2|0,*ql from 000230 aa 000000 0520 03 adwp2 0,du 000231 aa 2 00000 2351 00 lda pr2|0 word 000232 aa 6 00111 7551 00 sta pr6|73 STATEMENT 1 ON LINE 151 if instruction.modifier = "110100"b then /* relocate like a simple instruction */ goto arrgh; 000233 aa 6 00111 2351 00 lda pr6|73 instruction.modifier 000234 aa 000036 7350 00 als 30 000235 aa 640000 1150 03 cmpa 212992,du 000236 aa 000024 6000 04 tze 20,ic 000262 STATEMENT 1 ON LINE 153 if instruction.modifier = "000100"b | instruction.modifier = "010100"b then instruction.address = instruction.address + delta; 000237 aa 6 00121 7551 00 sta pr6|81 instruction.modifier 000240 aa 040000 1150 03 cmpa 16384,du 000241 aa 000003 6000 04 tze 3,ic 000244 000242 aa 240000 1150 03 cmpa 81920,du 000243 aa 000006 6010 04 tnz 6,ic 000251 000244 aa 6 00111 2351 00 lda pr6|73 instruction.address 000245 aa 000066 7330 00 lrs 54 000246 aa 6 00104 0761 00 adq pr6|68 delta 000247 aa 000066 7370 00 lls 54 000250 aa 6 00111 5511 60 stba pr6|73,60 instruction.address STATEMENT 1 ON LINE 155 addrel (to, i) -> word = unspec (instruction); 000251 aa 6 00110 2361 00 ldq pr6|72 i 000252 aa 7 00004 3521 20 epp2 pr7|4,* to 000253 aa 2 00000 3521 66 epp2 pr2|0,*ql to 000254 aa 000000 0520 03 adwp2 0,du 000255 aa 6 00111 2351 00 lda pr6|73 000256 aa 2 00000 7551 00 sta pr2|0 word STATEMENT 1 ON LINE 156 end; 000257 aa 6 00110 0541 00 aos pr6|72 i 000260 aa 777742 7100 04 tra -30,ic 000222 STATEMENT 1 ON LINE 157 end; STATEMENT 1 ON LINE 159 return; 000261 aa 0 00631 7101 00 tra pr0|409 return_mac STATEMENT 1 ON LINE 161 arrgh: code = error_table_$action_not_performed; 000262 aa 6 00044 3701 20 epp4 pr6|36,* 000263 la 4 00012 2361 20 ldq pr4|10,* error_table_$action_not_performed 000264 aa 6 00114 7561 20 stq pr6|76,* code STATEMENT 1 ON LINE 162 return; 000265 aa 0 00631 7101 00 tra pr0|409 return_mac ENTRY TO bce_relocate_instruction_ STATEMENT 1 ON LINE 164 bce_relocate_instruction_: entry (from, to, p_delta, p_instruction_len, p_special, code); 000266 at 000006000005 000267 tt 000005000004 000270 tt 000004000004 000271 ta 000003000000 000272 ta 000266000000 000273 da 000073300000 000274 aa 000140 6270 00 eax7 96 000275 aa 7 00034 3521 20 epp2 pr7|28,* 000276 aa 2 01045 2721 00 tsp2 pr2|549 ext_entry 000277 aa 000014000000 000300 aa 000000000000 000301 aa 6 00032 3735 20 epp7 pr6|26,* 000302 aa 7 00014 3715 20 epp5 pr7|12,* 000303 aa 6 00114 6515 00 spri5 pr6|76 STATEMENT 1 ON LINE 166 delta = p_delta; 000304 aa 6 00032 3735 20 epp7 pr6|26,* 000305 aa 7 00006 2361 20 ldq pr7|6,* p_delta 000306 aa 6 00104 7561 00 stq pr6|68 delta STATEMENT 1 ON LINE 167 instruction_len = p_instruction_len; 000307 aa 7 00010 2361 20 ldq pr7|8,* p_instruction_len 000310 aa 6 00106 7561 00 stq pr6|70 instruction_len STATEMENT 1 ON LINE 168 special = p_special; 000311 aa 7 00012 2361 20 ldq pr7|10,* p_special 000312 aa 6 00107 7561 00 stq pr6|71 special STATEMENT 1 ON LINE 169 go to common; 000313 aa 777536 7100 04 tra -162,ic 000051 STATEMENT 1 ON LINE 174 end relocate_instruction_; END PROCEDURE relocate_instruction_ ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved