COMPILATION LISTING OF SEGMENT !BBBJZjXmhKLMcq Compiled by: Multics PL/I Compiler, Release 32f, of October 9, 1989 Compiled at: Bull HN, Phoenix AZ, System-M Compiled on: 11/11/89 1100.7 mst Sat Options: table map 1 /* *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Bull Inc., 1987 * 4* * * 5* * Copyright, (C) Honeywell Information Systems Inc., 1984 * 6* * * 7* * Copyright (c) 1972 by Massachusetts Institute of * 8* * Technology and Honeywell Information Systems, Inc. * 9* * * 10* *********************************************************** */ 11 12 13 /* SCS - The System Communications Segment 14* modified 3/27/77 by Noel I. Morris 15* last modified 4/26/78 by J. A. Bush for processor testing 16* Modified 2/79 by BSG for 8-cpu port expander 17* Modified 9/16/80 by J. A. Bush for the DPS8/70M CPU 18* Modified 1/09/81 W. Olin Sibert to remove all initializations to scs_and_clock_init 19* Modified 01/16/81 W. Olin Sibert, to add scs$port_data 20* Modified Jabuary 1981 by C. Hornig for new I/O. 21* Modified 2/22/81 by J. Bongiovanni for fast connect code 22* Modified 4/23/81 by J. Bongiovanni for cycle_priority_template 23* Modified 4/09/82 by J. Bongiovanni for switch 0, processor_data_switch_value 24* Modified 7/30/82 by J. Bongiovanni for trouble_processid 25* Modified 4/11/83 by E. N. Kittlitz for drl_message_pointer. 26* Modified 10/25/83 by Keith Loepere for start_of_scs 27**/ 28 29 scs: 30 procedure; 31 32 /* Static */ 33 34 dcl exclude_pad (1) char (32) static options (constant) init ("pad*"); 35 36 /* Automatic */ 37 38 dcl code fixed bin (35); 39 dcl 1 cdsa aligned like cds_args; 40 dcl i fixed bin; 41 42 /* Builtins */ 43 44 dcl (addr, bin, bit, null, size, string, unspec) builtin; 45 46 /* Entries */ 47 48 dcl create_data_segment_ entry (ptr, fixed bin (35)); 49 50 dcl 1 scs aligned, /* Information about system controllers */ 51 2 start_of_scs fixed bin (71), 52 2 controller_data (0:7) aligned like scs$controller_data, 53 /* per-controller info */ 54 /* Information about CPUs */ 55 2 processor_data (0:7) aligned like scs$processor_data, 56 /* information about CPUs in the system */ 57 2 port_data (0:7) like scs$port_data aligned, /* Info on what is connected to each SCU port */ 58 2 cow (0:7) like scs$cow, /* Actual COW's. */ 59 2 cow_ptrs (0:7) aligned like scs$cow_ptrs, /* Rel pointers to COW's. */ 60 2 reconfig_general_cow aligned like scs$reconfig_general_cow, 61 /* Used for reconfiguration operations */ 62 /* MASKS and PATTERNS */ 63 2 sys_level aligned bit (72), /* mask used while handling I/O interrupts */ 64 2 open_level aligned bit (72), /* mask used during normal operation */ 65 2 processor_start_mask aligned bit (72), /* mask used when starting up a CPU */ 66 2 cpu_test_mask aligned bit (72), /* mask used for ISOLTS CPU testing */ 67 2 number_of_masks fixed bin, /* number of masks (starting at sys_level) */ 68 2 processor_start_pattern bit (36) aligned, /* SMIC pattern used to send processor start interrupt */ 69 2 cpu_test_pattern bit (36) aligned, /* SMIC pattern used for ISOLTS processor testing */ 70 2 expanded_ports bit (1) unaligned dim (0:7), /* Which ports have expanders */ 71 /* CAM and CACHE clear info */ 72 2 cam_pair fixed bin (71), /* instructions XEDd when CAMing and clearing CACHE */ 73 2 cam_wait bit (8) aligned, /* Used when evicting pages from main memory */ 74 2 pad1 fixed bin, /* MASKING INSTRUCTIONS & POINTERS */ 75 2 set_mask (0:7) bit (36) aligned, /* instructions to set mask (STAQ or SMCM) */ 76 2 read_mask (0:7) bit (36) aligned, /* instructions to read mask (LDAQ or RMCM) */ 77 2 mask_ptr (0:7) ptr unaligned, /* pointers for real or simulated masks */ 78 /* MISCELLANEOUS */ 79 2 idle_aptep (0:7) ptr unaligned, /* pointer to idle process APTE for each processor */ 80 2 connect_lock bit (36) aligned, /* lock for sending connects */ 81 2 reconfig_lock bit (36) aligned, /* lock used during reconfiguration */ 82 2 trouble_flags bit (8) aligned, /* checkoff flags for sys_trouble stopping */ 83 2 bos_restart_flags bit (8) aligned, /* checkoff flags for restarting after sys_trouble */ 84 2 nprocessors fixed bin, /* number of processors online */ 85 2 bos_processor_tag fixed bin (3), /* CPU tag of processor running BOS */ 86 2 faults_initialized bit (1) aligned, /* ON after faults have been enabled */ 87 2 sys_trouble_pending bit (1) aligned, /* sys_trouble event is pending in the system */ 88 2 fast_cam_pending (0:7) bit (36) aligned, /* checkoff flags for cam connect */ 89 2 interrupt_controller fixed bin (3), /* port number of low order controller */ 90 2 cycle_priority_template bit (7) aligned, 91 2 set_cycle_switches bit (1) aligned, 92 2 processor_start_int_no fixed bin (5), /* interrupt cell for starting a processor */ 93 2 processor bit (8) aligned, /* bits ON for online CPUs */ 94 2 processor_start_wait bit (8) aligned, /* checkoff flags for waiting for new processor */ 95 2 trouble_processid bit (36) aligned, /* processid causing crash */ 96 2 drl_message_pointer ptr unal, /* pointer to DRL message text */ 97 2 processor_test_data aligned like scs$processor_test_data, 98 /* info for cpu testing */ 99 2 pad2 fixed bin, 100 2 trouble_dbrs (0:7) fixed bin (71), /* DBR values at system crash time */ 101 2 port_addressing_word (0:7) bit (3) aligned, /* active module port number for each controller */ 102 2 cfg_data (0:7) fixed bin (71), /* RSCR-CFG data from each controller */ 103 2 cfg_data_save fixed bin (71), /* RSCR-CFG save area for ISOLTS CPU testing */ 104 2 processor_switch_data (0:4) bit (36) aligned, /* actual processor RSW data */ 105 2 processor_switch_template (0:4) bit (36) aligned, /* expected data from RSW 0 thru 4 */ 106 2 processor_switch_compare (0:4) bit (36) aligned, /* discrepancies from expected data */ 107 2 processor_switch_mask (0:4) bit (36) aligned, /* masks for comparing switch data */ 108 2 processor_data_switch_value bit (36) aligned, /* Correct value of CPU data switches */ 109 /* Data used by init_sst and collect_free_core, from config cards. */ 110 2 controller_config_size (0:7) fixed bin (14) aligned,/* config card-stated size of controller */ 111 2 reconfig_locker_id char (32) aligned, /* process group ID of process doing reconfiguration */ 112 2 scas_page_table (0:31) bit (36) aligned, /* Page table for SCAS */ 113 2 end_of_scs fixed bin; /* For initialization */ 114 115 unspec (scs) = "0"b; /* clear entire structure */ 116 117 /* Now set up for call to create_data_segment_ */ 118 119 cdsa.sections (1).p = addr (scs); 120 cdsa.sections (1).len = size (scs); 121 cdsa.sections (1).struct_name = "scs"; 122 123 cdsa.seg_name = "scs"; 124 cdsa.num_exclude_names = 1; 125 cdsa.exclude_array_ptr = addr (exclude_pad); 126 127 string (cdsa.switches) = "0"b; 128 cdsa.switches.have_text = "1"b; 129 130 call create_data_segment_ (addr (cdsa), code); 131 return; 132 1 1 /* BEGIN INCLUDE FILE scs.incl.pl1 ... March 1983 */ 1 2 /* format: style4 */ 1 3 1 4 /* Information about system controllers */ 1 5 1 6 dcl 1 scs$controller_data (0:7) aligned ext, /* per-controller info */ 1 7 2 size fixed bin (17) unaligned, /* size (in 1024 word blocks) of this controller */ 1 8 2 base fixed bin (17) unaligned, /* abs address (0 mod 1024) for base of this controller */ 1 9 2 eima_data (4) unaligned, /* EIMA information for this controller */ 1 10 3 mask_available bit (1) unaligned, /* ON if corresponding mask exists */ 1 11 3 mask_assigned bit (1) unaligned, /* ON if mask assigned to a port */ 1 12 3 mbz bit (3) unaligned, 1 13 3 mask_assignment fixed bin (3) unaligned, /* port to which mask is assigned */ 1 14 2 info aligned, 1 15 3 online bit (1) unaligned, /* ON if controller is online */ 1 16 3 offline bit (1) unaligned, /* ON if controller is offline but can be added */ 1 17 3 store_a_online bit (1) unaligned, /* ON if store A is online */ 1 18 3 store_a1_online bit (1) unaligned, /* ON if store A1 is online */ 1 19 3 store_b_online bit (1) unaligned, /* ON if store B is online */ 1 20 3 store_b1_online bit (1) unaligned, /* ON if store B1 is online */ 1 21 3 store_b_is_lower bit (1) unaligned, /* ON if store B is lower */ 1 22 3 ext_interlaced bit (1) unaligned, /* ON if this SCU is interlaced with other SCU */ 1 23 3 int_interlaced bit (1) unaligned, /* ON if this SCU is internally interlaced */ 1 24 3 four_word bit (1) unaligned, /* ON if external interlace is 4-word */ 1 25 3 cyclic_priority (7) bit (1) unaligned, /* Cyclic priority for adjacent ports */ 1 26 3 type bit (4) unaligned, /* Model number for this controller */ 1 27 3 abs_wired bit (1) unaligned, /* ON if controller can have abs_wired pages */ 1 28 3 program bit (1) unaligned, /* PROGRAM/MANUAL switch setting */ 1 29 3 mbz bit (13) unaligned, 1 30 2 lower_store_size fixed bin (17) unaligned, /* size (in 1024 word blocks) of lower store */ 1 31 2 upper_store_size fixed bin (17) unaligned; /* size (in 1024 word blocks) of upper store */ 1 32 1 33 /* Information about CPUs */ 1 34 1 35 dcl 1 scs$processor_data (0:7) aligned ext, /* information about CPUs in the system */ 1 36 ( 1 37 2 online bit (1), /* "1"b if CPU is online */ 1 38 2 offline bit (1), /* "1"b if CPU is offline but can be added */ 1 39 2 release_mask bit (1), /* "1"b is this CPU is to give up its mask */ 1 40 2 accept_mask bit (1), /* "1"b if this CPU is to grap mask in idle loop */ 1 41 2 delete_cpu bit (1), /* "1"b if this CPU is to delete itself */ 1 42 2 interrupt_cpu bit (1), /* "1"b if this CPU takes hardware interrupts */ 1 43 2 halted_cpu bit (1), /* "1"b if this CPU has stopped itself (going to BOS) */ 1 44 2 cpu_type fixed bin (2) unsigned, /* 0 => DPS or L68, 1 => DPS8 */ 1 45 2 mbz1 bit (6), 1 46 2 cache_size fixed bin (3) unsigned, /* 0 = No cache; 1 = L68 2K cache; 1 47* 2 = DPS8 8K cache; 3 = DPS8 VS&SC 8K cache; 1 48* 4 = DPS8 VS&SC 16K cache; 5 = DPS8 VS&SC 32K cache 1 49* 7 = ignore cache size (set by ISOLTS reconfig) */ 1 50 2 mbz2 bit (12), 1 51 2 expanded_port bit (1), /* "1"b = on expanded port */ 1 52 2 expander_port fixed bin (2) unsigned, /* The actual expander port */ 1 53 2 controller_port fixed bin (3) unsigned 1 54 ) unaligned; /* Port on controller */ 1 55 1 56 dcl 1 scs$port_data (0:7) aligned external static, /* Info about what is connected to each SCU port */ 1 57 2 assigned fixed bin (4) unsigned unaligned, /* Type of device on this port */ 1 58 2 expander_port bit (1) unaligned, /* "1"b => this port has a port expander */ 1 59 2 expanded_cpu (0:3) bit (1) unaligned, /* "1"b => this expander port has a CPU attached */ 1 60 2 iom_number fixed bin (3) unsigned unaligned, /* IOM number of IOM attached to this port */ 1 61 2 cpu_number (0:3) fixed bin (3) unsigned unaligned, /* CPU number of CPU(s) attached to this port */ 1 62 /* cpu_number (0) is only one if expander_port is "0"b */ 1 63 2 pad bit (12) unaligned; 1 64 1 65 dcl 1 scs$cow (0:7) aligned external, /* Actual connect words */ 1 66 2 pad bit (36) aligned, /* Expander COW's must be odd-word */ 1 67 2 cow, 1 68 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 1 69 3 mbz1 bit (13) unaligned, 1 70 3 expander_command bit (3) unaligned, /* Expander command. */ 1 71 3 mbz2 bit (2) unaligned, 1 72 3 expanded_port bit (1) unaligned, /* "1"b = on expanded port */ 1 73 3 expander_port fixed bin (3) unsigned unaligned, /* Port on expander for cioc */ 1 74 3 mbz3 bit (3) unaligned, 1 75 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 1 76 1 77 dcl 1 scs$cow_ptrs (0:7) external aligned, /* Pointers to COW's */ 1 78 2 rel_cow_ptr bit (18) unal, /* Relative pointer to COW */ 1 79 2 pad bit (12) unal, 1 80 2 tag bit (6) unal; /* Better be zero. */ 1 81 1 82 dcl 1 scs$reconfig_general_cow aligned external, /* Used during reconfig ops. */ 1 83 2 pad bit (36) aligned, 1 84 2 cow, /* Connect operand word, in odd location. */ 1 85 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 1 86 3 mbz1 bit (13) unaligned, 1 87 3 expander_command bit (3) unaligned, /* Expander command. */ 1 88 3 mbz2 bit (9) unaligned, 1 89 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 1 90 1 91 /* MASKS and PATTERNS */ 1 92 1 93 dcl scs$sys_level bit (72) aligned ext; /* mask used while handling I/O interrupts */ 1 94 dcl scs$open_level bit (72) aligned ext; /* mask used during normal operation */ 1 95 dcl scs$processor_start_mask bit (72) aligned ext; /* mask used when starting up a CPU */ 1 96 dcl scs$cpu_test_mask bit (72) aligned ext; /* mask used for ISOLTS CPU testing */ 1 97 dcl scs$number_of_masks fixed bin ext; /* number of masks (starting at sys_level) */ 1 98 dcl scs$processor_start_pattern bit (36) aligned ext; /* SMIC pattern used to send processor start interrupt */ 1 99 dcl scs$cpu_test_pattern bit (36) aligned ext; /* SMIC pattern used for ISOLTS processor testing */ 1 100 1 101 /* CAM and CACHE clear info */ 1 102 1 103 dcl scs$cam_pair fixed bin (71) ext; /* instructions XEDd when CAMing and clearing CACHE */ 1 104 dcl scs$cam_wait bit (8) aligned ext; /* Used when evicting pages from main memory */ 1 105 1 106 /* MASKING INSTRUCTIONS & POINTERS */ 1 107 1 108 dcl scs$set_mask (0:7) bit (36) aligned ext; /* instructions to set mask (STAQ or SMCM) */ 1 109 dcl scs$read_mask (0:7) bit (36) aligned ext; /* instructions to read mask (LDAQ or RMCM) */ 1 110 dcl scs$mask_ptr (0:7) ptr unaligned ext; /* pointers for real or simulated masks */ 1 111 1 112 /* MISCELLANEOUS */ 1 113 1 114 dcl 1 scs$processor_test_data aligned ext, /* info used for cpu testing */ 1 115 ( 1 116 2 active bit (1), /* = "1"b if cpu currently under test */ 1 117 2 scu_state bit (2), /* state of scu being used for testing (see definition below) */ 1 118 2 pad1 bit (4), 1 119 2 req_mem fixed bin (10), /* dedicated memory required to test this cpu */ 1 120 2 cpu_tag fixed bin (5), /* tag of cpu under test */ 1 121 2 scu_tag fixed bin (5), /* tag of scu being used for cpu testing */ 1 122 2 mask_cpu fixed bin (5) 1 123 ) unaligned; /* tag of active cpu that has mask asigned to above scu */ 1 124 1 125 /* scu_state = "00"b => SCU defined by scs$processor_test_data.scu_tag not yet effected */ 1 126 /* scu_state = "01"b => all core removed from SCU, port mask not yet changed */ 1 127 /* scu_state = "10"b => all core removed from SCU, port mask changed */ 1 128 /* scu_state = "11"b => only 64k at base of SCU being used for testing, original port mask restored */ 1 129 1 130 dcl scs$idle_aptep (0:7) ptr unaligned ext; /* pointer to idle process APTE for each processor */ 1 131 1 132 dcl scs$connect_lock bit (36) aligned ext; /* lock for sending connects */ 1 133 dcl scs$reconfig_lock bit (36) aligned ext; /* Lock used during reconfiguration */ 1 134 dcl scs$trouble_flags bit (8) aligned ext; /* checkoff flags for sys_trouble stopping */ 1 135 dcl scs$bos_restart_flags bit (8) aligned ext; /* checkoff flags for restarting after sys_trouble */ 1 136 dcl scs$nprocessors fixed bin ext; /* number of runnung processors */ 1 137 dcl scs$bos_processor_tag fixed bin (3) ext; /* CPU tag of processor running BOS */ 1 138 dcl scs$faults_initialized bit (1) aligned ext; /* ON after faults have been enabled */ 1 139 dcl scs$sys_trouble_pending bit (1) aligned ext; /* sys_trouble event is pending in the system */ 1 140 dcl scs$fast_cam_pending (0:7) bit (36) aligned ext; /* checkoff cells for cam connect */ 1 141 dcl scs$interrupt_controller fixed bin (3) ext; /* port number of low order controller */ 1 142 dcl scs$processor_start_int_no fixed bin (5) ext; /* interrupt cell for starting a processor */ 1 143 dcl scs$processor bit (8) aligned ext; /* bits ON for online CPUs */ 1 144 dcl scs$processor_start_wait bit (8) aligned ext; /* checkoff flags for waiting for new processor */ 1 145 1 146 dcl scs$trouble_dbrs (0:7) fixed bin (71); /* DBR values at system crash time */ 1 147 1 148 dcl scs$port_addressing_word (0:7) bit (3) aligned ext; /* active module port number for each controller */ 1 149 1 150 dcl scs$cfg_data (0:7) fixed bin (71) aligned ext; /* RSCR-CFG data from each controller */ 1 151 1 152 dcl scs$cfg_data_save fixed bin (71) aligned ext; /* RSCR-CFG save area for ISOLTS CPU testing */ 1 153 1 154 dcl scs$expanded_ports bit (1) unaligned dim (0:7) external; 1 155 /* Which ports have expanders */ 1 156 1 157 dcl scs$processor_switch_data (0:4) bit (36) aligned ext; /* raw data from RSW 0 thru 4 */ 1 158 dcl scs$processor_switch_template (0:4) bit (36) aligned ext; /* expected data from RSW 0 thru 4 */ 1 159 dcl scs$processor_switch_compare (0:4) bit (36) aligned ext; /* discrepancies from expected data */ 1 160 dcl scs$processor_switch_mask (0:4) bit (36) aligned ext; /* masks for comparing switch data */ 1 161 1 162 dcl scs$processor_data_switch_value bit (36) aligned ext; /* Correct value for CPU data switches */ 1 163 1 164 dcl scs$controller_config_size (0:7) fixed bin (14) aligned ext; 1 165 /* Controller size on config card */ 1 166 1 167 dcl scs$reconfig_locker_id char (32) aligned ext; /* process group ID of process doing reconfiguration */ 1 168 1 169 dcl scs$scas_page_table (0:31) bit (36) aligned external static; 1 170 /* PTWs for SCAS pages */ 1 171 1 172 dcl scs$cycle_priority_template bit (7) aligned ext; /* template for setting anti-hog switches */ 1 173 dcl scs$set_cycle_switches bit (1) aligned ext; /* flag to set ant-hog switches */ 1 174 1 175 1 176 dcl ( 1 177 IOM_PORT init (1), 1 178 CPU_PORT init (2), 1 179 BULK_PORT init (3) 1 180 ) fixed bin int static options (constant); /* values for scs$port_data.assigned */ 1 181 1 182 1 183 /* END INCLUDE FILE scs.incl.pl1 */ 133 2 1 /* BEGIN INCLUDE FILE cds_args.incl.pl1 */ 2 2 2 3 dcl 1 cds_args based aligned, 2 4 2 sections (2), 2 5 3 p ptr, /* pointer to data for text/static section */ 2 6 3 len fixed bin (18), /* size of text/static section */ 2 7 3 struct_name char (32), /* name of declared structure for this section */ 2 8 2 seg_name char (32), /* name to create segment by */ 2 9 2 num_exclude_names fixed bin, /* number of names in exclude array */ 2 10 2 exclude_array_ptr ptr, /* pointer to array of exclude names */ 2 11 2 switches, /* control switches */ 2 12 3 defs_in_link bit (1) unal, /* says put defs in linkage */ 2 13 3 separate_static bit (1) unal, /* says separate static section is wanted */ 2 14 3 have_text bit (1) unal, /* ON if text section given */ 2 15 3 have_static bit (1) unal, /* ON if static section given */ 2 16 3 pad bit (32) unal; 2 17 2 18 dcl exclude_names (1) char (32) based; /* pointed to be cds_args.exclude_array_ptr */ 2 19 2 20 /* END INCLUDE FILE cds_args.incl.pl1 */ 134 135 136 end scs; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/11/89 0800.9 !BBBJZjXmhKLMcq.pl1 >spec>install>1110>scs.cds 133 1 10/12/83 0943.5 scs.incl.pl1 >ldd>include>scs.incl.pl1 134 2 04/01/76 2209.5 cds_args.incl.pl1 >ldd>include>cds_args.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. addr builtin function dcl 44 ref 119 125 130 130 cds_args based structure level 1 dcl 2-3 cdsa 000102 automatic structure level 1 dcl 39 set ref 130 130 code 000100 automatic fixed bin(35,0) dcl 38 set ref 130* create_data_segment_ 000012 constant entry external dcl 48 ref 130 exclude_array_ptr 42 000102 automatic pointer level 2 dcl 39 set ref 125* exclude_pad 000000 constant char(32) initial array packed unaligned dcl 34 set ref 125 have_text 44(02) 000102 automatic bit(1) level 3 packed packed unaligned dcl 39 set ref 128* len 2 000102 automatic fixed bin(18,0) array level 3 dcl 39 set ref 120* num_exclude_names 40 000102 automatic fixed bin(17,0) level 2 dcl 39 set ref 124* p 000102 automatic pointer array level 3 dcl 39 set ref 119* scs 000150 automatic structure level 1 dcl 50 set ref 115* 119 120 scs$controller_data 000014 external static structure array level 1 dcl 1-6 scs$cow 000022 external static structure array level 1 dcl 1-65 scs$cow_ptrs 000024 external static structure array level 1 dcl 1-77 scs$port_data 000020 external static structure array level 1 dcl 1-56 scs$processor_data 000016 external static structure array level 1 dcl 1-35 scs$processor_test_data 000060 external static structure level 1 dcl 1-114 scs$reconfig_general_cow 000026 external static structure level 1 dcl 1-82 sections 000102 automatic structure array level 2 dcl 39 seg_name 30 000102 automatic char(32) level 2 dcl 39 set ref 123* size builtin function dcl 44 ref 120 string builtin function dcl 44 set ref 127* struct_name 3 000102 automatic char(32) array level 3 dcl 39 set ref 121* switches 44 000102 automatic structure level 2 dcl 39 set ref 127* unspec builtin function dcl 44 set ref 115* NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. BULK_PORT constant fixed bin(17,0) initial dcl 1-176 CPU_PORT constant fixed bin(17,0) initial dcl 1-176 IOM_PORT constant fixed bin(17,0) initial dcl 1-176 bin builtin function dcl 44 bit builtin function dcl 44 exclude_names based char(32) array packed unaligned dcl 2-18 i 000147 automatic fixed bin(17,0) dcl 40 null builtin function dcl 44 scs$bos_processor_tag 000076 external static fixed bin(3,0) dcl 1-137 scs$bos_restart_flags 000072 external static bit(8) dcl 1-135 scs$cam_pair 000046 external static fixed bin(71,0) dcl 1-103 scs$cam_wait 000050 external static bit(8) dcl 1-104 scs$cfg_data 000120 external static fixed bin(71,0) array dcl 1-150 scs$cfg_data_save 000122 external static fixed bin(71,0) dcl 1-152 scs$connect_lock 000064 external static bit(36) dcl 1-132 scs$controller_config_size 000140 external static fixed bin(14,0) array dcl 1-164 scs$cpu_test_mask 000036 external static bit(72) dcl 1-96 scs$cpu_test_pattern 000044 external static bit(36) dcl 1-99 scs$cycle_priority_template 000146 external static bit(7) dcl 1-172 scs$expanded_ports 000124 external static bit(1) array packed unaligned dcl 1-154 scs$fast_cam_pending 000104 external static bit(36) array dcl 1-140 scs$faults_initialized 000100 external static bit(1) dcl 1-138 scs$idle_aptep 000062 external static pointer array packed unaligned dcl 1-130 scs$interrupt_controller 000106 external static fixed bin(3,0) dcl 1-141 scs$mask_ptr 000056 external static pointer array packed unaligned dcl 1-110 scs$nprocessors 000074 external static fixed bin(17,0) dcl 1-136 scs$number_of_masks 000040 external static fixed bin(17,0) dcl 1-97 scs$open_level 000032 external static bit(72) dcl 1-94 scs$port_addressing_word 000116 external static bit(3) array dcl 1-148 scs$processor 000112 external static bit(8) dcl 1-143 scs$processor_data_switch_value 000136 external static bit(36) dcl 1-162 scs$processor_start_int_no 000110 external static fixed bin(5,0) dcl 1-142 scs$processor_start_mask 000034 external static bit(72) dcl 1-95 scs$processor_start_pattern 000042 external static bit(36) dcl 1-98 scs$processor_start_wait 000114 external static bit(8) dcl 1-144 scs$processor_switch_compare 000132 external static bit(36) array dcl 1-159 scs$processor_switch_data 000126 external static bit(36) array dcl 1-157 scs$processor_switch_mask 000134 external static bit(36) array dcl 1-160 scs$processor_switch_template 000130 external static bit(36) array dcl 1-158 scs$read_mask 000054 external static bit(36) array dcl 1-109 scs$reconfig_lock 000066 external static bit(36) dcl 1-133 scs$reconfig_locker_id 000142 external static char(32) dcl 1-167 scs$scas_page_table 000144 external static bit(36) array dcl 1-169 scs$set_cycle_switches 000150 external static bit(1) dcl 1-173 scs$set_mask 000052 external static bit(36) array dcl 1-108 scs$sys_level 000030 external static bit(72) dcl 1-93 scs$sys_trouble_pending 000102 external static bit(1) dcl 1-139 scs$trouble_dbrs 000556 automatic fixed bin(71,0) array dcl 1-146 scs$trouble_flags 000070 external static bit(8) dcl 1-134 NAME DECLARED BY EXPLICIT CONTEXT. scs 000012 constant entry external dcl 29 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 662 1034 56 672 Length 6620 56 152 5550 603 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME scs 390 external procedure is an external procedure. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME scs 000100 code scs 000102 cdsa scs 000147 i scs 000150 scs scs 000556 scs$trouble_dbrs scs THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out return_mac ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. create_data_segment_ THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. scs$controller_data scs$cow scs$cow_ptrs scs$port_data scs$processor_data scs$processor_test_data scs$reconfig_general_cow LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 29 000011 115 000017 119 000022 120 000024 121 000026 123 000031 124 000034 125 000036 127 000040 128 000041 130 000043 131 000055 Object Segment >spec>install>1110>scs Created on 11/11/89 1100.8 mst Sat by Hirneisen.SysMaint.a using create_data_segment_, Version II of Thursday, November 20, 1986 Object Text Defs Link Symb Static Start 0 0 406 1232 1242 1242 Length 1514 406 624 10 236 0 54 Definitions: segname: scs text|201 bos_processor_tag text|177 bos_restart_flags text|130 cam_pair text|132 cam_wait text|256 cfg_data text|276 cfg_data_save text|174 connect_lock text|325 controller_config_size text|2 controller_data text|62 cow text|102 cow_ptrs text|122 cpu_test_mask text|126 cpu_test_pattern text|215 cycle_priority_template text|223 drl_message_pointer text|405 end_of_scs text|127 expanded_ports text|204 fast_cam_pending text|202 faults_initialized text|164 idle_aptep text|214 interrupt_controller text|154 mask_ptr text|200 nprocessors text|124 number_of_masks text|116 open_level text|246 port_addressing_word text|52 port_data text|220 processor text|42 processor_data text|324 processor_data_switch_value text|217 processor_start_int_no text|120 processor_start_mask text|125 processor_start_pattern text|221 processor_start_wait text|312 processor_switch_compare text|300 processor_switch_data text|317 processor_switch_mask text|305 processor_switch_template text|224 processor_test_data text|144 read_mask text|112 reconfig_general_cow text|175 reconfig_lock text|335 reconfig_locker_id text|345 scas_page_table text|216 set_cycle_switches text|134 set_mask text|0 start_of_scs symb|0 symbol_table text|114 sys_level text|203 sys_trouble_pending text|226 trouble_dbrs text|176 trouble_flags text|222 trouble_processid No Links. ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved