COMPILATION LISTING OF SEGMENT stop_cpu Compiled by: Multics PL/I Compiler, Release 32f, of October 9, 1989 Compiled at: Bull HN, Phoenix AZ, System-M Compiled on: 11/11/89 1026.9 mst Sat Options: optimize map 1 /****^ *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Bull Inc., 1987 * 4* * * 5* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 6* * * 7* *********************************************************** */ 8 9 /* STOP_CPU - Remove a Central Processor. 10* modified 3/5/76 by Noel I. Morris for new reconfig 11* modified 03/01/77 by THVV for prds with branch 12* modified 02/05/79 by BSG for port expanders 13* modified September 1981 by J. Bongiovanni for set_procs_required 14* modified April 1984 by Chris Jones to update config deck to its partition when changed 15* except during shutdown (added shutdown entry too) 16**/ 17 18 19 /****^ HISTORY COMMENTS: 20* 1) change(86-09-23,Beattie), approve(86-08-11,MCR7517), 21* audit(86-10-23,Fawcett), install(86-11-03,MR12.0-1206): 22* No BOS support for MR12. 23* END HISTORY COMMENTS */ 24 25 26 /* format: style4,delnl,insnl,indattr,ifthen,dclind10 */ 27 stop_cpu: 28 proc (tag, rcode); 29 30 dcl tag fixed bin (3); 31 dcl rcode fixed bin (35); 32 33 dcl pdp ptr; /* pointer to correct element of processor data */ 34 dcl new_pdp ptr; /* pointer to correct element of processor data */ 35 dcl new_tag fixed bin (3); /* tag of another CPU */ 36 dcl found bit (1) aligned; /* useful switch */ 37 dcl mask_temp fixed bin (71); /* for call to wire_and_mask */ 38 dcl ptp ptr; /* for call to wired_and_mask */ 39 dcl cpu_mask bit (8) aligned; /* for set_procs_required */ 40 dcl code fixed bin (35); /* error code */ 41 dcl timnow fixed bin (52); /* time when waiting for CPU to stop */ 42 dcl shutdown_entry bit (1) aligned; 43 44 dcl LETTERS char (8) static options (constant) init ("ABCDEFGH"); 45 dcl my_name char (8) static options (constant) init ("stop_cpu"); 46 47 dcl prds$simulated_mask ext, 48 tc_data$ncpu fixed bin ext; 49 50 dcl set_procs_required entry (bit (8) aligned, fixed bin (35)), 51 pxss$unthread_apte entry (ptr), 52 privileged_mode_ut$cioc 53 entry (ptr), 54 privileged_mode_ut$wire_and_mask 55 entry (fixed bin (71), ptr), 56 privileged_mode_ut$unwire_unmask 57 entry (fixed bin (71), ptr), 58 wire_proc$wire_me entry, 59 wire_proc$unwire_me entry, 60 scr_util$set_mask entry (fixed bin (3), fixed bin (3), bit (72) aligned), 61 scr_util$reassign_mask entry (fixed bin (3), fixed bin (3)), 62 scr_util$set_port_enable 63 entry (fixed bin (3), bit (1) unal), 64 scr_util$update_export_xipmsk 65 entry (fixed bin (3)), 66 scr_util$set_export_enable 67 entry (fixed bin (3), fixed bin (3), bit (1) aligned), 68 mask_instruction$staq entry returns (bit (36) aligned), 69 mask_instruction$ldaq entry returns (bit (36) aligned), 70 config_$find_2 entry (char (4) aligned, fixed bin (35), ptr), 71 config_$update entry (), 72 syserr$error_code entry options (variable), 73 syserr entry options (variable); 74 75 dcl 1 pdata based (pdp) like scs$processor_data aligned; 76 dcl 1 npdata based (new_pdp) like scs$processor_data aligned; 77 78 dcl (addr, clock, substr, unspec) 79 builtin; 80 81 82 shutdown_entry = "0"b; 83 goto SHUTDOWN_COMMON; 84 85 shutdown: 86 entry (tag, rcode); 87 88 shutdown_entry = "1"b; 89 90 SHUTDOWN_COMMON: /* The following code effects the first steps in removing a processor. */ 91 pdp = addr (scs$processor_data (tag)); /* Get ptr to data for CPU to be deleted. */ 92 fgbxp = addr (flagbox$); /* Get pointer to BCE flagbox segment. */ 93 94 95 /* If the bootload processor is being removed, find another CPU 96* to be the bootload processor. */ 97 98 if tag = scs$bos_processor_tag then do; 99 found = "0"b; /* Initialize switch. */ 100 do new_tag = 0 to 7 while (^found); 101 new_pdp = addr (scs$processor_data (new_tag)); 102 /* If booload processor, look for another. */ 103 104 if npdata.online then /* If online ... */ 105 if new_tag ^= tag then /* ... and we're not looking at CPU to be removed ... */ 106 if npdata.interrupt_cpu /* ... and CPU can take interrupts */ 107 & ^npdata.expanded_port then do; 108 /* ...and not on expander */ 109 found = "1"b; /* Found candidate to be bootload processor. */ 110 scs$bos_processor_tag = new_tag; 111 call syserr (ANNOUNCE, "^a: CPU ^a is now the bootload processor.", my_name, 112 substr (LETTERS, new_tag + 1, 1)); 113 fgbx.hc_dbr = unspec (scs$idle_aptep (new_tag) -> apte.dbr); 114 end; /* Save DBR of new bootload processor's idle process. */ 115 end; 116 if ^found then do; 117 rcode = rcerr_delcpu_no_good_blcpu; 118 return; 119 end; 120 end; 121 122 123 /* Issue connect for processor to remove itself (it will reset procs 124* required when it goes offline) */ 125 126 cpu_mask = "0"b; 127 substr (cpu_mask, scs$bos_processor_tag + 1, 1) = "1"b; 128 call set_procs_required (cpu_mask, code); 129 if code ^= 0 then do; /* Couldn't run on bootload processor */ 130 rcode = rcerr_sprq_failed; 131 return; 132 end; 133 134 pdata.delete_cpu = "1"b; /* Set flag telling CPU to delete itself. */ 135 call privileged_mode_ut$cioc (addr (scs$cow (tag).cow)); 136 /* Send connect to the CPU. */ 137 138 call set_procs_required ("0"b, code); /* Run on any processor now. */ 139 140 /* Wait for processor to come to a stop. */ 141 142 timnow = clock; /* Get time now. */ 143 do while (^pdata.halted_cpu); /* Wait for processor to stop itself. */ 144 if clock - timnow > 30000000 then do; /* Allow 30 seconds. */ 145 rcode = rcerr_delcpu_no_stop; /* Then return error code. */ 146 return; 147 end; 148 end; 149 150 /* The following code effects the final steps in removing a processor. 151* The processor has already stopped itself. */ 152 153 pdp = addr (scs$processor_data (tag)); /* Get pointer to processor data. */ 154 155 /* Now update config info. */ 156 157 scs$nprocessors = scs$nprocessors - 1; /* Keep count of number of CPU's. */ 158 tc_data$ncpu = tc_data$ncpu - 1; 159 160 call syserr (ANNOUNCE, "^a: Removed CPU ^a.", my_name, substr (LETTERS, tag + 1, 1)); 161 go to destroy; 162 163 destroy_1: 164 entry (tag, rcode); 165 166 shutdown_entry = "0"b; 167 168 destroy: 169 pdp = addr (scs$processor_data (tag)); /* Get pointer to data for stopped processor. */ 170 171 /* Update the config deck. */ 172 173 if ^shutdown_entry then do; 174 call config_$find_2 (CPU_CARD_WORD, tag + 1, cpu_cardp); 175 /* Get pointer to correct config card. */ 176 cpu_card.state = "off "; 177 call config_$update (); 178 end; 179 180 /* Destroy the idle process belonging to the stopped processor. */ 181 182 call pxss$unthread_apte ((scs$idle_aptep (tag))); /* Unthread APTE from idle queue */ 183 184 /* Disable all interrupts to the removed processor. Turn off 185* the port enable bit for this processor in all controllers. */ 186 187 call scr_util$set_mask (scs$interrupt_controller, (pdata.controller_port), scs$sys_level); 188 /* Mask interrupts to stopped CPU. */ 189 190 if ^pdata.expanded_port /* Vanilla port? */ 191 then 192 call scr_util$set_port_enable ((pdata.controller_port), "0"b); 193 /* Disable the port in all controllers. */ 194 else call scr_util$set_export_enable ((pdata.controller_port), (pdata.expander_port), "0"b); 195 /* Leave gross disabling and interrupt disabling 'till last */ 196 197 198 /* If another running processor needs a controller mask, and the removed 199* processor had one, give the mask to the running processor. */ 200 201 found = "0"b; /* Initialize flag. */ 202 if pdata.interrupt_cpu then do; /* If removed processor took interrupts ... */ 203 do new_tag = 0 to 7 while (^found); /* Search for CPU to give interrupts to. */ 204 new_pdp = addr (scs$processor_data (new_tag)); 205 206 if npdata.online & ^npdata.interrupt_cpu then do; 207 208 209 call scr_util$reassign_mask (tag, new_tag); 210 /* Assign mask to new CPU. */ 211 212 cpu_mask = "0"b; 213 substr (cpu_mask, new_tag + 1, 1) = "1"b; 214 call set_procs_required (cpu_mask, code); 215 /* Run on specified CPU */ 216 if code ^= 0 then 217 call syserr$error_code (CRASH, code, "^a: Unable to run on CPU ^a", my_name, 218 substr (LETTERS, new_tag + 1, 1)); 219 else do; 220 found = "1"b; /* Found a candidate */ 221 call wire_proc$wire_me; /* Wire this code down. */ 222 call privileged_mode_ut$wire_and_mask (mask_temp, ptp); 223 /* Don't allow interrupts now. */ 224 225 scs$mask_ptr (new_tag) = scs$mask_ptr (tag); 226 /* Set mask pointer. */ 227 scs$set_mask (new_tag) = scs$set_mask (tag); 228 /* Set SMCM instruction. */ 229 scs$read_mask (new_tag) = scs$read_mask (tag); 230 /* Set RMCM instruction. */ 231 npdata.interrupt_cpu = "1"b; /* CPU can now receive interrupts. */ 232 call privileged_mode_ut$unwire_unmask (mask_temp, ptp); 233 call wire_proc$unwire_me; /* No longer need to be wired and masked. */ 234 call set_procs_required ("0"b, code); 235 /* Can continue running on any CPU. */ 236 237 pdata.interrupt_cpu = "0"b; /* This processor no longer will get interrupts. */ 238 scs$mask_ptr (tag) = addr (prds$simulated_mask); 239 /* Set pointer to simulated mask. */ 240 scs$set_mask (tag) = mask_instruction$staq (); 241 /* Make SMCM into STAQ. */ 242 scs$read_mask (tag) = mask_instruction$ldaq (); 243 /* Make RMCM into LDAQ. */ 244 end; 245 end; 246 end; 247 end; 248 249 /* Set the port expander XIP enable bits the new way; 250* maybe disable entire SC port. */ 251 252 if pdata.expanded_port then do; 253 call scr_util$update_export_xipmsk ((pdata.controller_port)); 254 call scr_util$set_export_enable ((pdata.controller_port), (pdata.expander_port), "0"b); 255 found = "0"b; /* Look for major port users */ 256 do new_tag = 0 to 7 while (^found); 257 new_pdp = addr (scs$processor_data (new_tag)); 258 if npdata.controller_port = pdata.controller_port & npdata.online & tag ^= new_tag then 259 found = "1"b; 260 end; 261 if ^found then 262 call scr_util$set_port_enable ((pdata.controller_port), "0"b); 263 end; 264 265 rcode = 0; 266 267 return; 268 1 1 1 2 /* Begin include file ...... rcerr.incl.pl1 */ 1 3 /* These are the reconfiguration error codes. */ 1 4 /* Created 4/5/76 by Noel I. Morris */ 1 5 /* Modified 5/25/78 by J. A. Bush to add ISOLTS reconfig error codes */ 1 6 /* Modified 5/79 by BSG for port expander */ 1 7 1 8 1 9 /****^ HISTORY COMMENTS: 1 10* 1) change(88-07-27,Farley), approve(88-10-05,MCR7968), 1 11* audit(88-10-10,Beattie), install(88-10-14,MR12.2-1166): 1 12* Added new rcerr_addscu_memoverlap error code. 1 13* END HISTORY COMMENTS */ 1 14 1 15 1 16 dcl (rcerr_addcpu_no_response init (1), /* no response from CPU */ 1 17 rcerr_addcpu_bad_switches init (2), /* CPU config switches set improperly */ 1 18 rcerr_addcpu_trouble init (3), /* trouble fault adding CPU */ 1 19 rcerr_addcpu_startup init (4), /* startup fault adding CPU */ 1 20 rcerr_addcpu_lockup init (5), /* lockup fault adding CPU */ 1 21 rcerr_addcpu_gcos init (6), /* attempt to add processor in GCOS mode */ 1 22 rcerr_addcpu_amoff init (7), /* attempt to add processor with assoc mem off */ 1 23 rcerr_addcpu_enable init (8) /* controller port for CPU not enabled */ 1 24 ) fixed bin static options (constant); 1 25 1 26 dcl (rcerr_delcpu_no_stop init (1), /* CPU did not stop running */ 1 27 rcerr_delcpu_last init (2), /* attempt to delete last CPU */ 1 28 rcerr_delcpu_no_good_blcpu init (3) /* no suitable bootload CPU left */ 1 29 ) fixed bin static options (constant); 1 30 1 31 dcl (rcerr_addscu_size init (1), /* memory size discrepancy */ 1 32 rcerr_addscu_dup_mask init (2), /* duplicate mask assignment */ 1 33 rcerr_addscu_no_mask init (3), /* no mask assigned to CPU */ 1 34 rcerr_addscu_bad_mask init (4), /* mask assigned to non-CPU port */ 1 35 rcerr_addscu_fault init (5), /* fault trying to add controller */ 1 36 rcerr_addscu_switches init (6), /* some active module has incorrect switches */ 1 37 rcerr_addscu_enable init (7), /* some active module not enabled */ 1 38 rcerr_addscu_manual init (8), /* 4MW SCU is in manual mode */ 1 39 rcerr_addscu_oldexpand init (9), /* Adding 6000 SCU with port expander */ 1 40 rcerr_addscu_bigconfig init (10), /* SCU has less memory than config cards say */ 1 41 rcerr_addscu_memoverlap init (11) /* SCU has possible memory address overlap */ 1 42 ) fixed bin static options (constant); 1 43 1 44 dcl (rcerr_delmain_nomem init (1), /* not enough main memory left */ 1 45 rcerr_delmain_abs_wired init (2) /* abs wired pages in memory */ 1 46 ) fixed bin static options (constant); 1 47 1 48 dcl (rcerr_locked init (12), /* database already locked */ 1 49 rcerr_online init (13), /* device already online */ 1 50 rcerr_no_config init (14), /* device not in configuration */ 1 51 rcerr_not_online init (15), /* device not online */ 1 52 rcerr_range init (16), /* request is out of range */ 1 53 rcerr_sprq_failed init (17) /* could not set CPU required */ 1 54 1 55 ) fixed bin static options (constant); 1 56 1 57 dcl (rcerr_isolts_locked init (1), /* reconfig_lock locked to another process */ 1 58 rcerr_isolts_illegal_cpu init (2), /* illegal cpu tag */ 1 59 rcerr_isolts_cpu_online init (3), /* requested cpu is online */ 1 60 rcerr_isolts_no_config init (4), /* requested cpu is not configured */ 1 61 rcerr_isolts_two_scu init (5), /* Must have at least two SCUs to run ISOLTS */ 1 62 rcerr_isolts_illegal_scu init (6), /* illegal scu tag */ 1 63 rcerr_isolts_bootload_scu init (7), /* requested scu is the bootload memory */ 1 64 rcerr_isolts_scu_not init (8), /* requested scu is not configured */ 1 65 rcerr_isolts_not init (9), /* requesting process is not ISOLTS process */ 1 66 rcerr_isolts_wrong_cell init (10), /* interrupt answered in correct scu but wrong cell */ 1 67 rcerr_isolts_wrong_scu init (11), /* interrupt answered in wrong scu */ 1 68 rcerr_isolts_wrong_scu_cell init (12), /* interrupt answered in wrong scu on wrong cell */ 1 69 rcerr_isolts_no_response init (13), /* No response to a processor start interrupt */ 1 70 rcerr_isolts_bad_switches init (14), /* read switch data is not in expected format */ 1 71 rcerr_isolts_lda_fail init (15), /* A LDA 2 did not operate correctly */ 1 72 rcerr_isolts_no_str_flt init (16), /* No store falt when a LDA 64k was executed */ 1 73 rcerr_isolts_no_mask init (17) /* No mask set for test cpu */ 1 74 ) fixed bin static options (constant); 1 75 1 76 dcl 1 switch_w1 aligned based, /* template for switch word 1, when containing diagnostic info */ 1 77 (2 cell fixed bin (5), /* interrupt cell being used */ 1 78 2 errtag fixed bin (5), /* tag of scu in error */ 1 79 2 valid bit (1), /* if on then offset field is valid */ 1 80 2 pad bit (5), 1 81 2 offset bit (18)) unaligned; /* offset of error if any */ 1 82 1 83 /* End of include file ...... rcerr.incl.pl1 */ 1 84 269 270 2 1 /* BEGIN INCLUDE FILE ... config_cpu_card.incl.pl1 ... 11/27/80 W. Olin Sibert */ 2 2 /* format: style4 */ 2 3 2 4 dcl cpu_cardp pointer; /* pointer to CPU card */ 2 5 2 6 dcl 1 cpu_card aligned based (cpu_cardp), /* CPU card declaration */ 2 7 2 word char (4), /* "cpu" */ 2 8 2 tag fixed bin (3), /* CPU tag from switches, plus one */ 2 9 2 port fixed bin (3), /* Controller port for CPU */ 2 10 2 state char (4), /* "on", "off", "shut", or "test" */ 2 11 2 type char (4), /* "l68", "dps", "dps8" */ 2 12 2 13 2 model fixed bin, /* 60., 80., or 70. */ 2 14 2 cache_size fixed bin, /* either 0. 2. 8. 16. or 32. */ 2 15 2 expander_port fixed bin (3), /* If present, indicates expander sub-port */ 2 16 2 17 2 pad (7) bit (36) aligned, /* Pad to 15 fields */ 2 18 2 19 2 type_word aligned, 2 20 3 field_type (14) bit (2) unaligned, /* type of each field; see config_deck.incl.pl1 */ 2 21 3 pad1 bit (4) unaligned, 2 22 3 n_fields fixed bin (4) unsigned unaligned; /* number of fields used on card */ 2 23 2 24 dcl CPU_CARD_WORD char (4) aligned internal static options (constant) init ("cpu"); 2 25 2 26 /* END INCLUDE FILE ... config_cpu_card.incl.pl1 */ 271 272 3 1 /* BEGIN INCLUDE FILE ... flagbox.incl.pl1 */ 3 2 3 3 3 4 /****^ HISTORY COMMENTS: 3 5* 1) change(87-02-26,Farley), approve(87-04-15,MCR7661), 3 6* audit(87-04-21,Fawcett), install(87-04-28,MR12.1-1028): 3 7* Added io_reconfig flag to inhibit BCE from attempting an emergency 3 8* shutdown when the data in memory could be corrupted. 3 9* END HISTORY COMMENTS */ 3 10 3 11 3 12 /* last modified 5/3/77 by Noel I. Morris */ 3 13 /* Modified 8/79 by R.J.C. Kissel to add FNP blast message. */ 3 14 /* Modified 7/82 BIM for recognizable sentinel field */ 3 15 /* Modified for bootload Multics flagbox starting in 8/83 by Keith Loepere. */ 3 16 3 17 /* The contents of this segment are data shared by Multics and bce. 3 18* This entity occupies the locations within the toehold starting at 40o 3 19* (not counting the toehold_used spacer at the beginning). */ 3 20 3 21 dcl flagbox$ ext; 3 22 dcl fgbxp ptr; 3 23 3 24 dcl 1 fgbx based (fgbxp) aligned, 3 25 2 toehold_used (32) bit (36) aligned, /* flagbox seg now mapped onto all of first page of toehold - 3 26* This is what was unused before. */ 3 27 2 flags (36) bit (1) unal, /* communications switches */ 3 28 2 slt_segno bit (18), /* segment # of the SLT */ 3 29 2 pad1 fixed bin, 3 30 2 rtb, /* return to bce info */ 3 31 (3 ssenb bit (1), /* "1"b if storage system enabled */ 3 32 3 call_bce bit (1), /* "1"b if bce called by operator */ 3 33 3 shut bit (1), /* "1"b if bce called after shutdown */ 3 34 3 mess bit (1), /* "1"b if message has been provided */ 3 35 3 alert bit (1), /* "1"b if audible alarm to be sounded */ 3 36 3 breakpoint bit (1), /* "1"b is breakpoint caused call to bce */ 3 37 3 manual_crash bit (1), /* either manual entry or execute fault */ 3 38 3 io_reconfig bit (1), /* "1"b if I/O reconfiguration */ 3 39 /* could cause memory corruption */ 3 40 3 pad bit (21), 3 41 3 bce_entry fixed bin (6) uns) unal, /* type of entry into bce 3 42* 00o => Multics entry 3 43* 20o => manual entry 3 44* 40o => esd entry */ 3 45 2 sentinel char (32) aligned, /* set by bce (for now) */ 3 46 2 sst_sdw bit (72), /* set by init_sst */ 3 47 2 hc_dbr bit (72), /* set by start_cpu, idle DBR */ 3 48 2 message char (64), /* message for return to bce */ 3 49 2 return_to_bce_command char (128) unal; /* command to run upon crash/shutdown */ 3 50 3 51 declare FLAGBOX_SENTINEL char (32) init ("Flagbox & Toehold Valid") int static options (constant); 3 52 3 53 /* END INCLUDE FILE ... flagbox.incl.pl1 */ 273 274 4 1 /* BEGIN INCLUDE FILE scs.incl.pl1 ... March 1983 */ 4 2 /* format: style4 */ 4 3 4 4 /* Information about system controllers */ 4 5 4 6 dcl 1 scs$controller_data (0:7) aligned ext, /* per-controller info */ 4 7 2 size fixed bin (17) unaligned, /* size (in 1024 word blocks) of this controller */ 4 8 2 base fixed bin (17) unaligned, /* abs address (0 mod 1024) for base of this controller */ 4 9 2 eima_data (4) unaligned, /* EIMA information for this controller */ 4 10 3 mask_available bit (1) unaligned, /* ON if corresponding mask exists */ 4 11 3 mask_assigned bit (1) unaligned, /* ON if mask assigned to a port */ 4 12 3 mbz bit (3) unaligned, 4 13 3 mask_assignment fixed bin (3) unaligned, /* port to which mask is assigned */ 4 14 2 info aligned, 4 15 3 online bit (1) unaligned, /* ON if controller is online */ 4 16 3 offline bit (1) unaligned, /* ON if controller is offline but can be added */ 4 17 3 store_a_online bit (1) unaligned, /* ON if store A is online */ 4 18 3 store_a1_online bit (1) unaligned, /* ON if store A1 is online */ 4 19 3 store_b_online bit (1) unaligned, /* ON if store B is online */ 4 20 3 store_b1_online bit (1) unaligned, /* ON if store B1 is online */ 4 21 3 store_b_is_lower bit (1) unaligned, /* ON if store B is lower */ 4 22 3 ext_interlaced bit (1) unaligned, /* ON if this SCU is interlaced with other SCU */ 4 23 3 int_interlaced bit (1) unaligned, /* ON if this SCU is internally interlaced */ 4 24 3 four_word bit (1) unaligned, /* ON if external interlace is 4-word */ 4 25 3 cyclic_priority (7) bit (1) unaligned, /* Cyclic priority for adjacent ports */ 4 26 3 type bit (4) unaligned, /* Model number for this controller */ 4 27 3 abs_wired bit (1) unaligned, /* ON if controller can have abs_wired pages */ 4 28 3 program bit (1) unaligned, /* PROGRAM/MANUAL switch setting */ 4 29 3 mbz bit (13) unaligned, 4 30 2 lower_store_size fixed bin (17) unaligned, /* size (in 1024 word blocks) of lower store */ 4 31 2 upper_store_size fixed bin (17) unaligned; /* size (in 1024 word blocks) of upper store */ 4 32 4 33 /* Information about CPUs */ 4 34 4 35 dcl 1 scs$processor_data (0:7) aligned ext, /* information about CPUs in the system */ 4 36 ( 4 37 2 online bit (1), /* "1"b if CPU is online */ 4 38 2 offline bit (1), /* "1"b if CPU is offline but can be added */ 4 39 2 release_mask bit (1), /* "1"b is this CPU is to give up its mask */ 4 40 2 accept_mask bit (1), /* "1"b if this CPU is to grap mask in idle loop */ 4 41 2 delete_cpu bit (1), /* "1"b if this CPU is to delete itself */ 4 42 2 interrupt_cpu bit (1), /* "1"b if this CPU takes hardware interrupts */ 4 43 2 halted_cpu bit (1), /* "1"b if this CPU has stopped itself (going to BOS) */ 4 44 2 cpu_type fixed bin (2) unsigned, /* 0 => DPS or L68, 1 => DPS8 */ 4 45 2 mbz1 bit (6), 4 46 2 cache_size fixed bin (3) unsigned, /* 0 = No cache; 1 = L68 2K cache; 4 47* 2 = DPS8 8K cache; 3 = DPS8 VS&SC 8K cache; 4 48* 4 = DPS8 VS&SC 16K cache; 5 = DPS8 VS&SC 32K cache 4 49* 7 = ignore cache size (set by ISOLTS reconfig) */ 4 50 2 mbz2 bit (12), 4 51 2 expanded_port bit (1), /* "1"b = on expanded port */ 4 52 2 expander_port fixed bin (2) unsigned, /* The actual expander port */ 4 53 2 controller_port fixed bin (3) unsigned 4 54 ) unaligned; /* Port on controller */ 4 55 4 56 dcl 1 scs$port_data (0:7) aligned external static, /* Info about what is connected to each SCU port */ 4 57 2 assigned fixed bin (4) unsigned unaligned, /* Type of device on this port */ 4 58 2 expander_port bit (1) unaligned, /* "1"b => this port has a port expander */ 4 59 2 expanded_cpu (0:3) bit (1) unaligned, /* "1"b => this expander port has a CPU attached */ 4 60 2 iom_number fixed bin (3) unsigned unaligned, /* IOM number of IOM attached to this port */ 4 61 2 cpu_number (0:3) fixed bin (3) unsigned unaligned, /* CPU number of CPU(s) attached to this port */ 4 62 /* cpu_number (0) is only one if expander_port is "0"b */ 4 63 2 pad bit (12) unaligned; 4 64 4 65 dcl 1 scs$cow (0:7) aligned external, /* Actual connect words */ 4 66 2 pad bit (36) aligned, /* Expander COW's must be odd-word */ 4 67 2 cow, 4 68 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 4 69 3 mbz1 bit (13) unaligned, 4 70 3 expander_command bit (3) unaligned, /* Expander command. */ 4 71 3 mbz2 bit (2) unaligned, 4 72 3 expanded_port bit (1) unaligned, /* "1"b = on expanded port */ 4 73 3 expander_port fixed bin (3) unsigned unaligned, /* Port on expander for cioc */ 4 74 3 mbz3 bit (3) unaligned, 4 75 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 4 76 4 77 dcl 1 scs$cow_ptrs (0:7) external aligned, /* Pointers to COW's */ 4 78 2 rel_cow_ptr bit (18) unal, /* Relative pointer to COW */ 4 79 2 pad bit (12) unal, 4 80 2 tag bit (6) unal; /* Better be zero. */ 4 81 4 82 dcl 1 scs$reconfig_general_cow aligned external, /* Used during reconfig ops. */ 4 83 2 pad bit (36) aligned, 4 84 2 cow, /* Connect operand word, in odd location. */ 4 85 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 4 86 3 mbz1 bit (13) unaligned, 4 87 3 expander_command bit (3) unaligned, /* Expander command. */ 4 88 3 mbz2 bit (9) unaligned, 4 89 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 4 90 4 91 /* MASKS and PATTERNS */ 4 92 4 93 dcl scs$sys_level bit (72) aligned ext; /* mask used while handling I/O interrupts */ 4 94 dcl scs$open_level bit (72) aligned ext; /* mask used during normal operation */ 4 95 dcl scs$processor_start_mask bit (72) aligned ext; /* mask used when starting up a CPU */ 4 96 dcl scs$cpu_test_mask bit (72) aligned ext; /* mask used for ISOLTS CPU testing */ 4 97 dcl scs$number_of_masks fixed bin ext; /* number of masks (starting at sys_level) */ 4 98 dcl scs$processor_start_pattern bit (36) aligned ext; /* SMIC pattern used to send processor start interrupt */ 4 99 dcl scs$cpu_test_pattern bit (36) aligned ext; /* SMIC pattern used for ISOLTS processor testing */ 4 100 4 101 /* CAM and CACHE clear info */ 4 102 4 103 dcl scs$cam_pair fixed bin (71) ext; /* instructions XEDd when CAMing and clearing CACHE */ 4 104 dcl scs$cam_wait bit (8) aligned ext; /* Used when evicting pages from main memory */ 4 105 4 106 /* MASKING INSTRUCTIONS & POINTERS */ 4 107 4 108 dcl scs$set_mask (0:7) bit (36) aligned ext; /* instructions to set mask (STAQ or SMCM) */ 4 109 dcl scs$read_mask (0:7) bit (36) aligned ext; /* instructions to read mask (LDAQ or RMCM) */ 4 110 dcl scs$mask_ptr (0:7) ptr unaligned ext; /* pointers for real or simulated masks */ 4 111 4 112 /* MISCELLANEOUS */ 4 113 4 114 dcl 1 scs$processor_test_data aligned ext, /* info used for cpu testing */ 4 115 ( 4 116 2 active bit (1), /* = "1"b if cpu currently under test */ 4 117 2 scu_state bit (2), /* state of scu being used for testing (see definition below) */ 4 118 2 pad1 bit (4), 4 119 2 req_mem fixed bin (10), /* dedicated memory required to test this cpu */ 4 120 2 cpu_tag fixed bin (5), /* tag of cpu under test */ 4 121 2 scu_tag fixed bin (5), /* tag of scu being used for cpu testing */ 4 122 2 mask_cpu fixed bin (5) 4 123 ) unaligned; /* tag of active cpu that has mask asigned to above scu */ 4 124 4 125 /* scu_state = "00"b => SCU defined by scs$processor_test_data.scu_tag not yet effected */ 4 126 /* scu_state = "01"b => all core removed from SCU, port mask not yet changed */ 4 127 /* scu_state = "10"b => all core removed from SCU, port mask changed */ 4 128 /* scu_state = "11"b => only 64k at base of SCU being used for testing, original port mask restored */ 4 129 4 130 dcl scs$idle_aptep (0:7) ptr unaligned ext; /* pointer to idle process APTE for each processor */ 4 131 4 132 dcl scs$connect_lock bit (36) aligned ext; /* lock for sending connects */ 4 133 dcl scs$reconfig_lock bit (36) aligned ext; /* Lock used during reconfiguration */ 4 134 dcl scs$trouble_flags bit (8) aligned ext; /* checkoff flags for sys_trouble stopping */ 4 135 dcl scs$bos_restart_flags bit (8) aligned ext; /* checkoff flags for restarting after sys_trouble */ 4 136 dcl scs$nprocessors fixed bin ext; /* number of runnung processors */ 4 137 dcl scs$bos_processor_tag fixed bin (3) ext; /* CPU tag of processor running BOS */ 4 138 dcl scs$faults_initialized bit (1) aligned ext; /* ON after faults have been enabled */ 4 139 dcl scs$sys_trouble_pending bit (1) aligned ext; /* sys_trouble event is pending in the system */ 4 140 dcl scs$fast_cam_pending (0:7) bit (36) aligned ext; /* checkoff cells for cam connect */ 4 141 dcl scs$interrupt_controller fixed bin (3) ext; /* port number of low order controller */ 4 142 dcl scs$processor_start_int_no fixed bin (5) ext; /* interrupt cell for starting a processor */ 4 143 dcl scs$processor bit (8) aligned ext; /* bits ON for online CPUs */ 4 144 dcl scs$processor_start_wait bit (8) aligned ext; /* checkoff flags for waiting for new processor */ 4 145 4 146 dcl scs$trouble_dbrs (0:7) fixed bin (71); /* DBR values at system crash time */ 4 147 4 148 dcl scs$port_addressing_word (0:7) bit (3) aligned ext; /* active module port number for each controller */ 4 149 4 150 dcl scs$cfg_data (0:7) fixed bin (71) aligned ext; /* RSCR-CFG data from each controller */ 4 151 4 152 dcl scs$cfg_data_save fixed bin (71) aligned ext; /* RSCR-CFG save area for ISOLTS CPU testing */ 4 153 4 154 dcl scs$expanded_ports bit (1) unaligned dim (0:7) external; 4 155 /* Which ports have expanders */ 4 156 4 157 dcl scs$processor_switch_data (0:4) bit (36) aligned ext; /* raw data from RSW 0 thru 4 */ 4 158 dcl scs$processor_switch_template (0:4) bit (36) aligned ext; /* expected data from RSW 0 thru 4 */ 4 159 dcl scs$processor_switch_compare (0:4) bit (36) aligned ext; /* discrepancies from expected data */ 4 160 dcl scs$processor_switch_mask (0:4) bit (36) aligned ext; /* masks for comparing switch data */ 4 161 4 162 dcl scs$processor_data_switch_value bit (36) aligned ext; /* Correct value for CPU data switches */ 4 163 4 164 dcl scs$controller_config_size (0:7) fixed bin (14) aligned ext; 4 165 /* Controller size on config card */ 4 166 4 167 dcl scs$reconfig_locker_id char (32) aligned ext; /* process group ID of process doing reconfiguration */ 4 168 4 169 dcl scs$scas_page_table (0:31) bit (36) aligned external static; 4 170 /* PTWs for SCAS pages */ 4 171 4 172 dcl scs$cycle_priority_template bit (7) aligned ext; /* template for setting anti-hog switches */ 4 173 dcl scs$set_cycle_switches bit (1) aligned ext; /* flag to set ant-hog switches */ 4 174 4 175 4 176 dcl ( 4 177 IOM_PORT init (1), 4 178 CPU_PORT init (2), 4 179 BULK_PORT init (3) 4 180 ) fixed bin int static options (constant); /* values for scs$port_data.assigned */ 4 181 4 182 4 183 /* END INCLUDE FILE scs.incl.pl1 */ 275 276 5 1 /* BEGIN INCLUDE FILE ... apte.incl.pl1 */ 5 2 5 3 /* Modified 1984-11-11 by E. Swenson for IPC event channel validation. */ 5 4 5 5 dcl aptep pointer; 5 6 5 7 dcl 1 apte based (aptep) aligned, /* APT entry declaration for an active (known) process */ 5 8 2 thread unaligned, /* List thread */ 5 9 3 fp bit (18), /* Forward pointer */ 5 10 3 bp bit (18), /* Backward pointer */ 5 11 2 flags unaligned, /* Flags and miscellaneous */ 5 12 3 mbz bit (1), /* This bit must be zero (sentinel bit) */ 5 13 3 wakeup_waiting bit (1), /* ON if process has received wakeup */ 5 14 3 stop_pending bit (1), /* ON if process has received stop connect */ 5 15 3 pre_empted bit (1), /* ON if process is being pre-empted by get_processor */ 5 16 3 hproc bit (1), /* ON if process is hardcore process */ 5 17 3 loaded bit (1), /* ON if required per-process pages are in memory and wired */ 5 18 3 eligible bit (1), /* ON if process is eligible */ 5 19 3 idle bit (1), /* ON if this is an idle process */ 5 20 3 interaction bit (1), /* ON if process has interacted recently */ 5 21 3 pre_empt_pending bit (1), /* ON if process has received pre-empt connect */ 5 22 3 default_procs_required bit (1), /* ON if apte.procs_required is system default */ 5 23 3 realtime_burst bit (1), /* ON if next eligibility is realtime */ 5 24 3 always_loaded bit (1), /* ON if process is not to be unloaded */ 5 25 3 dbr_loaded bit (1), /* ON if DBR is loaded on some CPU */ 5 26 3 being_loaded bit (1), /* ON if somebody loading this process */ 5 27 3 shared_stack_0 bit (1), /* ON if a shared stack_0 is assigned */ 5 28 3 page_wait_flag bit (1), /* flag ON if waiting for page */ 5 29 3 firstsw bit (1), /* OFF until process is intialized */ 5 30 3 state bit (18), /* execution state */ 5 31 2 page_faults fixed bin (35), /* total page faults for the process */ 5 32 2 processid bit (36), /* bit 0-17: offset of ATPE */ 5 33 /* bit 18-35: sequential number */ 5 34 2 te fixed bin (35), /* virtual time since eligibility award */ 5 35 2 ts fixed bin (35), /* virtual time since scheduling */ 5 36 2 ti fixed bin (35), /* virtual time since interaction */ 5 37 2 timax fixed bin (35), /* maximum value allowed for apte.ti */ 5 38 5 39 /* * * * * * * * */ 5 40 5 41 2 ipc_pointers unaligned, 5 42 3 event_thread bit (18), /* relative pointer to ITT list */ 5 43 3 pad3 bit (18), 5 44 2 ips_message bit (36), /* IPS signals pending */ 5 45 2 asteps unaligned, /* relative ASTE pointers */ 5 46 3 pds bit (18), /* PDS (per-process) */ 5 47 3 dseg bit (18), /* DSEG (per-process) */ 5 48 3 prds bit (18), /* PRDS (per-processor) */ 5 49 2 savex7 bit (18) unaligned, /* x7 at call to getwork (return point in pxss) */ 5 50 2 term_processid bit (36), /* process to send wakeup at temination */ 5 51 2 lock_id bit (36), /* File System unqieu ID associated with process */ 5 52 2 time_used_clock fixed bin (71), /* Total CPU time when process last lost CPU */ 5 53 5 54 /* * * * * * * * */ 5 55 5 56 2 wait_event bit (36) aligned, /* Event ID process awaiting */ 5 57 2 wct_index bit (18) unaligned, /* rel offset of WCTE */ 5 58 2 flags2 unaligned, 5 59 3 priority_scheduling bit (1), /* ON if guaranteed eligibility */ 5 60 3 special_wakeups bit (6), /* Special wakeup channels */ 5 61 3 pad7 bit (7), 5 62 3 batch bit (1), /* ON if absentee */ 5 63 3 pr_tag bit (3), /* CPU tag running or last run */ 5 64 2 state_change_time fixed bin (71), /* Time apte.state last changed */ 5 65 2 alarm_event fixed bin (71), /* wakeup event for alarm clock manager */ 5 66 2 alarm_time_thread bit (18) unaligned, /* thread of processes with pending alarms */ 5 67 2 alarm_time bit (54) unaligned, /* wakeup time for alarm */ 5 68 5 69 /* * * * * * */ 5 70 5 71 2 term_channel fixed bin (71), /* wakeup event for account overflow */ 5 72 2 ws_size fixed bin, /* working set estimate for the process */ 5 73 2 temax fixed bin (35), /* maximum eligibility slice (vcpu) */ 5 74 2 deadline fixed bin (71), /* time of next run */ 5 75 2 lock bit (18) unaligned, /* 0 => APTE locked, unlocked => return point of last unlock */ 5 76 2 unusable bit (18) unaligned, /* locking routines destroy */ 5 77 2 cpu_monitor fixed bin (35), /* if not 0, send wakeup to term_processid when virtual cpu 5 78* /* reaches this (units = 1/1024 sec) */ 5 79 2 paging_measure fixed bin (71), /* cumulative memory units */ 5 80 2 access_authorization bit (72), /* authorization of this process */ 5 81 2 dbr fixed bin (71), /* DBR value (constant since DSEG entry-held) */ 5 82 5 83 2 virtual_cpu_time fixed bin (71), /* cumulative virtual CPU time for the process */ 5 84 2 ittes_sent fixed bin (18), /* Unprocessed ITTs sent by this process */ 5 85 2 ittes_got fixed bin (18), /* Unprocessed ITTs received by this process */ 5 86 5 87 /* Cells used to drive and instrument finite-state model for response time 5 88* measurement. Maintained by meter_response_time */ 5 89 5 90 2 current_response_state fixed bin (17) unaligned, /* Process state in modle */ 5 91 2 pad18 bit (18) unaligned, 5 92 2 number_processing fixed bin (35), /* Number interactions */ 5 93 2 last_response_state_time fixed bin (71), /* Clock time at last response state change */ 5 94 2 total_processing_time fixed bin (71), /* Total interaction processing time */ 5 95 5 96 /* * * * * * */ 5 97 5 98 2 begin_interaction_vcpu fixed bin (71), /* Virtual cpu at beginning of last interaction */ 5 99 5 100 /* End of cells for finite-state model */ 5 101 5 102 2 saved_temax fixed bin (35), /* temax at eligibility award */ 5 103 2 procs_required bit (8) unaligned, /* bit mask of CPUs this process can run */ 5 104 2 pad4 bit (28) unaligned, 5 105 2 ipc_r_offset fixed bin (18) unsigned, 5 106 2 ipc_r_factor fixed bin (35) unsigned, 5 107 2 apad (10) fixed bin (35); 5 108 5 109 /* END INCLUDE FILE ... apte.incl.pl1 */ 277 278 6 1 /* BEGIN INCLUDE FILE syserr_constants.incl.pl1 ... 11/11/80 W. Olin Sibert */ 6 2 /* 85-02-12, EJ Sharpe - Added sorting class constants, removed AIM_MESSAGE, added new action code names. */ 6 3 /* 85-04-24, G. Palter - Renamed SYSERR_UNUSED_10 to SYSERR_RING1_ERROR to reflect its actual use. */ 6 4 6 5 /* This include file has an ALM version. Keep 'em in sync! */ 6 6 6 7 dcl ( 6 8 6 9 /* The following constants define the message action codes. This indicates 6 10*how a message is to be handled. */ 6 11 6 12 SYSERR_CRASH_SYSTEM init (1), 6 13 CRASH init (1), /* Crash the system, and bleat plaintively. */ 6 14 6 15 SYSERR_TERMINATE_PROCESS init (2), 6 16 TERMINATE_PROCESS init (2), /* Terminate the process, print the message, and beep. */ 6 17 6 18 SYSERR_PRINT_WITH_ALARM init (3), 6 19 BEEP init (3), /* Beep and print the message on the console. */ 6 20 6 21 SYSERR_PRINT_ON_CONSOLE init (0), 6 22 ANNOUNCE init (0), /* Just print the message on the console. */ 6 23 6 24 SYSERR_LOG_OR_PRINT init (4), 6 25 LOG init (4), /* Log the message, or print it if it can't be logged */ 6 26 6 27 SYSERR_LOG_OR_DISCARD init (5), 6 28 JUST_LOG init (5), /* Just try to log the message, and discard it if it can't be */ 6 29 6 30 6 31 /* The following constants are added to the normal severities to indicate 6 32*different sorting classes of messages. */ 6 33 6 34 SYSERR_SYSTEM_ERROR init (00), /* indicates a standard level system error */ 6 35 SYSERR_RING1_ERROR init (10), /* indicates an error detected in ring 1 (mseg_, RCP) */ 6 36 SYSERR_COVERT_CHANNEL init (20), /* indicates covert channel audit trail message */ 6 37 SYSERR_UNSUCCESSFUL_ACCESS init (30), /* indicates access denial audit trail message */ 6 38 SYSERR_SUCCESSFUL_ACCESS init (40) /* indicates access grant audit trail message */ 6 39 ) fixed bin internal static options (constant); 6 40 6 41 /* END INCLUDE FILE syserr_constants.incl.pl1 */ 279 280 281 /* BEGIN MESSAGE DOCUMENTATION 282* 283* Message: 284* stop_mpx: CPU CPUTAG is now the bootload processor. 285* 286* S: $info 287* 288* T: In response to an operator "rcf dl cpu CPUTAG" command. 289* 290* M: The CPU whose tag is CPUTAG is now the processor on which 291* BCE will run at system shutdown or crash time, unless some 292* other processor is so designated in this way before the next 293* shutdown or crash time. Unless BCE is rebooted after 294* shutdown, that CPU will be the bootload processor of the next 295* bootload. 296* 297* A: $ignore 298* 299* Message: 300* stop_cpu: Removed CPU CPUTAG. 301* 302* S: $info 303* 304* T: In response to an operator "rcf dl cpu CPUTAG" command. 305* 306* M: The system has successfully deleted the CPU whose tag is CPUTAG 307* from the configuration. The CPU is now halted at a DIS instruction. 308* 309* A: The operator can, but need not, physically remove the CPU from 310* the configuration by disabling appropriate ports if desired. 311* 312* Message: 313* stop_cpu: Unable to run on CPU X ERRORMESSAGE 314* 315* S: $crash 316* 317* T: When deleting a CPU. 318* 319* M: The system has just deleted a CPU which owned an interrupt mask. 320* In trying to assign the mask to a different CPU (X), it was unable to 321* run on that CPU. This indicates hardware or software malfunction. 322* 323* A: $recover 324* 325* END MESSAGE DOCUMENTATION */ 326 end stop_cpu; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/11/89 0800.9 stop_cpu.pl1 >spec>install>1110>stop_cpu.pl1 269 1 10/18/88 1206.7 rcerr.incl.pl1 >ldd>include>rcerr.incl.pl1 271 2 10/14/83 0957.2 config_cpu_card.incl.pl1 >ldd>include>config_cpu_card.incl.pl1 273 3 04/30/87 1513.7 flagbox.incl.pl1 >ldd>include>flagbox.incl.pl1 275 4 10/12/83 0943.5 scs.incl.pl1 >ldd>include>scs.incl.pl1 277 5 01/06/85 1422.2 apte.incl.pl1 >ldd>include>apte.incl.pl1 279 6 05/17/85 0615.7 syserr_constants.incl.pl1 >ldd>include>syserr_constants.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. ANNOUNCE 000016 constant fixed bin(17,0) initial dcl 6-7 set ref 111* 160* CPU_CARD_WORD 000000 constant char(4) initial dcl 2-24 set ref 174* CRASH 000021 constant fixed bin(17,0) initial dcl 6-7 set ref 216* LETTERS 000004 constant char(8) initial packed unaligned dcl 44 ref 111 111 160 160 216 216 addr builtin function dcl 78 ref 90 92 101 135 135 153 168 204 238 257 apte based structure level 1 dcl 5-7 clock builtin function dcl 78 ref 142 144 code 000113 automatic fixed bin(35,0) dcl 40 set ref 128* 129 138* 214* 216 216* 234* config_$find_2 000050 constant entry external dcl 50 ref 174 config_$update 000052 constant entry external dcl 50 ref 177 controller_port 0(33) based fixed bin(3,0) level 2 in structure "npdata" packed packed unsigned unaligned dcl 76 in procedure "stop_cpu" ref 258 controller_port 0(33) based fixed bin(3,0) level 2 in structure "pdata" packed packed unsigned unaligned dcl 75 in procedure "stop_cpu" ref 187 190 194 253 254 258 261 cow 1 000064 external static structure array level 2 dcl 4-65 set ref 135 135 cpu_card based structure level 1 dcl 2-6 cpu_cardp 000120 automatic pointer dcl 2-4 set ref 174* 176 cpu_mask 000112 automatic bit(8) dcl 39 set ref 126* 127* 128* 212* 213* 214* dbr 44 based fixed bin(71,0) level 2 dcl 5-7 ref 113 delete_cpu 0(04) based bit(1) level 2 packed packed unaligned dcl 75 set ref 134* expanded_port 0(30) based bit(1) level 2 in structure "pdata" packed packed unaligned dcl 75 in procedure "stop_cpu" ref 190 252 expanded_port 0(30) based bit(1) level 2 in structure "npdata" packed packed unaligned dcl 76 in procedure "stop_cpu" ref 104 expander_port 0(31) based fixed bin(2,0) level 2 packed packed unsigned unaligned dcl 75 ref 194 254 fgbx based structure level 1 dcl 3-24 fgbxp 000122 automatic pointer dcl 3-22 set ref 92* 113 flagbox$ 000060 external static fixed bin(17,0) dcl 3-21 set ref 92 found 000105 automatic bit(1) dcl 36 set ref 99* 100 109* 116 201* 203 220* 255* 256 258* 261 halted_cpu 0(06) based bit(1) level 2 packed packed unaligned dcl 75 ref 143 hc_dbr 56 based bit(72) level 2 dcl 3-24 set ref 113* interrupt_cpu 0(05) based bit(1) level 2 in structure "pdata" packed packed unaligned dcl 75 in procedure "stop_cpu" set ref 202 237* interrupt_cpu 0(05) based bit(1) level 2 in structure "npdata" packed packed unaligned dcl 76 in procedure "stop_cpu" set ref 104 206 231* mask_instruction$ldaq 000046 constant entry external dcl 50 ref 242 mask_instruction$staq 000044 constant entry external dcl 50 ref 240 mask_temp 000106 automatic fixed bin(71,0) dcl 37 set ref 222* 232* my_name 000002 constant char(8) initial packed unaligned dcl 45 set ref 111* 160* 216* new_pdp 000102 automatic pointer dcl 34 set ref 101* 104 104 104 204* 206 206 231 257* 258 258 new_tag 000104 automatic fixed bin(3,0) dcl 35 set ref 100* 101 104 110 111 111 113* 203* 204 209* 213 216 216 225 227 229* 256* 257 258* npdata based structure level 1 dcl 76 online based bit(1) level 2 packed packed unaligned dcl 76 ref 104 206 258 pdata based structure level 1 dcl 75 pdp 000100 automatic pointer dcl 33 set ref 90* 134 143 153* 168* 187 190 190 194 194 202 237 252 253 254 254 258 261 prds$simulated_mask 000010 external static fixed bin(17,0) dcl 47 set ref 238 privileged_mode_ut$cioc 000020 constant entry external dcl 50 ref 135 privileged_mode_ut$unwire_unmask 000024 constant entry external dcl 50 ref 232 privileged_mode_ut$wire_and_mask 000022 constant entry external dcl 50 ref 222 ptp 000110 automatic pointer dcl 38 set ref 222* 232* pxss$unthread_apte 000016 constant entry external dcl 50 ref 182 rcerr_delcpu_no_good_blcpu constant fixed bin(17,0) initial dcl 1-26 ref 117 rcerr_delcpu_no_stop constant fixed bin(17,0) initial dcl 1-26 ref 145 rcerr_sprq_failed constant fixed bin(17,0) initial dcl 1-48 ref 130 rcode parameter fixed bin(35,0) dcl 31 set ref 27 85 117* 130* 145* 163 265* scr_util$reassign_mask 000034 constant entry external dcl 50 ref 209 scr_util$set_export_enable 000042 constant entry external dcl 50 ref 194 254 scr_util$set_mask 000032 constant entry external dcl 50 ref 187 scr_util$set_port_enable 000036 constant entry external dcl 50 ref 190 261 scr_util$update_export_xipmsk 000040 constant entry external dcl 50 ref 253 scs$bos_processor_tag 000102 external static fixed bin(3,0) dcl 4-137 set ref 98 110* 127 scs$cow 000064 external static structure array level 1 dcl 4-65 scs$idle_aptep 000076 external static pointer array packed unaligned dcl 4-130 ref 113 182 scs$interrupt_controller 000104 external static fixed bin(3,0) dcl 4-141 set ref 187* scs$mask_ptr 000074 external static pointer array packed unaligned dcl 4-110 set ref 225* 225 238* scs$nprocessors 000100 external static fixed bin(17,0) dcl 4-136 set ref 157* 157 scs$processor_data 000062 external static structure array level 1 dcl 4-35 set ref 90 101 153 168 204 257 scs$read_mask 000072 external static bit(36) array dcl 4-109 set ref 229* 229 242* scs$set_mask 000070 external static bit(36) array dcl 4-108 set ref 227* 227 240* scs$sys_level 000066 external static bit(72) dcl 4-93 set ref 187* set_procs_required 000014 constant entry external dcl 50 ref 128 138 214 234 shutdown_entry 000116 automatic bit(1) dcl 42 set ref 82* 88* 166* 173 state 3 based char(4) level 2 dcl 2-6 set ref 176* substr builtin function dcl 78 set ref 111 111 127* 160 160 213* 216 216 syserr 000056 constant entry external dcl 50 ref 111 160 syserr$error_code 000054 constant entry external dcl 50 ref 216 tag parameter fixed bin(3,0) dcl 30 set ref 27 85 90 98 104 135 135 153 160 160 163 168 174 182 209* 225 227 229 238 240 242 258 tc_data$ncpu 000012 external static fixed bin(17,0) dcl 47 set ref 158* 158 timnow 000114 automatic fixed bin(52,0) dcl 41 set ref 142* 144 unspec builtin function dcl 78 ref 113 wire_proc$unwire_me 000030 constant entry external dcl 50 ref 233 wire_proc$wire_me 000026 constant entry external dcl 50 ref 221 NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. BEEP internal static fixed bin(17,0) initial dcl 6-7 BULK_PORT internal static fixed bin(17,0) initial dcl 4-176 CPU_PORT internal static fixed bin(17,0) initial dcl 4-176 FLAGBOX_SENTINEL internal static char(32) initial packed unaligned dcl 3-51 IOM_PORT internal static fixed bin(17,0) initial dcl 4-176 JUST_LOG internal static fixed bin(17,0) initial dcl 6-7 LOG internal static fixed bin(17,0) initial dcl 6-7 SYSERR_COVERT_CHANNEL internal static fixed bin(17,0) initial dcl 6-7 SYSERR_CRASH_SYSTEM internal static fixed bin(17,0) initial dcl 6-7 SYSERR_LOG_OR_DISCARD internal static fixed bin(17,0) initial dcl 6-7 SYSERR_LOG_OR_PRINT internal static fixed bin(17,0) initial dcl 6-7 SYSERR_PRINT_ON_CONSOLE internal static fixed bin(17,0) initial dcl 6-7 SYSERR_PRINT_WITH_ALARM internal static fixed bin(17,0) initial dcl 6-7 SYSERR_RING1_ERROR internal static fixed bin(17,0) initial dcl 6-7 SYSERR_SUCCESSFUL_ACCESS internal static fixed bin(17,0) initial dcl 6-7 SYSERR_SYSTEM_ERROR internal static fixed bin(17,0) initial dcl 6-7 SYSERR_TERMINATE_PROCESS internal static fixed bin(17,0) initial dcl 6-7 SYSERR_UNSUCCESSFUL_ACCESS internal static fixed bin(17,0) initial dcl 6-7 TERMINATE_PROCESS internal static fixed bin(17,0) initial dcl 6-7 aptep automatic pointer dcl 5-5 rcerr_addcpu_amoff internal static fixed bin(17,0) initial dcl 1-16 rcerr_addcpu_bad_switches internal static fixed bin(17,0) initial dcl 1-16 rcerr_addcpu_enable internal static fixed bin(17,0) initial dcl 1-16 rcerr_addcpu_gcos internal static fixed bin(17,0) initial dcl 1-16 rcerr_addcpu_lockup internal static fixed bin(17,0) initial dcl 1-16 rcerr_addcpu_no_response internal static fixed bin(17,0) initial dcl 1-16 rcerr_addcpu_startup internal static fixed bin(17,0) initial dcl 1-16 rcerr_addcpu_trouble internal static fixed bin(17,0) initial dcl 1-16 rcerr_addscu_bad_mask internal static fixed bin(17,0) initial dcl 1-31 rcerr_addscu_bigconfig internal static fixed bin(17,0) initial dcl 1-31 rcerr_addscu_dup_mask internal static fixed bin(17,0) initial dcl 1-31 rcerr_addscu_enable internal static fixed bin(17,0) initial dcl 1-31 rcerr_addscu_fault internal static fixed bin(17,0) initial dcl 1-31 rcerr_addscu_manual internal static fixed bin(17,0) initial dcl 1-31 rcerr_addscu_memoverlap internal static fixed bin(17,0) initial dcl 1-31 rcerr_addscu_no_mask internal static fixed bin(17,0) initial dcl 1-31 rcerr_addscu_oldexpand internal static fixed bin(17,0) initial dcl 1-31 rcerr_addscu_size internal static fixed bin(17,0) initial dcl 1-31 rcerr_addscu_switches internal static fixed bin(17,0) initial dcl 1-31 rcerr_delcpu_last internal static fixed bin(17,0) initial dcl 1-26 rcerr_delmain_abs_wired internal static fixed bin(17,0) initial dcl 1-44 rcerr_delmain_nomem internal static fixed bin(17,0) initial dcl 1-44 rcerr_isolts_bad_switches internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_bootload_scu internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_cpu_online internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_illegal_cpu internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_illegal_scu internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_lda_fail internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_locked internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_no_config internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_no_mask internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_no_response internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_no_str_flt internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_not internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_scu_not internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_two_scu internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_wrong_cell internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_wrong_scu internal static fixed bin(17,0) initial dcl 1-57 rcerr_isolts_wrong_scu_cell internal static fixed bin(17,0) initial dcl 1-57 rcerr_locked internal static fixed bin(17,0) initial dcl 1-48 rcerr_no_config internal static fixed bin(17,0) initial dcl 1-48 rcerr_not_online internal static fixed bin(17,0) initial dcl 1-48 rcerr_online internal static fixed bin(17,0) initial dcl 1-48 rcerr_range internal static fixed bin(17,0) initial dcl 1-48 scs$bos_restart_flags external static bit(8) dcl 4-135 scs$cam_pair external static fixed bin(71,0) dcl 4-103 scs$cam_wait external static bit(8) dcl 4-104 scs$cfg_data external static fixed bin(71,0) array dcl 4-150 scs$cfg_data_save external static fixed bin(71,0) dcl 4-152 scs$connect_lock external static bit(36) dcl 4-132 scs$controller_config_size external static fixed bin(14,0) array dcl 4-164 scs$controller_data external static structure array level 1 dcl 4-6 scs$cow_ptrs external static structure array level 1 dcl 4-77 scs$cpu_test_mask external static bit(72) dcl 4-96 scs$cpu_test_pattern external static bit(36) dcl 4-99 scs$cycle_priority_template external static bit(7) dcl 4-172 scs$expanded_ports external static bit(1) array packed unaligned dcl 4-154 scs$fast_cam_pending external static bit(36) array dcl 4-140 scs$faults_initialized external static bit(1) dcl 4-138 scs$number_of_masks external static fixed bin(17,0) dcl 4-97 scs$open_level external static bit(72) dcl 4-94 scs$port_addressing_word external static bit(3) array dcl 4-148 scs$port_data external static structure array level 1 dcl 4-56 scs$processor external static bit(8) dcl 4-143 scs$processor_data_switch_value external static bit(36) dcl 4-162 scs$processor_start_int_no external static fixed bin(5,0) dcl 4-142 scs$processor_start_mask external static bit(72) dcl 4-95 scs$processor_start_pattern external static bit(36) dcl 4-98 scs$processor_start_wait external static bit(8) dcl 4-144 scs$processor_switch_compare external static bit(36) array dcl 4-159 scs$processor_switch_data external static bit(36) array dcl 4-157 scs$processor_switch_mask external static bit(36) array dcl 4-160 scs$processor_switch_template external static bit(36) array dcl 4-158 scs$processor_test_data external static structure level 1 dcl 4-114 scs$reconfig_general_cow external static structure level 1 dcl 4-82 scs$reconfig_lock external static bit(36) dcl 4-133 scs$reconfig_locker_id external static char(32) dcl 4-167 scs$scas_page_table external static bit(36) array dcl 4-169 scs$set_cycle_switches external static bit(1) dcl 4-173 scs$sys_trouble_pending external static bit(1) dcl 4-139 scs$trouble_dbrs automatic fixed bin(71,0) array dcl 4-146 scs$trouble_flags external static bit(8) dcl 4-134 switch_w1 based structure level 1 dcl 1-76 NAMES DECLARED BY EXPLICIT CONTEXT. SHUTDOWN_COMMON 000076 constant label dcl 90 ref 83 destroy 000372 constant label dcl 168 ref 161 destroy_1 000364 constant entry external dcl 163 shutdown 000067 constant entry external dcl 85 stop_cpu 000056 constant entry external dcl 27 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 1474 1602 1104 1504 Length 2144 1104 106 325 370 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME stop_cpu 140 external procedure is an external procedure. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME stop_cpu 000100 pdp stop_cpu 000102 new_pdp stop_cpu 000104 new_tag stop_cpu 000105 found stop_cpu 000106 mask_temp stop_cpu 000110 ptp stop_cpu 000112 cpu_mask stop_cpu 000113 code stop_cpu 000114 timnow stop_cpu 000116 shutdown_entry stop_cpu 000120 cpu_cardp stop_cpu 000122 fgbxp stop_cpu THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out_desc call_ext_out return_mac ext_entry clock_mac THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. config_$find_2 config_$update mask_instruction$ldaq mask_instruction$staq privileged_mode_ut$cioc privileged_mode_ut$unwire_unmask privileged_mode_ut$wire_and_mask pxss$unthread_apte scr_util$reassign_mask scr_util$set_export_enable scr_util$set_mask scr_util$set_port_enable scr_util$update_export_xipmsk set_procs_required syserr syserr$error_code wire_proc$unwire_me wire_proc$wire_me THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. flagbox$ prds$simulated_mask scs$bos_processor_tag scs$cow scs$idle_aptep scs$interrupt_controller scs$mask_ptr scs$nprocessors scs$processor_data scs$read_mask scs$set_mask scs$sys_level tc_data$ncpu LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 27 000052 82 000063 83 000064 85 000065 88 000074 90 000076 92 000103 98 000105 99 000111 100 000112 101 000121 104 000124 109 000140 110 000142 111 000143 113 000176 115 000206 116 000210 117 000212 118 000215 126 000216 127 000217 128 000224 129 000234 130 000236 131 000241 134 000242 135 000244 138 000261 142 000274 143 000276 144 000301 145 000310 146 000313 148 000314 153 000315 157 000322 158 000324 160 000326 161 000361 163 000362 166 000371 168 000372 173 000377 174 000401 176 000417 177 000422 182 000427 187 000442 190 000460 194 000502 201 000526 202 000527 203 000532 204 000541 206 000544 209 000552 212 000563 213 000564 214 000570 216 000601 220 000645 221 000647 222 000654 225 000665 227 000673 229 000675 231 000677 232 000701 233 000711 234 000716 237 000731 238 000733 240 000740 242 000747 246 000760 252 000762 253 000765 254 000777 255 001023 256 001024 257 001033 258 001036 260 001056 261 001060 265 001100 267 001102 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved