COMPILATION LISTING OF SEGMENT tc_init Compiled by: Multics PL/I Compiler, Release 32f, of October 9, 1989 Compiled at: Bull HN, Phoenix AZ, System-M Compiled on: 11/11/89 1020.0 mst Sat Options: optimize map 1 /****^ *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Bull Inc., 1987 * 4* * * 5* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 6* * * 7* * Copyright (c) 1972 by Massachusetts Institute of * 8* * Technology and Honeywell Information Systems, Inc. * 9* * * 10* *********************************************************** */ 11 12 /* format: style4,delnl,insnl,tree,ifthenstmt,indnoniterend */ 13 tc_init: 14 proc; 15 16 /* This program initializes the various traffic controller data bases, the idle process 17* data bases, and starts up the traffic controller. The entry part_2 is called after paging is 18* operative and after the initializer's descriptor segment has all permanent hardcore SDW's filled 19* in. It creates the idle processes and turns ON multiprogramming after starting the bootload cpu. 20* The entry start_other_cpus is called late in initialization to get the other processors running. 21**/ 22 23 /* Last modified (date and reason): 24* 5/11/77 by RE Mullen for concurrent scheduler 25* 2/4/76 by S. Webber rewrite for new reconfiguration 26* 4/20/77 by B. Greenberg for PRDS renaming 27* 6/21/77 by M. Weaver to move template_pds stuff to part_2 28* 5/10/79 by B. Greenberg for stack_0 sharing 29* 10/29/80 by M. Pierret for pin_weight and io_priority 30* 3/5/81 by J. Bongiovanni for site-settable prds size 31* 11/11/81 by J. A. Bush to display contents of bootload cpu ID PROM (DPS8 CPU) 32* before adding other cpus whose state is "ON". 33* 04/04/81 by W. Olin Sibert, to remove direct SDW hacking 34* 01/09/81 by W. Olin Sibert, to make it runnable twice for Bootload Multics. 35* 4/27/82 by J. Bongiovanni for wcte.interactive_q, gv_integration 36* 7/15/82 by BIM to merge Siberts changes with Bongiovanni's. 37* 8/13/82 by BIM to fiddle, once again, with PID's. 38* 9/17/82 by J. Bongiovanni for tc_data$abort_ips_mask 39* 2/16/83 by E. N. Kittlitz for hex floating point. 40* 6/27/83 by Keith Loepere for early entrypoint. 41* 830728 by E. A. Ranzenbach for operator console polling time. 42* 10/4/83 by Keith Loepere for paged idle_pdses and idle_dsegs. 43* 84.11.15 by M. Pandolf to include hc_lock. 44* 11/05/84 by Keith Loepere to rename terminate to terminate_. 45* Modified 1984-11-12 by E. Swenson for IPC event channel validation. 46* The value of apte.ipc_r_offset is initialized here for the 47* Initializer process. 48* Modified March 1985 by Keith Loepere to fix a bug in multiple pass init. 49**/ 50 51 /* Automatic */ 52 53 dcl early_call bit (1) aligned; 54 dcl n_words fixed bin (18); 55 dcl first_segno fixed bin; 56 dcl processor_index fixed bin; 57 dcl prdsp ptr; 58 dcl no_apt fixed bin; 59 dcl no_itt fixed bin; 60 dcl tc_data_size fixed bin (18); 61 dcl tc_data_no fixed bin; 62 dcl tc_data_header_no fixed bin; 63 dcl tc_data_header_ptr pointer; 64 dcl tsdw fixed bin (71); 65 dcl i fixed bin; 66 dcl template_pds_size fixed bin (18); 67 dcl idle_pds_p ptr; 68 dcl aptp ptr; 69 dcl aptx fixed bin; 70 dcl ittp ptr; 71 dcl ittx fixed bin; 72 dcl tsize fixed bin (18); 73 dcl time fixed bin (71); 74 dcl code fixed bin (35); 75 dcl prds_name char (32); 76 dcl prds_length_kw fixed bin; 77 dcl cpu_model char (13) aligned; /* storage for cpu model number (from ID PROM) */ 78 dcl cpu_serial char (13) aligned; /* storage for cpu serial number (from ID PROM) */ 79 dcl cpu_ship_date char (8) aligned; /* storage for cpu ship date (from ID PROM) */ 80 dcl table_value fixed bin; 81 82 dcl dseg_no fixed bin static; 83 dcl pds_no fixed bin static; 84 dcl prds_no fixed bin static; 85 dcl template_pds_p ptr static; 86 dcl tag fixed bin static; 87 dcl idle_dsegs_sdw fixed bin (71) internal static; /* pointers and SDWs for idle_dsegs$ and idle_pdses */ 88 dcl idle_pdses_sdw fixed bin (71) internal static; 89 dcl idle_dsegs_p ptr static; 90 dcl idle_pdses_p ptr static; 91 dcl dseg_size fixed bin (18) internal static; /* Amount to actually copy into idle dseg */ 92 dcl pds_size fixed bin (18) static; 93 94 dcl header (n_words) fixed bin based; 95 dcl copy_id bit (36) aligned based; 96 dcl copy_ptr ptr based; 97 dcl copy_group_id char (32) aligned based; 98 dcl copy_pds (pds_size) fixed bin based; 99 dcl copy_dseg (0:255) fixed bin (71) based; /* stop copying before init segs */ 100 dcl 1 apt (1) aligned like apte based (aptp); 101 dcl 1 itt (1) aligned based (ittp), 102 2 fp bit (18) unaligned, 103 2 bp bit (18) unaligned, 104 2 filler (7) fixed bin; 105 106 dcl append$branchx 107 entry (char (*), char (*), fixed bin (5), (3) fixed bin, char (*), fixed bin, fixed bin, fixed bin, 108 fixed bin (35)); 109 dcl chname$cfile entry (char (*), char (*), char (*), char (*), fixed bin (35)); 110 dcl config_$find entry (char (4) aligned, ptr); 111 dcl config_$find_table entry (char (4) aligned, fixed bin); 112 dcl delentry$dfile entry (char (*), char (*), fixed bin (35)); 113 dcl getuid entry returns (bit (36) aligned); 114 dcl get_main entry (ptr, fixed bin (18), fixed bin (71)); 115 dcl get_ptrs_$given_segno entry (fixed bin) returns (ptr); 116 dcl grab_aste$prewithdraw entry (ptr, fixed bin (19), fixed bin (35)) returns (ptr); 117 dcl init_processor$init entry; 118 dcl init_processor$return entry ext; 119 dcl initiate entry (char (*), char (*), char (*), fixed bin, fixed bin, ptr, fixed bin (35)); 120 dcl pmut$swap_sdw entry (ptr, ptr); 121 dcl privileged_mode_ut$read_id_prom entry (char (*) aligned, fixed bin); 122 dcl pxss$get_entry entry (ptr); 123 dcl sdw_util_$construct entry (ptr, ptr); 124 dcl sdw_util_$dissect entry (ptr, ptr); 125 dcl start_cpu entry (fixed bin, fixed bin (35)); 126 dcl syserr entry options (variable); 127 dcl syserr$error_code entry options (variable); 128 dcl terminate_$teseg entry (ptr, fixed bin (1), fixed bin (35)); 129 dcl thread$cin entry (ptr, bit (18) unaligned); 130 131 dcl active_all_rings_data$stack_base_segno fixed bin (18) ext; 132 dcl dseg$ (0:1023) fixed bin (71) external static; 133 dcl error_table_$noentry external fixed bin (35); 134 dcl idle_pdses$ (0:16383) fixed bin external static; 135 dcl idle_dsegs$ (0:8191) fixed bin (71) external static; /* All the idle process DSEGs */ 136 dcl prds$ ext; 137 dcl prds$processor_tag fixed bin (3) external; 138 dcl slt$ ext; 139 dcl sys_info$hfp_exponent_available bit (1) aligned external; 140 dcl sys_info$quit_mask bit (36) aligned external; 141 dcl sys_info$susp_mask bit (36) aligned external; 142 dcl sys_info$term_mask bit (36) aligned external; 143 dcl sys_info$system_type fixed bin external static; 144 dcl tc_data$ ext; 145 dcl tc_data$prds_length fixed bin (19) external; 146 dcl tc_data_header$ fixed bin external static; 147 148 dcl pds$ ext; 149 dcl pds$apt_ptr ptr ext; 150 dcl pds$data fixed bin ext; 151 dcl pds$lock_id bit (36) aligned external; 152 dcl pds$dstep bit (18) aligned ext; 153 dcl pds$initial_procedure ptr ext; 154 dcl pds$process_group_id char (32) ext; 155 dcl pds$processid bit (36) aligned ext; 156 dcl pds$stack_0_ptr ptr ext; 157 dcl pds$stack_0_sdwp ptr ext; 158 dcl pds$trace ext; 159 160 dcl template_pds$ ext; 161 dcl template_pds$quota_inhib fixed bin external; 162 dcl template_pds$save_history_regs bit (1) aligned external; 163 dcl template_pds$apt_ptr ptr ext; 164 dcl template_pds$initial_procedure ptr ext; 165 dcl template_pds$process_group_id char (32) ext; 166 dcl template_pds$processid bit (36) aligned ext; 167 dcl template_pds$stack_0_sdwp ptr ext; 168 dcl template_pds$stack_0_ptr ptr ext; 169 170 dcl LETTERS char (8) internal static options (constant) init ("ABCDEFGH"); 171 dcl PRDS_DIR char (32) internal static options (constant) init (">system_library_1"); 172 dcl RW_mode fixed bin (5) internal static options (constant) init (01010b); 173 dcl seg_rb (3) fixed bin internal static options (constant) init (0, 0, 0); 174 175 dcl (addr, addrel, baseno, baseptr, bin, binary, bit, clock, divide, hbound, lbound, max, min, null, ptr, rel, size, 176 string, substr, unspec) builtin; 177 178 early_call = "0"b; 179 go to part_1; 180 181 early: 182 entry; 183 early_call = "1"b; 184 185 part_1: 186 tcmp = addr (tc_data$); /* get necessary pointers, etc. */ 187 idle_pdses_p = addr (idle_pdses$); 188 idle_dsegs_p = addr (idle_dsegs$); 189 tc_data_no = bin (baseno (tcmp), 18); 190 tc_data_header_ptr = addr (tc_data_header$); 191 tc_data_header_no = binary (baseno (tc_data_header_ptr), 18); 192 pds_no = bin (baseno (addr (pds$)), 18); 193 dseg_no = bin (baseno (addr (dseg$)), 18); 194 prds_no = bin (baseno (addr (prds$)), 18); 195 196 if dseg$ (tc_data_header_no) = 0 then do; /* First time - make header valid */ 197 addr (addr (slt$) -> slt.seg (tc_data_no)) -> slte.paged = "0"b; 198 /* Force to low memory */ 199 call pmut$swap_sdw (tc_data_header_ptr, addr (dseg$ (tc_data_no))); 200 end; 201 202 n_words = bin (rel (addr (tcm.apt)), 18); 203 tag = scs$bos_processor_tag; 204 205 if early_call then do; 206 no_apt = 4; 207 no_itt = 20; 208 end; 209 else do; 210 tcd_cardp = null (); 211 call config_$find (TCD_CARD_WORD, tcd_cardp);/* get TCD card for sizes of APT and ITT. */ 212 if tcd_cardp = null () then do; /* not found, use defaults */ 213 no_apt = tc_data_header_ptr -> tcm.apt_size; 214 no_itt = tc_data_header_ptr -> tcm.itt_size; 215 end; 216 else do; /* use values from card */ 217 no_apt = tcd_card.no_apt; 218 no_itt = tcd_card.no_itt; 219 end; 220 end; 221 222 /* Now, allocate the new tc_data in wired memory. The header specifies it as paged, since 223* the header is created as a cds and must be copied into the wired tc_data. The first time 224* this code is executed, the tc_data_header segment will be created (defined in the header 225* as a zero length fabricated segment) as a segment defining the version of tc_data read 226* from the tape, which contains only the tc_data header. Subsequently, tc_data is allocated 227* in wired memory, and the header (defined by tc_data_header) is copied into it. 228**/ 229 230 tc_data_size = n_words + no_apt * size (apt) + no_itt * size (itt); 231 232 call get_main (tcmp, tc_data_size, tsdw); /* get storage for tc_data */ 233 call pmut$swap_sdw (tcmp, addr (tsdw)); /* copy tc_data into new storage */ 234 tcmp -> header = tc_data_header_ptr -> header; /* copy header */ 235 236 /* We are now using the new wired version of tc_data. */ 237 238 tcm.apt_size = no_apt; 239 tcm.itt_size = no_itt; 240 241 tcm.system_type = sys_info$system_type; /* Remember this fellow here */ 242 243 /* Init WCTE's, then setup first two for self and others respectively. */ 244 245 246 do i = 0 to 16; 247 tcm.wcte (i).fp, tcm.wcte (i).bp = rel (addr (tcm.wcte (i))); 248 tcm.wcte (i).mnbz = "1"b; /* Make this a sentinel */ 249 tcm.wcte (i).resp1 = 2 * 1024 * 1024; 250 tcm.wcte (i).quantum1 = 1024 * 1024; 251 tcm.wcte (i).resp2 = 64 * 1024 * 1024; 252 tcm.wcte (i).quantum2 = 2 * 1024 * 1024; 253 tcm.wcte (i).realtime = 0; 254 tcm.wcte (i).purging = 1; 255 tcm.wcte (i).maxel = 0; /* 0 means no limit */ 256 tcm.wcte (i).nel = 0; 257 tcm.wcte (i).pin_weight = 1; 258 tcm.wcte (i).flags.io_priority = "0"b; 259 tcm.wcte (i).flags.interactive_q = "1"b; 260 end; 261 262 263 264 tcm.credits_per_scatter = 512 * 1024; /* passout this many credits this often */ 265 /* credits are in microseconds */ 266 tcm.wcte (0).flags.defined = "1"b; 267 tcm.wcte (0).flags.io_priority = "1"b; 268 tcm.wcte (0).minf = 256 * 1024; /* 50% for Initializer if need be. */ 269 tcm.wcte (0).resp1, tcm.wcte (0).resp2 = 256 * 1024; 270 /* within 1/4 sec */ 271 tcm.wcte (0).quantum1, tcm.wcte (0).quantum2 = 2 * 1024 * 1024; 272 /* give 2 sec */ 273 tcm.wcte (0).pin_weight = 3; /* This number may have to be tuned */ 274 tcm.wcte (0).realtime = 1; 275 tcm.wcte (1).flags.defined = "1"b; 276 tcm.wcte (1).minf = 512 * 1024; /* and 100% for everybody else. */ 277 /* The initializer does not generate credits */ 278 tcm.min_wct_index = rel (addr (tcm.wcte (0))); 279 tcm.max_wct_index = rel (addr (tcm.wcte (1))); 280 281 /* Now set up the APT */ 282 283 aptp = ptr (tcmp, n_words); /* APT is right after header */ 284 tcm.empty_q = rel (aptp); /* thread first into empty list */ 285 do aptx = 1 to no_apt - 1; 286 apt (aptx).fp = rel (addr (apt (aptx + 1))); 287 apt (aptx).lock = "777777"b3; /* init to unlocked, anyting but zero */ 288 end; 289 apt (no_apt).lock = "777777"b3; /* init to unlocked, anyting but zero */ 290 291 tcm.stat (0) = no_apt; /* all processes are empty */ 292 293 /* Now do the ITT */ 294 295 tcm.used_itt = 0; 296 ittp = addr (apt (no_apt + 1)); 297 do ittx = 1 to no_itt - 1; 298 itt (ittx).fp = rel (addr (itt (ittx + 1))); 299 end; 300 itt (no_itt).fp = (18)"1"b; /* head -1 when all itte taken, 0 means locked */ 301 tcm.itt_free_list = rel (ittp); 302 tcm.cid2 = divide (no_itt - no_apt, 2, 18, 0); 303 tcm.cid3 = divide (no_itt - no_apt, 3, 18, 0); 304 tcm.cid4 = divide (no_itt - no_apt, 4, 18, 0); 305 306 /* Fill in data from SCHD card. */ 307 308 schd_cardp = null (); /* search for config card */ 309 call config_$find (SCHD_CARD_WORD, schd_cardp); 310 if schd_cardp ^= null () then do; /* if found */ 311 tcm.working_set_factor = schd_card.ws_factor; 312 tcm.tefirst = schd_card.tefirst * 125000; 313 tcm.telast = schd_card.telast * 125000; 314 tcm.timax = schd_card.timax * 125000; 315 if schd_card.min_eligible > 0 then tcm.min_eligible = schd_card.min_eligible * 262144; 316 if schd_card.max_eligible > 0 317 then if schd_card.max_eligible * 262144 >= tcm.min_eligible 318 then tcm.max_eligible = schd_card.max_eligible * 262144; 319 if schd_card.max_max_eligible > 0 & schd_card.max_max_eligible < 1000 320 then tcm.max_max_eligible = schd_card.max_max_eligible * 262144; 321 else tcm.max_max_eligible = tcm.max_eligible + (10 * 262144); 322 end; 323 324 if (tcm.max_eligible + tcm.max_stopped_stack_0 * 262144) <= tcm.max_max_eligible 325 & tcm.min_eligible <= tcm.max_eligible 326 then ; /* All OK */ 327 else call syserr (1, "Inconsistent SCHD config card values."); 328 329 tcm.gv_integration = 4 * tcm.telast; 330 331 tcm.abort_ips_mask = sys_info$quit_mask | sys_info$susp_mask | sys_info$term_mask; 332 333 /* Set up the length of the prds, either from the slt or the TBLS Config Card */ 334 335 sltep = addr (addr (slt$) -> slt.seg (prds_no)); 336 prds_length_kw = max (slte_uns.cur_length, slte_uns.max_length); 337 /* default */ 338 339 call config_$find_table ("prds", table_value); /* See if a TBLS PRDS card is to be found */ 340 if (table_value >= 0) & (table_value < prds_length_kw) 341 then call syserr (ANNOUNCE, "tc_init: Size of PRDS on TBLS card too small; ^d KW will be used.", prds_length_kw) 342 ; 343 344 if table_value > 0 then prds_length_kw = min (255, table_value); 345 /* Don't let it be too big */ 346 /* else just stick with default */ 347 348 tcm.prds_length = 1024 * prds_length_kw; 349 slte_uns.cur_length, slte_uns.max_length = prds_length_kw; 350 351 /* Allocate the stack_0_data segment */ 352 353 sdtp = addr (stack_0_data$); 354 stack_0_data_init_number_of_stacks = divide (tcm.max_max_eligible, 262144, 17, 0); 355 call get_main (sdtp, size (sdt), tsdw); 356 call pmut$swap_sdw (sdtp, addr (tsdw)); 357 sdt.num_stacks = stack_0_data_init_number_of_stacks; 358 unspec (sdt) = ""b; 359 sdt.num_stacks = stack_0_data_init_number_of_stacks; 360 361 /* Allocate the APT entries for the initializer and the idle processes. 362* Also figure out the total size of idle_dsegs and idle_pdses. */ 363 364 tsize = 0; 365 call pxss$get_entry (aptep); 366 pds$apt_ptr = aptep; 367 do i = 0 to 7; 368 if scs$processor_data (i).offline then do; /* All cpus are flagged as offline at this point */ 369 call pxss$get_entry (aptep); 370 scs$idle_aptep (i) = aptep; 371 tsize = tsize + 1; 372 end; 373 end; 374 375 /* Now get the DSEGs and PDSs for the idle procs */ 376 377 /* Now get enough storage for the PDSes and DSEGs */ 378 379 if sys_info$system_type = ADP_SYSTEM then do; /* For the ADP, because of cache sharing/overlap problems */ 380 dseg_size = 2048; /* each of these must be two pages. No further special */ 381 pds_size = 2048; /* casing need be done, since the initialization DSEG and */ 382 end; /* PDS are already this large */ 383 384 else do; /* otherwise one page is more than enough */ 385 dseg_size = 1024; 386 pds_size = 1024; 387 end; 388 389 call get_main (idle_dsegs_p, tsize * dseg_size, idle_dsegs_sdw); 390 391 call get_main (idle_pdses_p, tsize * pds_size, idle_pdses_sdw); 392 393 call pmut$swap_sdw (idle_dsegs_p, addr (idle_dsegs_sdw)); 394 call pmut$swap_sdw (idle_pdses_p, addr (idle_pdses_sdw)); 395 return; 396 397 part_2: 398 entry; 399 400 /* This entry is called after the initializer's DSEG is filled in and after paged segments 401* have their ASTE's. It completes initialization of the traffic controller, starts the 402* bootload CPU, and turns on multiprogramming. */ 403 404 tcmp = addr (tc_data$); 405 406 /* Now initialize the template_pds segment */ 407 408 template_pds_size = bin (rel (addr (pds$data)), 18); 409 /* get size to copy */ 410 tcm.pdscopyl = template_pds_size; /* save for later process creations */ 411 412 template_pds_p = addr (template_pds$); /* get pointer to template_pds */ 413 414 /* Now fill in some variables in template_pds */ 415 416 template_pds$quota_inhib = 0; 417 template_pds$save_history_regs = "0"b; 418 template_pds$stack_0_ptr = baseptr (active_all_rings_data$stack_base_segno); 419 template_pds$stack_0_sdwp = addr (dseg$ (binary (baseno (template_pds$stack_0_ptr)))); 420 template_pds$processid = "444444444444"b3; 421 template_pds$apt_ptr = null (); 422 template_pds$process_group_id = "Idle.SysControl.z"; 423 template_pds$initial_procedure = null (); 424 425 processor_index = -1; 426 do i = lbound (scs$processor_data, 1) to hbound (scs$processor_data, 1); 427 /* loop through all possible processors */ 428 if scs$processor_data (i).offline then do; /* Only do it for configurable CPUs */ 429 /* All cpus are flagged as offline at this point */ 430 processor_index = processor_index + 1; 431 first_segno = processor_index * divide (dseg_size, 2, 17, 0); 432 /* index, in idle_dsegs$, of first SDW for this */ 433 addr (idle_dsegs$ (first_segno)) -> copy_dseg = addr (dseg$) -> copy_dseg; 434 /* idle process */ 435 436 idle_pds_p = addr (idle_pdses$ (processor_index * pds_size)); 437 idle_pds_p -> copy_pds = template_pds_p -> copy_pds; 438 /* copy virgin pds */ 439 440 addrel (idle_pds_p, rel (addr (pds$processid))) -> copy_id = rel (scs$idle_aptep (i)) || "555555"b3; 441 addrel (idle_pds_p, rel (addr (pds$apt_ptr))) -> copy_ptr = scs$idle_aptep (i); 442 addrel (idle_pds_p, rel (addr (pds$stack_0_ptr))) -> copy_ptr = addr (prds$); 443 addrel (idle_pds_p, rel (addr (pds$stack_0_sdwp))) -> copy_ptr = 444 addr (dseg$ (binary (baseno (addr (prds$))))); 445 substr (addrel (idle_pds_p, rel (addr (pds$process_group_id))) -> copy_group_id, 17, 1) = 446 substr ("abcdefgh", i + 1, 1); 447 addrel (idle_pds_p, rel (addr (pds$trace))) -> trace.last_available = 4; 448 addrel (idle_pds_p, rel (addr (pds$trace))) -> trace.next_free = 0; 449 450 call shrink_sdw (idle_dsegs_sdw, processor_index * dseg_size, dseg_size, tsdw); 451 idle_dsegs$ (first_segno + dseg_no) = tsdw; 452 scs$idle_aptep (i) -> apte.dbr = tsdw; 453 454 call shrink_sdw (idle_pdses_sdw, processor_index * pds_size, pds_size, tsdw); 455 idle_dsegs$ (first_segno + pds_no) = tsdw; 456 end; 457 end; 458 459 /* Now initialize the initializer process */ 460 461 pds$initial_procedure = addr (init_processor$return); 462 aptep = pds$apt_ptr; 463 pds$processid = rel (aptep) || (18)"1"b; 464 pds$stack_0_sdwp = addr (dseg$ (binary (baseno (pds$stack_0_ptr)))); 465 tcm.initializer_id = pds$processid; 466 apte.wct_index = tcm.min_wct_index; 467 apte.deadline = clock (); 468 call thread$cin (aptep, tcm.eligible_q_head.fp); 469 apte.loaded = "1"b; 470 apte.eligible = "1"b; 471 apte.state = bit (bin (2, 18), 18); 472 apte.dbr = dseg$ (dseg_no); 473 apte.processid = pds$processid; 474 apte.lock_id = getuid (); 475 pds$lock_id = apte.lock_id; 476 apte.timax = 0; 477 apte.pds = rel (get_ptrs_$given_segno (pds_no)); 478 apte.dseg = pds$dstep; 479 480 /**** Here we set up apte.ipc_r_offset for the Initializer process. This 481* is an 18-bit unsigned integer used by IPC to validate event channel 482* names in conjunction with apte.ipc_r_factor. This latter number 483* is determined later, in init_proc. This is done on order to provide 484* an undeterministic delay between the initialization of these two 485* numbers in order to make it difficult to guess one given the other. */ 486 487 apte.ipc_r_offset = binary (substr (bit (binary (clock (), 54), 54), 37, 18), 18); 488 489 /**** Set the value of apte.ipc_r_factor to zero for debugging purposes 490* so that we can determine whether it is getting set or not later. */ 491 492 apte.ipc_r_factor = 0; 493 494 aptep = scs$idle_aptep (tag); 495 apte.prds = rel (get_ptrs_$given_segno (prds_no)); 496 497 tcm.stat (2) = 1; /* one process is ready */ 498 tcm.wcte (0).nel = 1; /* one eligible in wc zero */ 499 500 /* Now set up miscellaneous tc_data variables */ 501 502 tcm.n_eligible = 1; 503 time = clock (); /* get current time */ 504 tcm.next_alarm_time = time; 505 tcm.opc_polling_time = time; 506 tcm.disk_polling_time = time; 507 tcm.tape_polling_time = time; 508 tcm.volmap_polling_time = time; 509 tcm.initialize_time = time; 510 tcm.define_wc_time = time; 511 tcm.nto_check_time = time; 512 tcm.nto_delta = 30000000; /* nto every 30 to 60 sec */ 513 514 /* Now finish up creating the first idle process */ 515 516 call init_processor$init; /* Initialize variables. */ 517 518 call start_cpu (tag, code); /* Now start bootload CPU idle process. */ 519 if code ^= 0 then call syserr (CRASH, "tc_init: Cannot start up first idle process. Check switches."); 520 521 tcm.wait_enable = 1; 522 523 return; 524 525 shrink_sdw: 526 proc (old_sdw, base, bound, new_sdw); 527 528 dcl old_sdw fixed bin (71) parameter; 529 dcl base fixed bin (24) parameter; 530 dcl bound fixed bin (18) parameter; 531 dcl new_sdw fixed bin (71) parameter; 532 533 dcl 1 sdwi aligned like sdw_info automatic; 534 535 536 call sdw_util_$dissect (addr (old_sdw), addr (sdwi)); 537 /* Take the old one apart */ 538 sdwi.address = sdwi.address + divide (base, 1024, 26); 539 /* Alter the base and bounds appropriately 540* (update the ptw address by n ptws) */ 541 sdwi.size = bound; 542 call sdw_util_$construct (addr (new_sdw), addr (sdwi)); 543 /* And put it back */ 544 545 end shrink_sdw; 546 547 start_other_cpus: 548 entry; 549 550 /* This entry is called late in initialization to start any 551* CPUs in the configuration that are marked as online in 552* the config deck */ 553 554 /* first, if the bootload cpu is a DPS8M, enter the contents of the ID PROM in 555* the syserr_log. We could not do it earlier in initialization beause syserr 556* logging was not enabled. */ 557 558 if scs$processor_data (tag).cpu_type > 0 559 then /* if DPS8 cpu... */ 560 if addr (scs$processor_switch_data (2)) -> dps8_rsw_2.id_prom then do; 561 /* and id prom present */ 562 call privileged_mode_ut$read_id_prom (cpu_model, 0); 563 /* get cpu model from ID PROM */ 564 call privileged_mode_ut$read_id_prom (cpu_serial, 13); 565 /* get cpu serial # from ID PROM */ 566 call privileged_mode_ut$read_id_prom (cpu_ship_date, 26); 567 /* get ship date from ID PROM */ 568 call syserr (4, "CPU ^a: Model #: ^a; Serial #: ^a; Ship date: ^a.", 569 /* log info from id prom */ 570 substr ("ABCDEFGH", tag + 1, 1), cpu_model, cpu_serial, cpu_ship_date); 571 end; 572 573 /* second, delete all old prds's, to guard against changes in prds format from one bootload to the next. */ 574 575 576 do i = 1 to 8; 577 prds_name = "cpu_" || substr (LETTERS, i, 1) || ".prds"; 578 call delentry$dfile (PRDS_DIR, prds_name, code); 579 if code ^= 0 580 then if code = error_table_$noentry then code = 0; 581 if code = 0 then do; 582 if i - 1 = prds$processor_tag then do; /* This processor. */ 583 call chname$cfile (PRDS_DIR, "prds", "prds", prds_name, code); 584 if code ^= 0 585 then call syserr$error_code (ANNOUNCE, code, "tc_init: could not rename prds to ^a.", prds_name); 586 end; 587 end; 588 else call syserr$error_code (ANNOUNCE, code, "tc_init: could not delete old ^a.", prds_name); 589 end; 590 591 cpu_cardp = null (); 592 sys_info$hfp_exponent_available = "1"b; /* let's pretend there are no L68s */ 593 other_loop: 594 call config_$find (CPU_CARD_WORD, cpu_cardp); 595 if cpu_cardp = null () then return; /* Return after all cards examined. */ 596 597 i = cpu_card.tag - 1; 598 599 /* Create and entry-hold the PRDS for all but the bootload CPU. This has already been done for 600* the bootload PRDS, which is deciduous. Save the astep result in the idle APTE. */ 601 602 if i ^= tag then do; /* Don't do bootload. */ 603 prds_name = "cpu_" || substr (LETTERS, i + 1, 1) || ".prds"; 604 call append$branchx (PRDS_DIR, prds_name, RW_mode, seg_rb, pds$process_group_id, 0, 0, 0, code); 605 if code = 0 606 then call initiate (PRDS_DIR, prds_name, "", 0, 0, prdsp, code); 607 else prdsp = null (); 608 if code = 0 609 then scs$idle_aptep (i) -> apte.prds = rel (grab_aste$prewithdraw (prdsp, tc_data$prds_length, code)); 610 if code ^= 0 then do; 611 call syserr$error_code (ANNOUNCE, code, "tc_init: cannot create ^a. This CPU may not be added.", 612 prds_name); 613 cpu_card.state = "off"; /* avoid trying to start it. */ 614 scs$idle_aptep (i) = null (); /* Cause easy crawlout later */ 615 end; 616 if prdsp ^= null () then call terminate_$teseg (prdsp, (0), code); 617 end; 618 if cpu_card.state = "on" 619 then /* If CPU is to be added ... */ 620 if i ^= tag then do; /* If not the bootload processor ... */ 621 call start_cpu (i, code); 622 if code ^= 0 623 then call syserr (ANNOUNCE, "tc_init: Could not start CPU ^a.", substr ("ABCDEFGH", cpu_card.tag, 1)); 624 end; 625 if cpu_card.type ^= "dps8" 626 then /* oh well */ 627 sys_info$hfp_exponent_available = "0"b; /* no mixed configurations for hex fp */ 628 go to other_loop; /* Loop. */ 629 630 /* format: off */ 631 /* BEGIN INCLUDE FILE ... stack_0_data.incl.pl1 */ 1 2 1 3 /* Created 790509 by Mike Grady */ 1 4 1 5 dcl stack_0_data$ fixed bin ext; /* shared stack 0 data base seg */ 1 6 dcl stack_0_data_init_number_of_stacks fixed bin; /* Make PL/I work */ 1 7 dcl sdtp ptr; 1 8 1 9 dcl 1 sdt aligned based (sdtp), /* stack 0 database */ 1 10 2 lock bit (36), /* lock before changing threads */ 1 11 2 num_stacks fixed bin, /* number of stacks in pool */ 1 12 2 freep bit (18), /* head of free thread, managed LIFO */ 1 13 2 pad fixed bin, 1 14 2 stacks (stack_0_data_init_number_of_stacks 1 15 refer (sdt.num_stacks)) like sdte; 1 16 1 17 dcl sdtep ptr; 1 18 1 19 dcl 1 sdte aligned based (sdtep), /* stack data table entry */ 1 20 2 nextp bit (18) unal, /* thread to next free entry (if free) */ 1 21 2 pad bit (18) unal, 1 22 2 astep bit (18) unal, /* ptr to ASTE for this stack seg */ 1 23 2 aptep bit (18) unal, /* ptr to APTE of process using this stack, if not free */ 1 24 2 sdw bit (72); /* SDW for this stack seg */ 1 25 1 26 /* END INCLUDE FILE ... stack_0_data.incl.pl1 */ 631 632 /* BEGIN INCLUDE FILE sys_trace.incl.pl1 -- Last modified Jan. 1982 */ 2 2 /* Modified for new pgt_ signal technology, Benson Margulies, 83-12 */ 2 3 /* format: style3 */ 2 4 2 5 declare trace_ptr ptr; 2 6 2 7 declare 1 trace based (trace_ptr) aligned, /* system trace data structure */ 2 8 2 next_free fixed bin (17) uns unal, /* index to next free trace entry */ 2 9 2 pad1 bit (19) unal, 2 10 2 last_available fixed bin (17) uns unal, /* index to first unusable entry in list */ 2 11 2 pad2 bit (19) unal, 2 12 2 ttime fixed bin (71), /* time used to figure incremental times */ 2 13 2 temp bit (36), /* temporary used by page$enter_data */ 2 14 2 index bit (17), /* index to end of post purge list */ 2 15 2 threshold fixed bin (17) unsigned unaligned, 2 16 2 pad3 bit (1) unaligned, /* to halfword */ 2 17 2 flags unaligned, 2 18 3 send_ips bit (1) unaligned, /* send pgt_ when index reached threshold */ 2 19 3 pad bit (17) unaligned, 2 20 2 pad4 bit (36) aligned, 2 21 2 data (1024), /* trace data entry structure */ 2 22 3 data_word char (4), /* per-type data word */ 2 23 3 type fixed bin (6) uns unaligned, /* type of trace entry */ 2 24 3 pad bit (14) unaligned, 2 25 3 dtime fixed bin (16) uns unaligned; /* time increment since last trace entry (in 64 micsec) */ 2 26 2 27 declare 1 page_trace_entry based (trace_ptr) aligned, /* entry for page fault data */ 2 28 2 pad bit (18) unaligned, 2 29 2 ring fixed bin (3) uns unaligned, /* ring number fault occured in */ 2 30 2 segment_number fixed bin (15) uns unaligned, /* segment number of segment getting page fault */ 2 31 2 type fixed bin (6) uns unaligned, /* MBZ for page faults */ 2 32 2 page_number fixed bin (12) uns unaligned, /* page number which caused fault */ 2 33 2 pad1 bit (2) unal, 2 34 2 time fixed bin (16) uns unaligned; /* time increment since last trace entry (res = 64 micro-secs) */ 2 35 2 36 declare 1 extended_page_trace_entry 2 37 based (trace_ptr) aligned, /* page fault data with more info */ 2 38 2 psr_segno fixed bin (12) uns unaligned, /* segment number of proc faulting */ 2 39 2 psr_offset fixed bin (18) uns unaligned, /* IC of proc faulting */ 2 40 2 tsr_segno_1 bit (6) unaligned, /* 1st 6 bits of segment number faulted */ 2 41 2 type fixed bin (6) uns unaligned, /* 15 decimal */ 2 42 2 tsr_segno_2 bit (6) unaligned, /* last 6 bits of segment number faulted */ 2 43 2 tsr_pageno fixed bin (8) uns unaligned, /* page number faulted */ 2 44 2 time fixed bin (16) uns unaligned; /* time increment since last trace entry (res = 64 micro-secs) */ 2 45 2 46 2 47 /* END INCLUDE FILE sys_trace.incl.pl1 */ 632 633 /* BEGIN INCLUDE FILE ... apte.incl.pl1 */ 3 2 3 3 /* Modified 1984-11-11 by E. Swenson for IPC event channel validation. */ 3 4 3 5 dcl aptep pointer; 3 6 3 7 dcl 1 apte based (aptep) aligned, /* APT entry declaration for an active (known) process */ 3 8 2 thread unaligned, /* List thread */ 3 9 3 fp bit (18), /* Forward pointer */ 3 10 3 bp bit (18), /* Backward pointer */ 3 11 2 flags unaligned, /* Flags and miscellaneous */ 3 12 3 mbz bit (1), /* This bit must be zero (sentinel bit) */ 3 13 3 wakeup_waiting bit (1), /* ON if process has received wakeup */ 3 14 3 stop_pending bit (1), /* ON if process has received stop connect */ 3 15 3 pre_empted bit (1), /* ON if process is being pre-empted by get_processor */ 3 16 3 hproc bit (1), /* ON if process is hardcore process */ 3 17 3 loaded bit (1), /* ON if required per-process pages are in memory and wired */ 3 18 3 eligible bit (1), /* ON if process is eligible */ 3 19 3 idle bit (1), /* ON if this is an idle process */ 3 20 3 interaction bit (1), /* ON if process has interacted recently */ 3 21 3 pre_empt_pending bit (1), /* ON if process has received pre-empt connect */ 3 22 3 default_procs_required bit (1), /* ON if apte.procs_required is system default */ 3 23 3 realtime_burst bit (1), /* ON if next eligibility is realtime */ 3 24 3 always_loaded bit (1), /* ON if process is not to be unloaded */ 3 25 3 dbr_loaded bit (1), /* ON if DBR is loaded on some CPU */ 3 26 3 being_loaded bit (1), /* ON if somebody loading this process */ 3 27 3 shared_stack_0 bit (1), /* ON if a shared stack_0 is assigned */ 3 28 3 page_wait_flag bit (1), /* flag ON if waiting for page */ 3 29 3 firstsw bit (1), /* OFF until process is intialized */ 3 30 3 state bit (18), /* execution state */ 3 31 2 page_faults fixed bin (35), /* total page faults for the process */ 3 32 2 processid bit (36), /* bit 0-17: offset of ATPE */ 3 33 /* bit 18-35: sequential number */ 3 34 2 te fixed bin (35), /* virtual time since eligibility award */ 3 35 2 ts fixed bin (35), /* virtual time since scheduling */ 3 36 2 ti fixed bin (35), /* virtual time since interaction */ 3 37 2 timax fixed bin (35), /* maximum value allowed for apte.ti */ 3 38 3 39 /* * * * * * * * */ 3 40 3 41 2 ipc_pointers unaligned, 3 42 3 event_thread bit (18), /* relative pointer to ITT list */ 3 43 3 pad3 bit (18), 3 44 2 ips_message bit (36), /* IPS signals pending */ 3 45 2 asteps unaligned, /* relative ASTE pointers */ 3 46 3 pds bit (18), /* PDS (per-process) */ 3 47 3 dseg bit (18), /* DSEG (per-process) */ 3 48 3 prds bit (18), /* PRDS (per-processor) */ 3 49 2 savex7 bit (18) unaligned, /* x7 at call to getwork (return point in pxss) */ 3 50 2 term_processid bit (36), /* process to send wakeup at temination */ 3 51 2 lock_id bit (36), /* File System unqieu ID associated with process */ 3 52 2 time_used_clock fixed bin (71), /* Total CPU time when process last lost CPU */ 3 53 3 54 /* * * * * * * * */ 3 55 3 56 2 wait_event bit (36) aligned, /* Event ID process awaiting */ 3 57 2 wct_index bit (18) unaligned, /* rel offset of WCTE */ 3 58 2 flags2 unaligned, 3 59 3 priority_scheduling bit (1), /* ON if guaranteed eligibility */ 3 60 3 special_wakeups bit (6), /* Special wakeup channels */ 3 61 3 pad7 bit (7), 3 62 3 batch bit (1), /* ON if absentee */ 3 63 3 pr_tag bit (3), /* CPU tag running or last run */ 3 64 2 state_change_time fixed bin (71), /* Time apte.state last changed */ 3 65 2 alarm_event fixed bin (71), /* wakeup event for alarm clock manager */ 3 66 2 alarm_time_thread bit (18) unaligned, /* thread of processes with pending alarms */ 3 67 2 alarm_time bit (54) unaligned, /* wakeup time for alarm */ 3 68 3 69 /* * * * * * */ 3 70 3 71 2 term_channel fixed bin (71), /* wakeup event for account overflow */ 3 72 2 ws_size fixed bin, /* working set estimate for the process */ 3 73 2 temax fixed bin (35), /* maximum eligibility slice (vcpu) */ 3 74 2 deadline fixed bin (71), /* time of next run */ 3 75 2 lock bit (18) unaligned, /* 0 => APTE locked, unlocked => return point of last unlock */ 3 76 2 unusable bit (18) unaligned, /* locking routines destroy */ 3 77 2 cpu_monitor fixed bin (35), /* if not 0, send wakeup to term_processid when virtual cpu 3 78* /* reaches this (units = 1/1024 sec) */ 3 79 2 paging_measure fixed bin (71), /* cumulative memory units */ 3 80 2 access_authorization bit (72), /* authorization of this process */ 3 81 2 dbr fixed bin (71), /* DBR value (constant since DSEG entry-held) */ 3 82 3 83 2 virtual_cpu_time fixed bin (71), /* cumulative virtual CPU time for the process */ 3 84 2 ittes_sent fixed bin (18), /* Unprocessed ITTs sent by this process */ 3 85 2 ittes_got fixed bin (18), /* Unprocessed ITTs received by this process */ 3 86 3 87 /* Cells used to drive and instrument finite-state model for response time 3 88* measurement. Maintained by meter_response_time */ 3 89 3 90 2 current_response_state fixed bin (17) unaligned, /* Process state in modle */ 3 91 2 pad18 bit (18) unaligned, 3 92 2 number_processing fixed bin (35), /* Number interactions */ 3 93 2 last_response_state_time fixed bin (71), /* Clock time at last response state change */ 3 94 2 total_processing_time fixed bin (71), /* Total interaction processing time */ 3 95 3 96 /* * * * * * */ 3 97 3 98 2 begin_interaction_vcpu fixed bin (71), /* Virtual cpu at beginning of last interaction */ 3 99 3 100 /* End of cells for finite-state model */ 3 101 3 102 2 saved_temax fixed bin (35), /* temax at eligibility award */ 3 103 2 procs_required bit (8) unaligned, /* bit mask of CPUs this process can run */ 3 104 2 pad4 bit (28) unaligned, 3 105 2 ipc_r_offset fixed bin (18) unsigned, 3 106 2 ipc_r_factor fixed bin (35) unsigned, 3 107 2 apad (10) fixed bin (35); 3 108 3 109 /* END INCLUDE FILE ... apte.incl.pl1 */ 633 634 /* BEGIN INCLUDE FILE ... sdw_info.incl.pl1 ... 12/16/80, for ADP conversion */ 4 2 /* Note: This include file has an ALM counterpart made with cif. Keep it up to date */ 4 3 4 4 dcl sdw_info_ptr pointer; 4 5 4 6 dcl 1 sdw_info aligned based (sdw_info_ptr), /* Structure describing SDW contents */ 4 7 2 address fixed bin (26), /* Address of seg base or of page table */ 4 8 2 size fixed bin (19), /* Max length of segment (NOT offset of last word) */ 4 9 4 10 2 access unaligned, /* REWP */ 4 11 3 read bit (1) unaligned, 4 12 3 execute bit (1) unaligned, 4 13 3 write bit (1) unaligned, 4 14 3 privileged bit (1) unaligned, 4 15 4 16 2 pad1 bit (32) unaligned, 4 17 4 18 2 rings unaligned, /* Ring brackets */ 4 19 3 r1 bit (3) unaligned, 4 20 3 r2 bit (3) unaligned, 4 21 3 r3 bit (3) unaligned, 4 22 4 23 2 pad2 bit (27) unaligned, 4 24 4 25 2 flags aligned, 4 26 3 paged bit (1) unaligned, /* "1"b => Segment is paged */ 4 27 3 faulted bit (1) unaligned, /* "1"b => SDW has fault set */ 4 28 3 cache bit (1) unaligned, /* "1"b => Segment is encacheable */ 4 29 3 pad3 bit (33) unaligned, 4 30 4 31 2 gate_entry_bound fixed bin (14); /* Number of entrypoints in gate, or zero */ 4 32 4 33 /* END INCLUDE FILE ... sdw_info.incl.pl1 */ 634 635 /* BEGIN INCLUDE FILE ... tcm.incl.pl1 ... used to generate tc_data cds */ 5 2 /* NOTE -- This include file has TWO counterparts in ALM: tc_meters.incl.alm and */ 5 3 /* wcte.incl.alm. They cannot be produced with cif, and must be kept up to date manually. */ 5 4 /* Modified 830914 to replace tty_polling_time with opc_polling_time... -E. A. Ranzenbach */ 5 5 /* Modified 1984.05.21 by M. Pandolf to add tc_suspend_lock */ 5 6 /* Modified 1984.11.26 by Keith Loepere for uid_array. */ 5 7 /* Modified 1984.12.06 by Keith Loepere for page create delaying. */ 5 8 5 9 dcl tcmp ptr; 5 10 5 11 dcl 1 tcm aligned based (tcmp), 5 12 2 tc_suspend_lock like lock, /* when locked, tc is suspended */ 5 13 2 cid2 fixed bin (18), 5 14 2 cid3 fixed bin (18), 5 15 2 cid4 fixed bin (18), 5 16 2 depth_count fixed bin (18), /* depth last process run */ 5 17 2 loadings fixed bin (18), /* number of process loadings */ 5 18 5 19 2 blocks fixed bin (18), /* number of calls to block */ 5 20 2 wakeups fixed bin (18), /* number of calls to wakeup */ 5 21 2 waits fixed bin (18), /* number of calls to wait */ 5 22 2 notifies fixed bin (18), /* number of calls to notify */ 5 23 2 schedulings fixed bin (18), 5 24 2 interactions fixed bin (18), /* number of interactive schedulings */ 5 25 2 avequeue fixed bin (35, 18), /* recent time average of number in queue */ 5 26 2 te_wait fixed bin (18), /* times te called from wait */ 5 27 5 28 2 te_block fixed bin (18), /* times te updated from block */ 5 29 2 te_i_stop fixed bin (18), /* times te updated from i_stop */ 5 30 2 te_pre_empt fixed bin (18), /* times te updated from pre_empt */ 5 31 2 p_interactions fixed bin, /* times interaction bit turned off because of high priority */ 5 32 2 idle fixed bin (71), /* total idle time */ 5 33 2 mp_idle fixed bin (71), /* multi-programming idle */ 5 34 5 35 2 nmp_idle fixed bin (71), /* non-multi-programming idle time */ 5 36 2 zero_idle fixed bin (71), /* zero idle time */ 5 37 2 last_time fixed bin (71), /* last time a process was run */ 5 38 2 loop_locks fixed bin (18), /* times looped on the APT lock */ 5 39 2 loop_lock_time fixed bin (18), /* time looping on the APT lock */ 5 40 2 ave_eligible fixed bin (35, 18), /* average length of eligible queue */ 5 41 2 sort_to_elhead fixed bin (18), /* 0=> no one,1 => int've only, 2 => everybody */ 5 42 2 processor_time fixed bin (71), /* total processor time on system */ 5 43 2 response_time fixed bin (71), /* estimate of response time */ 5 44 2 eligible_time fixed bin (71), /* estimate of eligible time */ 5 45 2 response_count fixed bin, /* count of response meters */ 5 46 2 eligible_count fixed bin, /* count of eligible meters */ 5 47 2 quit_counts (0:5) fixed bin, /* array of buckets indexed by state */ 5 48 2 loading_idle fixed bin (71), /* loading_idle time */ 5 49 2 delta_vcpu fixed bin (71), /* delta virtual CPU time for the system */ 5 50 2 post_purge_switch fixed bin, /* ON if post purging is to be done */ 5 51 2 time_out_severity fixed bin, /* syserr first arg for notify time outs */ 5 52 2 notify_check fixed bin, /* obsolete */ 5 53 2 quit_priority fixed bin, /* factor for scheduler quit response */ 5 54 2 iobm_polling_time fixed bin (71), /* time to poll iobm */ 5 55 2 end_of_time fixed bin (71), /* very large time */ 5 56 2 gp_at_notify fixed bin (18), /* 0 => just do get_idle_processor */ 5 57 2 gp_at_ptlnotify fixed bin (18), /* 0 => just do get_idle_processor */ 5 58 2 int_q_enabled fixed bin (18), /* 0 => no intv q in percent mode */ 5 59 2 fnp_buffer_threshold fixed bin (18), /* if fewer free buffs then stingy alloc strategy */ 5 60 /* set this to >= half n_ttylines/fnp for safety */ 5 61 5 62 /* 100 octal */ 5 63 5 64 2 depths (8) fixed bin (18), /* histogram of run depths */ 5 65 2 tdepths (8) fixed bin (71), /* histogram of times run per depth */ 5 66 2 pfdepth (8) fixed bin (18), /* histogram of page faults per depth */ 5 67 5 68 2 ptl_not_waits fixed bin (18), /* times ptl_wait noticed ptl was unlocked */ 5 69 2 gw_gp_window_count fixed bin (18), /* times window noticed */ 5 70 2 metering_lock fixed bin (18), /* 0=locked, else unlocked */ 5 71 2 ptl_waits fixed bin (18), /* num calls to ptl_wait */ 5 72 2 gp_start_count fixed bin (18), /* to detect gw_gp window lossage */ 5 73 2 gp_done_count fixed bin (18), 5 74 2 nto_check_time fixed bin (71), /* next time at which nto code will be called */ 5 75 2 nto_delta fixed bin (35), /* microsec between nto checks */ 5 76 2 nto_count fixed bin (18), /* number of times nto detected */ 5 77 2 tcpu_scheduling fixed bin (18), /* obsolete */ 5 78 2 nto_event bit (36), /* last event which NTO'd */ 5 79 2 page_notifies fixed bin (18), 5 80 2 notify_nobody_count fixed bin (18), 5 81 2 notify_nobody_event bit (36), 5 82 2 system_type fixed bin, /* used to be tcm.inter */ 5 83 5 84 2 stat (0:15) fixed bin (18), /* num apte's in each state */ 5 85 5 86 /* 200 octal */ 5 87 5 88 2 wait (8), 5 89 3 time fixed bin (18), /* histogram of page fault waiting times versus did */ 5 90 3 count fixed bin (18), 5 91 5 92 2 ready (8), 5 93 3 time fixed bin (18), /* histogram of times in ready queue */ 5 94 3 count fixed bin (18), 5 95 5 96 2 total_pf_time fixed bin (71), /* total time spent from start to end of 5 97* all page faults */ 5 98 2 total_pf_count fixed bin (18), /* total number of page faults metered */ 5 99 2 auto_tune_ws fixed bin (18), /* 0=> dont, atherwise compensate for quantum len */ 5 100 2 ocore_delta fixed bin (18), /* number of pages reserved for int users */ 5 101 2 ws_sum fixed bin (18), /* total of eligible's ws_sizes */ 5 102 2 nonidle_force_count fixed bin (18), /* count of eligibilities forced */ 5 103 2 itt_list_lock bit (36) aligned, /* Lock on ITT free list */ 5 104 2 cpu_pf_time fixed bin (71), /* total cpu time spent handling page faults */ 5 105 2 cpu_pf_count fixed bin (18), /* total count of cpu time meterings */ 5 106 2 special_offsets unaligned, 5 107 3 apt_offset bit (18), 5 108 3 pad bit (18), 5 109 2 getwork_time fixed bin (71), /* total time spent in getwork */ 5 110 2 getwork_count fixed bin (18), /* total times through getwork */ 5 111 2 short_pf_count fixed bin (18), /* number of short page faults */ 5 112 2 interrupt_time fixed bin (71), /* total time spent in interrupt */ 5 113 2 interrupt_count fixed bin (71), /* total number of metered interrupts */ 5 114 2 ocore fixed bin (35, 18), /* fraction of core for int've users */ 5 115 2 pre_empt_flag bit (36) aligned, /* controls whether preempting at done time */ 5 116 2 cumulative_memory_usage fixed binary (71), /* total number of memory usage units */ 5 117 2 processor_time_at_define_wc fixed bin (71), /* value of processor_time when WC's last defined */ 5 118 2 boost_priority fixed bin, /* number of times priority process given high priority */ 5 119 2 lost_priority fixed bin, /* number of times priority process lost eligibility */ 5 120 2 total_clock_lag fixed bin (71), /* sum of all simulated clock delays */ 5 121 2 clock_simulations fixed bin, /* number of times alarm clock interrupt was simulated */ 5 122 2 max_clock_lag fixed bin, /* largest simulated alarm clock delay */ 5 123 5 124 /* 300 octal */ 5 125 5 126 2 pdscopyl fixed bin (18), /* amount of pds to copy for new process */ 5 127 2 max_hproc_segno fixed bin, /* largest allowed hardcore segment number */ 5 128 2 prds_length fixed bin (18), /* length of PRDS */ 5 129 2 pds_length fixed bin (18), /* length of PDS */ 5 130 2 lock fixed bin (18), /* process id generator lock */ 5 131 2 id bit (36) aligned, /* next uid to be added to uid_array */ 5 132 2 system_shutdown fixed bin (18), 5 133 2 working_set_factor fixed bin (35, 18), /* working set factor */ 5 134 5 135 2 ncpu fixed bin (18), /* number of processors currently being used */ 5 136 2 last_eligible bit (18), /* last process to gain eligibility */ 5 137 2 apt_lock fixed bin (35), /* + write; 0 hidden; -1 unlocked; -(N+1) Nreaders */ 5 138 2 apt_size fixed bin (18), /* number of APT entries */ 5 139 2 realtime_q aligned like based_sentinel, /* processes with realtime deadlines */ 5 140 2 aht_size fixed bin (18), /* APT hash table size */ 5 141 2 itt_size fixed bin (18), /* number of ITT entries */ 5 142 5 143 2 dst_size fixed bin (18), /* number of allowed DST entries */ 5 144 2 itt_free_list bit (18), /* pointer to ITT free list */ 5 145 2 used_itt fixed bin (18), /* number of used ITT entries */ 5 146 2 initializer_id bit (36) aligned, /* process id of initializer */ 5 147 2 n_eligible fixed bin (18), /* number of processes eligible */ 5 148 2 max_eligible fixed bin (30), /* maximum allowed number of eligible processes */ 5 149 2 wait_enable fixed bin (18), /* turned on when waiting mechanism works */ 5 150 2 apt_entry_size fixed bin (18), /* size of an APT entry */ 5 151 5 152 2 interactive_q aligned like based_sentinel, /* head of interactive queue */ 5 153 2 dst_ptr ptr, /* pointer to device signal table */ 5 154 2 old_user ptr, /* last process to run (apt ptr ) */ 5 155 2 initialize_time fixed bin (71), /* time of initialization */ 5 156 5 157 2 init_event fixed bin (18), /* wait event during initialization */ 5 158 2 oldt fixed bin (18), /* timer reading from previous process */ 5 159 2 newt fixed bin (18), /* timer setting for new process */ 5 160 2 tefirst fixed bin (30), /* first eligible time */ 5 161 2 telast fixed bin (30), /* last eligible time */ 5 162 2 timax fixed bin (35), /* time in queue for lowest level */ 5 163 2 empty_q bit (18), /* thread of empty APT entries */ 5 164 2 working_set_addend fixed bin (18), /* additive working set parameter */ 5 165 2 ready_q_head bit (0) aligned, /* for added segdef */ 5 166 2 eligible_q_head aligned like based_sentinel, /* head of eligible queue */ 5 167 2 ready_q_tail bit (0) aligned, /* for added segdef */ 5 168 2 eligible_q_tail aligned like based_sentinel, /* tail of eligible queue */ 5 169 2 idle_tail aligned like based_sentinel, /* tail of idle list */ 5 170 2 min_eligible fixed bin (30), 5 171 2 alarm_timer_list bit (18) aligned, /* rel pointer to apt entry for next alarm timer */ 5 172 2 guaranteed_elig_inc fixed bin (35), /* amount of guaranteed eligibility time in microsecs. */ 5 173 2 priority_sched_inc fixed bin (35), /* amount of block time before process is given priority */ 5 174 2 next_alarm_time fixed bin (71), /* clock time for next alarm timer */ 5 175 2 priority_sched_time fixed bin (71), /* time for priority process to be given priority */ 5 176 2 opc_polling_time fixed bin (71), /* time to poll console DIM */ 5 177 2 disk_polling_time fixed bin (71), /* time to poll disk DIM */ 5 178 2 tape_polling_time fixed bin (71), /* time to poll tape DIM */ 5 179 2 imp_polling_time fixed bin (71), /* time to poll imp */ 5 180 2 imp_polling_lock fixed bin (18), /* do not poll if lock set */ 5 181 2 max_channels fixed bin (18), /* num special channels per process */ 5 182 5 183 /* 400 octal */ 5 184 5 185 2 system_virtual_time fixed bin (71), /* non-idle virtual time */ 5 186 2 credit_bank fixed bin (71), /* credits not yet passed out */ 5 187 2 min_wct_index bit (18) aligned, /* offset of initializer work class table entry */ 5 188 2 max_wct_index bit (18) aligned, /* offset of highest wcte currently defined */ 5 189 2 delta_vt fixed bin (71), /* temp used by pxss.compute_virtual_clocks */ 5 190 2 gross_idle_time fixed bin (71), /* idle time_used_clock */ 5 191 2 credits_per_scatter fixed bin (35), /* total number of credits awarded at once */ 5 192 2 best_credit_value fixed bin (18), /* temp for pxss.find_next_eligible */ 5 193 2 define_wc_time fixed bin (71), /* clock time when workclasses last degined */ 5 194 2 max_batch_elig fixed bin (35), 5 195 2 num_batch_elig fixed bin (35), 5 196 2 deadline_mode fixed bin (35), /* 0=> ti sorts, else deadline sorts */ 5 197 2 credits_scattered fixed bin (35), 5 198 2 max_max_eligible fixed bin (30), /* Maximum of maxe */ 5 199 2 max_stopped_stack_0 fixed bin (35), /* Maximum stack_0's suspended by stopped procs */ 5 200 2 stopped_stack_0 fixed bin (35), /* Number stack_0's suspended by stopped procs */ 5 201 2 mos_polling_interval fixed bin (35), /* for heals */ 5 202 2 mos_polling_time fixed bin (71), /* for heals */ 5 203 2 vcpu_response_bounds (VCPU_RESPONSE_BOUNDS) fixed bin (35), 5 204 2 vcpu_response_bounds_size fixed bin (35), 5 205 2 meter_response_time_calls fixed bin (35), 5 206 2 meter_response_time_invalid fixed bin (35), 5 207 2 meter_response_time_overhead fixed bin (71), 5 208 2 init_wait_time fixed bin (71), /* used by wait/notify during initialization */ 5 209 2 init_wait_timeout fixed bin (71), /* notify-timeout interval during initialization */ 5 210 2 init_timeout_severity fixed bin, /* notify-timeout severity during initialization */ 5 211 2 init_timeout_recurse fixed bin, /* count of NTO recursion during initialization */ 5 212 2 max_timer_register fixed bin (71), /* max cpu burst = # cpus x pre_empt_sample_time */ 5 213 2 pre_empt_sample_time fixed bin (35), /* tuning parameter - max time between samples */ 5 214 2 governing_credit_bank fixed bin (35), /* used for limiting eligibility on governed work classes*/ 5 215 2 process_initial_quantum fixed bin (35), /* eligibility quantum first eligibility */ 5 216 2 default_procs_required bit (8) aligned, /* default mask of CPUs required */ 5 217 2 work_class_idle fixed bin (71), /* idle time due to work class restrictions */ 5 218 5 219 /* Tuning Parameters for Stack Truncation */ 5 220 5 221 2 stk_truncate bit (1) aligned, 5 222 2 stk_truncate_always bit (1) aligned, 5 223 2 stk_trunc_avg_f1 fixed bin (35, 18), 5 224 2 stk_trunc_avg_f2 fixed bin (35, 18), 5 225 2 lock_error_severity fixed bin, /* syserr severity */ 5 226 5 227 2 gv_integration fixed bin (35), /* Integration interval for governing */ 5 228 2 gv_integration_set bit (1) aligned, /* ON => gv_integration set by ctp */ 5 229 2 pauses fixed bin (35), /* Calls to pause (reschedule) */ 5 230 2 volmap_polling_time fixed bin (71), 5 231 2 next_ring0_timer fixed bin (71), /* next time that ring 0 timer goes off */ 5 232 2 realtime_io_priority_switch fixed bin, /* 0 => give I/O interrupt wakeups realtime priotiry */ 5 233 2 realtime_io_deadline fixed bin (35), /* Delta to clock for I/O realtime deadline */ 5 234 2 realtime_io_quantum fixed bin (35), /* Quantum for I/O realtime burst */ 5 235 2 realtime_priorities fixed bin (35), /* Count for metering */ 5 236 2 relinquishes fixed bin (35), /* Calls to relinquish_priority */ 5 237 2 abort_ips_mask bit (36) aligned, /* IPS mask for tc_util$check_abort */ 5 238 5 239 /* 500 octal */ 5 240 5 241 2 uid_array (0:15) bit (36) aligned, /* array from which a uid is chosen (randomly) */ 5 242 2 pad5 (176) fixed bin (35), /* room for expansion compatibly */ 5 243 5 244 /* 1000 octal */ 5 245 5 246 2 pad7 (64) fixed bin (35), 5 247 5 248 /* 1100 octal */ 5 249 5 250 2 pad6 (8) fixed bin (35), 5 251 2 work_class_table aligned, /* array of per workclass information */ 5 252 3 wcte (0:16) aligned like wct_entry, 5 253 5 254 /* 3000 octal */ 5 255 5 256 2 apt fixed bin; 5 257 5 258 dcl wctep ptr; 5 259 5 260 dcl 1 wct_entry aligned based (wctep), /* Work class entry */ 5 261 2 thread unaligned, /* Ready list */ 5 262 3 fp bit (18), /* Head of ready list */ 5 263 3 bp bit (18), /* Tail of ready list */ 5 264 2 flags unaligned, 5 265 3 mnbz bit (1), /* Sentinel bit must not be zero. */ 5 266 3 defined bit (1), 5 267 3 io_priority bit (1), 5 268 3 governed bit (1), 5 269 3 interactive_q bit (1), 5 270 3 pad bit (31), 5 271 2 credits fixed bin (35), /* Current worthiness of group */ 5 272 2 minf fixed bin (35), /* min fraction of cpu */ 5 273 2 pin_weight fixed bin (35), /* number of cycles to pin pages */ 5 274 2 eligibilities fixed bin (35), /* Count of eligibilities awarded */ 5 275 2 cpu_sum fixed bin (71), /* CPU used by members */ 5 276 2 resp1 fixed bin (71), 5 277 2 resp2 fixed bin (71), 5 278 2 quantum1 fixed bin (35), 5 279 2 quantum2 fixed bin (35), 5 280 2 rmeter1 fixed bin (71), 5 281 2 rmeter2 fixed bin (71), 5 282 2 rcount1 fixed bin (35), 5 283 2 rcount2 fixed bin (35), 5 284 2 realtime fixed bin (35), 5 285 2 purging fixed bin (35), 5 286 2 maxel fixed bin (35), 5 287 2 nel fixed bin (35), 5 288 2 number_thinks fixed bin (35), /* number times process entered "think" state */ 5 289 2 number_queues fixed bin (35), /* number times process entered "queued" state */ 5 290 2 total_think_time fixed bin (71), 5 291 2 total_queue_time fixed bin (71), 5 292 5 293 /* The next three arrays correspond to the array vcpu_response_bounds */ 5 294 5 295 2 number_processing (VCPU_RESPONSE_BOUNDS+1) fixed bin (35), /* number times entered "processing" state */ 5 296 2 total_processing_time (VCPU_RESPONSE_BOUNDS+1) fixed bin (71), 5 297 2 total_vcpu_time (VCPU_RESPONSE_BOUNDS+1) fixed bin (71), 5 298 2 maxf fixed bin (35), /* maximum fraction of cpu time */ 5 299 2 governing_credits fixed bin (35), /* for limiting cpu resources */ 5 300 2 pad1 (4) fixed bin (35); 5 301 5 302 5 303 dcl 1 based_sentinel aligned based, /* format of pxss-style sentinel */ 5 304 2 fp bit (18) unal, 5 305 2 bp bit (18) unal, 5 306 2 sentinel bit (36) aligned; 5 307 5 308 dcl VCPU_RESPONSE_BOUNDS fixed bin init (3) int static options (constant); 5 309 5 310 /* END INCLUDE FILE tcm.incl.pl1 */ 635 636 /* Begin include file hc_lock.incl.pl1 BIM 2/82 */ 6 2 /* Replaced by hc_fast_lock.incl.pl1 RSC 11/84 because name of structure 6 3* encourages name conflicts. 6 4* USE HC_FAST_LOCK INSTEAD! 6 5**/ 6 6 6 7 /* Lock format suitable for use with lock$lock_fast, unlock_fast */ 6 8 6 9 /* format: style3 */ 6 10 6 11 declare lock_ptr pointer; 6 12 declare 1 lock aligned based (lock_ptr), 6 13 2 pid bit (36) aligned, /* holder of lock */ 6 14 2 event bit (36) aligned, /* event associated with lock */ 6 15 2 flags aligned, 6 16 3 notify_sw bit (1) unaligned, 6 17 3 pad bit (35) unaligned; /* certain locks use this pad, like dirs */ 6 18 6 19 /* End include file hc_lock.incl.pl1 */ 636 637 /* BEGIN INCLUDE FILE scs.incl.pl1 ... March 1983 */ 7 2 /* format: style4 */ 7 3 7 4 /* Information about system controllers */ 7 5 7 6 dcl 1 scs$controller_data (0:7) aligned ext, /* per-controller info */ 7 7 2 size fixed bin (17) unaligned, /* size (in 1024 word blocks) of this controller */ 7 8 2 base fixed bin (17) unaligned, /* abs address (0 mod 1024) for base of this controller */ 7 9 2 eima_data (4) unaligned, /* EIMA information for this controller */ 7 10 3 mask_available bit (1) unaligned, /* ON if corresponding mask exists */ 7 11 3 mask_assigned bit (1) unaligned, /* ON if mask assigned to a port */ 7 12 3 mbz bit (3) unaligned, 7 13 3 mask_assignment fixed bin (3) unaligned, /* port to which mask is assigned */ 7 14 2 info aligned, 7 15 3 online bit (1) unaligned, /* ON if controller is online */ 7 16 3 offline bit (1) unaligned, /* ON if controller is offline but can be added */ 7 17 3 store_a_online bit (1) unaligned, /* ON if store A is online */ 7 18 3 store_a1_online bit (1) unaligned, /* ON if store A1 is online */ 7 19 3 store_b_online bit (1) unaligned, /* ON if store B is online */ 7 20 3 store_b1_online bit (1) unaligned, /* ON if store B1 is online */ 7 21 3 store_b_is_lower bit (1) unaligned, /* ON if store B is lower */ 7 22 3 ext_interlaced bit (1) unaligned, /* ON if this SCU is interlaced with other SCU */ 7 23 3 int_interlaced bit (1) unaligned, /* ON if this SCU is internally interlaced */ 7 24 3 four_word bit (1) unaligned, /* ON if external interlace is 4-word */ 7 25 3 cyclic_priority (7) bit (1) unaligned, /* Cyclic priority for adjacent ports */ 7 26 3 type bit (4) unaligned, /* Model number for this controller */ 7 27 3 abs_wired bit (1) unaligned, /* ON if controller can have abs_wired pages */ 7 28 3 program bit (1) unaligned, /* PROGRAM/MANUAL switch setting */ 7 29 3 mbz bit (13) unaligned, 7 30 2 lower_store_size fixed bin (17) unaligned, /* size (in 1024 word blocks) of lower store */ 7 31 2 upper_store_size fixed bin (17) unaligned; /* size (in 1024 word blocks) of upper store */ 7 32 7 33 /* Information about CPUs */ 7 34 7 35 dcl 1 scs$processor_data (0:7) aligned ext, /* information about CPUs in the system */ 7 36 ( 7 37 2 online bit (1), /* "1"b if CPU is online */ 7 38 2 offline bit (1), /* "1"b if CPU is offline but can be added */ 7 39 2 release_mask bit (1), /* "1"b is this CPU is to give up its mask */ 7 40 2 accept_mask bit (1), /* "1"b if this CPU is to grap mask in idle loop */ 7 41 2 delete_cpu bit (1), /* "1"b if this CPU is to delete itself */ 7 42 2 interrupt_cpu bit (1), /* "1"b if this CPU takes hardware interrupts */ 7 43 2 halted_cpu bit (1), /* "1"b if this CPU has stopped itself (going to BOS) */ 7 44 2 cpu_type fixed bin (2) unsigned, /* 0 => DPS or L68, 1 => DPS8 */ 7 45 2 mbz1 bit (6), 7 46 2 cache_size fixed bin (3) unsigned, /* 0 = No cache; 1 = L68 2K cache; 7 47* 2 = DPS8 8K cache; 3 = DPS8 VS&SC 8K cache; 7 48* 4 = DPS8 VS&SC 16K cache; 5 = DPS8 VS&SC 32K cache 7 49* 7 = ignore cache size (set by ISOLTS reconfig) */ 7 50 2 mbz2 bit (12), 7 51 2 expanded_port bit (1), /* "1"b = on expanded port */ 7 52 2 expander_port fixed bin (2) unsigned, /* The actual expander port */ 7 53 2 controller_port fixed bin (3) unsigned 7 54 ) unaligned; /* Port on controller */ 7 55 7 56 dcl 1 scs$port_data (0:7) aligned external static, /* Info about what is connected to each SCU port */ 7 57 2 assigned fixed bin (4) unsigned unaligned, /* Type of device on this port */ 7 58 2 expander_port bit (1) unaligned, /* "1"b => this port has a port expander */ 7 59 2 expanded_cpu (0:3) bit (1) unaligned, /* "1"b => this expander port has a CPU attached */ 7 60 2 iom_number fixed bin (3) unsigned unaligned, /* IOM number of IOM attached to this port */ 7 61 2 cpu_number (0:3) fixed bin (3) unsigned unaligned, /* CPU number of CPU(s) attached to this port */ 7 62 /* cpu_number (0) is only one if expander_port is "0"b */ 7 63 2 pad bit (12) unaligned; 7 64 7 65 dcl 1 scs$cow (0:7) aligned external, /* Actual connect words */ 7 66 2 pad bit (36) aligned, /* Expander COW's must be odd-word */ 7 67 2 cow, 7 68 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 7 69 3 mbz1 bit (13) unaligned, 7 70 3 expander_command bit (3) unaligned, /* Expander command. */ 7 71 3 mbz2 bit (2) unaligned, 7 72 3 expanded_port bit (1) unaligned, /* "1"b = on expanded port */ 7 73 3 expander_port fixed bin (3) unsigned unaligned, /* Port on expander for cioc */ 7 74 3 mbz3 bit (3) unaligned, 7 75 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 7 76 7 77 dcl 1 scs$cow_ptrs (0:7) external aligned, /* Pointers to COW's */ 7 78 2 rel_cow_ptr bit (18) unal, /* Relative pointer to COW */ 7 79 2 pad bit (12) unal, 7 80 2 tag bit (6) unal; /* Better be zero. */ 7 81 7 82 dcl 1 scs$reconfig_general_cow aligned external, /* Used during reconfig ops. */ 7 83 2 pad bit (36) aligned, 7 84 2 cow, /* Connect operand word, in odd location. */ 7 85 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 7 86 3 mbz1 bit (13) unaligned, 7 87 3 expander_command bit (3) unaligned, /* Expander command. */ 7 88 3 mbz2 bit (9) unaligned, 7 89 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 7 90 7 91 /* MASKS and PATTERNS */ 7 92 7 93 dcl scs$sys_level bit (72) aligned ext; /* mask used while handling I/O interrupts */ 7 94 dcl scs$open_level bit (72) aligned ext; /* mask used during normal operation */ 7 95 dcl scs$processor_start_mask bit (72) aligned ext; /* mask used when starting up a CPU */ 7 96 dcl scs$cpu_test_mask bit (72) aligned ext; /* mask used for ISOLTS CPU testing */ 7 97 dcl scs$number_of_masks fixed bin ext; /* number of masks (starting at sys_level) */ 7 98 dcl scs$processor_start_pattern bit (36) aligned ext; /* SMIC pattern used to send processor start interrupt */ 7 99 dcl scs$cpu_test_pattern bit (36) aligned ext; /* SMIC pattern used for ISOLTS processor testing */ 7 100 7 101 /* CAM and CACHE clear info */ 7 102 7 103 dcl scs$cam_pair fixed bin (71) ext; /* instructions XEDd when CAMing and clearing CACHE */ 7 104 dcl scs$cam_wait bit (8) aligned ext; /* Used when evicting pages from main memory */ 7 105 7 106 /* MASKING INSTRUCTIONS & POINTERS */ 7 107 7 108 dcl scs$set_mask (0:7) bit (36) aligned ext; /* instructions to set mask (STAQ or SMCM) */ 7 109 dcl scs$read_mask (0:7) bit (36) aligned ext; /* instructions to read mask (LDAQ or RMCM) */ 7 110 dcl scs$mask_ptr (0:7) ptr unaligned ext; /* pointers for real or simulated masks */ 7 111 7 112 /* MISCELLANEOUS */ 7 113 7 114 dcl 1 scs$processor_test_data aligned ext, /* info used for cpu testing */ 7 115 ( 7 116 2 active bit (1), /* = "1"b if cpu currently under test */ 7 117 2 scu_state bit (2), /* state of scu being used for testing (see definition below) */ 7 118 2 pad1 bit (4), 7 119 2 req_mem fixed bin (10), /* dedicated memory required to test this cpu */ 7 120 2 cpu_tag fixed bin (5), /* tag of cpu under test */ 7 121 2 scu_tag fixed bin (5), /* tag of scu being used for cpu testing */ 7 122 2 mask_cpu fixed bin (5) 7 123 ) unaligned; /* tag of active cpu that has mask asigned to above scu */ 7 124 7 125 /* scu_state = "00"b => SCU defined by scs$processor_test_data.scu_tag not yet effected */ 7 126 /* scu_state = "01"b => all core removed from SCU, port mask not yet changed */ 7 127 /* scu_state = "10"b => all core removed from SCU, port mask changed */ 7 128 /* scu_state = "11"b => only 64k at base of SCU being used for testing, original port mask restored */ 7 129 7 130 dcl scs$idle_aptep (0:7) ptr unaligned ext; /* pointer to idle process APTE for each processor */ 7 131 7 132 dcl scs$connect_lock bit (36) aligned ext; /* lock for sending connects */ 7 133 dcl scs$reconfig_lock bit (36) aligned ext; /* Lock used during reconfiguration */ 7 134 dcl scs$trouble_flags bit (8) aligned ext; /* checkoff flags for sys_trouble stopping */ 7 135 dcl scs$bos_restart_flags bit (8) aligned ext; /* checkoff flags for restarting after sys_trouble */ 7 136 dcl scs$nprocessors fixed bin ext; /* number of runnung processors */ 7 137 dcl scs$bos_processor_tag fixed bin (3) ext; /* CPU tag of processor running BOS */ 7 138 dcl scs$faults_initialized bit (1) aligned ext; /* ON after faults have been enabled */ 7 139 dcl scs$sys_trouble_pending bit (1) aligned ext; /* sys_trouble event is pending in the system */ 7 140 dcl scs$fast_cam_pending (0:7) bit (36) aligned ext; /* checkoff cells for cam connect */ 7 141 dcl scs$interrupt_controller fixed bin (3) ext; /* port number of low order controller */ 7 142 dcl scs$processor_start_int_no fixed bin (5) ext; /* interrupt cell for starting a processor */ 7 143 dcl scs$processor bit (8) aligned ext; /* bits ON for online CPUs */ 7 144 dcl scs$processor_start_wait bit (8) aligned ext; /* checkoff flags for waiting for new processor */ 7 145 7 146 dcl scs$trouble_dbrs (0:7) fixed bin (71); /* DBR values at system crash time */ 7 147 7 148 dcl scs$port_addressing_word (0:7) bit (3) aligned ext; /* active module port number for each controller */ 7 149 7 150 dcl scs$cfg_data (0:7) fixed bin (71) aligned ext; /* RSCR-CFG data from each controller */ 7 151 7 152 dcl scs$cfg_data_save fixed bin (71) aligned ext; /* RSCR-CFG save area for ISOLTS CPU testing */ 7 153 7 154 dcl scs$expanded_ports bit (1) unaligned dim (0:7) external; 7 155 /* Which ports have expanders */ 7 156 7 157 dcl scs$processor_switch_data (0:4) bit (36) aligned ext; /* raw data from RSW 0 thru 4 */ 7 158 dcl scs$processor_switch_template (0:4) bit (36) aligned ext; /* expected data from RSW 0 thru 4 */ 7 159 dcl scs$processor_switch_compare (0:4) bit (36) aligned ext; /* discrepancies from expected data */ 7 160 dcl scs$processor_switch_mask (0:4) bit (36) aligned ext; /* masks for comparing switch data */ 7 161 7 162 dcl scs$processor_data_switch_value bit (36) aligned ext; /* Correct value for CPU data switches */ 7 163 7 164 dcl scs$controller_config_size (0:7) fixed bin (14) aligned ext; 7 165 /* Controller size on config card */ 7 166 7 167 dcl scs$reconfig_locker_id char (32) aligned ext; /* process group ID of process doing reconfiguration */ 7 168 7 169 dcl scs$scas_page_table (0:31) bit (36) aligned external static; 7 170 /* PTWs for SCAS pages */ 7 171 7 172 dcl scs$cycle_priority_template bit (7) aligned ext; /* template for setting anti-hog switches */ 7 173 dcl scs$set_cycle_switches bit (1) aligned ext; /* flag to set ant-hog switches */ 7 174 7 175 7 176 dcl ( 7 177 IOM_PORT init (1), 7 178 CPU_PORT init (2), 7 179 BULK_PORT init (3) 7 180 ) fixed bin int static options (constant); /* values for scs$port_data.assigned */ 7 181 7 182 7 183 /* END INCLUDE FILE scs.incl.pl1 */ 637 638 /* BEGIN INCLUDE FILE slt.incl.pl1 --- Last modified 2/76 SHW */ 8 2 8 3 /* Declarations for Segment Loading Table header and array. 8 4* 8 5* Used by Initialization and MST Checker subroutines */ 8 6 8 7 dcl sltp ptr, /* pointer to base of SLT segment */ 8 8 names_ptr ptr, /* pointer to base of SLT names segment */ 8 9 namep ptr, /* pointer to segment name list block */ 8 10 pathp ptr, /* pointer to segment's directory path name */ 8 11 aclp ptr; /* pointer to acl structure */ 8 12 8 13 declare 1 slt based (sltp) aligned, /* declaration of Segment Loading Table (SLT) */ 8 14 2 name_seg_ptr ptr, /* words 0-1, pointer (ITS pair) to name segment */ 8 15 2 free_core_start fixed bin (24), /* word 2, start of free core after perm-wired */ 8 16 2 first_sup_seg fixed bin (18), /* word 3, first supervisor segment number */ 8 17 2 last_sup_seg fixed bin (18), /* word 4, last supervisor segment number */ 8 18 2 first_init_seg fixed bin (18), /* word 5, first initializer segment number */ 8 19 2 last_init_seg fixed bin (18), /* word 6, last initializer segment number */ 8 20 2 free_core_size fixed bin (24), /* size (in words) of free core after perm-wired */ 8 21 2 seg (0:8191) aligned, /* segment entries (4 words each) */ 8 22 3 slte (4) fixed bin (35); /* Space for SLT entries */ 8 23 8 24 /* auxiliary segment of SLT for storing of segment names and directory path names */ 8 25 8 26 declare 1 name_seg based (names_ptr) aligned, /* name segment header */ 8 27 2 pad bit (18) unal, 8 28 2 next_loc bit (18) unal, /* Next available free location in name seg */ 8 29 2 ht (0:127) bit (18) aligned; /* Names hash table */ 8 30 8 31 declare 1 segnam based (namep) aligned, /* declaration for segment name block */ 8 32 2 count fixed bin (17), /* number of segment names in this block */ 8 33 2 names (50 refer (segnam.count)), /* segment name array */ 8 34 3 hp bit (18) unal, /* hash thread pointer */ 8 35 3 ref bit (1) unal, /* "1"b if name referenced */ 8 36 3 pad bit (5) unal, 8 37 3 segno bit (12) unal, /* segment number associated with this name */ 8 38 3 name char (32) unal; /* space for name (max 32 characters) */ 8 39 8 40 declare 1 path based (pathp) aligned, /* declaration for directory path name */ 8 41 2 size fixed bin (17), /* length of pathname */ 8 42 2 name char (168 refer (path.size)) unal, /* directory path name */ 8 43 2 acls fixed bin; /* ACL list starts here */ 8 44 8 45 declare 1 acls based (aclp) aligned, /* declaration for acl list */ 8 46 2 count fixed bin, /* number of entries in acl list */ 8 47 2 acl (50 refer (acls.count)), /* array of acl entries */ 8 48 3 userid char (32), /* user specification */ 8 49 3 mode bit (36) aligned, /* mode for the specified user */ 8 50 3 pad bit (36) aligned, 8 51 3 code fixed bin; 8 52 8 53 8 54 /* END INCLUDE FILE slt.incl.pl1 */ 638 639 /* BEGIN INCLUDE FILE slte.incl.pl1 */ 9 2 /* Declaration for Segment Loading Table Entry structure. 9 3* Used by Initialization, MST Generation, and MST Checker subroutines */ 9 4 /* modified 5/4/76 by Noel I. Morris */ 9 5 /* last modified 12/12/83 by Keith Loepere for breakpointable */ 9 6 /* format: style3 */ 9 7 9 8 dcl sltep ptr; 9 9 9 10 dcl 1 slte_uns based (sltep) aligned, 9 11 ( 2 names_ptr bit (18), /* rel pointer to thread of names */ 9 12 2 path_ptr bit (18), /* rel pointer to pathname (if present) */ 9 13 /**** End of word 1 */ 9 14 2 access bit (4), /* SDW access bit (REWP) */ 9 15 2 cache bit (1), /* Segment to be allowed in cache */ 9 16 2 abs_seg bit (1), /* segment is an abs seg if ON */ 9 17 2 firmware_seg bit (1), /* load in low 256 */ 9 18 2 layout_seg bit (1), /* mailbox & such */ 9 19 2 breakpointable bit (1), /* includes breakpoint_page */ 9 20 2 pad1 bit (3), /* unused */ 9 21 2 wired bit (1), /* segment is wired if ON */ 9 22 2 paged bit (1), /* segment is paged if ON */ 9 23 2 per_process bit (1), /* segment is per-process if ON */ 9 24 2 pad3 bit (2), 9 25 2 acl_provided bit (1), /* ON if acl structure follows path_name on MST */ 9 26 /**** End of 1st half of word 2 */ 9 27 2 pad4 bit (3), 9 28 2 branch_required bit (1), /* path name supplied if ON */ 9 29 2 init_seg bit (1), /* segment is init_seg if ON */ 9 30 2 temp_seg bit (1), /* segment is temp_seg if ON */ 9 31 2 link_provided bit (1), /* linkage segment provided if ON */ 9 32 2 link_sect bit (1), /* segment is linkage segment if ON */ 9 33 2 link_sect_wired bit (1), /* linkage segment is wired if ON */ 9 34 2 combine_link bit (1), /* linkage is combined if ON */ 9 35 2 pre_linked bit (1), /* lot entry has been made if ON */ 9 36 2 defs bit (1), /* segment is definitions segment if ON */ 9 37 /***** End of word 2 */ 9 38 2 pad5 bit (6), 9 39 2 cur_length fixed bin (9) uns, /* current length of segment (in 1024 word blocks) */ 9 40 2 ringbrack (3) fixed bin (3) uns, /* ringbrackets */ 9 41 2 segno fixed bin (18) uns, /* text/link segment number */ 9 42 /***** End of word 3 */ 9 43 2 pad7 bit (3), 9 44 2 max_length fixed bin (9) uns, /* maximum length for segment */ 9 45 2 bit_count fixed bin (24) uns 9 46 ) unaligned; /* bitcount of segment */ 9 47 9 48 dcl 1 slte based (sltep) aligned, 9 49 ( 2 names_ptr bit (18), /* rel pointer to thread of names */ 9 50 2 path_ptr bit (18), /* rel pointer to pathname (if present) */ 9 51 2 access bit (4), /* SDW access bit (REWP) */ 9 52 2 cache bit (1), /* Segment to be allowed in cache */ 9 53 2 abs_seg bit (1), /* segment is an abs seg if ON */ 9 54 2 firmware_seg bit (1), 9 55 2 layout_seg bit (1), 9 56 2 breakpointable bit (1), 9 57 2 pad2 bit (3), 9 58 2 wired bit (1), /* segment is wired if ON */ 9 59 2 paged bit (1), /* segment is paged if ON */ 9 60 2 per_process bit (1), /* segment is per-process if ON */ 9 61 2 pad3 bit (2), 9 62 2 acl_provided bit (1), /* ON if acl structure follows path_name on MST */ 9 63 2 pad4 bit (3), 9 64 2 branch_required bit (1), /* path name supplied if ON */ 9 65 2 init_seg bit (1), /* segment is init_seg if ON */ 9 66 2 temp_seg bit (1), /* segment is temp_seg if ON */ 9 67 2 link_provided bit (1), /* linkage segment provided if ON */ 9 68 2 link_sect bit (1), /* segment is linkage segment if ON */ 9 69 2 link_sect_wired bit (1), /* linkage segment is wired if ON */ 9 70 2 combine_link bit (1), /* linkage is combined if ON */ 9 71 2 pre_linked bit (1), /* lot entry has been made if ON */ 9 72 2 defs bit (1), /* segment is definitions segment if ON */ 9 73 2 pad5 bit (6), 9 74 2 cur_length bit (9), /* current length of segment (in 1024 word blocks) */ 9 75 2 ringbrack (3) bit (3), /* ringbrackets */ 9 76 2 segno bit (18), /* text/link segment number */ 9 77 2 pad6 bit (3), 9 78 2 max_length bit (9), /* maximum length for segment */ 9 79 2 bit_count bit (24) 9 80 ) unaligned; /* bitcount of segment */ 9 81 9 82 /* END INCLUDE FILE slte.incl.pl1 */ 639 640 /* BEGIN INCLUDE FILE ... config_cpu_card.incl.pl1 ... 11/27/80 W. Olin Sibert */ 10 2 /* format: style4 */ 10 3 10 4 dcl cpu_cardp pointer; /* pointer to CPU card */ 10 5 10 6 dcl 1 cpu_card aligned based (cpu_cardp), /* CPU card declaration */ 10 7 2 word char (4), /* "cpu" */ 10 8 2 tag fixed bin (3), /* CPU tag from switches, plus one */ 10 9 2 port fixed bin (3), /* Controller port for CPU */ 10 10 2 state char (4), /* "on", "off", "shut", or "test" */ 10 11 2 type char (4), /* "l68", "dps", "dps8" */ 10 12 10 13 2 model fixed bin, /* 60., 80., or 70. */ 10 14 2 cache_size fixed bin, /* either 0. 2. 8. 16. or 32. */ 10 15 2 expander_port fixed bin (3), /* If present, indicates expander sub-port */ 10 16 10 17 2 pad (7) bit (36) aligned, /* Pad to 15 fields */ 10 18 10 19 2 type_word aligned, 10 20 3 field_type (14) bit (2) unaligned, /* type of each field; see config_deck.incl.pl1 */ 10 21 3 pad1 bit (4) unaligned, 10 22 3 n_fields fixed bin (4) unsigned unaligned; /* number of fields used on card */ 10 23 10 24 dcl CPU_CARD_WORD char (4) aligned internal static options (constant) init ("cpu"); 10 25 10 26 /* END INCLUDE FILE ... config_cpu_card.incl.pl1 */ 640 641 /* BEGIN INCLUDE FILE ... config_schd_card.incl.pl1 ... 11/27/80 W. Olin Sibert */ 11 2 11 3 dcl schd_cardp pointer; /* pointer to SCHD card */ 11 4 11 5 dcl 1 schd_card aligned based (schd_cardp), /* SCHD card declaration */ 11 6 2 word char (4), /* "schd" */ 11 7 2 ws_factor fixed bin (35, 18), /* Working Set Factor */ 11 8 2 tefirst fixed bin, /* tefirst (in 1/8 second units) */ 11 9 2 telast fixed bin, /* telast (in 1/8 second units) */ 11 10 2 timax fixed bin, /* timax (in 1/8 second units) */ 11 11 11 12 2 min_eligible fixed bin, /* minimum number of eligible processes */ 11 13 2 max_eligible fixed bin, /* maximum number of eligible processes */ 11 14 2 max_max_eligible fixed bin, /* upper limit on max_eligible -- # of stack_0 segments */ 11 15 11 16 2 pad (7) bit (36) aligned, /* Pad to 15 fields */ 11 17 11 18 2 type_word aligned, 11 19 3 field_type (14) bit (2) unaligned, /* type of each field; see config_deck.incl.pl1 */ 11 20 3 pad1 bit (4) unaligned, 11 21 3 n_fields fixed bin (4) unsigned unaligned; /* number of fields used on card */ 11 22 11 23 dcl SCHD_CARD_WORD char (4) aligned internal static options (constant) init ("schd"); 11 24 11 25 /* END INCLUDE FILE ... config_schd_card.incl.pl1 */ 641 642 /* BEGIN INCLUDE FILE ... config_tcd_card.incl.pl1 ... 11/27/80 W. Olin Sibert */ 12 2 12 3 dcl tcd_cardp pointer; /* pointer to TCD card */ 12 4 12 5 dcl 1 tcd_card aligned based (tcd_cardp), /* TCD card declaration */ 12 6 2 word char (4), /* "tcd" */ 12 7 2 no_apt fixed bin, /* Number of APT entries */ 12 8 2 no_itt fixed bin, /* Number of ITT entries */ 12 9 12 10 2 pad (12) bit (36) aligned, /* Pad to 15 fields */ 12 11 12 12 2 type_word aligned, 12 13 3 field_type (14) bit (2) unaligned, /* type of each field; see config_deck.incl.pl1 */ 12 14 3 pad1 bit (4) unaligned, 12 15 3 n_fields fixed bin (4) unsigned unaligned; /* number of fields used on card */ 12 16 12 17 dcl TCD_CARD_WORD char (4) aligned internal static options (constant) init ("tcd"); 12 18 12 19 /* END INCLUDE FILE ... config_tcd_card.incl.pl1 */ 642 643 /* BEGIN INCLUDE FILE syserr_constants.incl.pl1 ... 11/11/80 W. Olin Sibert */ 13 2 /* 85-02-12, EJ Sharpe - Added sorting class constants, removed AIM_MESSAGE, added new action code names. */ 13 3 /* 85-04-24, G. Palter - Renamed SYSERR_UNUSED_10 to SYSERR_RING1_ERROR to reflect its actual use. */ 13 4 13 5 /* This include file has an ALM version. Keep 'em in sync! */ 13 6 13 7 dcl ( 13 8 13 9 /* The following constants define the message action codes. This indicates 13 10*how a message is to be handled. */ 13 11 13 12 SYSERR_CRASH_SYSTEM init (1), 13 13 CRASH init (1), /* Crash the system, and bleat plaintively. */ 13 14 13 15 SYSERR_TERMINATE_PROCESS init (2), 13 16 TERMINATE_PROCESS init (2), /* Terminate the process, print the message, and beep. */ 13 17 13 18 SYSERR_PRINT_WITH_ALARM init (3), 13 19 BEEP init (3), /* Beep and print the message on the console. */ 13 20 13 21 SYSERR_PRINT_ON_CONSOLE init (0), 13 22 ANNOUNCE init (0), /* Just print the message on the console. */ 13 23 13 24 SYSERR_LOG_OR_PRINT init (4), 13 25 LOG init (4), /* Log the message, or print it if it can't be logged */ 13 26 13 27 SYSERR_LOG_OR_DISCARD init (5), 13 28 JUST_LOG init (5), /* Just try to log the message, and discard it if it can't be */ 13 29 13 30 13 31 /* The following constants are added to the normal severities to indicate 13 32*different sorting classes of messages. */ 13 33 13 34 SYSERR_SYSTEM_ERROR init (00), /* indicates a standard level system error */ 13 35 SYSERR_RING1_ERROR init (10), /* indicates an error detected in ring 1 (mseg_, RCP) */ 13 36 SYSERR_COVERT_CHANNEL init (20), /* indicates covert channel audit trail message */ 13 37 SYSERR_UNSUCCESSFUL_ACCESS init (30), /* indicates access denial audit trail message */ 13 38 SYSERR_SUCCESSFUL_ACCESS init (40) /* indicates access grant audit trail message */ 13 39 ) fixed bin internal static options (constant); 13 40 13 41 /* END INCLUDE FILE syserr_constants.incl.pl1 */ 643 644 /* BEGIN INCLUDE FILE ... system_types.incl.pl1 ... 03/23/81 ... W. Olin Sibert */ 14 2 14 3 dcl L68_SYSTEM fixed bin (17) internal static options (constant) init (1); 14 4 dcl ADP_SYSTEM fixed bin (17) internal static options (constant) init (2); 14 5 14 6 dcl SYSTEM_TYPE_NAME (2) char (8) internal static options (constant) init 14 7 ("Level68", "ADP"); 14 8 14 9 /* END INCLUDE FILE ... system_types.incl.pl1 */ 644 645 /* *********************************************************** 15 2* * * 15 3* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 15 4* * * 15 5* *********************************************************** */ 15 6 /* Begin include file ...... rsw.incl.pl1 15 7* Modified 3/26/77 by Noel I. Morris 15 8* Modified 9/03/80 by J. A. Bush for the DPS8/70M CPU 15 9* Modified 3/24/82 by J. A. Bush to allow the L68 CPU to address 4MW/port */ 15 10 15 11 dcl rswp ptr; 15 12 15 13 dcl 1 dps_rsw_2 aligned based (rswp), /* rsw 2 template for DPS and L68 CPUs */ 15 14 (2 pad1 bit (4), 15 15 2 cpu_type fixed bin (2) unsigned, /* 0 = L68 or DPS, 1 = DPS8 */ 15 16 2 fault_base bit (7), /* high order bits of fault vector */ 15 17 2 pad2 bit (6), 15 18 2 dps_option bit (1), /* "1"b => DPS CPU, "0"b => L68 CPU */ 15 19 2 pad3 bit (7), 15 20 2 cache2 bit (1), /* "1"b => 2k cache installed, "0"b => no cache */ 15 21 2 ext_gcos bit (1), /* "1"b => ext gcos option installed */ 15 22 2 id bit (4), /* CPU ID - "1110"b => L68 */ 15 23 2 cpu_num fixed bin (3) unsigned) unaligned; /* processor number */ 15 24 15 25 dcl 1 dps8_rsw_2 aligned based (rswp), /* rsw 2 template for DPS8 CPUs */ 15 26 (2 interlace_info (0:3) bit (1), /* if interlace enabled; "0"b => 4-word, "1"b => 2-word */ 15 27 2 cpu_type fixed bin (2) unsigned, /* 0 = L68 or DPS, 1 = DPS8 */ 15 28 2 fault_base bit (7), /* high order bits of fault vector */ 15 29 2 id_prom bit (1), /* "1"b => id_prom present */ 15 30 2 pad1 bit (5), 15 31 2 dps_option bit (1), /* always "1"b for DPS8 CPU */ 15 32 2 cache8 bit (1), /* "1"b => 8k cache installed, "0"b => no cache */ 15 33 2 pad2 bit (2), 15 34 2 multics_cpu bit (1), /* always "1"b for Multics cpu */ 15 35 2 pad3 bit (5), 15 36 2 cpu_speed bit (4), /* cpu speed options */ 15 37 2 cpu_num fixed bin (3) unsigned) unaligned; /* processor number */ 15 38 15 39 dcl 1 rsw_1_3 aligned based (rswp), /* rsw 3 only valid on DPS and L68 CPUs */ 15 40 (2 port_info (0:3), /* controller port information */ 15 41 3 port_assignment bit (3), /* port address assignment */ 15 42 3 port_enable bit (1), /* "1"b => port enabled */ 15 43 3 initialize_enable bit (1), /* "1"b => system initialize enabled */ 15 44 3 interlace_enable bit (1), /* "1"b => port is interlaced with neighbor */ 15 45 3 mem_size fixed bin (3) unsigned) unaligned; /* encoded memory size on port */ 15 46 15 47 dcl 1 rsw_4 aligned based (rswp), /* rsw 4 only valid on DPS and L68 CPUs */ 15 48 (2 pad1 bit (13), 15 49 2 port_info (0:7), /* additional controller port information */ 15 50 3 four bit (1), /* "0"b => 4-word interlace - "1"b => 2-word interlace */ 15 51 3 half bit (1), /* "1"b => only half of memory on controller in use */ 15 52 2 pad2 bit (7)) unaligned; 15 53 15 54 dcl dps_mem_size_table (0:7) fixed bin (24) static options (constant) init /* DPS and L68 memory sizes */ 15 55 (32768, 65536, 4194304, 131072, 524288, 1048576, 2097152, 262144); 15 56 15 57 /* Note that the third array element above, is changed incompatibly in MR10.0. 15 58* In previous releases, this array element was used to decode a port size of 15 59* 98304 (96K). With MR10.0 it is now possible to address 4MW per CPU port, by 15 60* installing FCO # PHAF183 and using a group 10 patch plug, on L68 and DPS CPUs. 15 61**/ 15 62 15 63 dcl dps8_mem_size_table (0:7) fixed bin (24) static options (constant) init /* DPS8 memory sizes */ 15 64 (32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304); 15 65 15 66 dcl rsw_valid (0:1) fixed bin static options (constant) init (5, 3); /* # of rsw valid per cpu type */ 15 67 15 68 /* End of include file ...... rsw.incl.pl1 */ 645 646 647 648 /* BEGIN MESSAGE DOCUMENTATION 649* 650* Message: 651* tc_init: No valid processor tags on CPU cards. 652* 653* S: $crash 654* 655* T: $init 656* 657* M: No CPU CONFIG cards contained valid (A - H) CPU tags. Normally this message will 658* not appear if the bootload CPU is mis-specified, as this error will be detected by 659* scas_init, and thus this may be indicative of a supervisor logic problem. 660* 661* A: Check that all CPU CONFIG cards are correct. If not, perform an emergency 662* shutdown, correct them, and reboot. If so, be sure to get a dump and contact 663* system programming personnel. 664* 665* Message: 666* tc_init: Cannot start up first idle process. Check switches. 667* 668* S: $crash 669* 670* T: $init 671* 672* M: The idle process for the bootload CPU could not be started. This may be 673* an error in setting of configuration switches, or may be indicative of a logic problem in the 674* supervisor. 675* 676* A: Perform an emergency shutdown. Check all main module configuration switches. 677* If a problem was corrected, reboot. Otherwise, be sure to get a dump and contact 678* the systems programming staff. 679* 680* Message: 681* tc_init: Could not rename prds to PRDSNAME. ERRORMESSAGE 682* 683* S: $info 684* 685* T: $init 686* 687* M: The segment "prds" in >system_library_1 could not be renamed to PRDSNAME, which 688* is the correct name for the PRDS for the bootload processor. 689* ERRORMESSAGE is a standard error_table_ message. 690* 691* A: Notify the system programming staff. Action should be taken by the programming staff to rename this 692* segment. If the problem cannot be sorted out, avoid reconfiguring the bootload 693* CPU during this bootload. 694* 695* Message: 696* tc_init: Could not delete old PRDSNAME. ERRORMESSAGE 697* 698* S: $info 699* 700* T: $init 701* 702* M: The old PRDS PRDSNAME from the previous bootload, in >system_library_1, could not 703* be deleted. When the CPU whose tag is part of PRDSNAME is added, the old PRDS will be used. 704* ERRORMESSAGE is a standard error_table_ message. 705* 706* A: $notify 707* 708* Message: 709* tc_init: Could not start CPU CPUTAG. 710* 711* S: $info 712* 713* T: $init 714* 715* M: The CPU whose tag is CPUTAG could not be automatically started by system bootload. 716* 717* A: Check all configuration switches on CPU and main memory modules, especially 718* the CPU STEP switch on the CPU which could not be added, and its port 719* enable switches. If all switches were correct, add the CPU via the addcpu command. 720* 721* Message: 722* tc_init: cannot create cpu_X.prds. This CPU may not be added. ERROR_MESSAGE 723* 724* S: $info 725* 726* T: $init 727* 728* M: A difficulty was encountered in creating the PRDS for a configurable CPU. 729* Later attempts to add this CPU will fail. It will be marked as "off" in the CONFIG deck. 730* 731* A: $inform 732* When the problem has been remedied, shut down and reboot, and then add this CPU. 733* 734* Message: 735* tc_init: Inconsistent SCHD config card values. 736* 737* S: $crash 738* 739* T: $init 740* 741* M: The SCHD config card is not in the correct format, or some values 742* are out of acceptable range. In particular, the value of min_eligible 743* cannot exceed that of max_eligible; also, the value of max_eligible plus 744* the max number of stopped stack_0's (default = 4) cannot exceed 745* max_max_eligible. 746* 747* A: Check the SCHD config card (refer to the MOH) and correct. Re-boot the 748* system. 749* 750* Message: 751* tc_init: Size of PRDS on TBLS card too small; XXX KW will be used. 752* 753* S: $info 754* 755* T: $init 756* 757* M: The size of the PRDS specified on the TBLS card in the Configuration Deck 758* is smaller than the size of the PRDS defined in the MST header. The size of 759* the PRDS will be that defined in the MST header. Further, the TBLS card in 760* the Configuration Deck has been changed to reflect the minimum size of the 761* PRDS 762* 763* Message: 764* CPU CPUTAG: Model #: MODEL; Serial #: SERIAL; Ship date: YY/MM/DD. 765* 766* S: $log 767* 768* T: When the bootload CPU is a DPS8, whose tag is CPUTAG is "added" to 769* the system. 770* 771* M: The MODEL, SERIAL and YY/MM/DD information is read from the DPS8 cpu's ID PROM. 772* It is intended to be used as historical information 773* for identifing CPUs, regardless of what their current tag is assigned as. 774* 775* A: $ignore 776* 777* 778* END MESSAGE DOCUMENTATION */ 779 780 781 end tc_init; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/11/89 0800.0 tc_init.pl1 >spec>install>1110>tc_init.pl1 631 1 10/25/79 0712.2 stack_0_data.incl.pl1 >ldd>include>stack_0_data.incl.pl1 632 2 07/11/84 0937.3 sys_trace.incl.pl1 >ldd>include>sys_trace.incl.pl1 633 3 01/06/85 1422.2 apte.incl.pl1 >ldd>include>apte.incl.pl1 634 4 03/27/82 0430.3 sdw_info.incl.pl1 >ldd>include>sdw_info.incl.pl1 635 5 01/30/85 1523.9 tcm.incl.pl1 >ldd>include>tcm.incl.pl1 636 6 01/06/85 1422.1 hc_lock.incl.pl1 >ldd>include>hc_lock.incl.pl1 637 7 10/12/83 0943.5 scs.incl.pl1 >ldd>include>scs.incl.pl1 638 8 05/24/82 1005.0 slt.incl.pl1 >ldd>include>slt.incl.pl1 639 9 07/11/84 0937.3 slte.incl.pl1 >ldd>include>slte.incl.pl1 640 10 10/14/83 0957.2 config_cpu_card.incl.pl1 >ldd>include>config_cpu_card.incl.pl1 641 11 05/08/81 1853.7 config_schd_card.incl.pl1 >ldd>include>config_schd_card.incl.pl1 642 12 05/08/81 1853.7 config_tcd_card.incl.pl1 >ldd>include>config_tcd_card.incl.pl1 643 13 05/17/85 0615.7 syserr_constants.incl.pl1 >ldd>include>syserr_constants.incl.pl1 644 14 06/19/81 2115.0 system_types.incl.pl1 >ldd>include>system_types.incl.pl1 645 15 06/10/82 1045.2 rsw.incl.pl1 >ldd>include>rsw.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. ADP_SYSTEM constant fixed bin(17,0) initial dcl 14-4 ref 379 ANNOUNCE 000003 constant fixed bin(17,0) initial dcl 13-7 set ref 340* 584* 588* 611* 622* CPU_CARD_WORD 000002 constant char(4) initial dcl 10-24 set ref 593* CRASH 000054 constant fixed bin(17,0) initial dcl 13-7 set ref 519* LETTERS 000016 constant char(8) initial packed unaligned dcl 170 ref 577 603 PRDS_DIR 000006 constant char(32) initial packed unaligned dcl 171 set ref 578* 583* 604* 605* RW_mode 000051 constant fixed bin(5,0) initial dcl 172 set ref 604* SCHD_CARD_WORD 000001 constant char(4) initial dcl 11-23 set ref 309* TCD_CARD_WORD 000000 constant char(4) initial dcl 12-17 set ref 211* VCPU_RESPONSE_BOUNDS constant fixed bin(17,0) initial dcl 5-308 ref 202 202 202 202 247 247 247 247 247 247 247 247 247 247 247 247 248 248 248 248 249 249 249 249 250 250 250 250 251 251 251 251 252 252 252 252 253 253 253 253 254 254 254 254 255 255 255 255 256 256 256 256 257 257 257 257 258 258 258 258 259 259 259 259 266 267 268 269 269 271 271 273 274 275 275 275 275 276 276 276 276 278 279 279 279 279 329 331 498 508 abort_ips_mask based bit(36) level 2 dcl 5-11 set ref 331* active_all_rings_data$stack_base_segno 000106 external static fixed bin(18,0) dcl 131 ref 418 addr builtin function dcl 175 ref 185 187 188 190 192 193 194 197 197 199 199 202 233 233 247 278 279 286 296 298 335 335 353 356 356 393 393 394 394 404 408 412 419 433 433 436 440 441 442 442 443 443 443 445 447 448 461 464 536 536 536 536 542 542 542 542 558 addrel builtin function dcl 175 ref 440 441 442 443 445 447 448 address 000212 automatic fixed bin(26,0) level 2 dcl 533 set ref 538* 538 append$branchx 000032 constant entry external dcl 106 ref 604 apt based fixed bin(17,0) level 2 in structure "tcm" dcl 5-11 in procedure "tc_init" set ref 202 apt based structure array level 1 dcl 100 in procedure "tc_init" set ref 230 286 296 apt_size 313 based fixed bin(18,0) level 2 dcl 5-11 set ref 213 238* apte based structure level 1 dcl 3-7 aptep 000166 automatic pointer dcl 3-5 set ref 365* 366 369* 370 462* 463 466 467 468* 469 470 471 472 473 474 475 476 477 478 487 492 494* 495 aptp 000124 automatic pointer dcl 68 set ref 230 283* 284 286 286 287 289 296 aptx 000126 automatic fixed bin(17,0) dcl 69 set ref 285* 286 286 287* asteps 12 based structure level 2 packed packed unaligned dcl 3-7 base parameter fixed bin(24,0) dcl 529 ref 525 538 based_sentinel based structure level 1 dcl 5-303 baseno builtin function dcl 175 ref 189 191 192 193 194 419 443 464 baseptr builtin function dcl 175 ref 418 bin builtin function dcl 175 ref 189 192 193 194 202 408 471 binary builtin function dcl 175 ref 191 419 443 464 487 487 bit builtin function dcl 175 ref 471 487 bound parameter fixed bin(18,0) dcl 530 ref 525 541 bp based bit(18) array level 5 packed packed unaligned dcl 5-11 set ref 247* chname$cfile 000034 constant entry external dcl 109 ref 583 cid2 3 based fixed bin(18,0) level 2 dcl 5-11 set ref 302* cid3 4 based fixed bin(18,0) level 2 dcl 5-11 set ref 303* cid4 5 based fixed bin(18,0) level 2 dcl 5-11 set ref 304* clock builtin function dcl 175 ref 467 487 503 code 000136 automatic fixed bin(35,0) dcl 74 set ref 518* 519 578* 579 579 579* 581 583* 584 584* 588* 604* 605 605* 608 608* 610 611* 616* 621* 622 config_$find 000036 constant entry external dcl 110 ref 211 309 593 config_$find_table 000040 constant entry external dcl 111 ref 339 copy_dseg based fixed bin(71,0) array dcl 99 set ref 433* 433 copy_group_id based char(32) dcl 97 set ref 445* copy_id based bit(36) dcl 95 set ref 440* copy_pds based fixed bin(17,0) array dcl 98 set ref 437* 437 copy_ptr based pointer dcl 96 set ref 441* 442* 443* cpu_card based structure level 1 dcl 10-6 cpu_cardp 000174 automatic pointer dcl 10-4 set ref 591* 593* 595 597 613 618 622 622 625 cpu_model 000150 automatic char(13) dcl 77 set ref 562* 568* cpu_serial 000154 automatic char(13) dcl 78 set ref 564* 568* cpu_ship_date 000160 automatic char(8) dcl 79 set ref 566* 568* cpu_type 0(07) 000220 external static fixed bin(2,0) array level 2 packed packed unsigned unaligned dcl 7-35 ref 558 credits_per_scatter 412 based fixed bin(35,0) level 2 dcl 5-11 set ref 264* cur_length 2 based fixed bin(9,0) level 2 packed packed unsigned unaligned dcl 9-10 set ref 336 349* dbr 44 based fixed bin(71,0) level 2 dcl 3-7 set ref 452* 472* deadline 34 based fixed bin(71,0) level 2 dcl 3-7 set ref 467* define_wc_time 414 based fixed bin(71,0) level 2 dcl 5-11 set ref 510* defined based bit(1) array level 5 packed packed unaligned dcl 5-11 set ref 266* 275* delentry$dfile 000042 constant entry external dcl 112 ref 578 disk_polling_time 370 based fixed bin(71,0) level 2 dcl 5-11 set ref 506* divide builtin function dcl 175 ref 302 303 304 354 431 538 dps8_rsw_2 based structure level 1 dcl 15-25 dseg 12(18) based bit(18) level 3 packed packed unaligned dcl 3-7 set ref 478* dseg$ 000110 external static fixed bin(71,0) array dcl 132 set ref 193 196 199 199 419 433 443 464 472 dseg_no 000010 internal static fixed bin(17,0) dcl 82 set ref 193* 451 472 dseg_size 000030 internal static fixed bin(18,0) dcl 91 set ref 380* 385* 389 431 450 450* early_call 000100 automatic bit(1) dcl 53 set ref 178* 183* 205 eligible 1(06) based bit(1) level 3 packed packed unaligned dcl 3-7 set ref 470* eligible_q_head 350 based structure level 2 dcl 5-11 empty_q 346 based bit(18) level 2 dcl 5-11 set ref 284* error_table_$noentry 000112 external static fixed bin(35,0) dcl 133 ref 579 first_segno 000102 automatic fixed bin(17,0) dcl 55 set ref 431* 433 451 455 flags 1 based structure level 2 in structure "apte" packed packed unaligned dcl 3-7 in procedure "tc_init" flags based structure array level 4 in structure "tcm" packed packed unaligned dcl 5-11 in procedure "tc_init" fp based bit(18) array level 2 in structure "itt" packed packed unaligned dcl 101 in procedure "tc_init" set ref 298* 300* fp based bit(18) array level 5 in structure "tcm" packed packed unaligned dcl 5-11 in procedure "tc_init" set ref 247* fp based bit(18) array level 3 in structure "apt" packed packed unaligned dcl 100 in procedure "tc_init" set ref 286* fp 350 based bit(18) level 3 in structure "tcm" packed packed unaligned dcl 5-11 in procedure "tc_init" set ref 468* get_main 000046 constant entry external dcl 114 ref 232 355 389 391 get_ptrs_$given_segno 000050 constant entry external dcl 115 ref 477 495 getuid 000044 constant entry external dcl 113 ref 474 grab_aste$prewithdraw 000052 constant entry external dcl 116 ref 608 gv_integration based fixed bin(35,0) level 2 dcl 5-11 set ref 329* hbound builtin function dcl 175 ref 426 header based fixed bin(17,0) array dcl 94 set ref 234* 234 i 000120 automatic fixed bin(17,0) dcl 65 set ref 246* 247 247 247 248 249 250 251 252 253 254 255 256 257 258 259* 367* 368 370* 426* 428 440 441 445 452* 576* 577 582* 597* 602 603 608 614 618 621* id_prom 0(13) based bit(1) level 2 packed packed unaligned dcl 15-25 ref 558 idle_dsegs$ 000116 external static fixed bin(71,0) array dcl 135 set ref 188 433 451* 455* idle_dsegs_p 000024 internal static pointer dcl 89 set ref 188* 389* 393* idle_dsegs_sdw 000020 internal static fixed bin(71,0) dcl 87 set ref 389* 393 393 450* idle_pds_p 000122 automatic pointer dcl 67 set ref 436* 437 440 441 442 443 445 447 448 idle_pdses$ 000114 external static fixed bin(17,0) array dcl 134 set ref 187 436 idle_pdses_p 000026 internal static pointer dcl 90 set ref 187* 391* 394* idle_pdses_sdw 000022 internal static fixed bin(71,0) dcl 88 set ref 391* 394 394 454* init_processor$init 000054 constant entry external dcl 117 ref 516 init_processor$return 000056 constant entry external dcl 118 set ref 461 initialize_time 336 based fixed bin(71,0) level 2 dcl 5-11 set ref 509* initializer_id 323 based bit(36) level 2 dcl 5-11 set ref 465* initiate 000060 constant entry external dcl 119 ref 605 interactive_q based bit(1) array level 5 packed packed unaligned dcl 5-11 set ref 259* io_priority based bit(1) array level 5 packed packed unaligned dcl 5-11 set ref 258* 267* ipc_r_factor 65 based fixed bin(35,0) level 2 unsigned dcl 3-7 set ref 492* ipc_r_offset 64 based fixed bin(18,0) level 2 unsigned dcl 3-7 set ref 487* itt based structure array level 1 dcl 101 set ref 230 298 itt_free_list 321 based bit(18) level 2 dcl 5-11 set ref 301* itt_size 317 based fixed bin(18,0) level 2 dcl 5-11 set ref 214 239* ittp 000130 automatic pointer dcl 70 set ref 230 296* 298 298 300 301 ittx 000132 automatic fixed bin(17,0) dcl 71 set ref 297* 298 298* last_available 1 based fixed bin(17,0) level 2 packed packed unsigned unaligned dcl 2-7 set ref 447* lbound builtin function dcl 175 ref 426 loaded 1(05) based bit(1) level 3 packed packed unaligned dcl 3-7 set ref 469* lock based structure level 1 dcl 6-12 in procedure "tc_init" lock 36 based bit(18) array level 2 in structure "apt" packed packed unaligned dcl 100 in procedure "tc_init" set ref 287* 289* lock_id 15 based bit(36) level 2 dcl 3-7 set ref 474* 475 max builtin function dcl 175 ref 336 max_eligible 325 based fixed bin(30,0) level 2 in structure "tcm" dcl 5-11 in procedure "tc_init" set ref 316* 321 324 324 max_eligible 6 based fixed bin(17,0) level 2 in structure "schd_card" dcl 11-5 in procedure "tc_init" ref 316 316 316 max_length 3(03) based fixed bin(9,0) level 2 packed packed unsigned unaligned dcl 9-10 set ref 336 349* max_max_eligible 422 based fixed bin(30,0) level 2 in structure "tcm" dcl 5-11 in procedure "tc_init" set ref 319* 321* 324 354 max_max_eligible 7 based fixed bin(17,0) level 2 in structure "schd_card" dcl 11-5 in procedure "tc_init" ref 319 319 319 max_stopped_stack_0 423 based fixed bin(35,0) level 2 dcl 5-11 ref 324 max_wct_index 405 based bit(18) level 2 dcl 5-11 set ref 279* maxel based fixed bin(35,0) array level 4 dcl 5-11 set ref 255* min builtin function dcl 175 ref 344 min_eligible 356 based fixed bin(30,0) level 2 in structure "tcm" dcl 5-11 in procedure "tc_init" set ref 315* 316 324 min_eligible 5 based fixed bin(17,0) level 2 in structure "schd_card" dcl 11-5 in procedure "tc_init" ref 315 315 min_wct_index 404 based bit(18) level 2 dcl 5-11 set ref 278* 466 minf based fixed bin(35,0) array level 4 dcl 5-11 set ref 268* 276* mnbz based bit(1) array level 5 packed packed unaligned dcl 5-11 set ref 248* n_eligible 324 based fixed bin(18,0) level 2 dcl 5-11 set ref 502* n_words 000101 automatic fixed bin(18,0) dcl 54 set ref 202* 230 234 283 nel based fixed bin(35,0) array level 4 dcl 5-11 set ref 256* 498* new_sdw parameter fixed bin(71,0) dcl 531 set ref 525 542 542 next_alarm_time 362 based fixed bin(71,0) level 2 dcl 5-11 set ref 504* next_free based fixed bin(17,0) level 2 packed packed unsigned unaligned dcl 2-7 set ref 448* no_apt 1 based fixed bin(17,0) level 2 in structure "tcd_card" dcl 12-5 in procedure "tc_init" ref 217 no_apt 000106 automatic fixed bin(17,0) dcl 58 in procedure "tc_init" set ref 206* 213* 217* 230 238 285 289 291 296 302 303 304 no_itt 000107 automatic fixed bin(17,0) dcl 59 in procedure "tc_init" set ref 207* 214* 218* 230 239 297 300 302 303 304 no_itt 2 based fixed bin(17,0) level 2 in structure "tcd_card" dcl 12-5 in procedure "tc_init" ref 218 nto_check_time 146 based fixed bin(71,0) level 2 dcl 5-11 set ref 511* nto_delta 150 based fixed bin(35,0) level 2 dcl 5-11 set ref 512* null builtin function dcl 175 ref 210 212 308 310 421 423 591 595 607 614 616 num_stacks 1 based fixed bin(17,0) level 2 dcl 1-9 set ref 357* 358 359* offline 0(01) 000220 external static bit(1) array level 2 packed packed unaligned dcl 7-35 ref 368 428 old_sdw parameter fixed bin(71,0) dcl 528 set ref 525 536 536 opc_polling_time 366 based fixed bin(71,0) level 2 dcl 5-11 set ref 505* paged 1(13) based bit(1) level 2 packed packed unaligned dcl 9-48 set ref 197* pds 12 based bit(18) level 3 packed packed unaligned dcl 3-7 set ref 477* pds$ 000146 external static fixed bin(17,0) dcl 148 set ref 192 pds$apt_ptr 000150 external static pointer dcl 149 set ref 366* 441 462 pds$data 000152 external static fixed bin(17,0) dcl 150 set ref 408 pds$dstep 000156 external static bit(18) dcl 152 ref 478 pds$initial_procedure 000160 external static pointer dcl 153 set ref 461* pds$lock_id 000154 external static bit(36) dcl 151 set ref 475* pds$process_group_id 000162 external static char(32) packed unaligned dcl 154 set ref 445 604* pds$processid 000164 external static bit(36) dcl 155 set ref 440 463* 465 473 pds$stack_0_ptr 000166 external static pointer dcl 156 set ref 442 464 pds$stack_0_sdwp 000170 external static pointer dcl 157 set ref 443 464* pds$trace 000172 external static fixed bin(17,0) dcl 158 set ref 447 448 pds_no 000011 internal static fixed bin(17,0) dcl 83 set ref 192* 455 477* pds_size 000031 internal static fixed bin(18,0) dcl 92 set ref 381* 386* 391 436 437 454 454* pdscopyl 300 based fixed bin(18,0) level 2 dcl 5-11 set ref 410* pin_weight based fixed bin(35,0) array level 4 dcl 5-11 set ref 257* 273* pmut$swap_sdw 000062 constant entry external dcl 120 ref 199 233 356 393 394 prds 13 based bit(18) level 3 packed packed unaligned dcl 3-7 set ref 495* 608* prds$ 000120 external static fixed bin(17,0) dcl 136 set ref 194 442 443 prds$processor_tag 000122 external static fixed bin(3,0) dcl 137 ref 582 prds_length 302 based fixed bin(18,0) level 2 dcl 5-11 set ref 348* prds_length_kw 000147 automatic fixed bin(17,0) dcl 76 set ref 336* 340 340* 344* 348 349 prds_name 000137 automatic char(32) packed unaligned dcl 75 set ref 577* 578* 583* 584* 588* 603* 604* 605* 611* prds_no 000012 internal static fixed bin(17,0) dcl 84 set ref 194* 335 495* prdsp 000104 automatic pointer dcl 57 set ref 605* 607* 608* 616 616* privileged_mode_ut$read_id_prom 000064 constant entry external dcl 121 ref 562 564 566 processid 3 based bit(36) level 2 dcl 3-7 set ref 473* processor_index 000103 automatic fixed bin(17,0) dcl 56 set ref 425* 430* 430 431 436 450 454 ptr builtin function dcl 175 ref 283 purging based fixed bin(35,0) array level 4 dcl 5-11 set ref 254* pxss$get_entry 000066 constant entry external dcl 122 ref 365 369 quantum1 based fixed bin(35,0) array level 4 dcl 5-11 set ref 250* 271* quantum2 based fixed bin(35,0) array level 4 dcl 5-11 set ref 252* 271* realtime based fixed bin(35,0) array level 4 dcl 5-11 set ref 253* 274* rel builtin function dcl 175 ref 202 247 278 279 284 286 298 301 408 440 440 441 442 443 445 447 448 463 477 495 608 resp1 based fixed bin(71,0) array level 4 dcl 5-11 set ref 249* 269* resp2 based fixed bin(71,0) array level 4 dcl 5-11 set ref 251* 269* schd_card based structure level 1 dcl 11-5 schd_cardp 000176 automatic pointer dcl 11-3 set ref 308* 309* 310 311 312 313 314 315 315 316 316 316 319 319 319 scs$bos_processor_tag 000224 external static fixed bin(3,0) dcl 7-137 ref 203 scs$idle_aptep 000222 external static pointer array packed unaligned dcl 7-130 set ref 370* 440 441 452 494 608 614* scs$processor_data 000220 external static structure array level 1 dcl 7-35 ref 426 426 scs$processor_switch_data 000226 external static bit(36) array dcl 7-157 set ref 558 sdt based structure level 1 dcl 1-9 set ref 355 355 358* sdte based structure level 1 dcl 1-19 sdtp 000164 automatic pointer dcl 1-7 set ref 353* 355* 355 355 356* 357 358 359 sdw_info based structure level 1 dcl 4-6 sdw_util_$construct 000070 constant entry external dcl 123 ref 542 sdw_util_$dissect 000072 constant entry external dcl 124 ref 536 sdwi 000212 automatic structure level 1 dcl 533 set ref 536 536 542 542 seg 10 based structure array level 2 dcl 8-13 set ref 197 335 seg_rb 000003 constant fixed bin(17,0) initial array dcl 173 set ref 604* size builtin function dcl 175 in procedure "tc_init" ref 230 230 355 355 size 1 000212 automatic fixed bin(19,0) level 2 in structure "sdwi" dcl 533 in procedure "shrink_sdw" set ref 541* slt based structure level 1 dcl 8-13 slt$ 000124 external static fixed bin(17,0) dcl 138 set ref 197 335 slte based structure level 1 dcl 9-48 slte_uns based structure level 1 dcl 9-10 sltep 000172 automatic pointer dcl 9-8 set ref 335* 336 336 349 349 stack_0_data$ 000216 external static fixed bin(17,0) dcl 1-5 set ref 353 stack_0_data_init_number_of_stacks 000163 automatic fixed bin(17,0) dcl 1-6 set ref 354* 355 355 357 359 start_cpu 000074 constant entry external dcl 125 ref 518 621 stat 160 based fixed bin(18,0) array level 2 dcl 5-11 set ref 291* 497* state 1(18) based bit(18) level 3 in structure "apte" packed packed unaligned dcl 3-7 in procedure "tc_init" set ref 471* state 3 based char(4) level 2 in structure "cpu_card" dcl 10-6 in procedure "tc_init" set ref 613* 618 substr builtin function dcl 175 set ref 445* 445 487 568 568 577 603 622 622 sys_info$hfp_exponent_available 000126 external static bit(1) dcl 139 set ref 592* 625* sys_info$quit_mask 000130 external static bit(36) dcl 140 ref 331 sys_info$susp_mask 000132 external static bit(36) dcl 141 ref 331 sys_info$system_type 000136 external static fixed bin(17,0) dcl 143 ref 241 379 sys_info$term_mask 000134 external static bit(36) dcl 142 ref 331 syserr 000076 constant entry external dcl 126 ref 327 340 519 568 622 syserr$error_code 000100 constant entry external dcl 127 ref 584 588 611 system_type 157 based fixed bin(17,0) level 2 dcl 5-11 set ref 241* table_value 000162 automatic fixed bin(17,0) dcl 80 set ref 339* 340 340 344 344 tag 1 based fixed bin(3,0) level 2 in structure "cpu_card" dcl 10-6 in procedure "tc_init" ref 597 622 622 tag 000016 internal static fixed bin(17,0) dcl 86 in procedure "tc_init" set ref 203* 494 518* 558 568 568 602 618 tape_polling_time 372 based fixed bin(71,0) level 2 dcl 5-11 set ref 507* tc_data$ 000140 external static fixed bin(17,0) dcl 144 set ref 185 404 tc_data$prds_length 000142 external static fixed bin(19,0) dcl 145 set ref 608* tc_data_header$ 000144 external static fixed bin(17,0) dcl 146 set ref 190 tc_data_header_no 000112 automatic fixed bin(17,0) dcl 62 set ref 191* 196 tc_data_header_ptr 000114 automatic pointer dcl 63 set ref 190* 191 199* 213 214 234 tc_data_no 000111 automatic fixed bin(17,0) dcl 61 set ref 189* 197 199 199 tc_data_size 000110 automatic fixed bin(18,0) dcl 60 set ref 230* 232* tcd_card based structure level 1 dcl 12-5 tcd_cardp 000200 automatic pointer dcl 12-3 set ref 210* 211* 212 217 218 tcm based structure level 1 dcl 5-11 tcmp 000170 automatic pointer dcl 5-9 set ref 185* 189 202 232* 233* 234 238 239 241 247 247 247 248 249 250 251 252 253 254 255 256 257 258 259 264 266 267 268 269 269 271 271 273 274 275 276 278 278 279 279 283 284 291 295 301 302 303 304 311 312 313 314 315 316 316 319 321 321 324 324 324 324 324 329 329 331 348 354 404* 410 465 466 468 497 498 502 504 505 506 507 508 509 510 511 512 521 tefirst 343 based fixed bin(30,0) level 2 in structure "tcm" dcl 5-11 in procedure "tc_init" set ref 312* tefirst 2 based fixed bin(17,0) level 2 in structure "schd_card" dcl 11-5 in procedure "tc_init" ref 312 telast 344 based fixed bin(30,0) level 2 in structure "tcm" dcl 5-11 in procedure "tc_init" set ref 313* 329 telast 3 based fixed bin(17,0) level 2 in structure "schd_card" dcl 11-5 in procedure "tc_init" ref 313 template_pds$ 000174 external static fixed bin(17,0) dcl 160 set ref 412 template_pds$apt_ptr 000202 external static pointer dcl 163 set ref 421* template_pds$initial_procedure 000204 external static pointer dcl 164 set ref 423* template_pds$process_group_id 000206 external static char(32) packed unaligned dcl 165 set ref 422* template_pds$processid 000210 external static bit(36) dcl 166 set ref 420* template_pds$quota_inhib 000176 external static fixed bin(17,0) dcl 161 set ref 416* template_pds$save_history_regs 000200 external static bit(1) dcl 162 set ref 417* template_pds$stack_0_ptr 000214 external static pointer dcl 168 set ref 418* 419 template_pds$stack_0_sdwp 000212 external static pointer dcl 167 set ref 419* template_pds_p 000014 internal static pointer dcl 85 set ref 412* 437 template_pds_size 000121 automatic fixed bin(18,0) dcl 66 set ref 408* 410 terminate_$teseg 000102 constant entry external dcl 128 ref 616 thread based structure array level 2 in structure "apt" packed packed unaligned dcl 100 in procedure "tc_init" thread based structure array level 4 in structure "tcm" packed packed unaligned dcl 5-11 in procedure "tc_init" thread$cin 000104 constant entry external dcl 129 ref 468 timax 4 based fixed bin(17,0) level 2 in structure "schd_card" dcl 11-5 in procedure "tc_init" ref 314 timax 345 based fixed bin(35,0) level 2 in structure "tcm" dcl 5-11 in procedure "tc_init" set ref 314* timax 7 based fixed bin(35,0) level 2 in structure "apte" dcl 3-7 in procedure "tc_init" set ref 476* time 000134 automatic fixed bin(71,0) dcl 73 set ref 503* 504 505 506 507 508 509 510 511 trace based structure level 1 dcl 2-7 tsdw 000116 automatic fixed bin(71,0) dcl 64 set ref 232* 233 233 355* 356 356 450* 451 452 454* 455 tsize 000133 automatic fixed bin(18,0) dcl 72 set ref 364* 371* 371 389 391 type 4 based char(4) level 2 dcl 10-6 ref 625 unspec builtin function dcl 175 set ref 358* used_itt 322 based fixed bin(18,0) level 2 dcl 5-11 set ref 295* volmap_polling_time based fixed bin(71,0) level 2 dcl 5-11 set ref 508* wait_enable 326 based fixed bin(18,0) level 2 dcl 5-11 set ref 521* wct_entry based structure level 1 dcl 5-260 wct_index 21 based bit(18) level 2 packed packed unaligned dcl 3-7 set ref 466* wcte based structure array level 3 dcl 5-11 set ref 247 278 279 work_class_table based structure level 2 dcl 5-11 working_set_factor 307 based fixed bin(35,18) level 2 dcl 5-11 set ref 311* ws_factor 1 based fixed bin(35,18) level 2 dcl 11-5 ref 311 NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. BEEP internal static fixed bin(17,0) initial dcl 13-7 BULK_PORT internal static fixed bin(17,0) initial dcl 7-176 CPU_PORT internal static fixed bin(17,0) initial dcl 7-176 IOM_PORT internal static fixed bin(17,0) initial dcl 7-176 JUST_LOG internal static fixed bin(17,0) initial dcl 13-7 L68_SYSTEM internal static fixed bin(17,0) initial dcl 14-3 LOG internal static fixed bin(17,0) initial dcl 13-7 SYSERR_COVERT_CHANNEL internal static fixed bin(17,0) initial dcl 13-7 SYSERR_CRASH_SYSTEM internal static fixed bin(17,0) initial dcl 13-7 SYSERR_LOG_OR_DISCARD internal static fixed bin(17,0) initial dcl 13-7 SYSERR_LOG_OR_PRINT internal static fixed bin(17,0) initial dcl 13-7 SYSERR_PRINT_ON_CONSOLE internal static fixed bin(17,0) initial dcl 13-7 SYSERR_PRINT_WITH_ALARM internal static fixed bin(17,0) initial dcl 13-7 SYSERR_RING1_ERROR internal static fixed bin(17,0) initial dcl 13-7 SYSERR_SUCCESSFUL_ACCESS internal static fixed bin(17,0) initial dcl 13-7 SYSERR_SYSTEM_ERROR internal static fixed bin(17,0) initial dcl 13-7 SYSERR_TERMINATE_PROCESS internal static fixed bin(17,0) initial dcl 13-7 SYSERR_UNSUCCESSFUL_ACCESS internal static fixed bin(17,0) initial dcl 13-7 SYSTEM_TYPE_NAME internal static char(8) initial array packed unaligned dcl 14-6 TERMINATE_PROCESS internal static fixed bin(17,0) initial dcl 13-7 aclp automatic pointer dcl 8-7 acls based structure level 1 dcl 8-45 dps8_mem_size_table internal static fixed bin(24,0) initial array dcl 15-63 dps_mem_size_table internal static fixed bin(24,0) initial array dcl 15-54 dps_rsw_2 based structure level 1 dcl 15-13 extended_page_trace_entry based structure level 1 dcl 2-36 lock_ptr automatic pointer dcl 6-11 name_seg based structure level 1 dcl 8-26 namep automatic pointer dcl 8-7 names_ptr automatic pointer dcl 8-7 page_trace_entry based structure level 1 dcl 2-27 path based structure level 1 dcl 8-40 pathp automatic pointer dcl 8-7 rsw_1_3 based structure level 1 dcl 15-39 rsw_4 based structure level 1 dcl 15-47 rsw_valid internal static fixed bin(17,0) initial array dcl 15-66 rswp automatic pointer dcl 15-11 scs$bos_restart_flags external static bit(8) dcl 7-135 scs$cam_pair external static fixed bin(71,0) dcl 7-103 scs$cam_wait external static bit(8) dcl 7-104 scs$cfg_data external static fixed bin(71,0) array dcl 7-150 scs$cfg_data_save external static fixed bin(71,0) dcl 7-152 scs$connect_lock external static bit(36) dcl 7-132 scs$controller_config_size external static fixed bin(14,0) array dcl 7-164 scs$controller_data external static structure array level 1 dcl 7-6 scs$cow external static structure array level 1 dcl 7-65 scs$cow_ptrs external static structure array level 1 dcl 7-77 scs$cpu_test_mask external static bit(72) dcl 7-96 scs$cpu_test_pattern external static bit(36) dcl 7-99 scs$cycle_priority_template external static bit(7) dcl 7-172 scs$expanded_ports external static bit(1) array packed unaligned dcl 7-154 scs$fast_cam_pending external static bit(36) array dcl 7-140 scs$faults_initialized external static bit(1) dcl 7-138 scs$interrupt_controller external static fixed bin(3,0) dcl 7-141 scs$mask_ptr external static pointer array packed unaligned dcl 7-110 scs$nprocessors external static fixed bin(17,0) dcl 7-136 scs$number_of_masks external static fixed bin(17,0) dcl 7-97 scs$open_level external static bit(72) dcl 7-94 scs$port_addressing_word external static bit(3) array dcl 7-148 scs$port_data external static structure array level 1 dcl 7-56 scs$processor external static bit(8) dcl 7-143 scs$processor_data_switch_value external static bit(36) dcl 7-162 scs$processor_start_int_no external static fixed bin(5,0) dcl 7-142 scs$processor_start_mask external static bit(72) dcl 7-95 scs$processor_start_pattern external static bit(36) dcl 7-98 scs$processor_start_wait external static bit(8) dcl 7-144 scs$processor_switch_compare external static bit(36) array dcl 7-159 scs$processor_switch_mask external static bit(36) array dcl 7-160 scs$processor_switch_template external static bit(36) array dcl 7-158 scs$processor_test_data external static structure level 1 dcl 7-114 scs$read_mask external static bit(36) array dcl 7-109 scs$reconfig_general_cow external static structure level 1 dcl 7-82 scs$reconfig_lock external static bit(36) dcl 7-133 scs$reconfig_locker_id external static char(32) dcl 7-167 scs$scas_page_table external static bit(36) array dcl 7-169 scs$set_cycle_switches external static bit(1) dcl 7-173 scs$set_mask external static bit(36) array dcl 7-108 scs$sys_level external static bit(72) dcl 7-93 scs$sys_trouble_pending external static bit(1) dcl 7-139 scs$trouble_dbrs automatic fixed bin(71,0) array dcl 7-146 scs$trouble_flags external static bit(8) dcl 7-134 sdtep automatic pointer dcl 1-17 sdw_info_ptr automatic pointer dcl 4-4 segnam based structure level 1 dcl 8-31 sltp automatic pointer dcl 8-7 string builtin function dcl 175 trace_ptr automatic pointer dcl 2-5 wctep automatic pointer dcl 5-258 NAMES DECLARED BY EXPLICIT CONTEXT. early 000256 constant entry external dcl 181 other_loop 003064 constant label dcl 593 ref 628 part_1 000265 constant label dcl 185 ref 179 part_2 001730 constant entry external dcl 397 shrink_sdw 003442 constant entry internal dcl 525 ref 450 454 start_other_cpus 002513 constant entry external dcl 547 tc_init 000246 constant entry external dcl 13 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 4404 4634 3507 4414 Length 5464 3507 230 613 675 22 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME tc_init 322 external procedure is an external procedure. shrink_sdw internal procedure shares stack frame of external procedure tc_init. STORAGE FOR INTERNAL STATIC VARIABLES. LOC IDENTIFIER BLOCK NAME 000010 dseg_no tc_init 000011 pds_no tc_init 000012 prds_no tc_init 000014 template_pds_p tc_init 000016 tag tc_init 000020 idle_dsegs_sdw tc_init 000022 idle_pdses_sdw tc_init 000024 idle_dsegs_p tc_init 000026 idle_pdses_p tc_init 000030 dseg_size tc_init 000031 pds_size tc_init STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME tc_init 000100 early_call tc_init 000101 n_words tc_init 000102 first_segno tc_init 000103 processor_index tc_init 000104 prdsp tc_init 000106 no_apt tc_init 000107 no_itt tc_init 000110 tc_data_size tc_init 000111 tc_data_no tc_init 000112 tc_data_header_no tc_init 000114 tc_data_header_ptr tc_init 000116 tsdw tc_init 000120 i tc_init 000121 template_pds_size tc_init 000122 idle_pds_p tc_init 000124 aptp tc_init 000126 aptx tc_init 000130 ittp tc_init 000132 ittx tc_init 000133 tsize tc_init 000134 time tc_init 000136 code tc_init 000137 prds_name tc_init 000147 prds_length_kw tc_init 000150 cpu_model tc_init 000154 cpu_serial tc_init 000160 cpu_ship_date tc_init 000162 table_value tc_init 000163 stack_0_data_init_number_of_stacks tc_init 000164 sdtp tc_init 000166 aptep tc_init 000170 tcmp tc_init 000172 sltep tc_init 000174 cpu_cardp tc_init 000176 schd_cardp tc_init 000200 tcd_cardp tc_init 000212 sdwi shrink_sdw THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. alloc_char_temp call_ext_out_desc call_ext_out return_mac mpfx2 shorten_stack ext_entry clock_mac THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. append$branchx chname$cfile config_$find config_$find_table delentry$dfile get_main get_ptrs_$given_segno getuid grab_aste$prewithdraw init_processor$init init_processor$return initiate pmut$swap_sdw privileged_mode_ut$read_id_prom pxss$get_entry sdw_util_$construct sdw_util_$dissect start_cpu syserr syserr$error_code terminate_$teseg thread$cin THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. active_all_rings_data$stack_base_segno dseg$ error_table_$noentry idle_dsegs$ idle_pdses$ pds$ pds$apt_ptr pds$data pds$dstep pds$initial_procedure pds$lock_id pds$process_group_id pds$processid pds$stack_0_ptr pds$stack_0_sdwp pds$trace prds$ prds$processor_tag scs$bos_processor_tag scs$idle_aptep scs$processor_data scs$processor_switch_data slt$ stack_0_data$ sys_info$hfp_exponent_available sys_info$quit_mask sys_info$susp_mask sys_info$system_type sys_info$term_mask tc_data$ tc_data$prds_length tc_data_header$ template_pds$ template_pds$apt_ptr template_pds$initial_procedure template_pds$process_group_id template_pds$processid template_pds$quota_inhib template_pds$save_history_regs template_pds$stack_0_ptr template_pds$stack_0_sdwp LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 13 000245 178 000253 179 000254 181 000255 183 000263 185 000265 187 000270 188 000272 189 000274 190 000300 191 000302 192 000306 193 000313 194 000320 196 000325 197 000332 199 000340 202 000360 203 000423 205 000426 206 000430 207 000432 208 000434 210 000435 211 000437 212 000450 213 000454 214 000457 215 000461 217 000462 218 000465 230 000467 232 000476 233 000511 234 000524 238 000533 239 000535 241 000537 246 000542 247 000547 248 000631 249 000636 250 000644 251 000652 252 000660 253 000666 254 000672 255 000700 256 000704 257 000710 258 000716 259 000727 260 000735 264 000737 266 000742 267 000777 268 001005 269 001014 271 001030 273 001044 274 001052 275 001060 276 001103 278 001111 279 001116 283 001123 284 001127 285 001131 286 001143 287 001151 288 001154 289 001156 291 001164 295 001170 296 001171 297 001173 298 001203 299 001211 300 001213 301 001221 302 001224 303 001231 304 001234 308 001237 309 001241 310 001252 311 001256 312 001262 313 001265 314 001270 315 001273 316 001277 319 001311 321 001320 324 001323 327 001340 329 001362 331 001400 335 001412 336 001417 339 001431 340 001443 344 001472 348 001500 349 001504 353 001516 354 001521 355 001524 356 001541 357 001554 358 001557 359 001567 364 001571 365 001572 366 001601 367 001604 368 001611 369 001615 370 001623 371 001627 373 001630 379 001632 380 001636 381 001640 382 001641 385 001642 386 001644 389 001645 391 001662 393 001700 394 001713 395 001726 397 001727 404 001735 408 001740 410 001744 412 001745 416 001747 417 001750 418 001751 419 001755 420 001766 421 001770 422 001772 423 001776 425 001777 426 002001 428 002006 430 002012 431 002013 433 002017 436 002025 437 002032 440 002040 441 002053 442 002061 443 002067 445 002110 447 002117 448 002130 450 002134 451 002157 452 002166 454 002172 455 002211 457 002220 461 002222 462 002225 463 002230 464 002235 465 002250 466 002253 467 002256 468 002260 469 002272 470 002275 471 002277 472 002304 473 002311 474 002313 475 002321 476 002325 477 002326 478 002341 487 002345 492 002356 494 002357 495 002363 497 002376 498 002401 502 002430 503 002432 504 002434 505 002435 506 002436 507 002437 508 002440 509 002441 510 002442 511 002443 512 002444 516 002446 518 002453 519 002464 521 002506 523 002511 547 002512 558 002520 562 002532 564 002547 566 002566 568 002605 576 002653 577 002661 578 002703 579 002724 581 002732 582 002734 583 002741 584 002772 587 003024 588 003025 589 003055 591 003057 592 003061 593 003064 595 003075 597 003101 602 003105 603 003110 604 003132 605 003202 607 003246 608 003250 610 003274 611 003276 613 003326 614 003331 616 003335 618 003355 621 003367 622 003377 625 003433 628 003441 525 003442 536 003444 538 003461 541 003465 542 003467 545 003504 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved