COMPILATION LISTING OF SEGMENT validate_cpu_card Compiled by: Multics PL/I Compiler, Release 32f, of October 9, 1989 Compiled at: Bull HN, Phoenix AZ, System-M Compiled on: 11/11/89 1026.6 mst Sat Options: optimize map 1 /****^ *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Bull Inc., 1987 * 4* * * 5* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 6* * * 7* * Copyright (c) 1972 by Massachusetts Institute of * 8* * Technology and Honeywell Information Systems, Inc. * 9* * * 10* *********************************************************** */ 11 12 /* format: style4 */ 13 14 validate_cpu_card: proc (tag, rswp); 15 16 /* validate_cpu_card - entry to validate (and change if necessary) the cpu 17* type and model fields on a cpu config card image. 18* 19* The entry parameter rswp is a pointer and is declared in rsw.incl.pl1 20* The pointer, rswp should be pointing to the RSW (2) data that will be used to get 21* the correct type and model of the desired cpu. 22* 23* Last Modified (Date and Reason) 24* 09/11/80 by J. A. Bush initial coding for the DPS8/70M CPU 25* 07/20/81 by J. A. Bush to remove references to the hc_psp segment. 26* 03/25/83 by J. A. Bush to correct DPS8/52 and DPS8/62 RSW (2) decodes. 27* 09/20/83 by J. A. Bush to add cpu cache size to cpu card image. 28* 04/09/84 by Chris Jones to use modern include files. 29**/ 30 31 32 /****^ HISTORY COMMENTS: 33* 1) change(86-10-23,Fawcett), approve(86-10-23,MCR7517), 34* audit(86-10-30,Beattie), install(86-11-03,MR12.0-1206): 35* Changed to remove the word BOS from Error message documentation. 36* END HISTORY COMMENTS */ 37 38 39 dcl (unspec, substr) builtin; 40 dcl tag fixed bin (3); /* tag of cpu to be validated */ 41 dcl ctype char (4); /* for checking cpu type in config card */ 42 dcl cmodel fixed bin; /* for checking cpu model in config card */ 43 dcl cs_idx fixed bin; 44 dcl (discrep, set_fields) bit (1); 45 dcl LETTERS char (8) static options (constant) init ("ABCDEFGH"); 46 dcl CS_ARRAY (0:5) fixed bin int static options (constant) init (0, 2, 8, 8, 16, 32); 47 dcl FENCE bit (36) int static options (constant) init ("777777777777"b3); 48 dcl IGNORE_CACHE_SIZE fixed bin int static options (constant) init (7); 49 dcl config_$find_2 entry (char (4) aligned, fixed bin, ptr); 50 dcl syserr entry options (variable); 51 52 discrep, set_fields = "0"b; /* reset error flag */ 53 call config_$find_2 (CPU_CARD_WORD, tag + 1, cpu_cardp); /* Find correct CPU card. */ 54 cardp = cpu_cardp; 55 56 cs_idx = scs$processor_data (tag).cache_size; /* get auto cache size index */ 57 58 /* determine correct type and model info from rsw (2) data */ 59 60 if dps8_rsw_2.cpu_type > 0 then do; /* if DPS8 cpu */ 61 ctype = "dps8"; 62 if dps8_rsw_2.cpu_speed = "0000"b then /* if model 70 */ 63 cmodel = 70; 64 else if dps8_rsw_2.cpu_speed = "0001"b then /* else if model 52 */ 65 cmodel = 52; 66 else if dps8_rsw_2.cpu_speed = "0100"b then /* else if model 62 */ 67 cmodel = 62; 68 else cmodel = 77; /* this indicates a bad cpu_speed code */ 69 end; 70 else do; /* must be DPS or L68 cpu */ 71 if dps_rsw_2.dps_option then /* if this is on it must be DPS cpu */ 72 ctype = "dps "; 73 else ctype = "l68 "; /* otherwise must be L68 */ 74 if dps_rsw_2.cache2 then /* if we have cache */ 75 cmodel = 80; 76 else cmodel = 60; /* no cache */ 77 end; 78 79 /* now check type and model values obtained from rsw (2) data against current cpu card values */ 80 81 if cpu_card.type ^= ctype then do; /* cpu type field is wrong */ 82 set_fields = "1"b; /* set flag to correct card image */ 83 if unspec (cpu_card.type) ^= FENCE then do; /* CPU type recorded incorrectly? */ 84 call syserr (BEEP, "validate_cpu_card: CPU type for CPU ^a is incorrect, should be ""^a""", 85 substr (LETTERS, tag + 1, 1), ctype); 86 discrep = "1"b; 87 end; 88 end; 89 90 if cpu_card.model ^= cmodel then do; /* cpu model field is wrong */ 91 set_fields = "1"b; /* set flag to correct card image */ 92 if cpu_card.model ^= -1 then do; /* cpu model recorded incorrectly? */ 93 call syserr (BEEP, "validate_cpu_card: CPU model for CPU ^a is incorrect, should be ""^d.""", 94 substr (LETTERS, tag + 1, 1), cmodel); 95 discrep = "1"b; /* set error flag */ 96 end; 97 end; 98 if cs_idx ^= IGNORE_CACHE_SIZE then /* if not being called by ISOLTS reconfig.. */ 99 if cpu_card.cache_size ^= CS_ARRAY (cs_idx) then do; /* cpu cache size is wrong */ 100 set_fields = "1"b; /* set flag to correct card image */ 101 if cpu_card.cache_size ^= -1 then do; /* cpu cache size recorded incorrectly? */ 102 call syserr (BEEP, "validate_cpu_card: CPU cache size for CPU ^a is incorrect, should be ""^d.""", 103 substr (LETTERS, tag + 1, 1), CS_ARRAY (cs_idx)); 104 discrep = "1"b; /* set error flag */ 105 end; 106 end; 107 if set_fields then do; /* if we must set/reset cpu card image fields */ 108 if discrep then /* if some discrepency exists ... */ 109 call syserr (ANNOUNCE, 110 "validate_cpu_card: CPU type, model, and/or cache size discrepencies will be corrected"); 111 cpu_card.type = ctype; /* set correct cpu type */ 112 cpu_card.model = cmodel; /* and model */ 113 if cs_idx = IGNORE_CACHE_SIZE then do; /* if being called by isolts, don't set cache size */ 114 if config_card.n_fields < 5 then /* if cpu type/model not defined */ 115 config_card.n_fields = 5; /* do it now */ 116 end; 117 else do; /* set cache size as well */ 118 cpu_card.cache_size = CS_ARRAY (cs_idx);/* and cache_size */ 119 if config_card.n_fields < 6 then /* if not enough fields defined */ 120 config_card.n_fields = 6; /* set it */ 121 end; 122 config_card.field_type (4) = CONFIG_STRING_TYPE; 123 config_card.field_type (5) = CONFIG_DECIMAL_TYPE; /* and decimal for model */ 124 config_card.field_type (6) = CONFIG_DECIMAL_TYPE; /* and decimal for cache size */ 125 end; 126 1 1 /* BEGIN INCLUDE FILE ... config_deck.incl.pl1 ... 11/13/80, W. Olin Sibert */ 1 2 1 3 dcl (configp, cardp) pointer; 1 4 dcl config_n_cards fixed bin; /* Number of cards used in config */ 1 5 dcl config_max_cards fixed bin; /* Max number of cards in config */ 1 6 1 7 dcl config_deck$ fixed bin external static; 1 8 1 9 dcl 1 config_deck aligned based (configp), 1 10 2 cards (config_n_cards) aligned like config_card, 1 11 2 pad_cards (config_max_cards - config_n_cards) aligned like config_card; 1 12 1 13 dcl 1 config_card aligned based (cardp), 1 14 2 word char (4) aligned, 1 15 2 data_field (14) bit (36) aligned, 1 16 2 type_word aligned like config_card_type_word; 1 17 1 18 dcl 1 config_card_type_word aligned based, 1 19 2 field_type (14) bit (2) unaligned, 1 20 2 pad1 bit (4) unaligned, 1 21 2 n_fields fixed bin (4) unsigned unaligned; 1 22 1 23 dcl (CONFIG_DECIMAL_TYPE init ("11"b), 1 24 CONFIG_OCTAL_TYPE init ("00"b), 1 25 CONFIG_SINGLE_CHAR_TYPE init ("01"b), 1 26 CONFIG_STRING_TYPE init ("10"b)) bit (2) aligned static options (constant); 1 27 1 28 dcl ZERO_CARD_WORD char (4) aligned internal static options (constant) init (""); 1 29 dcl FREE_CARD_WORD char (4) aligned internal static options (constant) init ("ÿÿÿÿ"); 1 30 1 31 dcl VALID_CARD_WORD_CHARACTERS char (38) internal static options (constant) init 1 32 ("abcdefghijklmnopqrstuvwxyz0123456789_."); /* lowercase letters, digits, period and underscore */ 1 33 1 34 dcl EMPTY_FIELD bit (36) aligned internal static options (constant) init ("777777777777"b3); 1 35 1 36 /* END INCLUDE FILE config_deck.incl.pl1 */ 127 128 2 1 /* BEGIN INCLUDE FILE ... config_cpu_card.incl.pl1 ... 11/27/80 W. Olin Sibert */ 2 2 /* format: style4 */ 2 3 2 4 dcl cpu_cardp pointer; /* pointer to CPU card */ 2 5 2 6 dcl 1 cpu_card aligned based (cpu_cardp), /* CPU card declaration */ 2 7 2 word char (4), /* "cpu" */ 2 8 2 tag fixed bin (3), /* CPU tag from switches, plus one */ 2 9 2 port fixed bin (3), /* Controller port for CPU */ 2 10 2 state char (4), /* "on", "off", "shut", or "test" */ 2 11 2 type char (4), /* "l68", "dps", "dps8" */ 2 12 2 13 2 model fixed bin, /* 60., 80., or 70. */ 2 14 2 cache_size fixed bin, /* either 0. 2. 8. 16. or 32. */ 2 15 2 expander_port fixed bin (3), /* If present, indicates expander sub-port */ 2 16 2 17 2 pad (7) bit (36) aligned, /* Pad to 15 fields */ 2 18 2 19 2 type_word aligned, 2 20 3 field_type (14) bit (2) unaligned, /* type of each field; see config_deck.incl.pl1 */ 2 21 3 pad1 bit (4) unaligned, 2 22 3 n_fields fixed bin (4) unsigned unaligned; /* number of fields used on card */ 2 23 2 24 dcl CPU_CARD_WORD char (4) aligned internal static options (constant) init ("cpu"); 2 25 2 26 /* END INCLUDE FILE ... config_cpu_card.incl.pl1 */ 129 130 3 1 /* *********************************************************** 3 2* * * 3 3* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 3 4* * * 3 5* *********************************************************** */ 3 6 /* Begin include file ...... rsw.incl.pl1 3 7* Modified 3/26/77 by Noel I. Morris 3 8* Modified 9/03/80 by J. A. Bush for the DPS8/70M CPU 3 9* Modified 3/24/82 by J. A. Bush to allow the L68 CPU to address 4MW/port */ 3 10 3 11 dcl rswp ptr; 3 12 3 13 dcl 1 dps_rsw_2 aligned based (rswp), /* rsw 2 template for DPS and L68 CPUs */ 3 14 (2 pad1 bit (4), 3 15 2 cpu_type fixed bin (2) unsigned, /* 0 = L68 or DPS, 1 = DPS8 */ 3 16 2 fault_base bit (7), /* high order bits of fault vector */ 3 17 2 pad2 bit (6), 3 18 2 dps_option bit (1), /* "1"b => DPS CPU, "0"b => L68 CPU */ 3 19 2 pad3 bit (7), 3 20 2 cache2 bit (1), /* "1"b => 2k cache installed, "0"b => no cache */ 3 21 2 ext_gcos bit (1), /* "1"b => ext gcos option installed */ 3 22 2 id bit (4), /* CPU ID - "1110"b => L68 */ 3 23 2 cpu_num fixed bin (3) unsigned) unaligned; /* processor number */ 3 24 3 25 dcl 1 dps8_rsw_2 aligned based (rswp), /* rsw 2 template for DPS8 CPUs */ 3 26 (2 interlace_info (0:3) bit (1), /* if interlace enabled; "0"b => 4-word, "1"b => 2-word */ 3 27 2 cpu_type fixed bin (2) unsigned, /* 0 = L68 or DPS, 1 = DPS8 */ 3 28 2 fault_base bit (7), /* high order bits of fault vector */ 3 29 2 id_prom bit (1), /* "1"b => id_prom present */ 3 30 2 pad1 bit (5), 3 31 2 dps_option bit (1), /* always "1"b for DPS8 CPU */ 3 32 2 cache8 bit (1), /* "1"b => 8k cache installed, "0"b => no cache */ 3 33 2 pad2 bit (2), 3 34 2 multics_cpu bit (1), /* always "1"b for Multics cpu */ 3 35 2 pad3 bit (5), 3 36 2 cpu_speed bit (4), /* cpu speed options */ 3 37 2 cpu_num fixed bin (3) unsigned) unaligned; /* processor number */ 3 38 3 39 dcl 1 rsw_1_3 aligned based (rswp), /* rsw 3 only valid on DPS and L68 CPUs */ 3 40 (2 port_info (0:3), /* controller port information */ 3 41 3 port_assignment bit (3), /* port address assignment */ 3 42 3 port_enable bit (1), /* "1"b => port enabled */ 3 43 3 initialize_enable bit (1), /* "1"b => system initialize enabled */ 3 44 3 interlace_enable bit (1), /* "1"b => port is interlaced with neighbor */ 3 45 3 mem_size fixed bin (3) unsigned) unaligned; /* encoded memory size on port */ 3 46 3 47 dcl 1 rsw_4 aligned based (rswp), /* rsw 4 only valid on DPS and L68 CPUs */ 3 48 (2 pad1 bit (13), 3 49 2 port_info (0:7), /* additional controller port information */ 3 50 3 four bit (1), /* "0"b => 4-word interlace - "1"b => 2-word interlace */ 3 51 3 half bit (1), /* "1"b => only half of memory on controller in use */ 3 52 2 pad2 bit (7)) unaligned; 3 53 3 54 dcl dps_mem_size_table (0:7) fixed bin (24) static options (constant) init /* DPS and L68 memory sizes */ 3 55 (32768, 65536, 4194304, 131072, 524288, 1048576, 2097152, 262144); 3 56 3 57 /* Note that the third array element above, is changed incompatibly in MR10.0. 3 58* In previous releases, this array element was used to decode a port size of 3 59* 98304 (96K). With MR10.0 it is now possible to address 4MW per CPU port, by 3 60* installing FCO # PHAF183 and using a group 10 patch plug, on L68 and DPS CPUs. 3 61**/ 3 62 3 63 dcl dps8_mem_size_table (0:7) fixed bin (24) static options (constant) init /* DPS8 memory sizes */ 3 64 (32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304); 3 65 3 66 dcl rsw_valid (0:1) fixed bin static options (constant) init (5, 3); /* # of rsw valid per cpu type */ 3 67 3 68 /* End of include file ...... rsw.incl.pl1 */ 131 132 4 1 /* BEGIN INCLUDE FILE syserr_constants.incl.pl1 ... 11/11/80 W. Olin Sibert */ 4 2 /* 85-02-12, EJ Sharpe - Added sorting class constants, removed AIM_MESSAGE, added new action code names. */ 4 3 /* 85-04-24, G. Palter - Renamed SYSERR_UNUSED_10 to SYSERR_RING1_ERROR to reflect its actual use. */ 4 4 4 5 /* This include file has an ALM version. Keep 'em in sync! */ 4 6 4 7 dcl ( 4 8 4 9 /* The following constants define the message action codes. This indicates 4 10*how a message is to be handled. */ 4 11 4 12 SYSERR_CRASH_SYSTEM init (1), 4 13 CRASH init (1), /* Crash the system, and bleat plaintively. */ 4 14 4 15 SYSERR_TERMINATE_PROCESS init (2), 4 16 TERMINATE_PROCESS init (2), /* Terminate the process, print the message, and beep. */ 4 17 4 18 SYSERR_PRINT_WITH_ALARM init (3), 4 19 BEEP init (3), /* Beep and print the message on the console. */ 4 20 4 21 SYSERR_PRINT_ON_CONSOLE init (0), 4 22 ANNOUNCE init (0), /* Just print the message on the console. */ 4 23 4 24 SYSERR_LOG_OR_PRINT init (4), 4 25 LOG init (4), /* Log the message, or print it if it can't be logged */ 4 26 4 27 SYSERR_LOG_OR_DISCARD init (5), 4 28 JUST_LOG init (5), /* Just try to log the message, and discard it if it can't be */ 4 29 4 30 4 31 /* The following constants are added to the normal severities to indicate 4 32*different sorting classes of messages. */ 4 33 4 34 SYSERR_SYSTEM_ERROR init (00), /* indicates a standard level system error */ 4 35 SYSERR_RING1_ERROR init (10), /* indicates an error detected in ring 1 (mseg_, RCP) */ 4 36 SYSERR_COVERT_CHANNEL init (20), /* indicates covert channel audit trail message */ 4 37 SYSERR_UNSUCCESSFUL_ACCESS init (30), /* indicates access denial audit trail message */ 4 38 SYSERR_SUCCESSFUL_ACCESS init (40) /* indicates access grant audit trail message */ 4 39 ) fixed bin internal static options (constant); 4 40 4 41 /* END INCLUDE FILE syserr_constants.incl.pl1 */ 133 134 5 1 /* BEGIN INCLUDE FILE scs.incl.pl1 ... March 1983 */ 5 2 /* format: style4 */ 5 3 5 4 /* Information about system controllers */ 5 5 5 6 dcl 1 scs$controller_data (0:7) aligned ext, /* per-controller info */ 5 7 2 size fixed bin (17) unaligned, /* size (in 1024 word blocks) of this controller */ 5 8 2 base fixed bin (17) unaligned, /* abs address (0 mod 1024) for base of this controller */ 5 9 2 eima_data (4) unaligned, /* EIMA information for this controller */ 5 10 3 mask_available bit (1) unaligned, /* ON if corresponding mask exists */ 5 11 3 mask_assigned bit (1) unaligned, /* ON if mask assigned to a port */ 5 12 3 mbz bit (3) unaligned, 5 13 3 mask_assignment fixed bin (3) unaligned, /* port to which mask is assigned */ 5 14 2 info aligned, 5 15 3 online bit (1) unaligned, /* ON if controller is online */ 5 16 3 offline bit (1) unaligned, /* ON if controller is offline but can be added */ 5 17 3 store_a_online bit (1) unaligned, /* ON if store A is online */ 5 18 3 store_a1_online bit (1) unaligned, /* ON if store A1 is online */ 5 19 3 store_b_online bit (1) unaligned, /* ON if store B is online */ 5 20 3 store_b1_online bit (1) unaligned, /* ON if store B1 is online */ 5 21 3 store_b_is_lower bit (1) unaligned, /* ON if store B is lower */ 5 22 3 ext_interlaced bit (1) unaligned, /* ON if this SCU is interlaced with other SCU */ 5 23 3 int_interlaced bit (1) unaligned, /* ON if this SCU is internally interlaced */ 5 24 3 four_word bit (1) unaligned, /* ON if external interlace is 4-word */ 5 25 3 cyclic_priority (7) bit (1) unaligned, /* Cyclic priority for adjacent ports */ 5 26 3 type bit (4) unaligned, /* Model number for this controller */ 5 27 3 abs_wired bit (1) unaligned, /* ON if controller can have abs_wired pages */ 5 28 3 program bit (1) unaligned, /* PROGRAM/MANUAL switch setting */ 5 29 3 mbz bit (13) unaligned, 5 30 2 lower_store_size fixed bin (17) unaligned, /* size (in 1024 word blocks) of lower store */ 5 31 2 upper_store_size fixed bin (17) unaligned; /* size (in 1024 word blocks) of upper store */ 5 32 5 33 /* Information about CPUs */ 5 34 5 35 dcl 1 scs$processor_data (0:7) aligned ext, /* information about CPUs in the system */ 5 36 ( 5 37 2 online bit (1), /* "1"b if CPU is online */ 5 38 2 offline bit (1), /* "1"b if CPU is offline but can be added */ 5 39 2 release_mask bit (1), /* "1"b is this CPU is to give up its mask */ 5 40 2 accept_mask bit (1), /* "1"b if this CPU is to grap mask in idle loop */ 5 41 2 delete_cpu bit (1), /* "1"b if this CPU is to delete itself */ 5 42 2 interrupt_cpu bit (1), /* "1"b if this CPU takes hardware interrupts */ 5 43 2 halted_cpu bit (1), /* "1"b if this CPU has stopped itself (going to BOS) */ 5 44 2 cpu_type fixed bin (2) unsigned, /* 0 => DPS or L68, 1 => DPS8 */ 5 45 2 mbz1 bit (6), 5 46 2 cache_size fixed bin (3) unsigned, /* 0 = No cache; 1 = L68 2K cache; 5 47* 2 = DPS8 8K cache; 3 = DPS8 VS&SC 8K cache; 5 48* 4 = DPS8 VS&SC 16K cache; 5 = DPS8 VS&SC 32K cache 5 49* 7 = ignore cache size (set by ISOLTS reconfig) */ 5 50 2 mbz2 bit (12), 5 51 2 expanded_port bit (1), /* "1"b = on expanded port */ 5 52 2 expander_port fixed bin (2) unsigned, /* The actual expander port */ 5 53 2 controller_port fixed bin (3) unsigned 5 54 ) unaligned; /* Port on controller */ 5 55 5 56 dcl 1 scs$port_data (0:7) aligned external static, /* Info about what is connected to each SCU port */ 5 57 2 assigned fixed bin (4) unsigned unaligned, /* Type of device on this port */ 5 58 2 expander_port bit (1) unaligned, /* "1"b => this port has a port expander */ 5 59 2 expanded_cpu (0:3) bit (1) unaligned, /* "1"b => this expander port has a CPU attached */ 5 60 2 iom_number fixed bin (3) unsigned unaligned, /* IOM number of IOM attached to this port */ 5 61 2 cpu_number (0:3) fixed bin (3) unsigned unaligned, /* CPU number of CPU(s) attached to this port */ 5 62 /* cpu_number (0) is only one if expander_port is "0"b */ 5 63 2 pad bit (12) unaligned; 5 64 5 65 dcl 1 scs$cow (0:7) aligned external, /* Actual connect words */ 5 66 2 pad bit (36) aligned, /* Expander COW's must be odd-word */ 5 67 2 cow, 5 68 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 5 69 3 mbz1 bit (13) unaligned, 5 70 3 expander_command bit (3) unaligned, /* Expander command. */ 5 71 3 mbz2 bit (2) unaligned, 5 72 3 expanded_port bit (1) unaligned, /* "1"b = on expanded port */ 5 73 3 expander_port fixed bin (3) unsigned unaligned, /* Port on expander for cioc */ 5 74 3 mbz3 bit (3) unaligned, 5 75 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 5 76 5 77 dcl 1 scs$cow_ptrs (0:7) external aligned, /* Pointers to COW's */ 5 78 2 rel_cow_ptr bit (18) unal, /* Relative pointer to COW */ 5 79 2 pad bit (12) unal, 5 80 2 tag bit (6) unal; /* Better be zero. */ 5 81 5 82 dcl 1 scs$reconfig_general_cow aligned external, /* Used during reconfig ops. */ 5 83 2 pad bit (36) aligned, 5 84 2 cow, /* Connect operand word, in odd location. */ 5 85 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 5 86 3 mbz1 bit (13) unaligned, 5 87 3 expander_command bit (3) unaligned, /* Expander command. */ 5 88 3 mbz2 bit (9) unaligned, 5 89 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 5 90 5 91 /* MASKS and PATTERNS */ 5 92 5 93 dcl scs$sys_level bit (72) aligned ext; /* mask used while handling I/O interrupts */ 5 94 dcl scs$open_level bit (72) aligned ext; /* mask used during normal operation */ 5 95 dcl scs$processor_start_mask bit (72) aligned ext; /* mask used when starting up a CPU */ 5 96 dcl scs$cpu_test_mask bit (72) aligned ext; /* mask used for ISOLTS CPU testing */ 5 97 dcl scs$number_of_masks fixed bin ext; /* number of masks (starting at sys_level) */ 5 98 dcl scs$processor_start_pattern bit (36) aligned ext; /* SMIC pattern used to send processor start interrupt */ 5 99 dcl scs$cpu_test_pattern bit (36) aligned ext; /* SMIC pattern used for ISOLTS processor testing */ 5 100 5 101 /* CAM and CACHE clear info */ 5 102 5 103 dcl scs$cam_pair fixed bin (71) ext; /* instructions XEDd when CAMing and clearing CACHE */ 5 104 dcl scs$cam_wait bit (8) aligned ext; /* Used when evicting pages from main memory */ 5 105 5 106 /* MASKING INSTRUCTIONS & POINTERS */ 5 107 5 108 dcl scs$set_mask (0:7) bit (36) aligned ext; /* instructions to set mask (STAQ or SMCM) */ 5 109 dcl scs$read_mask (0:7) bit (36) aligned ext; /* instructions to read mask (LDAQ or RMCM) */ 5 110 dcl scs$mask_ptr (0:7) ptr unaligned ext; /* pointers for real or simulated masks */ 5 111 5 112 /* MISCELLANEOUS */ 5 113 5 114 dcl 1 scs$processor_test_data aligned ext, /* info used for cpu testing */ 5 115 ( 5 116 2 active bit (1), /* = "1"b if cpu currently under test */ 5 117 2 scu_state bit (2), /* state of scu being used for testing (see definition below) */ 5 118 2 pad1 bit (4), 5 119 2 req_mem fixed bin (10), /* dedicated memory required to test this cpu */ 5 120 2 cpu_tag fixed bin (5), /* tag of cpu under test */ 5 121 2 scu_tag fixed bin (5), /* tag of scu being used for cpu testing */ 5 122 2 mask_cpu fixed bin (5) 5 123 ) unaligned; /* tag of active cpu that has mask asigned to above scu */ 5 124 5 125 /* scu_state = "00"b => SCU defined by scs$processor_test_data.scu_tag not yet effected */ 5 126 /* scu_state = "01"b => all core removed from SCU, port mask not yet changed */ 5 127 /* scu_state = "10"b => all core removed from SCU, port mask changed */ 5 128 /* scu_state = "11"b => only 64k at base of SCU being used for testing, original port mask restored */ 5 129 5 130 dcl scs$idle_aptep (0:7) ptr unaligned ext; /* pointer to idle process APTE for each processor */ 5 131 5 132 dcl scs$connect_lock bit (36) aligned ext; /* lock for sending connects */ 5 133 dcl scs$reconfig_lock bit (36) aligned ext; /* Lock used during reconfiguration */ 5 134 dcl scs$trouble_flags bit (8) aligned ext; /* checkoff flags for sys_trouble stopping */ 5 135 dcl scs$bos_restart_flags bit (8) aligned ext; /* checkoff flags for restarting after sys_trouble */ 5 136 dcl scs$nprocessors fixed bin ext; /* number of runnung processors */ 5 137 dcl scs$bos_processor_tag fixed bin (3) ext; /* CPU tag of processor running BOS */ 5 138 dcl scs$faults_initialized bit (1) aligned ext; /* ON after faults have been enabled */ 5 139 dcl scs$sys_trouble_pending bit (1) aligned ext; /* sys_trouble event is pending in the system */ 5 140 dcl scs$fast_cam_pending (0:7) bit (36) aligned ext; /* checkoff cells for cam connect */ 5 141 dcl scs$interrupt_controller fixed bin (3) ext; /* port number of low order controller */ 5 142 dcl scs$processor_start_int_no fixed bin (5) ext; /* interrupt cell for starting a processor */ 5 143 dcl scs$processor bit (8) aligned ext; /* bits ON for online CPUs */ 5 144 dcl scs$processor_start_wait bit (8) aligned ext; /* checkoff flags for waiting for new processor */ 5 145 5 146 dcl scs$trouble_dbrs (0:7) fixed bin (71); /* DBR values at system crash time */ 5 147 5 148 dcl scs$port_addressing_word (0:7) bit (3) aligned ext; /* active module port number for each controller */ 5 149 5 150 dcl scs$cfg_data (0:7) fixed bin (71) aligned ext; /* RSCR-CFG data from each controller */ 5 151 5 152 dcl scs$cfg_data_save fixed bin (71) aligned ext; /* RSCR-CFG save area for ISOLTS CPU testing */ 5 153 5 154 dcl scs$expanded_ports bit (1) unaligned dim (0:7) external; 5 155 /* Which ports have expanders */ 5 156 5 157 dcl scs$processor_switch_data (0:4) bit (36) aligned ext; /* raw data from RSW 0 thru 4 */ 5 158 dcl scs$processor_switch_template (0:4) bit (36) aligned ext; /* expected data from RSW 0 thru 4 */ 5 159 dcl scs$processor_switch_compare (0:4) bit (36) aligned ext; /* discrepancies from expected data */ 5 160 dcl scs$processor_switch_mask (0:4) bit (36) aligned ext; /* masks for comparing switch data */ 5 161 5 162 dcl scs$processor_data_switch_value bit (36) aligned ext; /* Correct value for CPU data switches */ 5 163 5 164 dcl scs$controller_config_size (0:7) fixed bin (14) aligned ext; 5 165 /* Controller size on config card */ 5 166 5 167 dcl scs$reconfig_locker_id char (32) aligned ext; /* process group ID of process doing reconfiguration */ 5 168 5 169 dcl scs$scas_page_table (0:31) bit (36) aligned external static; 5 170 /* PTWs for SCAS pages */ 5 171 5 172 dcl scs$cycle_priority_template bit (7) aligned ext; /* template for setting anti-hog switches */ 5 173 dcl scs$set_cycle_switches bit (1) aligned ext; /* flag to set ant-hog switches */ 5 174 5 175 5 176 dcl ( 5 177 IOM_PORT init (1), 5 178 CPU_PORT init (2), 5 179 BULK_PORT init (3) 5 180 ) fixed bin int static options (constant); /* values for scs$port_data.assigned */ 5 181 5 182 5 183 /* END INCLUDE FILE scs.incl.pl1 */ 135 136 137 /* BEGIN MESSAGE DOCUMENTATION 138* 139* Message: 140* validate_cpu_card: CPU type for CPU CPUTAG is incorrect, should be "CPUTYPE" 141* 142* S: $beep 143* 144* T: $run 145* 146* M: The CPUTYPE as determined from RSW (2) information, did not match the 147* CPUTYPE in the cpu type field of the config card image for CPU CPUTAG. 148* 149* A: $ignore 150* 151* Message: 152* validate_cpu_card: CPU model for CPU CPUTAG is incorrect, should be "CPUMODEL." 153* 154* S: $beep 155* 156* T: $run 157* 158* M: The CPUMODEL as determined from RSW (2) information, did not match the 159* CPUMODEL in the cpu model field of the config card image for CPU CPUTAG. 160* 161* A: $ignore 162* 163* Message: 164* validate_cpu_card: CPU cache size for CPU CPUTAG is incorrect, should be "CACHE_SIZE." 165* 166* S: $beep 167* 168* T: $run 169* 170* M: The CACHE_SIZE as determined from cpu registers, did not match the 171* CACHE_SIZE in the cpu cache size field of the config card image for CPU 172* CPUTAG. 173* 174* A: $ignore 175* 176* Message: 177* validate_cpu_card: CPU type, model, and/or cache size discrepencies will be corrected 178* 179* S: $info 180* 181* T: $run 182* 183* M: The indicated discrepencies in the cpu type, model, and cache size 184* fields, will be corrected by validate_cpu_card. 185* 186* A: The type, model, and/or cache size fields of the indicated cpu 187* config card image should be corrected at BCE, before the next bootload. 188* 189* END MESSAGE DOCUMENTATION */ 190 191 end validate_cpu_card; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/11/89 0800.9 validate_cpu_card.pl1 >spec>install>1110>validate_cpu_card.pl1 127 1 05/08/81 1853.6 config_deck.incl.pl1 >ldd>include>config_deck.incl.pl1 129 2 10/14/83 0957.2 config_cpu_card.incl.pl1 >ldd>include>config_cpu_card.incl.pl1 131 3 06/10/82 1045.2 rsw.incl.pl1 >ldd>include>rsw.incl.pl1 133 4 05/17/85 0615.7 syserr_constants.incl.pl1 >ldd>include>syserr_constants.incl.pl1 135 5 10/12/83 0943.5 scs.incl.pl1 >ldd>include>scs.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. ANNOUNCE 000001 constant fixed bin(17,0) initial dcl 4-7 set ref 108* BEEP 000024 constant fixed bin(17,0) initial dcl 4-7 set ref 84* 93* 102* CONFIG_DECIMAL_TYPE constant bit(2) initial dcl 1-23 ref 123 124 CONFIG_STRING_TYPE constant bit(2) initial dcl 1-23 ref 122 CPU_CARD_WORD 000000 constant char(4) initial dcl 2-24 set ref 53* CS_ARRAY 000001 constant fixed bin(17,0) initial array dcl 46 set ref 98 102* 118 FENCE 000542 constant bit(36) initial packed unaligned dcl 47 ref 83 IGNORE_CACHE_SIZE constant fixed bin(17,0) initial dcl 48 ref 98 113 LETTERS 000010 constant char(8) initial packed unaligned dcl 45 ref 84 84 93 93 102 102 cache2 0(27) based bit(1) level 2 packed packed unaligned dcl 3-13 ref 74 cache_size 6 based fixed bin(17,0) level 2 in structure "cpu_card" dcl 2-6 in procedure "validate_cpu_card" set ref 98 101 118* cache_size 0(15) 000014 external static fixed bin(3,0) array level 2 in structure "scs$processor_data" packed packed unsigned unaligned dcl 5-35 in procedure "validate_cpu_card" ref 56 cardp 000106 automatic pointer dcl 1-3 set ref 54* 114 114 119 119 122 123 124 cmodel 000101 automatic fixed bin(17,0) dcl 42 set ref 62* 64* 66* 68* 74* 76* 90 93* 112 config_$find_2 000010 constant entry external dcl 49 ref 53 config_card based structure level 1 dcl 1-13 config_card_type_word based structure level 1 dcl 1-18 cpu_card based structure level 1 dcl 2-6 cpu_cardp 000110 automatic pointer dcl 2-4 set ref 53* 54 81 83 90 92 98 101 111 112 118 cpu_speed 0(29) based bit(4) level 2 packed packed unaligned dcl 3-25 ref 62 64 66 cpu_type 0(04) based fixed bin(2,0) level 2 packed packed unsigned unaligned dcl 3-25 ref 60 cs_idx 000102 automatic fixed bin(17,0) dcl 43 set ref 56* 98 98 102 113 118 ctype 000100 automatic char(4) packed unaligned dcl 41 set ref 61* 71* 73* 81 84* 111 discrep 000103 automatic bit(1) packed unaligned dcl 44 set ref 52* 86* 95* 104* 108 dps8_rsw_2 based structure level 1 dcl 3-25 dps_option 0(19) based bit(1) level 2 packed packed unaligned dcl 3-13 ref 71 dps_rsw_2 based structure level 1 dcl 3-13 field_type 17 based bit(2) array level 3 packed packed unaligned dcl 1-13 set ref 122* 123* 124* model 5 based fixed bin(17,0) level 2 dcl 2-6 set ref 90 92 112* n_fields 17(32) based fixed bin(4,0) level 3 packed packed unsigned unaligned dcl 1-13 set ref 114 114* 119 119* rswp parameter pointer dcl 3-11 ref 14 60 62 64 66 71 74 scs$processor_data 000014 external static structure array level 1 dcl 5-35 set_fields 000104 automatic bit(1) packed unaligned dcl 44 set ref 52* 82* 91* 100* 107 substr builtin function dcl 39 ref 84 84 93 93 102 102 syserr 000012 constant entry external dcl 50 ref 84 93 102 108 tag parameter fixed bin(3,0) dcl 40 ref 14 53 56 84 84 93 93 102 102 type 4 based char(4) level 2 dcl 2-6 set ref 81 83 111* type_word 17 based structure level 2 dcl 1-13 unspec builtin function dcl 39 ref 83 NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. BULK_PORT internal static fixed bin(17,0) initial dcl 5-176 CONFIG_OCTAL_TYPE internal static bit(2) initial dcl 1-23 CONFIG_SINGLE_CHAR_TYPE internal static bit(2) initial dcl 1-23 CPU_PORT internal static fixed bin(17,0) initial dcl 5-176 CRASH internal static fixed bin(17,0) initial dcl 4-7 EMPTY_FIELD internal static bit(36) initial dcl 1-34 FREE_CARD_WORD internal static char(4) initial dcl 1-29 IOM_PORT internal static fixed bin(17,0) initial dcl 5-176 JUST_LOG internal static fixed bin(17,0) initial dcl 4-7 LOG internal static fixed bin(17,0) initial dcl 4-7 SYSERR_COVERT_CHANNEL internal static fixed bin(17,0) initial dcl 4-7 SYSERR_CRASH_SYSTEM internal static fixed bin(17,0) initial dcl 4-7 SYSERR_LOG_OR_DISCARD internal static fixed bin(17,0) initial dcl 4-7 SYSERR_LOG_OR_PRINT internal static fixed bin(17,0) initial dcl 4-7 SYSERR_PRINT_ON_CONSOLE internal static fixed bin(17,0) initial dcl 4-7 SYSERR_PRINT_WITH_ALARM internal static fixed bin(17,0) initial dcl 4-7 SYSERR_RING1_ERROR internal static fixed bin(17,0) initial dcl 4-7 SYSERR_SUCCESSFUL_ACCESS internal static fixed bin(17,0) initial dcl 4-7 SYSERR_SYSTEM_ERROR internal static fixed bin(17,0) initial dcl 4-7 SYSERR_TERMINATE_PROCESS internal static fixed bin(17,0) initial dcl 4-7 SYSERR_UNSUCCESSFUL_ACCESS internal static fixed bin(17,0) initial dcl 4-7 TERMINATE_PROCESS internal static fixed bin(17,0) initial dcl 4-7 VALID_CARD_WORD_CHARACTERS internal static char(38) initial packed unaligned dcl 1-31 ZERO_CARD_WORD internal static char(4) initial dcl 1-28 config_deck based structure level 1 dcl 1-9 config_deck$ external static fixed bin(17,0) dcl 1-7 config_max_cards automatic fixed bin(17,0) dcl 1-5 config_n_cards automatic fixed bin(17,0) dcl 1-4 configp automatic pointer dcl 1-3 dps8_mem_size_table internal static fixed bin(24,0) initial array dcl 3-63 dps_mem_size_table internal static fixed bin(24,0) initial array dcl 3-54 rsw_1_3 based structure level 1 dcl 3-39 rsw_4 based structure level 1 dcl 3-47 rsw_valid internal static fixed bin(17,0) initial array dcl 3-66 scs$bos_processor_tag external static fixed bin(3,0) dcl 5-137 scs$bos_restart_flags external static bit(8) dcl 5-135 scs$cam_pair external static fixed bin(71,0) dcl 5-103 scs$cam_wait external static bit(8) dcl 5-104 scs$cfg_data external static fixed bin(71,0) array dcl 5-150 scs$cfg_data_save external static fixed bin(71,0) dcl 5-152 scs$connect_lock external static bit(36) dcl 5-132 scs$controller_config_size external static fixed bin(14,0) array dcl 5-164 scs$controller_data external static structure array level 1 dcl 5-6 scs$cow external static structure array level 1 dcl 5-65 scs$cow_ptrs external static structure array level 1 dcl 5-77 scs$cpu_test_mask external static bit(72) dcl 5-96 scs$cpu_test_pattern external static bit(36) dcl 5-99 scs$cycle_priority_template external static bit(7) dcl 5-172 scs$expanded_ports external static bit(1) array packed unaligned dcl 5-154 scs$fast_cam_pending external static bit(36) array dcl 5-140 scs$faults_initialized external static bit(1) dcl 5-138 scs$idle_aptep external static pointer array packed unaligned dcl 5-130 scs$interrupt_controller external static fixed bin(3,0) dcl 5-141 scs$mask_ptr external static pointer array packed unaligned dcl 5-110 scs$nprocessors external static fixed bin(17,0) dcl 5-136 scs$number_of_masks external static fixed bin(17,0) dcl 5-97 scs$open_level external static bit(72) dcl 5-94 scs$port_addressing_word external static bit(3) array dcl 5-148 scs$port_data external static structure array level 1 dcl 5-56 scs$processor external static bit(8) dcl 5-143 scs$processor_data_switch_value external static bit(36) dcl 5-162 scs$processor_start_int_no external static fixed bin(5,0) dcl 5-142 scs$processor_start_mask external static bit(72) dcl 5-95 scs$processor_start_pattern external static bit(36) dcl 5-98 scs$processor_start_wait external static bit(8) dcl 5-144 scs$processor_switch_compare external static bit(36) array dcl 5-159 scs$processor_switch_data external static bit(36) array dcl 5-157 scs$processor_switch_mask external static bit(36) array dcl 5-160 scs$processor_switch_template external static bit(36) array dcl 5-158 scs$processor_test_data external static structure level 1 dcl 5-114 scs$read_mask external static bit(36) array dcl 5-109 scs$reconfig_general_cow external static structure level 1 dcl 5-82 scs$reconfig_lock external static bit(36) dcl 5-133 scs$reconfig_locker_id external static char(32) dcl 5-167 scs$scas_page_table external static bit(36) array dcl 5-169 scs$set_cycle_switches external static bit(1) dcl 5-173 scs$set_mask external static bit(36) array dcl 5-108 scs$sys_level external static bit(72) dcl 5-93 scs$sys_trouble_pending external static bit(1) dcl 5-139 scs$trouble_dbrs automatic fixed bin(71,0) array dcl 5-146 scs$trouble_flags external static bit(8) dcl 5-134 NAME DECLARED BY EXPLICIT CONTEXT. validate_cpu_card 000147 constant entry external dcl 14 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 616 634 543 626 Length 1110 543 16 240 52 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME validate_cpu_card 180 external procedure is an external procedure. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME validate_cpu_card 000100 ctype validate_cpu_card 000101 cmodel validate_cpu_card 000102 cs_idx validate_cpu_card 000103 discrep validate_cpu_card 000104 set_fields validate_cpu_card 000106 cardp validate_cpu_card 000110 cpu_cardp validate_cpu_card THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out_desc call_ext_out return_mac ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. config_$find_2 syserr THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. scs$processor_data LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 14 000143 52 000154 53 000156 54 000174 56 000176 60 000205 61 000212 62 000214 64 000224 66 000231 68 000236 69 000240 71 000241 73 000247 74 000251 76 000257 81 000261 82 000264 83 000266 84 000271 86 000324 90 000326 91 000332 92 000334 93 000336 95 000373 98 000375 100 000405 101 000407 102 000411 104 000446 107 000450 108 000452 111 000474 112 000477 113 000501 114 000504 116 000515 118 000516 119 000520 122 000531 123 000535 124 000537 191 000541 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved