COMPILATION LISTING OF SEGMENT prepare_mc_restart_ Compiled by: Multics PL/I Compiler, Release 27d, of October 11, 1982 Compiled at: Honeywell LISD Phoenix, System M Compiled on: 11/04/82 1802.6 mst Thu Options: optimize map 1 /* *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 4* * * 5* * Copyright (c) 1972 by Massachusetts Institute of * 6* * Technology and Honeywell Information Systems, Inc. * 7* * * 8* *********************************************************** */ 9 10 11 prepare_mc_restart_: proc (amcptr, code); 12 13 /* PREPARE_MC_RESTART_ - Modify machine conditions and 14* insure that control unit can be restored. 15* 16* This program has four entry points: 17* 18* prepare_mc_restart_ Just check machine conditions. 19* 20* prepare_mc_restart_$retry Make faulting instruction retry from the beginning. 21* 22* prepare_mc_restart_$replace Replace faulting instruction with argument, then 23* . continue in sequence. 24* 25* prepare_mc_restart_$tra Restart execution at some other location in virtual memory. 26* 27* THVV */ 28 29 /* parameters */ 30 31 dcl amcptr ptr, /* ptr to machine conditions */ 32 code fixed bin (35); /* err code */ 33 34 /* automatic */ 35 36 dcl dummy ptr; /* Temporary ptr for $tra check */ 37 dcl (high, low) fixed bin; /* Current segment number maxima */ 38 39 /* based */ 40 41 dcl 1 dum aligned based (addr (dummy)), /* Overlay for a pointer. */ 42 2 xxw bit (3) unal, 43 2 segno bit (15) unal, /* .. segment number */ 44 2 ring bit (3) unal, /* .. ring number */ 45 2 xxx bit (9) unal, 46 2 its bit (6) unal, /* .. ITS modifier */ 47 2 offset bit (18) unal, /* .. segment address */ 48 2 xxy bit (3) unal, 49 2 bit_offset bit (6) unal, /* .. bit offset */ 50 2 xxz bit (3) unal, 51 2 mod bit (6) unal; /* .. further indirection */ 52 53 /* external static */ 54 55 dcl error_table_$bad_arg_acc fixed bin (35) ext, /* Return if bad mcptr */ 56 error_table_$no_restart fixed bin (35) ext, /* Return if mc are illegal. */ 57 error_table_$bad_ptr fixed bin (35) ext; /* Return if restart loc is unlegal. */ 58 59 /* entries */ 60 61 dcl hcs_$high_low_seg_count entry (fixed bin, fixed bin); /* Obtain size of address space from KST */ 62 dcl get_ring_ entry () returns (fixed bin); /* Obtain current execution ring. */ 63 64 /* builtins */ 65 66 dcl (addr, fixed, null) builtin; 67 68 /* include files */ 69 1 1 /* */ 1 2 /* BEGIN INCLUDE FILE mc.incl.pl1 Created Dec 72 for 6180 - WSS. */ 1 3 /* Modified 06/07/76 by Greenberg for mc.resignal */ 1 4 /* Modified 07/07/76 by Morris for fault register data */ 1 5 /* Modified 08/28/80 by J. A. Bush for the DPS8/70M CVPU */ 1 6 1 7 1 8 /* words 0-15 pointer registers */ 1 9 1 10 dcl mcp ptr; 1 11 1 12 dcl 1 mc based (mcp) aligned, 1 13 2 prs (0:7) ptr, /* POINTER REGISTERS */ 1 14 (2 regs, /* registers */ 1 15 3 x (0:7) bit (18), /* index registers */ 1 16 3 a bit (36), /* accumulator */ 1 17 3 q bit (36), /* q-register */ 1 18 3 e bit (8), /* exponent */ 1 19 3 pad1 bit (28), 1 20 3 t bit (27), /* timer register */ 1 21 3 pad2 bit (6), 1 22 3 ralr bit (3), /* ring alarm register */ 1 23 1 24 2 scu (0:7) bit (36), 1 25 1 26 2 mask bit (72), /* mem controller mask at time of fault */ 1 27 2 ips_temp bit (36), /* Temporary storage for IPS info */ 1 28 2 errcode fixed bin (35), /* fault handler's error code */ 1 29 2 fim_temp, 1 30 3 unique_index bit (18) unal, /* unique index for restarting faults */ 1 31 3 resignal bit (1) unal, /* recompute signal name with fcode below */ 1 32 3 fcode bit (17) unal, /* fault code used as index to FIM table and SCT */ 1 33 2 fault_reg bit (36), /* fault register */ 1 34 2 pad2 bit (1), 1 35 2 cpu_type fixed bin (2) unsigned, /* L68 = 0, DPS8/70M = 1 */ 1 36 2 ext_fault_reg bit (15), /* extended fault reg for DPS8/70M CPU */ 1 37 2 fault_time bit (54), /* time of fault */ 1 38 1 39 2 eis_info (0:7) bit (36)) unaligned; 1 40 1 41 1 42 dcl (apx fixed bin init (0), 1 43 abx fixed bin init (1), 1 44 bpx fixed bin init (2), 1 45 bbx fixed bin init (3), 1 46 lpx fixed bin init (4), 1 47 lbx fixed bin init (5), 1 48 spx fixed bin init (6), 1 49 sbx fixed bin init (7)) internal static; 1 50 1 51 1 52 1 53 1 54 dcl scup ptr; 1 55 1 56 dcl 1 scu based (scup) aligned, /* SCU DATA */ 1 57 1 58 1 59 /* WORD (0) */ 1 60 1 61 (2 ppr, /* PROCEDURE POINTER REGISTER */ 1 62 3 prr bit (3), /* procedure ring register */ 1 63 3 psr bit (15), /* procedure segment register */ 1 64 3 p bit (1), /* procedure privileged bit */ 1 65 1 66 2 apu, /* APPENDING UNIT STATUS */ 1 67 3 xsf bit (1), /* ext seg flag - IT modification */ 1 68 3 sdwm bit (1), /* match in SDW Ass. Mem. */ 1 69 3 sd_on bit (1), /* SDW Ass. Mem. ON */ 1 70 3 ptwm bit (1), /* match in PTW Ass. Mem. */ 1 71 3 pt_on bit (1), /* PTW Ass. Mem. ON */ 1 72 3 pi_ap bit (1), /* Instr Fetch or Append cycle */ 1 73 3 dsptw bit (1), /* Fetch of DSPTW */ 1 74 3 sdwnp bit (1), /* Fetch of SDW non paged */ 1 75 3 sdwp bit (1), /* Fetch of SDW paged */ 1 76 3 ptw bit (1), /* Fetch of PTW */ 1 77 3 ptw2 bit (1), /* Fetch of pre-paged PTW */ 1 78 3 fap bit (1), /* Fetch of final address paged */ 1 79 3 fanp bit (1), /* Fetch of final address non-paged */ 1 80 3 fabs bit (1), /* Fetch of final address absolute */ 1 81 1 82 2 fault_cntr bit (3), /* number of retrys of EIS instructions */ 1 83 1 84 1 85 /* WORD (1) */ 1 86 1 87 2 fd, /* FAULT DATA */ 1 88 3 iro bit (1), /* illegal ring order */ 1 89 3 oeb bit (1), /* out of execute bracket */ 1 90 3 e_off bit (1), /* no execute */ 1 91 3 orb bit (1), /* out of read bracket */ 1 92 3 r_off bit (1), /* no read */ 1 93 3 owb bit (1), /* out of write bracket */ 1 94 3 w_off bit (1), /* no write */ 1 95 3 no_ga bit (1), /* not a gate */ 1 96 3 ocb bit (1), /* out of call bracket */ 1 97 3 ocall bit (1), /* outward call */ 1 98 3 boc bit (1), /* bad outward call */ 1 99 3 inret bit (1), /* inward return */ 1 100 3 crt bit (1), /* cross ring transfer */ 1 101 3 ralr bit (1), /* ring alarm register */ 1 102 3 am_er bit (1), /* associative memory fault */ 1 103 3 oosb bit (1), /* out of segment bounds */ 1 104 3 paru bit (1), /* processor parity upper */ 1 105 3 parl bit (1), /* processor parity lower */ 1 106 3 onc_1 bit (1), /* op not complete type 1 */ 1 107 3 onc_2 bit (1), /* op not complete type 2 */ 1 108 1 109 2 port_stat, /* PORT STATUS */ 1 110 3 ial bit (4), /* illegal action lines */ 1 111 3 iac bit (3), /* illegal action channel */ 1 112 3 con_chan bit (3), /* connect channel */ 1 113 1 114 2 fi_num bit (5), /* (fault/interrupt) number */ 1 115 2 fi_flag bit (1), /* 1 => fault, 0 => interrupt */ 1 116 1 117 1 118 /* WORD (2) */ 1 119 1 120 2 tpr, /* TEMPORARY POINTER REGISTER */ 1 121 3 trr bit (3), /* temporary ring register */ 1 122 3 tsr bit (15), /* temporary segment register */ 1 123 1 124 2 pad2 bit (9), 1 125 1 126 2 cpu_no bit (3), /* CPU number */ 1 127 1 128 2 delta bit (6), /* tally modification DELTA */ 1 129 1 130 1 131 /* WORD (3) */ 1 132 1 133 2 word3 bit (18), 1 134 1 135 2 tsr_stat, /* TSR STATUS for 1,2,&3 word instructions */ 1 136 3 tsna, /* Word 1 status */ 1 137 4 prn bit (3), /* Word 1 PR number */ 1 138 4 prv bit (1), /* Word 1 PR valid bit */ 1 139 3 tsnb, /* Word 2 status */ 1 140 4 prn bit (3), /* Word 2 PR number */ 1 141 4 prv bit (1), /* Word 2 PR valid bit */ 1 142 3 tsnc, /* Word 3 status */ 1 143 4 prn bit (3), /* Word 3 PR number */ 1 144 4 prv bit (1), /* Word 3 PR valid bit */ 1 145 1 146 2 tpr_tbr bit (6), /* TPR.TBR field */ 1 147 1 148 1 149 /* WORD (4) */ 1 150 1 151 2 ilc bit (18), /* INSTRUCTION COUNTER */ 1 152 1 153 2 ir, /* INDICATOR REGISTERS */ 1 154 3 zero bit (1), /* zero indicator */ 1 155 3 neg bit (1), /* negative indicator */ 1 156 3 carry bit (1), /* carryry indicator */ 1 157 3 ovfl bit (1), /* overflow indicator */ 1 158 3 eovf bit (1), /* eponent overflow */ 1 159 3 eufl bit (1), /* exponent underflow */ 1 160 3 oflm bit (1), /* overflow mask */ 1 161 3 tro bit (1), /* tally runout */ 1 162 3 par bit (1), /* parity error */ 1 163 3 parm bit (1), /* parity mask */ 1 164 3 bm bit (1), /* ^bar mode */ 1 165 3 tru bit (1), /* truncation mode */ 1 166 3 mif bit (1), /* multi-word instruction mode */ 1 167 3 abs bit (1), /* absolute mode */ 1 168 3 pad bit (4), 1 169 1 170 1 171 /* WORD (5) */ 1 172 1 173 2 ca bit (18), /* COMPUTED ADDRESS */ 1 174 1 175 2 cu, /* CONTROL UNIT STATUS */ 1 176 3 rf bit (1), /* on first cycle of repeat instr */ 1 177 3 rpt bit (1), /* repeat instruction */ 1 178 3 rd bit (1), /* repeat double instruction */ 1 179 3 rl bit (1), /* repeat link instruciton */ 1 180 3 pot bit (1), /* IT modification */ 1 181 3 pon bit (1), /* return type instruction */ 1 182 3 xde bit (1), /* XDE from Even location */ 1 183 3 xdo bit (1), /* XDE from Odd location */ 1 184 3 poa bit (1), /* operation preparation */ 1 185 3 rfi bit (1), /* tells CPU to refetch instruction */ 1 186 3 its bit (1), /* ITS modification */ 1 187 3 if bit (1), /* fault occured during instruction fetch */ 1 188 1 189 2 cpu_tag bit (6)) unaligned, /* computed tag field */ 1 190 1 191 1 192 /* WORDS (6,7) */ 1 193 1 194 2 even_inst bit (36), /* even instruction of faulting pair */ 1 195 1 196 2 odd_inst bit (36); /* odd instruction of faulting pair */ 1 197 1 198 1 199 1 200 1 201 1 202 1 203 /* ALTERNATE SCU DECLARATION */ 1 204 1 205 1 206 dcl 1 scux based (scup) aligned, 1 207 1 208 (2 pad0 bit (36), 1 209 1 210 2 fd, /* GROUP II FAULT DATA */ 1 211 3 isn bit (1), /* illegal segment number */ 1 212 3 ioc bit (1), /* illegal op code */ 1 213 3 ia_am bit (1), /* illegal address - modifier */ 1 214 3 isp bit (1), /* illegal slave procedure */ 1 215 3 ipr bit (1), /* illegal procedure */ 1 216 3 nea bit (1), /* non existent address */ 1 217 3 oobb bit (1), /* out of bounds */ 1 218 3 pad bit (29), 1 219 1 220 2 pad2 bit (36), 1 221 1 222 2 pad3a bit (18), 1 223 1 224 2 tsr_stat (0:2), /* TSR STATUS as an ARRAY */ 1 225 3 prn bit (3), /* PR number */ 1 226 3 prv bit (1), /* PR valid bit */ 1 227 1 228 2 pad3b bit (6)) unaligned, 1 229 1 230 2 pad45 (0:1) bit (36), 1 231 1 232 2 instr (0:1) bit (36); /* Instruction ARRAY */ 1 233 1 234 1 235 1 236 /* END INCLUDE FILE mc.incl.pl1 */ 70 71 72 /* ======================================================= */ 73 74 call check_mc; /* All he wants is a check of mach cond. */ 75 if code ^= 0 then return; /* If there is an error. */ 76 return; /* Restart is plausible. */ 77 78 /* ------------------------------------------------------ */ 79 80 retry: entry (amcptr, code); 81 82 call check_mc; /* Check machine cond. */ 83 if code ^= 0 then return; /* Give up if no good. */ 84 85 scu.rfi = "1"b; /* Refetch the instruction. */ 86 scu.if = "1"b; /* ... */ 87 return; 88 89 /* ------------------------------------------------------ */ 90 91 replace: entry (amcptr, new_instr, code); 92 93 dcl new_instr bit (36); /* The instruction to replace faulting instr. */ 94 95 call check_mc; /* Make sure valid machine cond. */ 96 if code ^= 0 then return; /* Die if no good. */ 97 98 scu.rfi = "0"b; /* No refetch instruction. */ 99 scu.if = "0"b; /* Fault not in instruction fetch (so I buffer is good) */ 100 scu.even_inst = new_instr; /* Replace instruction */ 101 return; 102 103 /* ------------------------------------------------------ */ 104 105 tra: entry (amcptr, newppr, code); 106 107 dcl newppr ptr; /* New execution point desired. */ 108 109 call check_mc; /* Validate machine conditions. */ 110 if code ^= 0 then return; /* Error if no good. */ 111 dummy = newppr; /* Copy pointer. */ 112 if fixed (dum.segno, 15) > low + high then do; /* Check segment which is target of transfer. */ 113 ilret: code = error_table_$bad_ptr; /* Nasty. This would cause a segment fault. */ 114 return; 115 end; 116 if dum.its ^= "100011"b then go to ilret; /* Our argument should be a regular pointer. */ 117 if dum.ring ^= scu.ppr.prr then go to ilret; /* Don't change rings. */ 118 if dum.bit_offset then go to ilret; /* Silly, can't start in middle of a word. */ 119 if dum.mod then go to ilret; /* This program does not handle further indirection. */ 120 121 scu.ppr.psr = dum.segno; /* Copy segment number. */ 122 scu.ilc = dum.offset; /* Copy offset. */ 123 124 scu.rfi = "1"b; /* Invalidate I buffer, so next instruction will be */ 125 scu.if = "1"b; /* .. pulled from memory. */ 126 return; 127 128 /* ======================================================= */ 129 130 check_mc: proc; 131 132 dcl i fixed bin; 133 134 mcp = amcptr; /* Copy user machine cond ptr. */ 135 code = error_table_$bad_arg_acc; /* Assume failure. */ 136 if mcp = null then return; /* Die right away if he has no machine cond. */ 137 scup = addr (mc.scu); /* Get ptr to SCU data. */ 138 code = error_table_$no_restart; /* Assume mc are garbage. */ 139 140 call hcs_$high_low_seg_count (low, high); /* Get address space range. */ 141 142 do i = 0 to 7; /* First check the PR's. */ 143 dummy = prs (i); /* Each should be an ITS */ 144 if dum.its ^= "100011"b then return; /* ... */ 145 if dum.mod then return; /* .. and have no junk. */ 146 end; 147 if fixed (dum.segno, 15) > low + high then return; /* Validate SB */ 148 149 if fixed (scu.ppr.prr, 3) ^= get_ring_ () then return; /* Forbid ring switches. */ 150 151 if ^(scu.cu.rpt|scu.cu.rd) then go to ok1; /* Check repeat-double bits. Must have 0 or 1 */ 152 if ^(scu.cu.rpt|scu.cu.rl) then go to ok1; /* .. */ 153 if ^(scu.cu.rd|scu.cu.rl) then go to ok1; /* .. */ 154 return; /* Bad. Has two repeat bits on at once. CPU wd hang. */ 155 156 ok1: if scu.cu.xde then if scu.cu.xdo then return; /* Cannot have both XDE and XDO. Hangs CPU */ 157 158 if scu.cu.pot then if scu.cu.pon then return; /* Similarly here. No IT with returns. */ 159 160 if scu.ir.abs then return; /* No absolute mode. */ 161 162 if scu.ppr.p then return; /* No return into privileged procedure. */ 163 164 if scu.ir.parm then return; /* User not to mask parity. */ 165 166 if fixed (scu.ppr.psr, 15) > low + high then return; /* Validate ppr. */ 167 if fixed (scu.tpr.tsr, 15) > low + high then return; /* Validate tpr. */ 168 169 code = 0; /* Success. Machine conditions look pretty good. */ 170 171 end check_mc; 172 173 end prepare_mc_restart_; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/04/82 1625.1 prepare_mc_restart_.pl1 >dumps>old>recomp>prepare_mc_restart_.pl1 70 1 08/12/81 2025.8 mc.incl.pl1 >ldd>include>mc.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. abs 4(31) based bit(1) level 3 packed unaligned dcl 1-56 ref 160 addr builtin function dcl 66 ref 112 116 117 118 119 121 122 137 144 145 147 amcptr parameter pointer dcl 31 ref 11 80 91 105 134 bit_offset 1(21) based bit(6) level 2 packed unaligned dcl 41 ref 118 code parameter fixed bin(35,0) dcl 31 set ref 11 75 80 83 91 96 105 110 113* 135* 138* 169* cu 5(18) based structure level 2 packed unaligned dcl 1-56 dum based structure level 1 dcl 41 dummy 000100 automatic pointer dcl 36 set ref 111* 112 116 117 118 119 121 122 143* 144 145 147 error_table_$bad_arg_acc 000010 external static fixed bin(35,0) dcl 55 ref 135 error_table_$bad_ptr 000014 external static fixed bin(35,0) dcl 55 ref 113 error_table_$no_restart 000012 external static fixed bin(35,0) dcl 55 ref 138 even_inst 6 based bit(36) level 2 dcl 1-56 set ref 100* fixed builtin function dcl 66 ref 112 147 149 166 167 get_ring_ 000020 constant entry external dcl 62 ref 149 hcs_$high_low_seg_count 000016 constant entry external dcl 61 ref 140 high 000102 automatic fixed bin(17,0) dcl 37 set ref 112 140* 147 166 167 i 000120 automatic fixed bin(17,0) dcl 132 set ref 142* 143* if 5(29) based bit(1) level 3 packed unaligned dcl 1-56 set ref 86* 99* 125* ilc 4 based bit(18) level 2 packed unaligned dcl 1-56 set ref 122* ir 4(18) based structure level 2 packed unaligned dcl 1-56 its 0(30) based bit(6) level 2 packed unaligned dcl 41 ref 116 144 low 000103 automatic fixed bin(17,0) dcl 37 set ref 112 140* 147 166 167 mc based structure level 1 dcl 1-12 mcp 000104 automatic pointer dcl 1-10 set ref 134* 136 137 143 mod 1(30) based bit(6) level 2 packed unaligned dcl 41 ref 119 145 new_instr parameter bit(36) unaligned dcl 93 ref 91 100 newppr parameter pointer dcl 107 ref 105 111 null builtin function dcl 66 ref 136 offset 1 based bit(18) level 2 packed unaligned dcl 41 ref 122 p 0(18) based bit(1) level 3 packed unaligned dcl 1-56 ref 162 parm 4(27) based bit(1) level 3 packed unaligned dcl 1-56 ref 164 pon 5(23) based bit(1) level 3 packed unaligned dcl 1-56 ref 158 pot 5(22) based bit(1) level 3 packed unaligned dcl 1-56 ref 158 ppr based structure level 2 packed unaligned dcl 1-56 prr based bit(3) level 3 packed unaligned dcl 1-56 ref 117 149 prs based pointer array level 2 dcl 1-12 ref 143 psr 0(03) based bit(15) level 3 packed unaligned dcl 1-56 set ref 121* 166 rd 5(20) based bit(1) level 3 packed unaligned dcl 1-56 ref 151 153 rfi 5(27) based bit(1) level 3 packed unaligned dcl 1-56 set ref 85* 98* 124* ring 0(18) based bit(3) level 2 packed unaligned dcl 41 ref 117 rl 5(21) based bit(1) level 3 packed unaligned dcl 1-56 ref 152 153 rpt 5(19) based bit(1) level 3 packed unaligned dcl 1-56 ref 151 152 scu based structure level 1 dcl 1-56 in procedure "prepare_mc_restart_" scu 30 based bit(36) array level 2 in structure "mc" packed unaligned dcl 1-12 in procedure "prepare_mc_restart_" set ref 137 scup 000106 automatic pointer dcl 1-54 set ref 85 86 98 99 100 117 121 122 124 125 137* 149 151 151 152 152 153 153 156 156 158 158 160 162 164 166 167 segno 0(03) based bit(15) level 2 packed unaligned dcl 41 ref 112 121 147 tpr 2 based structure level 2 packed unaligned dcl 1-56 tsr 2(03) based bit(15) level 3 packed unaligned dcl 1-56 ref 167 xde 5(24) based bit(1) level 3 packed unaligned dcl 1-56 ref 156 xdo 5(25) based bit(1) level 3 packed unaligned dcl 1-56 ref 156 NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. abx internal static fixed bin(17,0) initial dcl 1-42 apx internal static fixed bin(17,0) initial dcl 1-42 bbx internal static fixed bin(17,0) initial dcl 1-42 bpx internal static fixed bin(17,0) initial dcl 1-42 lbx internal static fixed bin(17,0) initial dcl 1-42 lpx internal static fixed bin(17,0) initial dcl 1-42 sbx internal static fixed bin(17,0) initial dcl 1-42 scux based structure level 1 dcl 1-206 spx internal static fixed bin(17,0) initial dcl 1-42 NAMES DECLARED BY EXPLICIT CONTEXT. check_mc 000205 constant entry internal dcl 130 ref 74 82 95 109 ilret 000142 constant label dcl 113 ref 116 117 118 119 ok1 000340 constant label dcl 156 ref 151 152 153 prepare_mc_restart_ 000012 constant entry external dcl 11 replace 000055 constant entry external dcl 91 retry 000030 constant entry external dcl 80 tra 000107 constant entry external dcl 105 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 526 550 415 536 Length 744 415 22 160 111 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME prepare_mc_restart_ 96 external procedure is an external procedure. check_mc internal procedure shares stack frame of external procedure prepare_mc_restart_. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME prepare_mc_restart_ 000100 dummy prepare_mc_restart_ 000102 high prepare_mc_restart_ 000103 low prepare_mc_restart_ 000104 mcp prepare_mc_restart_ 000106 scup prepare_mc_restart_ 000120 i check_mc THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out return ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. get_ring_ hcs_$high_low_seg_count THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. error_table_$bad_arg_acc error_table_$bad_ptr error_table_$no_restart LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 11 000006 74 000022 75 000023 76 000025 80 000026 82 000040 83 000041 85 000043 86 000046 87 000050 91 000051 95 000065 96 000066 98 000070 99 000073 100 000075 101 000102 105 000103 109 000117 110 000120 111 000122 112 000126 113 000142 114 000145 116 000146 117 000152 118 000162 119 000165 121 000170 122 000175 124 000200 125 000202 126 000204 130 000205 134 000206 135 000212 136 000215 137 000222 138 000224 140 000226 142 000236 143 000242 144 000246 145 000255 146 000261 147 000263 149 000274 151 000310 152 000324 153 000333 154 000337 156 000340 158 000347 160 000356 162 000362 164 000366 166 000372 167 000403 169 000411 171 000412 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved