COMPILATION LISTING OF SEGMENT resolve_linkage_error Compiled by: Multics PL/I Compiler, Release 28d, of October 4, 1983 Compiled at: Honeywell LCPD Phoenix, System M Compiled on: 02/06/84 0949.1 mst Mon Options: optimize map 1 /* *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 4* * * 5* * Copyright (c) 1972 by Massachusetts Institute of * 6* * Technology and Honeywell Information Systems, Inc. * 7* * * 8* *********************************************************** */ 9 10 11 resolve_linkage_error: rle: proc; 12 13 /* RESOLVE_LINKAGE_ERROR - satisfy a linkage_error with a specified pointer. 14* 15* THVV 2/77, after Max Smith */ 16 /* Usage message added 11/02/79 S. Herbst */ 17 /* Modified 7 Nov 83 by C Spitzer. use cv_ptr_ if cv_entry_ fails. Maybe not an object segment */ 18 19 dcl argl fixed bin, /* length of arg */ 20 bchr char (argl) based (tp) unal, /* for looking at argument */ 21 argno fixed bin, /* steps thru argument list to command */ 22 stackp ptr, /* pointer to rle's stack frame */ 23 p ptr, /* ptr to user proc */ 24 entry_to_use entry variable, 25 link_pair_ptr ptr, /* ptr to linkage fault */ 26 faultsp ptr, 27 tp ptr, /* work pointer */ 28 got_entry bit (1), 29 ec fixed bin (35); /* system error code */ 30 31 dcl (addr, baseno, baseptr, null, ptr, rel) builtin; 32 33 dcl 1 instr (0:1) based aligned, 34 2 address bit (18) unal, 35 2 op_code bit (12) unal, 36 2 mod bit (6) unal; 37 38 dcl 1 condinfo aligned, /* return struc from find_condition_info_ */ 39 2 mcptr ptr, 40 2 version fixed bin, 41 2 condition_name char (32) var, 42 2 infoptr ptr, 43 2 wcptr ptr, 44 2 loc_ptr ptr, 45 2 flags, 46 3 crawlout bit (1) unal, 47 3 pad1 bit (35) unal, 48 2 user_loc_ptr ptr, 49 2 pad (4) bit (36); 50 51 dcl 1 link based (link_pair_ptr) aligned, 52 2 tbr bit (18) unal, 53 2 xx bit (12) unal, 54 2 ft bit (6) unal, 55 2 ca bit (18) unal, 56 2 xx1 bit (18) unal; 57 58 dcl 1 based_entry_overlay based (addr (entry_to_use)) aligned, 59 2 procedure_ptr ptr, 60 2 stack_ptr ptr; 61 62 dcl error_table_$no_linkage fixed bin(35) ext static; 63 64 dcl (com_err_, com_err_$suppress_name) entry options (variable), 65 find_condition_frame_ entry (ptr) returns (ptr), 66 cv_entry_ entry (char (*), ptr, fixed bin (35)) returns (entry), 67 cv_ptr_ entry (char(*), fixed bin(35)) returns(ptr), 68 prepare_mc_restart_ entry (ptr, fixed bin (35)), 69 find_condition_info_ entry (ptr, ptr, fixed bin (35)), 70 cu_$stack_frame_ptr entry (ptr), 71 cu_$arg_ptr entry (fixed bin, ptr, fixed bin, fixed bin (35)); 72 73 /* ======================================================= */ 74 75 call cu_$stack_frame_ptr (stackp); /* get current stack pointer */ 76 condinfo.version = 1; 77 ec = 0; 78 got_entry = "0"b; 79 do argno = 1 by 1 while (ec = 0); 80 call cu_$arg_ptr (argno, tp, argl, ec); /* look at all arguments */ 81 if ec = 0 then do; 82 if got_entry then do; 83 USAGE: call com_err_$suppress_name (0, "resolve_linkage_error", 84 "Usage: resolve_linkage_error virtual_entry"); 85 return; 86 end; 87 got_entry = "1"b; 88 entry_to_use = cv_entry_ (bchr, null, ec); 89 if ec ^= 0 then do; 90 if ec = error_table_$no_linkage then do; 91 p = cv_ptr_ (bchr, ec); 92 if ec ^= 0 then goto nent; 93 end; 94 else do; 95 nent: call com_err_ (ec, "resolve_linkage_error", "cannot locate ^a", bchr); 96 return; 97 end; 98 end; 99 else do; 100 p = based_entry_overlay.procedure_ptr; 101 if p = null then go to nent; 102 end; 103 end; 104 end; 105 if ^got_entry then go to USAGE; 106 107 loop: faultsp = find_condition_frame_ (stackp); /* Search for fault frame. */ 108 if faultsp = null then do; /* .. error if not found */ 109 call com_err_ (0, "resolve_linkage_error", "no linkage fault on stack"); 110 return; 111 end; 112 call find_condition_info_ (faultsp, addr (condinfo), ec); /* Decode the frame */ 113 if condinfo.condition_name = "linkage_error" then do; 114 scup = addr (condinfo.mcptr -> mc.scu); /* Found linkage error. */ 115 link_pair_ptr = ptr (baseptr ("000"b || scu.tpr.tsr), scu.ca); /* Locate link */ 116 if link.ft ^= "46"b3 then do; /* Check that it's really a link fault */ 117 call com_err_ (0, "resolve_linkage_error", "Link pair at ^p lacks FT2 modifier. No change.", 118 link_pair_ptr); 119 return; 120 end; 121 link.tbr = baseno (p); /* Patch link to be entry found above */ 122 link.ca = rel (p); 123 link.ft = "43"b3; /* Over-write fault tag 2 */ 124 call prepare_mc_restart_ (condinfo.mcptr, ec); /* Check that MC are restartable */ 125 if ec ^= 0 then call com_err_ (ec, "resolve_linkage_error", ""); 126 return; /* Success */ 127 end; 128 stackp = faultsp; /* Wrong fault frame */ 129 go to loop; 130 1 1 /* */ 1 2 /* BEGIN INCLUDE FILE mc.incl.pl1 Created Dec 72 for 6180 - WSS. */ 1 3 /* Modified 06/07/76 by Greenberg for mc.resignal */ 1 4 /* Modified 07/07/76 by Morris for fault register data */ 1 5 /* Modified 08/28/80 by J. A. Bush for the DPS8/70M CVPU */ 1 6 /* Modified '82 to make values constant */ 1 7 1 8 /* words 0-15 pointer registers */ 1 9 1 10 dcl mcp ptr; 1 11 1 12 dcl 1 mc based (mcp) aligned, 1 13 2 prs (0:7) ptr, /* POINTER REGISTERS */ 1 14 (2 regs, /* registers */ 1 15 3 x (0:7) bit (18), /* index registers */ 1 16 3 a bit (36), /* accumulator */ 1 17 3 q bit (36), /* q-register */ 1 18 3 e bit (8), /* exponent */ 1 19 3 pad1 bit (28), 1 20 3 t bit (27), /* timer register */ 1 21 3 pad2 bit (6), 1 22 3 ralr bit (3), /* ring alarm register */ 1 23 1 24 2 scu (0:7) bit (36), 1 25 1 26 2 mask bit (72), /* mem controller mask at time of fault */ 1 27 2 ips_temp bit (36), /* Temporary storage for IPS info */ 1 28 2 errcode fixed bin (35), /* fault handler's error code */ 1 29 2 fim_temp, 1 30 3 unique_index bit (18) unal, /* unique index for restarting faults */ 1 31 3 resignal bit (1) unal, /* recompute signal name with fcode below */ 1 32 3 fcode bit (17) unal, /* fault code used as index to FIM table and SCT */ 1 33 2 fault_reg bit (36), /* fault register */ 1 34 2 pad2 bit (1), 1 35 2 cpu_type fixed bin (2) unsigned, /* L68 = 0, DPS8/70M = 1 */ 1 36 2 ext_fault_reg bit (15), /* extended fault reg for DPS8/70M CPU */ 1 37 2 fault_time bit (54), /* time of fault */ 1 38 1 39 2 eis_info (0:7) bit (36)) unaligned; 1 40 1 41 1 42 dcl (apx fixed bin init (0), 1 43 abx fixed bin init (1), 1 44 bpx fixed bin init (2), 1 45 bbx fixed bin init (3), 1 46 lpx fixed bin init (4), 1 47 lbx fixed bin init (5), 1 48 spx fixed bin init (6), 1 49 sbx fixed bin init (7)) internal static options (constant); 1 50 1 51 1 52 1 53 1 54 dcl scup ptr; 1 55 1 56 dcl 1 scu based (scup) aligned, /* SCU DATA */ 1 57 1 58 1 59 /* WORD (0) */ 1 60 1 61 (2 ppr, /* PROCEDURE POINTER REGISTER */ 1 62 3 prr bit (3), /* procedure ring register */ 1 63 3 psr bit (15), /* procedure segment register */ 1 64 3 p bit (1), /* procedure privileged bit */ 1 65 1 66 2 apu, /* APPENDING UNIT STATUS */ 1 67 3 xsf bit (1), /* ext seg flag - IT modification */ 1 68 3 sdwm bit (1), /* match in SDW Ass. Mem. */ 1 69 3 sd_on bit (1), /* SDW Ass. Mem. ON */ 1 70 3 ptwm bit (1), /* match in PTW Ass. Mem. */ 1 71 3 pt_on bit (1), /* PTW Ass. Mem. ON */ 1 72 3 pi_ap bit (1), /* Instr Fetch or Append cycle */ 1 73 3 dsptw bit (1), /* Fetch of DSPTW */ 1 74 3 sdwnp bit (1), /* Fetch of SDW non paged */ 1 75 3 sdwp bit (1), /* Fetch of SDW paged */ 1 76 3 ptw bit (1), /* Fetch of PTW */ 1 77 3 ptw2 bit (1), /* Fetch of pre-paged PTW */ 1 78 3 fap bit (1), /* Fetch of final address paged */ 1 79 3 fanp bit (1), /* Fetch of final address non-paged */ 1 80 3 fabs bit (1), /* Fetch of final address absolute */ 1 81 1 82 2 fault_cntr bit (3), /* number of retrys of EIS instructions */ 1 83 1 84 1 85 /* WORD (1) */ 1 86 1 87 2 fd, /* FAULT DATA */ 1 88 3 iro bit (1), /* illegal ring order */ 1 89 3 oeb bit (1), /* out of execute bracket */ 1 90 3 e_off bit (1), /* no execute */ 1 91 3 orb bit (1), /* out of read bracket */ 1 92 3 r_off bit (1), /* no read */ 1 93 3 owb bit (1), /* out of write bracket */ 1 94 3 w_off bit (1), /* no write */ 1 95 3 no_ga bit (1), /* not a gate */ 1 96 3 ocb bit (1), /* out of call bracket */ 1 97 3 ocall bit (1), /* outward call */ 1 98 3 boc bit (1), /* bad outward call */ 1 99 3 inret bit (1), /* inward return */ 1 100 3 crt bit (1), /* cross ring transfer */ 1 101 3 ralr bit (1), /* ring alarm register */ 1 102 3 am_er bit (1), /* associative memory fault */ 1 103 3 oosb bit (1), /* out of segment bounds */ 1 104 3 paru bit (1), /* processor parity upper */ 1 105 3 parl bit (1), /* processor parity lower */ 1 106 3 onc_1 bit (1), /* op not complete type 1 */ 1 107 3 onc_2 bit (1), /* op not complete type 2 */ 1 108 1 109 2 port_stat, /* PORT STATUS */ 1 110 3 ial bit (4), /* illegal action lines */ 1 111 3 iac bit (3), /* illegal action channel */ 1 112 3 con_chan bit (3), /* connect channel */ 1 113 1 114 2 fi_num bit (5), /* (fault/interrupt) number */ 1 115 2 fi_flag bit (1), /* 1 => fault, 0 => interrupt */ 1 116 1 117 1 118 /* WORD (2) */ 1 119 1 120 2 tpr, /* TEMPORARY POINTER REGISTER */ 1 121 3 trr bit (3), /* temporary ring register */ 1 122 3 tsr bit (15), /* temporary segment register */ 1 123 1 124 2 pad2 bit (9), 1 125 1 126 2 cpu_no bit (3), /* CPU number */ 1 127 1 128 2 delta bit (6), /* tally modification DELTA */ 1 129 1 130 1 131 /* WORD (3) */ 1 132 1 133 2 word3 bit (18), 1 134 1 135 2 tsr_stat, /* TSR STATUS for 1,2,&3 word instructions */ 1 136 3 tsna, /* Word 1 status */ 1 137 4 prn bit (3), /* Word 1 PR number */ 1 138 4 prv bit (1), /* Word 1 PR valid bit */ 1 139 3 tsnb, /* Word 2 status */ 1 140 4 prn bit (3), /* Word 2 PR number */ 1 141 4 prv bit (1), /* Word 2 PR valid bit */ 1 142 3 tsnc, /* Word 3 status */ 1 143 4 prn bit (3), /* Word 3 PR number */ 1 144 4 prv bit (1), /* Word 3 PR valid bit */ 1 145 1 146 2 tpr_tbr bit (6), /* TPR.TBR field */ 1 147 1 148 1 149 /* WORD (4) */ 1 150 1 151 2 ilc bit (18), /* INSTRUCTION COUNTER */ 1 152 1 153 2 ir, /* INDICATOR REGISTERS */ 1 154 3 zero bit (1), /* zero indicator */ 1 155 3 neg bit (1), /* negative indicator */ 1 156 3 carry bit (1), /* carryry indicator */ 1 157 3 ovfl bit (1), /* overflow indicator */ 1 158 3 eovf bit (1), /* eponent overflow */ 1 159 3 eufl bit (1), /* exponent underflow */ 1 160 3 oflm bit (1), /* overflow mask */ 1 161 3 tro bit (1), /* tally runout */ 1 162 3 par bit (1), /* parity error */ 1 163 3 parm bit (1), /* parity mask */ 1 164 3 bm bit (1), /* ^bar mode */ 1 165 3 tru bit (1), /* truncation mode */ 1 166 3 mif bit (1), /* multi-word instruction mode */ 1 167 3 abs bit (1), /* absolute mode */ 1 168 3 hex bit (1), /* hexadecimal exponent mode */ 1 169 3 pad bit (3), 1 170 1 171 1 172 /* WORD (5) */ 1 173 1 174 2 ca bit (18), /* COMPUTED ADDRESS */ 1 175 1 176 2 cu, /* CONTROL UNIT STATUS */ 1 177 3 rf bit (1), /* on first cycle of repeat instr */ 1 178 3 rpt bit (1), /* repeat instruction */ 1 179 3 rd bit (1), /* repeat double instruction */ 1 180 3 rl bit (1), /* repeat link instruciton */ 1 181 3 pot bit (1), /* IT modification */ 1 182 3 pon bit (1), /* return type instruction */ 1 183 3 xde bit (1), /* XDE from Even location */ 1 184 3 xdo bit (1), /* XDE from Odd location */ 1 185 3 poa bit (1), /* operation preparation */ 1 186 3 rfi bit (1), /* tells CPU to refetch instruction */ 1 187 3 its bit (1), /* ITS modification */ 1 188 3 if bit (1), /* fault occured during instruction fetch */ 1 189 1 190 2 cpu_tag bit (6)) unaligned, /* computed tag field */ 1 191 1 192 1 193 /* WORDS (6,7) */ 1 194 1 195 2 even_inst bit (36), /* even instruction of faulting pair */ 1 196 1 197 2 odd_inst bit (36); /* odd instruction of faulting pair */ 1 198 1 199 1 200 1 201 1 202 1 203 1 204 /* ALTERNATE SCU DECLARATION */ 1 205 1 206 1 207 dcl 1 scux based (scup) aligned, 1 208 1 209 (2 pad0 bit (36), 1 210 1 211 2 fd, /* GROUP II FAULT DATA */ 1 212 3 isn bit (1), /* illegal segment number */ 1 213 3 ioc bit (1), /* illegal op code */ 1 214 3 ia_am bit (1), /* illegal address - modifier */ 1 215 3 isp bit (1), /* illegal slave procedure */ 1 216 3 ipr bit (1), /* illegal procedure */ 1 217 3 nea bit (1), /* non existent address */ 1 218 3 oobb bit (1), /* out of bounds */ 1 219 3 pad bit (29), 1 220 1 221 2 pad2 bit (36), 1 222 1 223 2 pad3a bit (18), 1 224 1 225 2 tsr_stat (0:2), /* TSR STATUS as an ARRAY */ 1 226 3 prn bit (3), /* PR number */ 1 227 3 prv bit (1), /* PR valid bit */ 1 228 1 229 2 pad3b bit (6)) unaligned, 1 230 1 231 2 pad45 (0:1) bit (36), 1 232 1 233 2 instr (0:1) bit (36); /* Instruction ARRAY */ 1 234 1 235 1 236 1 237 /* END INCLUDE FILE mc.incl.pl1 */ 131 132 133 end resolve_linkage_error; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 02/06/84 0948.4 resolve_linkage_error.pl1 >spec>on>6596>resolve_linkage_error.pl1 131 1 12/15/83 1100.4 mc.incl.pl1 >ldd>include>mc.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. addr builtin function dcl 31 ref 100 112 112 114 argl 000100 automatic fixed bin(17,0) dcl 19 set ref 80* 88 88 91 91 95 95 argno 000101 automatic fixed bin(17,0) dcl 19 set ref 79* 80* based_entry_overlay based structure level 1 dcl 58 baseno builtin function dcl 31 ref 121 baseptr builtin function dcl 31 ref 115 bchr based char unaligned dcl 19 set ref 88* 91* 95* ca 5 based bit(18) level 2 in structure "scu" packed unaligned dcl 1-56 in procedure "rle" ref 115 ca 1 based bit(18) level 2 in structure "link" packed unaligned dcl 51 in procedure "rle" set ref 122* com_err_ 000012 constant entry external dcl 64 ref 95 109 117 125 com_err_$suppress_name 000014 constant entry external dcl 64 ref 83 condinfo 000122 automatic structure level 1 dcl 38 set ref 112 112 condition_name 3 000122 automatic varying char(32) level 2 dcl 38 set ref 113 cu_$arg_ptr 000032 constant entry external dcl 64 ref 80 cu_$stack_frame_ptr 000030 constant entry external dcl 64 ref 75 cv_entry_ 000020 constant entry external dcl 64 ref 88 cv_ptr_ 000022 constant entry external dcl 64 ref 91 ec 000121 automatic fixed bin(35,0) dcl 19 set ref 77* 79 80* 81 88* 89 90 91* 92 95* 112* 124* 125 125* entry_to_use 000106 automatic entry variable dcl 19 set ref 88* 100 error_table_$no_linkage 000010 external static fixed bin(35,0) dcl 62 ref 90 faultsp 000114 automatic pointer dcl 19 set ref 107* 108 112* 128 find_condition_frame_ 000016 constant entry external dcl 64 ref 107 find_condition_info_ 000026 constant entry external dcl 64 ref 112 ft 0(30) based bit(6) level 2 packed unaligned dcl 51 set ref 116 123* got_entry 000120 automatic bit(1) unaligned dcl 19 set ref 78* 82 87* 105 link based structure level 1 dcl 51 link_pair_ptr 000112 automatic pointer dcl 19 set ref 115* 116 117* 121 122 123 mc based structure level 1 dcl 1-12 mcptr 000122 automatic pointer level 2 dcl 38 set ref 114 124* null builtin function dcl 31 ref 88 88 101 108 p 000104 automatic pointer dcl 19 set ref 91* 100* 101 121 122 prepare_mc_restart_ 000024 constant entry external dcl 64 ref 124 procedure_ptr based pointer level 2 dcl 58 ref 100 ptr builtin function dcl 31 ref 115 rel builtin function dcl 31 ref 122 scu based structure level 1 dcl 1-56 in procedure "rle" scu 30 based bit(36) array level 2 in structure "mc" packed unaligned dcl 1-12 in procedure "rle" set ref 114 scup 000154 automatic pointer dcl 1-54 set ref 114* 115 115 stackp 000102 automatic pointer dcl 19 set ref 75* 107* 128* tbr based bit(18) level 2 packed unaligned dcl 51 set ref 121* tp 000116 automatic pointer dcl 19 set ref 80* 88 91 95 tpr 2 based structure level 2 packed unaligned dcl 1-56 tsr 2(03) based bit(15) level 3 packed unaligned dcl 1-56 ref 115 version 2 000122 automatic fixed bin(17,0) level 2 dcl 38 set ref 76* NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. abx internal static fixed bin(17,0) initial dcl 1-42 apx internal static fixed bin(17,0) initial dcl 1-42 bbx internal static fixed bin(17,0) initial dcl 1-42 bpx internal static fixed bin(17,0) initial dcl 1-42 instr based structure array level 1 dcl 33 lbx internal static fixed bin(17,0) initial dcl 1-42 lpx internal static fixed bin(17,0) initial dcl 1-42 mcp automatic pointer dcl 1-10 sbx internal static fixed bin(17,0) initial dcl 1-42 scux based structure level 1 dcl 1-207 spx internal static fixed bin(17,0) initial dcl 1-42 NAMES DECLARED BY EXPLICIT CONTEXT. USAGE 000145 constant label dcl 83 ref 105 loop 000346 constant label dcl 107 ref 129 nent 000270 constant label dcl 95 ref 92 101 resolve_linkage_error 000102 constant entry external dcl 11 rle 000073 constant entry external dcl 11 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 746 1002 601 756 Length 1202 601 34 164 144 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME rle 172 external procedure is an external procedure. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME rle 000100 argl rle 000101 argno rle 000102 stackp rle 000104 p rle 000106 entry_to_use rle 000112 link_pair_ptr rle 000114 faultsp rle 000116 tp rle 000120 got_entry rle 000121 ec rle 000122 condinfo rle 000154 scup rle THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out_desc call_ext_out return ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. com_err_ com_err_$suppress_name cu_$arg_ptr cu_$stack_frame_ptr cv_entry_ cv_ptr_ find_condition_frame_ find_condition_info_ prepare_mc_restart_ THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. error_table_$no_linkage LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 11 000072 75 000107 76 000115 77 000117 78 000120 79 000121 80 000124 81 000141 82 000143 83 000145 85 000200 87 000201 88 000203 89 000235 90 000237 91 000242 92 000265 93 000267 95 000270 96 000332 98 000333 100 000334 101 000336 104 000342 105 000344 107 000346 108 000357 109 000363 110 000416 112 000417 113 000434 114 000441 115 000444 116 000457 117 000464 119 000523 121 000524 122 000527 123 000531 124 000533 125 000544 126 000575 128 000576 129 000600 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved