COMPILATION LISTING OF SEGMENT azm_display_mc_ Compiled by: Multics PL/I Compiler, Release 28d, of October 4, 1983 Compiled at: Honeywell Multics Op. - System M Compiled on: 11/19/84 1123.4 mst Mon Options: optimize map 1 /* *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Information Systems Inc., 1983 * 4* * * 5* *********************************************************** */ 6 7 8 azm_display_mc_: proc (P_sci_ptr, P_amu_info_ptr, P_mc_ptr, P_arg_bits_ptr, P_code); 9 10 /* format: style4,delnl,insnl,ifthenstmt,indnoniterend,ifthendo,ifthen,^thendo */ 11 12 /* Routine to display machine conditions or portions of machine condition 13* frames for analyze_multics */ 14 15 /* 16* Written December 1981 by Rich Coppola 17* Modified 19 Jan 84 by BLB to call a temp seg with sci_ptr and not amu_info.sci_ptr. 18* Modified 29 Sept 84 by BLB to check all words of SCU data for zeros before aborting. (azm error 11). 19* Modified Sept 84 by R. A. Fawcett to remove some of the blank lines in output 20* Modified 01 Oct 84 by BLB to stop using decimal_date_time_. 21**/ 22 /* PARAMETERS */ 23 24 dcl P_amu_info_ptr ptr; /* ptr to amu info */ 25 dcl P_mc_ptr ptr; /* ptr to thr mc BLOCK */ 26 dcl P_sci_ptr ptr; 27 dcl P_arg_bits_ptr ptr; /* ptr to bit array defining the type of display desired */ 28 dcl P_code fixed bin (35); /* error code if any */ 29 30 31 /* EXTERNAL ENTRIES */ 32 dcl db_print entry (ptr, char (32), ptr, char (*) aligned, fixed bin, fixed bin, ptr, fixed bin, fixed bin); 33 dcl iox_$user_output ptr ext static; 34 dcl cv_bin_$oct entry (fixed bin, char (12) aligned); 35 dcl ( 36 ioa_, 37 ioa_$rsnnl 38 ) entry options (variable); 39 40 dcl amu_$get_name entry (ptr, ptr) returns (char (*)); 41 dcl convert_status_code_ entry (fixed bin (35), char (8) aligned, char (100) aligned); 42 dcl ssu_$get_temp_segment entry (ptr, char(*), ptr); 43 dcl ssu_$release_temp_segment entry (ptr, ptr); 44 45 46 /* AUTOMATIC */ 47 48 dcl error_code_mc fixed bin (35); 49 dcl iocb_name char (32); 50 dcl iocbp ptr; 51 dcl (by_name, ref_name) char (168); 52 dcl eis_info_valid bit (1); 53 dcl (line1, line2) char (80) varying; 54 dcl (line1_sw, line2_sw) bit (1) init ("0"b); 55 dcl at_by_wd char (2); 56 dcl cvbinbuf char (12) aligned; 57 dcl aligned_error_message char (100) aligned; 58 dcl (i, j) fixed bin; 59 dcl code fixed bin (35); 60 dcl time char (24); 61 dcl tsrpr bit (1); 62 dcl print_ia bit (1); 63 dcl (byptr, refptr) ptr; 64 dcl (lnpos, flt_lng, inst6) fixed bin; 65 dcl (no_scu_data, non_val_flt) bit (1); 66 dcl fault_index fixed bin (6) unsigned; 67 dcl temp_index fixed bin; 68 dcl fltdtab (0:35) bit (1) based (byptr) unaligned; 69 dcl (flt_ln, FLT_LN, IA_LN) char (100); 70 dcl flt_bf char (24) varying; 71 dcl sci_ptr ptr; 72 73 dcl 1 pwrd based (PR_ptr) aligned, 74 2 w1 fixed bin (35), 75 2 w2 fixed bin (35); 76 77 dcl PTR_STR char (24) aligned; 78 dcl PR_ptr ptr; /* temp ptr for PR display */ 79 80 81 dcl TAG_ptr ptr; /* pointer to tag table */ 82 dcl tag_prt bit (1) init ("0"b); 83 dcl tag_ char (4) init (""); 84 85 dcl 1 TAG (64) based (TAG_ptr), 86 2 code char (4) unal, 87 2 pad bit (8) unal, 88 2 chain bit (1); 89 dcl (addr, addrel, baseptr, bin, fixed, 90 length, hbound, lbound, null, rtrim, 91 string, substr, unspec) builtin; 92 93 dcl cleanup condition; 94 95 96 97 /* CONSTANTS */ 98 99 dcl TAG_table (8) char (40) int static options (constant) 100 init (/* tag table */ " au qu du ic al ql dl ", "x0 x1 x2 x3 x4 x5 x6 x7 ", 101 "n* aau* aqu* ailtg ic* aal* aql* ailtg ", "0* a1* a2* a3* a4* a5* a6* a7* a", 102 "fi itp iltg its sd scr f2 f3 ", "ci i sc ad di dic aid idc a", 103 "*n *au *qu iltg *ic *al *ql iltg ", "*0 *1 *2 *3 *4 *5 *6 *7 "); 104 105 106 dcl cpul (0:7) char (1) int static options (constant) init ("a", "b", "c", "d", "e", "f", "g", "h"); 107 dcl ptrfmt char (44) int static options (constant) init ("PR^o (^[ap^;ab^;bp^;bb^;lp^;lb^;sp^;sb^]) - "); 108 109 dcl port_name (4) char (3) int static options (constant) init ("A: ", "B: ", "C: ", "D: "); 110 111 dcl FAULT_TYPES (36) char (15) var int static options (constant) 112 init ("ILL OP", "ILL MOD", "ILL SLV", "ILL PROC", "NEM", "OOB", "WRT INH", "PROC PAR-UPR", "PROC PAR-LWR", 113 "$CON A", "$CON B", "$CON C", "$CON D", "ONC (DA ERR1)", "ONC (DA ERR2)", "", "", "", "", "", "", "", "", "", 114 "", "", "", "", "", "", "", "", "CACHE-PAR DIR", "CACHE-PAR STR", "CACHE-PAR IA", "CACHE-PAR BLK"); 115 116 117 dcl SC_IA_TYPES (1:15) char (42) var int static options (constant) 118 init ("Unassigned (01)", "Non-existent Address (02)", "Stop on Condition (03)", "Unassigned (04)", 119 "Data Parity, Store to SC (05)", "Data Parity in Store (06)", "Data Parity in Store AND Store to SC (07)", 120 "Not Control (10)", "Port Not Enabled (11)", "Illegal Command (12)", "Store Not Ready ( 13)", 121 "ZAC Parity, Active Module to SC (14)", "Data Parity, Active Module to SC (15)", "ZAC Parity, SC to Store (16)", 122 "Data Parity, SC to Store (17)"); 123 124 125 dcl EXT_FAULT_TYPES (15) char (39) var int static options (constant) 126 init ("Bffr. Ovflw - Port A", "Bffr. Ovflw - Port B", "Bffr. Ovflw - Port C", "Bffr. Ovflw - Port D", 127 "Bffr. Ovflw - Primary Dir", "Write Notify Parity Error on ANY Port", "Dup. Dir. LVL 0 Parity Error", 128 "Dup. Dir. LVL 1 Parity Error", "Dup. Dir. LVL 2 Parity Error", "Dup. Dir. LVL 3 Parity Error", 129 "Dup. Dir. Multi Match Error", "PTW Ass. Mem. Parity Error", "PTW Ass. Mem. Match Error", 130 "SDW Ass. Mem. Parity Error", "SDW Ass. Mem. Match Error"); 131 132 dcl ill_act (0:15) char (37) varying int static options (constant) 133 init ("...", "Unassigned", "Non Existent Address", "Fault on Condition", "Unassigned", 134 "Data Parity (Store -> SCU)", "Data Parity in Store", "Data Parity (Store -> SCU & in Store)", "Not Control", 135 "Port Not Enabled", "Illegal Command", "Store Not Ready", "ZAC Parity (Processor -> SCU)", 136 "Data Parity (Processor -> SCU)", "ZAC parity (SCU -> Store)", "Data Parity (SCU -> Store)"); 137 138 dcl indrs (18:31) char (4) varying int static options (constant) 139 init ("zero", "neg", "cary", "ovfl", "eovf", "eufl", "oflm", "tro", "par", "parm", "^bar", "tru", "mif", "abs"); 140 141 dcl APU (18:32) char (6) varying int static options (constant) 142 init ("priv", "xsf", "sdwamm", "sd-on", "ptwamm", "pt-on", "pi-ap", "dsptw", "sdwnp", "sdwp", "ptw", "ptw2", 143 "fap", "fanp", "fabs"); 144 145 dcl CU (18:29) char (3) varying int static options (constant) 146 init ("rf", "rpt", "rd", "rl", "pot", "pon", "xde", "xdo", "itp", "rfi", "its", "fif"); 147 148 dcl g1and7flts (5) bit (6) int static options (constant) unaligned init ("01"b3, "11"b3, "21"b3, "31"b3, "37"b3); 149 150 dcl grp1flt (0:19) char (24) varying int static options (constant) 151 init ("Illegal Ring Order", "Not in Execute Bracket", "Execute Bit off", "Not In Read Bracket", "Read Bit Off", 152 "Not In Write Bracket", "Write Bit Off", "Not A Gate", "Not In Call Bracket", "Outward Call", 153 "Bad Outward Call", "Inward Return", "Cross Ring Transfer", "Ring Alarm", "Associative Memory", 154 "Out of Segment Bounds", "Processor Parity Upper", "Processor Parity Lower", "SC To Proc. Seq. Error 1", 155 "SC To Proc. Seq. Error 2"); 156 157 dcl grp2flt (0:6) char (24) varying int static options (constant) 158 init ("Illegal Segment Number", "Illegal Op Code", "Illegal Address & Mod", "Illegal Slave Procedure", 159 "Illegal Procedure", "Non Existent Address", "Out Of Bounds"); 160 161 dcl flt_int_typ (0:63) char (24) varying int static options (constant) 162 init ("...", "Shutdown", "...", "Store", "Bulk Store 0 Term", "MME 1", "...", "Fault Tag 1", "IOM 0 Overhead", 163 "Timer Runout", "IOM 1 Overhead", "Command", "IOM 2 Overhead", "Derail", "IOM 3 Overhead", "Lockup", 164 "IOM 0 Terminate Ch 40-77", "Connect", "IOM 1 Terminate Ch 40-77", "Parity", "Bulk Store 1 Term", 165 "Illegal Procedure", "...", "Op Not Complete", "IOM 0 Terminate", "Startup", "IOM 1 Terminate", "Overflow", 166 "IOM 2 Terminate", "Divide Check", "IOM 3 Terminate", "Execute", "IOM 0 Marker Ch 40-77", "(DF0) Segment", 167 "IOM 1 Marker Ch 40-77", "(DF1) Page", "...", "Directed Fault 2", "...", "Directed Fault 3", "IOM 0 Marker", 168 "Access Violation", "IOM 1 Marker", "MME 2", "IOM 2 Marker", "MME 3", "IOM 3 Marker", "MME 4", "...", 169 "(FT2) Linkage", "...", "Fault Tag 3", "...", "...", "...", "...", "IOM 0 Special", "...", "IOM 1 Special", 170 "...", "IOM 2 Special", "...", "IOM 3 Special", "Trouble"); 171 172 173 174 175 call setup; 176 on condition(cleanup) begin; 177 if arg_bits_def.dump then call ssu_$release_temp_segment (sci_ptr, mcp); 178 end; 179 180 if arg_bits_def.dump then do; /* display the mc from the bos dump */ 181 182 call init_dump_display; 183 if code ^= 0 then do; 184 P_code = code; 185 return; 186 end; 187 end; 188 else do; /* set up the vars for the scu data */ 189 scup = addr (mc.scu); 190 call init_scu_data; 191 192 if no_scu_data then do; 193 arg_bits_def.mc_stored = "0"b; 194 call ioa_ ("No SCU data stored."); 195 return; 196 end; 197 else arg_bits_def.mc_stored = "1"b; 198 end; 199 200 start_display: 201 if arg_bits_def.all then do; /* display all the mc from the given pointer */ 202 203 call display_pr_regs_; 204 if code ^= 0 then goto error_return; 205 call display_regs_; 206 if code ^= 0 then goto error_return; 207 call ioa_ ("^a^[^/^a^]", FLT_LN,print_ia, IA_LN); 208 call display_scu_; 209 if code ^= 0 then goto error_return; 210 call display_misc_; 211 if code ^= 0 then goto error_return; 212 if eis_info_valid then do; 213 call display_eis_info_; 214 if code ^= 0 then goto error_return; 215 end; 216 return; 217 end; 218 219 call ioa_ ("^a^[^/^a^]", FLT_LN,print_ia, IA_LN); 220 if arg_bits_def.prs then do; 221 call display_pr_regs_; 222 if code ^= 0 then goto error_return; 223 goto bypass_prs; 224 end; 225 do i = 0 to 7; 226 if arg_bits_def.pr (i) then call print_pr_reg (i); 227 if code ^= 0 then goto error_return; 228 end; 229 230 bypass_prs: 231 if arg_bits_def.regs then do; 232 call display_regs_; 233 if code ^= 0 then goto error_return; 234 goto by_pass_reg; 235 end; 236 do i = 0 to 7; 237 if xreg (i) then call display_x_reg (i); 238 end; 239 if arg_bits_def.areg then call display_aq_reg ("1"b); 240 if arg_bits_def.qreg then call display_aq_reg ("0"b); 241 242 by_pass_reg: 243 if arg_bits_def.scu then do; 244 call display_scu_; 245 if code ^= 0 then goto error_return; 246 call display_mc_code; 247 goto bypass_ppr_tpr; 248 end; 249 else do; 250 if arg_bits_def.ppr then call print_ppr; 251 if arg_bits_def.tpr then call print_tpr; 252 if arg_bits_def.inst then call print_inst; 253 end; 254 255 bypass_ppr_tpr: 256 if arg_bits_def.mis then do; 257 call display_misc_; 258 goto bypass_misc; 259 end; 260 else do; 261 if arg_bits_def.mc_err then call display_mc_code; 262 if arg_bits_def.flt then do; 263 call interpret_fault_reg (mc.fault_reg); 264 if mc.cpu_type = 1 then 265 if mc.ext_fault_reg ^= "0"b then call interpret_ext_fault_reg (mc.ext_fault_reg); 266 end; 267 if arg_bits_def.tm then call display_time; 268 end; 269 270 bypass_misc: 271 if arg_bits_def.eis then do; 272 call display_eis_info_; 273 if code ^= 0 then goto error_return; 274 end; 275 276 if arg_bits_def.dump then call ssu_$release_temp_segment (sci_ptr, mcp); 277 return; 278 279 azm_display_mc_$regs_only: 280 entry (P_sci_ptr, P_amu_info_ptr, P_mc_ptr, P_arg_bits_ptr, P_code); 281 call setup; 282 call display_pr_regs_; 283 if code ^= 0 then goto error_return; 284 call display_regs_; 285 if code ^= 0 then goto error_return; 286 P_code = 0; 287 return; 288 289 setup: 290 proc; 291 292 293 amu_info_ptr = P_amu_info_ptr; 294 sci_ptr = P_sci_ptr; 295 arg_bits_ptr = P_arg_bits_ptr; 296 mcp = P_mc_ptr; 297 iocbp = iox_$user_output; 298 P_code, code = 0; 299 300 end setup; 301 302 303 304 init_scu_data: 305 proc; 306 307 308 scup = addr (mc.scu); 309 no_scu_data, non_val_flt, eis_info_valid, print_ia = "0"b; 310 if ^arg_bits_def.dump then 311 if string(scu) = "0"b then do; 312 no_scu_data = "1"b; 313 return; 314 end; 315 inst6 = 6; 316 fault_index = fixed (scu.fi_num || scu.fi_flag, 6); 317 FLT_LN, flt_ln, flt_bf = ""; 318 tsrpr = "0"b; 319 flt_bf = flt_int_typ (fault_index); 320 if substr (flt_bf, 1, 3) = "..." then 321 non_val_flt = "1"b; 322 else do; 323 flt_lng = length (flt_int_typ (fault_index)); 324 substr (flt_ln, 1, flt_lng) = substr (flt_bf, 1, flt_lng); 325 byptr = addrel (scup, 1); 326 if fltdtab (35) = "1"b then do; 327 substr (flt_ln, flt_lng + 2, 5) = "Fault"; 328 lnpos = flt_lng + 8; 329 do i = 1 to hbound (g1and7flts, 1); /* If grp 1 or 7 faults, don't print out tsr|ca */ 330 if unspec (fault_index) = g1and7flts (i) then tsrpr = "1"b; 331 end; 332 end; 333 else do; 334 substr (flt_ln, flt_lng + 2, 9) = "Interrupt"; 335 lnpos = flt_lng + 12; 336 tsrpr = "1"b; /* don't print out tsr|ca for interrupts */ 337 end; 338 temp_index = fault_index; 339 call cv_bin_$oct (temp_index, cvbinbuf); 340 substr (flt_ln, lnpos, 4) = "(" || substr (cvbinbuf, 11, 2) || ")"; 341 lnpos = lnpos + 4; 342 j = lnpos; 343 do i = 0 to hbound (grp1flt, 1); 344 if fltdtab (i) then do; 345 if substr (flt_ln, 1, 5) = "Store" | substr (flt_ln, 1, 12) = "Illegal Proc" then 346 if i <= 6 then 347 call ioa_$rsnnl ("^a, ^a", flt_ln, j, flt_ln, grp2flt (i)); 348 else ; 349 else call ioa_$rsnnl ("^a, ^a", flt_ln, j, flt_ln, grp1flt (i)); 350 end; 351 end; 352 FLT_LN = flt_ln; 353 end; 354 if scu.port_stat.ial ^= "0"b then do; /* display illegal action lines if present */ 355 call ioa_$rsnnl ("Illegal Action Code (^o) - ^a", IA_LN, j, fixed (scu.port_stat.ial, 4), 356 ill_act (fixed (scu.port_stat.ial, 4))); 357 print_ia = "1"b; 358 end; 359 if tsrpr then 360 at_by_wd = "At"; /* if not printing tsr */ 361 else at_by_wd = "By"; 362 if scu.ir.mif then 363 eis_info_valid = "1"b; 364 else eis_info_valid = "0"b; 365 366 return; 367 368 end init_scu_data; 369 370 371 372 /* dump - internal proc to display registers saved at time of dump */ 373 374 init_dump_display: 375 proc; 376 call ssu_$get_temp_segment (sci_ptr, "azm_display_mc", mcp); 377 call ioa_ ("^/Bootload CPU Registers at Time of Dump:"); 378 dumpptr = P_mc_ptr; 379 unspec (mc.prs) = unspec (dump.prs); 380 unspec (mc.regs) = unspec (dump.regs); 381 unspec (mc.scu) = unspec (dump.misc_registers.scu); 382 unspec (mc.mask) = unspec (dump.misc_registers.mcm); 383 mc.fault_reg = dump.faultreg; 384 mc.ext_fault_reg = dump.ext_fault_reg; 385 mc.eis_info = dump.ptrlen; 386 call ioa_ ("Descriptor Segment Base Register: ^12.3b ^12.3b", substr (dump.dbr, 1, 36), 387 substr (dump.dbr, 37, 36)); 388 if dump.modereg ^= "0"b then call ioa_ ("Mode Register: ^12.3b", dump.modereg); 389 if dump.cmodereg ^= "0"b then call ioa_ ("Cache Mode Register: ^12.3b", dump.cmodereg); 390 if dump.bar ^= "0"b then call ioa_ ("Base Address Register: ^12.3b", dump.bar); 391 call init_scu_data; 392 return; 393 end init_dump_display; 394 395 396 397 /* display_regs - internal proc to display processor registers included in machine conditions */ 398 399 400 display_regs_: 401 proc; 402 403 404 call ioa_ ("Processor Registers:"); 405 call ioa_ ("^3xX0 - ^o X1 - ^o X2 - ^o X3 - ^o^/^3xX4 - ^o X5 - ^o X6 - ^o X7 - ^o", fixed (mc.regs.x (0), 18), 406 fixed (mc.regs.x (1), 18), fixed (mc.regs.x (2), 18), fixed (mc.regs.x (3), 18), fixed (mc.regs.x (4), 18), 407 fixed (mc.regs.x (5), 18), fixed (mc.regs.x (6), 18), fixed (mc.regs.x (7), 18)); 408 409 call ioa_ ("^3xA Register - ^12.3b Q Register - ^12.3b E Register - ^o", mc.regs.a, mc.regs.q, 410 fixed (mc.regs.e, 8)); 411 412 call ioa_ ("^3xTimer Register - ^9.3b Ring Alarm Register - ^1.3b", mc.t, mc.ralr); 413 414 return; 415 end display_regs_; 416 display_x_reg: 417 proc (i); 418 dcl i fixed bin; 419 call ioa_ ("X^1d ^o", i, fixed (mc.regs.x (i), 18)); 420 end display_x_reg; 421 display_aq_reg: 422 proc (a); 423 dcl a bit (1); 424 if a then 425 call ioa_ ("A REG ^12.3b", mc.regs.a); 426 else call ioa_ ("Q REG ^12.3b", mc.regs.q); 427 end display_aq_reg; 428 429 display_misc_: 430 proc; 431 432 if mc.mask ^= "0"b then 433 call ioa_ ("Mem Controller Mask: ^12.3b ^12.3b", substr (mask, 1, 36), substr (mask, 37, 36)); 434 call display_mc_code; 435 call interpret_fault_reg (mc.fault_reg); 436 if mc.cpu_type = 1 then 437 if mc.ext_fault_reg ^= "0"b then call interpret_ext_fault_reg (mc.ext_fault_reg); 438 call display_time; 439 440 441 end display_misc_; 442 443 display_time: 444 proc; 445 446 dcl dt_form char(41) int static options(constant) init( 447 "^yc-^my-^dm ^Hd:^MH:^SM.^US ^xxxxza^xxxda"); 448 dcl date_time_$format entry(char(*), fixed bin(71), char(*), char(*)) returns(char(250) var); 449 450 call ioa_ ("MC Fault Time: ^a (^18.3b)", 451 date_time_$format(dt_form, fixed (mc.fault_time, 71),"",""), mc.fault_time); 452 end display_time; 453 454 455 display_mc_code: 456 proc; 457 if mc.errcode ^= 0 then do; 458 error_code_mc = mc.errcode; 459 call convert_status_code_ (error_code_mc, (""), aligned_error_message); 460 call ioa_ ("MC.ERRCODE:^/^a", rtrim (aligned_error_message)); 461 end; 462 end display_mc_code; 463 464 /* display_eis_info, internal proc to display Eis pointers and lengths */ 465 466 display_eis_info_: 467 proc; 468 dcl eis_info_ptr ptr; 469 dcl 1 eis_info_fmt based (eis_info_ptr), 470 2 mbz1 bit (9) unal, 471 2 neg_over bit (1) unal, 472 2 pd1 bit (2) unal, 473 2 char_tally bit (24) unal, 474 2 empty_word bit (36) unal, 475 2 dec1, 476 3 cur_wd_off bit (18) unal, 477 3 cur_char_off bit (2) unal, 478 3 cur_bit_off bit (4) unal, 479 3 pd2 bit (1) unal, 480 3 data_mode bit (2) unal, 481 3 pd3 bit (3) unal, 482 3 ingore_seg bit (1) unal, 483 3 first_time_used bit (1) unal, 484 3 active bit (1) unal, 485 3 pd4 bit (3) unal, 486 3 level_count bit (9) unal, 487 3 pd5 bit (3) unal, 488 3 residue fixed bin (23) signed unal, 489 2 dec2, 490 3 cur_wd_off bit (18) unal, 491 3 cur_char_off bit (2) unal, 492 3 cur_bit_off bit (4) unal, 493 3 d2pd1 bit (1) unal, 494 3 data_mode bit (2) unal, 495 3 d2pd2 bit (3) unal, 496 3 rpt_cycle bit (1) unal, 497 3 or_d2du_first bit (1) unal, 498 3 active bit (1) unal, 499 3 d2pd3 bit (1) unal, 500 3 first_time bit (1) unal, 501 3 d2du bit (1) unal, 502 3 d2mbz bit (9) unal, 503 3 d2pd4 bit (3) unal, 504 3 residue fixed bin (23) signed unal, 505 2 dec3, 506 3 cur_wd_off bit (18) unal, 507 3 cur_char_off bit (2) unal, 508 3 cur_bit_off bit (4) unal, 509 3 d3pd1 bit (1) unal, 510 3 data_mode bit (2) unal, 511 3 d3pd2 bit (3) unal, 512 3 rpt_cycle bit (1) unal, 513 3 first_time bit (1) unal, 514 3 active bit (1) unal, 515 3 jump_add_ind bit (3) unal, 516 3 mbz bit (9) unal, 517 3 d3pd3 bit (3) unal, 518 3 residue fixed bin (23) signed unal; 519 dcl three_desc bit (3) init ("100"b) static options (constant); 520 521 call ioa_ ("EIS Pointers and Lengths:^/"); 522 523 eis_info_ptr = addr (mc.eis_info); 524 525 if eis_info_fmt.char_tally ^= "0"b then call ioa_ ("^5xTally count = ^8.3b", eis_info_fmt.char_tally); 526 if dec1.active then do; 527 528 call ioa_ ("^-DESC1 active "); 529 if scu.tsr_stat.tsna.prv then 530 call ioa_ ("^-^2xUsing PR^1.3b segment number ^o", scu.tsr_stat.tsna.prn, 531 substr (unspec (mc.prs (fixed (scu.tsr_stat.tsna.prn, 3))), 4, 15)); 532 533 534 535 call ioa_ ("^-Cur word ptr ^6.3b char ^1.2b bit ^4b^/^-^2x data_mode ^d, level_count ^d, residue ^d", 536 dec1.cur_wd_off, dec1.cur_char_off, dec1.cur_bit_off, fixed (dec1.data_mode, 2), 537 fixed (dec1.level_count, 8), dec1.residue); 538 end; 539 else do; 540 call ioa_ ("^-DESC1 inactive"); 541 end; 542 if dec2.active then do; 543 call ioa_ ("^-DESC2 active "); 544 if scu.tsr_stat.tsnb.prv then 545 call ioa_ ("^-^2xUsing PR^1.3b segment number ^o", scu.tsr_stat.tsnb.prn, 546 substr (unspec (mc.prs (fixed (scu.tsr_stat.tsnb.prn, 3))), 4, 15)); 547 call ioa_ ("^-Cur word ptr ^6.3b, char ^2b ^4b^/^-^2x data_mode ^d, residue ^d", dec2.cur_wd_off, 548 dec2.cur_char_off, dec2.cur_bit_off, fixed (dec2.data_mode, 2), fixed (dec2.residue, 23)); 549 end; 550 else do; 551 call ioa_ ("^-DESC2 inactive"); 552 end; 553 if dec3.jump_add_ind ^= three_desc then goto eis_oct; 554 555 if dec3.active then do; 556 call ioa_ ("^-DESC3 active "); 557 if scu.tsr_stat.tsnc.prv then 558 call ioa_ ("^-^2xUsing PR^1.3b segment number ^o", scu.tsr_stat.tsnc.prn, 559 substr (unspec (mc.prs (fixed (scu.tsr_stat.tsnc.prn, 3))), 4, 15)); 560 561 call ioa_ ("^-Cur word ptr ^6.3b, char ^2b ^4b^/^-^2x residue ^d", dec3.cur_wd_off, dec3.cur_char_off, 562 dec3.cur_bit_off, fixed (dec3.residue, 23)); 563 564 end; 565 else do; 566 call ioa_ ("^-DESC3 inactive"); 567 end; 568 eis_oct: 569 if arg_bits_def.long then 570 call ioa_ ("^-^4(^w ^)^/^-^4(^w ^)", mc.eis_info (0), mc.eis_info (1), mc.eis_info (2), mc.eis_info (3), 571 mc.eis_info (4), mc.eis_info (5), mc.eis_info (6), mc.eis_info (7)); 572 return; 573 end display_eis_info_; 574 575 576 /* display_pr_regs - internal proc to display pointer registers */ 577 578 display_pr_regs_: 579 proc; 580 581 dcl i fixed bin; 582 call ioa_ ("Pointer Registers:"); 583 do i = 0 to 7; 584 call print_pr_reg (i); 585 end; 586 return; 587 end display_pr_regs_; 588 589 590 print_pr_reg: 591 proc (i); 592 dcl i fixed bin; 593 PR_ptr = addr (mc.prs (i)); 594 if PR_ptr -> its.its_mod ^= "100011"b then 595 call ioa_ (ptrfmt || "^w ^w", i, i + 1, pwrd.w1, pwrd.w2); 596 else do; 597 call ioa_$rsnnl (ptrfmt || "^p", PTR_STR, j, i, i + 1, mc.prs (i)); 598 599 call ioa_ ("^3x^22a ^a", PTR_STR, amu_$get_name (amu_info_ptr, mc.prs (i))); 600 if arg_bits_def.long then call ioa_ ("^-^5x^w ^w", pwrd.w1, pwrd.w2); 601 end; 602 end print_pr_reg; 603 604 605 606 607 608 display_scu_: 609 proc; 610 611 call ioa_ ("SCU Data:"); 612 613 if arg_bits_def.long then /* user wants octal dump too */ 614 call ioa_ ("^-^4(^w ^)^/^-^4(^w ^)^/", mc.scu (0), mc.scu (1), mc.scu (2), mc.scu (3), mc.scu (4), 615 mc.scu (5), mc.scu (6), mc.scu (7)); 616 617 if non_val_flt then call ioa_ ("Fault/Interrupt (^o), Undefined", fault_index); 618 call print_ppr; 619 if ^tsrpr then call print_tpr; 620 call ioa_ ("On: cpu ^a (#^o)", cpul (fixed (scu.cpu_no, 3)), fixed (scu.cpu_no, 3)); 621 flt_ln = ""; 622 byptr = addr (scu.ilc); /* display Indicator register if any bits present */ 623 do i = lbound (indrs, 1) to hbound (indrs, 1); 624 if fltdtab (i) then call ioa_$rsnnl ("^a ^a,", flt_ln, j, flt_ln, indrs (i)); 625 end; 626 if flt_ln ^= "" then do; 627 substr (flt_ln, j, 1) = " "; 628 call ioa_ ("Indicators: ^a", flt_ln); 629 flt_ln = ""; 630 end; 631 byptr = addr (scu.ppr); /* display interpreted APU status if any bits present */ 632 do i = lbound (APU, 1) to hbound (APU, 1); 633 if fltdtab (i) then call ioa_$rsnnl ("^a ^a,", flt_ln, j, flt_ln, APU (i)); 634 end; 635 if flt_ln ^= "" then do; 636 substr (flt_ln, j, 1) = " "; 637 call ioa_ ("APU Status: ^a", flt_ln); 638 flt_ln = ""; 639 end; 640 byptr = addr (scu.ca); /* display interprted CU status if any bits present */ 641 do i = lbound (CU, 1) to hbound (CU, 1); 642 if fltdtab (i) then call ioa_$rsnnl ("^a ^a,", flt_ln, j, flt_ln, CU (i)); 643 end; 644 645 TAG_ptr = addr (TAG_table); 646 i = fixed (scu.cpu_tag, 6); 647 648 if i ^= 0 then do; 649 tag_ = TAG.code (i + 1); 650 tag_prt = "1"b; 651 end; 652 653 if (flt_ln ^= "") | (tag_ ^= "") then do; 654 substr (flt_ln, j, 1) = " "; 655 call ioa_ ("CU Status: ^a ^[^/CT Hold: ^a^]", flt_ln, tag_prt, tag_); 656 end; 657 call print_inst; 658 659 return; 660 661 662 end display_scu_; 663 664 665 666 print_ppr: 667 proc; 668 byptr = addrel (baseptr (fixed (scu.ppr.psr, 18)), fixed (scu.ilc, 18)); 669 by_name = amu_$get_name (amu_info_ptr, byptr); 670 call ioa_ ("^a: ^p ^a", at_by_wd, byptr, by_name); 671 672 673 end print_ppr; 674 675 print_tpr: 676 proc; 677 refptr = addrel (baseptr (fixed (scu.tpr.tsr, 18)), fixed (scu.ca, 18)); 678 ref_name = amu_$get_name (amu_info_ptr, refptr); 679 call ioa_ ("Ref: ^p ^a", refptr, ref_name); 680 end print_tpr; 681 682 print_inst: 683 proc; 684 iocb_name = iocbp -> iocb.name; 685 call ioa_ ("Instructions: "); /* display Instructions (words 6 & 7) */ 686 call db_print (iocbp, iocb_name, addr (scu.even_inst), "i", inst6, 1, null, 0, 0); 687 call db_print (iocbp, iocb_name, addr (scu.odd_inst), "i", inst6 + 1, 1, null, 0, 0); 688 end print_inst; 689 690 /* Internal procedure to print fault reg data */ 691 692 interpret_fault_reg: 693 proc (fault_reg); 694 695 dcl fault_reg bit (36); 696 dcl (fault_no, break) fixed bin; 697 dcl 1 illeg_acts based (addr (fault_reg)), 698 ( 699 2 pad bit (16), 700 2 IA (4) bit (4), 701 2 pad1 bit (4) 702 ) unal; 703 704 if fault_reg = "0"b then return; 705 706 line1, line2 = ""; 707 708 do fault_no = 1 to 15; 709 if substr (fault_reg, fault_no, 1) = "1"b then do; 710 line1 = line1 || FAULT_TYPES (fault_no) || ", "; 711 line1_sw = "1"b; 712 end; 713 end; 714 715 break = 0; 716 do fault_no = 1 to 4 while (break = 0); /* do IAs now */ 717 if IA (fault_no) then do; 718 line2 = "Illegal Action on CPU Port " || port_name (fault_no); 719 line2 = line2 || SC_IA_TYPES (bin (IA (fault_no), 4)) || ", "; 720 line2_sw = "1"b; 721 break = 1; 722 end; 723 end; 724 725 do fault_no = 33 to 36; 726 if substr (fault_reg, fault_no, 1) = "1"b then do; 727 line1 = line1 || FAULT_TYPES (fault_no) || ", "; 728 line1_sw = "1"b; 729 end; 730 end; 731 732 if line1_sw then /* remove trailing comma & space */ line1 = substr (line1, 1, (length (line1) - 2)); 733 if line2_sw then line2 = substr (line2, 1, (length (line2) - 2)); 734 735 call ioa_ ("Fault Register: ^12.3b^[ (^a)^;^s^]^[^/^17t(^a)^]", fault_reg, line1_sw, line1, line2_sw, line2); 736 737 return; 738 739 740 741 end interpret_fault_reg; 742 743 744 interpret_ext_fault_reg: 745 proc (ext_fault_reg); 746 747 dcl ext_fault_reg bit (15); 748 dcl indx fixed bin; 749 750 line1 = ""; 751 do indx = 1 to 15; 752 if substr (ext_fault_reg, indx, 1) = "1"b then line1 = line1 || EXT_FAULT_TYPES (indx) || ", "; 753 end; 754 755 if line1 ^= "" then do; 756 line1 = substr (line1, 1, (length (line1) - 2)); 757 call ioa_ ("DPS8 Extended Fault Register: ^5.3b (^a)", ext_fault_reg, line1); 758 end; 759 760 761 return; 762 763 end interpret_ext_fault_reg; 764 765 error_return: 766 P_code = code; 767 return; 768 769 /* INCLUDE FILES */ 770 771 1 1 /* BEGIN INCLUDE FILE ..... iocb.incl.pl1 ..... 13 Feb 1975, M. Asherman */ 1 2 /* Modified 11/29/82 by S. Krupp to add new entries and to change 1 3* version number to IOX2. */ 1 4 /* format: style2 */ 1 5 1 6 dcl 1 iocb aligned based, /* I/O control block. */ 1 7 2 version character (4) aligned, /* IOX2 */ 1 8 2 name char (32), /* I/O name of this block. */ 1 9 2 actual_iocb_ptr ptr, /* IOCB ultimately SYNed to. */ 1 10 2 attach_descrip_ptr ptr, /* Ptr to printable attach description. */ 1 11 2 attach_data_ptr ptr, /* Ptr to attach data structure. */ 1 12 2 open_descrip_ptr ptr, /* Ptr to printable open description. */ 1 13 2 open_data_ptr ptr, /* Ptr to open data structure (old SDB). */ 1 14 2 reserved bit (72), /* Reserved for future use. */ 1 15 2 detach_iocb entry (ptr, fixed (35)),/* detach_iocb(p,s) */ 1 16 2 open entry (ptr, fixed, bit (1) aligned, fixed (35)), 1 17 /* open(p,mode,not_used,s) */ 1 18 2 close entry (ptr, fixed (35)),/* close(p,s) */ 1 19 2 get_line entry (ptr, ptr, fixed (21), fixed (21), fixed (35)), 1 20 /* get_line(p,bufptr,buflen,actlen,s) */ 1 21 2 get_chars entry (ptr, ptr, fixed (21), fixed (21), fixed (35)), 1 22 /* get_chars(p,bufptr,buflen,actlen,s) */ 1 23 2 put_chars entry (ptr, ptr, fixed (21), fixed (35)), 1 24 /* put_chars(p,bufptr,buflen,s) */ 1 25 2 modes entry (ptr, char (*), char (*), fixed (35)), 1 26 /* modes(p,newmode,oldmode,s) */ 1 27 2 position entry (ptr, fixed, fixed (21), fixed (35)), 1 28 /* position(p,u1,u2,s) */ 1 29 2 control entry (ptr, char (*), ptr, fixed (35)), 1 30 /* control(p,order,infptr,s) */ 1 31 2 read_record entry (ptr, ptr, fixed (21), fixed (21), fixed (35)), 1 32 /* read_record(p,bufptr,buflen,actlen,s) */ 1 33 2 write_record entry (ptr, ptr, fixed (21), fixed (35)), 1 34 /* write_record(p,bufptr,buflen,s) */ 1 35 2 rewrite_record entry (ptr, ptr, fixed (21), fixed (35)), 1 36 /* rewrite_record(p,bufptr,buflen,s) */ 1 37 2 delete_record entry (ptr, fixed (35)),/* delete_record(p,s) */ 1 38 2 seek_key entry (ptr, char (256) varying, fixed (21), fixed (35)), 1 39 /* seek_key(p,key,len,s) */ 1 40 2 read_key entry (ptr, char (256) varying, fixed (21), fixed (35)), 1 41 /* read_key(p,key,len,s) */ 1 42 2 read_length entry (ptr, fixed (21), fixed (35)), 1 43 /* read_length(p,len,s) */ 1 44 2 open_file entry (ptr, fixed bin, char (*), bit (1) aligned, fixed bin (35)), 1 45 /* open_file(p,mode,desc,not_used,s) */ 1 46 2 close_file entry (ptr, char (*), fixed bin (35)), 1 47 /* close_file(p,desc,s) */ 1 48 2 detach entry (ptr, char (*), fixed bin (35)); 1 49 /* detach(p,desc,s) */ 1 50 1 51 declare iox_$iocb_version_sentinel 1 52 character (4) aligned external static; 1 53 1 54 /* END INCLUDE FILE ..... iocb.incl.pl1 ..... */ 772 773 2 1 /* BEGIN INCLUDE FILE ... bos_dump.incl.pl1 ... */ 2 2 /* Modified 1 September 1976 */ 2 3 /* Modified 11/11/80 by J. A. Bush for the DPS8/70M CPU */ 2 4 /* Modified 6/12/81 by Rich Coppola to extend the dps8 extended fault reg to 2 5* 15 bits */ 2 6 /* Modified 02/23/81, W. Olin Sibert, to describe old and new FDUMP styles */ 2 7 2 8 2 9 dcl dumpptr ptr; /* pointer to following structure */ 2 10 2 11 dcl 1 dump based (dumpptr) aligned, /* header of dump by fdump */ 2 12 2 dump_header aligned like dump_header, 2 13 2 14 2 segs (1008), /* segment array */ 2 15 3 segno bit (18) unal, /* segment number */ 2 16 3 length bit (18) unal, /* length of segment in sector sized blocks */ 2 17 2 18 2 amptwregs (0 : 63) bit (36), /* assoc. mem. page table word regs */ 2 19 2 amptwptrs (0 : 63) bit (36), /* assoc. mem. page table word pointers */ 2 20 2 amsdwregs (0 : 63) bit (72), /* assoc. mem. segment descriptor word registers */ 2 21 2 amsdwptrs (0 : 63) bit (36), /* assoc. mem. segment descriptor word pointers */ 2 22 2 23 2 ouhist (0 : 63) bit (72), /* operations unit history registers */ 2 24 2 cuhist (0 : 63) bit (72), /* control unit history registers */ 2 25 2 duhist (0 : 63) bit (72), /* decimal unit history registers */ 2 26 2 auhist (0 : 63) bit (72), /* appending unit history registers */ 2 27 2 28 2 prs (0 : 7) ptr, /* pointer registers */ 2 29 2 30 2 regs aligned like dump_registers, /* assorted machine registers */ 2 31 2 32 2 low_order_port bit (3), /* from which clock is read */ 2 33 2 pad4 bit (36), 2 34 2 mctime fixed bin (52), /* time conditions were taken */ 2 35 2 pad5 (0 : 3) bit (36), 2 36 2 37 2 misc_registers like dump_misc_registers, /* Assorted registers & processor data */ 2 38 2 39 2 ptrlen (0 : 7) bit (36), /* pointers and lengths for EIS */ 2 40 2 41 2 coreblocks (0 : 7), 2 42 3 num_first bit (18) unal, /* first addr in coreblock */ 2 43 3 num_blocks bit (18) unal, /* number of blocks used */ 2 44 2 pad7 (112) fixed bin; 2 45 2 46 2 47 dcl 1 dump_header aligned based, /* Standard header for FDUMP */ 2 48 2 words_dumped fixed bin (35), /* total words in dump */ 2 49 2 valid bit (1), /* = 1 if there is a 6180 dump to be had */ 2 50 2 time fixed bin (71), /* time of dump */ 2 51 2 erfno fixed bin (18), /* Error Report Form Number */ 2 52 2 num_segs fixed bin, /* number of segments dumped */ 2 53 2 valid_355 bit (1), /* = 1 if there is a dn355 dump to be had */ 2 54 2 dumped_355s bit (4), /* indicates which 355s were dumped */ 2 55 2 time_355 fixed bin (71), /* time of 355 dump */ 2 56 2 version fixed bin, /* currently 2 */ 2 57 2 pad0 (5) fixed bin; /* pad0 to 16 words */ 2 58 2 59 dcl 1 dump_registers aligned based, /* Standard (SREG) arrangement of registers in dump */ 2 60 (2 x (0 : 7) bit (18), /* index registers */ 2 61 2 a bit (36), /* the a register */ 2 62 2 q bit (36), /* the q register */ 2 63 2 e bit (8), /* the e register */ 2 64 2 pad2 bit (28), /* pad */ 2 65 2 t bit (27), /* timer register */ 2 66 2 pad3 bit (6), /* pad */ 2 67 2 ralr bit (3)) unaligned; /* ring alarm register */ 2 68 2 69 dcl 1 dump_misc_registers aligned based, 2 70 2 scu (0 : 7) bit (36), /* from store control unit instr. */ 2 71 2 mcm (0 : 7) bit (72), /* memory controller masks every 64 K */ 2 72 2 dbr bit (72), /* descriptor segment base register */ 2 73 2 intrpts bit (36), /* interrupts */ 2 74 2 bar bit (36), /* base address register */ 2 75 2 modereg bit (36), /* mode register */ 2 76 2 cmodereg bit (36), /* cache mode register */ 2 77 2 faultreg bit (36), /* fault register */ 2 78 2 ext_fault_reg bit (15) unaligned, /* DPS8 extended fault register */ 2 79 2 pad6 bit (21) unaligned; 2 80 2 81 2 82 2 83 dcl 1 v1_dump aligned based (dumpptr), /* Old version of FDUMP (pre March, 1981) */ 2 84 2 dump_header aligned like dump_header, 2 85 2 86 2 segs (688), /* segment array */ 2 87 3 segno bit (18) unal, /* segment number */ 2 88 3 length bit (18) unal, /* length of segment in sector sized blocks */ 2 89 2 90 2 amsdwregs (0 : 15) bit (72), /* assoc. mem. segment descriptor word registers */ 2 91 2 amsdwptrs (0 : 15) bit (36), /* assoc. mem. segment descriptor word pointers */ 2 92 2 amptwregs (0 : 15) bit (36), /* assoc. mem. page table word regs */ 2 93 2 amptwptrs (0 : 15) bit (36), /* assoc. mem. page table word pointers */ 2 94 2 pad1 (0 : 15) bit (36), 2 95 2 96 2 ouhist (0 : 15) bit (72), /* operations unit history registers */ 2 97 2 cuhist (0 : 15) bit (72), /* control unit history registers */ 2 98 2 auhist (0 : 15) bit (72), /* appending unit history registers */ 2 99 2 duhist (0 : 15) bit (72), /* decimal unit history registers */ 2 100 2 101 2 prs (0 : 7) ptr, /* pointer registers */ 2 102 2 103 2 regs aligned like dump_registers, /* assorted machine registers */ 2 104 2 105 2 mctime fixed bin (52), /* time conditions were taken */ 2 106 2 pad4 (0 : 5) bit (36), 2 107 2 108 2 misc_registers aligned like dump_misc_registers, /* Assorted registers */ 2 109 2 110 2 pad5 bit (36), 2 111 2 ptrlen (0 : 7) bit (36), /* pointers and lengths for EIS */ 2 112 2 pad6 (15) bit (36), 2 113 2 low_order_port bit (3), /* from which clock was read */ 2 114 2 115 2 coreblocks (0 : 7), 2 116 3 num_first bit (18) unal, /* first addr in coreblock */ 2 117 3 num_blocks bit (18) unal; /* number of blocks used */ 2 118 2 119 2 120 dcl DUMP_VERSION_1 fixed bin internal static options (constant) init (1); 2 121 dcl DUMP_VERSION_2 fixed bin internal static options (constant) init (2); 2 122 2 123 /* END INCLUDE FILE ... bos_dump.incl.pl1 ... */ 774 775 3 1 /* */ 3 2 /* BEGIN INCLUDE FILE mc.incl.pl1 Created Dec 72 for 6180 - WSS. */ 3 3 /* Modified 06/07/76 by Greenberg for mc.resignal */ 3 4 /* Modified 07/07/76 by Morris for fault register data */ 3 5 /* Modified 08/28/80 by J. A. Bush for the DPS8/70M CVPU */ 3 6 /* Modified '82 to make values constant */ 3 7 3 8 /* words 0-15 pointer registers */ 3 9 3 10 dcl mcp ptr; 3 11 3 12 dcl 1 mc based (mcp) aligned, 3 13 2 prs (0:7) ptr, /* POINTER REGISTERS */ 3 14 (2 regs, /* registers */ 3 15 3 x (0:7) bit (18), /* index registers */ 3 16 3 a bit (36), /* accumulator */ 3 17 3 q bit (36), /* q-register */ 3 18 3 e bit (8), /* exponent */ 3 19 3 pad1 bit (28), 3 20 3 t bit (27), /* timer register */ 3 21 3 pad2 bit (6), 3 22 3 ralr bit (3), /* ring alarm register */ 3 23 3 24 2 scu (0:7) bit (36), 3 25 3 26 2 mask bit (72), /* mem controller mask at time of fault */ 3 27 2 ips_temp bit (36), /* Temporary storage for IPS info */ 3 28 2 errcode fixed bin (35), /* fault handler's error code */ 3 29 2 fim_temp, 3 30 3 unique_index bit (18) unal, /* unique index for restarting faults */ 3 31 3 resignal bit (1) unal, /* recompute signal name with fcode below */ 3 32 3 fcode bit (17) unal, /* fault code used as index to FIM table and SCT */ 3 33 2 fault_reg bit (36), /* fault register */ 3 34 2 pad2 bit (1), 3 35 2 cpu_type fixed bin (2) unsigned, /* L68 = 0, DPS8/70M = 1 */ 3 36 2 ext_fault_reg bit (15), /* extended fault reg for DPS8/70M CPU */ 3 37 2 fault_time bit (54), /* time of fault */ 3 38 3 39 2 eis_info (0:7) bit (36)) unaligned; 3 40 3 41 3 42 dcl (apx fixed bin init (0), 3 43 abx fixed bin init (1), 3 44 bpx fixed bin init (2), 3 45 bbx fixed bin init (3), 3 46 lpx fixed bin init (4), 3 47 lbx fixed bin init (5), 3 48 spx fixed bin init (6), 3 49 sbx fixed bin init (7)) internal static options (constant); 3 50 3 51 3 52 3 53 3 54 dcl scup ptr; 3 55 3 56 dcl 1 scu based (scup) aligned, /* SCU DATA */ 3 57 3 58 3 59 /* WORD (0) */ 3 60 3 61 (2 ppr, /* PROCEDURE POINTER REGISTER */ 3 62 3 prr bit (3), /* procedure ring register */ 3 63 3 psr bit (15), /* procedure segment register */ 3 64 3 p bit (1), /* procedure privileged bit */ 3 65 3 66 2 apu, /* APPENDING UNIT STATUS */ 3 67 3 xsf bit (1), /* ext seg flag - IT modification */ 3 68 3 sdwm bit (1), /* match in SDW Ass. Mem. */ 3 69 3 sd_on bit (1), /* SDW Ass. Mem. ON */ 3 70 3 ptwm bit (1), /* match in PTW Ass. Mem. */ 3 71 3 pt_on bit (1), /* PTW Ass. Mem. ON */ 3 72 3 pi_ap bit (1), /* Instr Fetch or Append cycle */ 3 73 3 dsptw bit (1), /* Fetch of DSPTW */ 3 74 3 sdwnp bit (1), /* Fetch of SDW non paged */ 3 75 3 sdwp bit (1), /* Fetch of SDW paged */ 3 76 3 ptw bit (1), /* Fetch of PTW */ 3 77 3 ptw2 bit (1), /* Fetch of pre-paged PTW */ 3 78 3 fap bit (1), /* Fetch of final address paged */ 3 79 3 fanp bit (1), /* Fetch of final address non-paged */ 3 80 3 fabs bit (1), /* Fetch of final address absolute */ 3 81 3 82 2 fault_cntr bit (3), /* number of retrys of EIS instructions */ 3 83 3 84 3 85 /* WORD (1) */ 3 86 3 87 2 fd, /* FAULT DATA */ 3 88 3 iro bit (1), /* illegal ring order */ 3 89 3 oeb bit (1), /* out of execute bracket */ 3 90 3 e_off bit (1), /* no execute */ 3 91 3 orb bit (1), /* out of read bracket */ 3 92 3 r_off bit (1), /* no read */ 3 93 3 owb bit (1), /* out of write bracket */ 3 94 3 w_off bit (1), /* no write */ 3 95 3 no_ga bit (1), /* not a gate */ 3 96 3 ocb bit (1), /* out of call bracket */ 3 97 3 ocall bit (1), /* outward call */ 3 98 3 boc bit (1), /* bad outward call */ 3 99 3 inret bit (1), /* inward return */ 3 100 3 crt bit (1), /* cross ring transfer */ 3 101 3 ralr bit (1), /* ring alarm register */ 3 102 3 am_er bit (1), /* associative memory fault */ 3 103 3 oosb bit (1), /* out of segment bounds */ 3 104 3 paru bit (1), /* processor parity upper */ 3 105 3 parl bit (1), /* processor parity lower */ 3 106 3 onc_1 bit (1), /* op not complete type 1 */ 3 107 3 onc_2 bit (1), /* op not complete type 2 */ 3 108 3 109 2 port_stat, /* PORT STATUS */ 3 110 3 ial bit (4), /* illegal action lines */ 3 111 3 iac bit (3), /* illegal action channel */ 3 112 3 con_chan bit (3), /* connect channel */ 3 113 3 114 2 fi_num bit (5), /* (fault/interrupt) number */ 3 115 2 fi_flag bit (1), /* 1 => fault, 0 => interrupt */ 3 116 3 117 3 118 /* WORD (2) */ 3 119 3 120 2 tpr, /* TEMPORARY POINTER REGISTER */ 3 121 3 trr bit (3), /* temporary ring register */ 3 122 3 tsr bit (15), /* temporary segment register */ 3 123 3 124 2 pad2 bit (9), 3 125 3 126 2 cpu_no bit (3), /* CPU number */ 3 127 3 128 2 delta bit (6), /* tally modification DELTA */ 3 129 3 130 3 131 /* WORD (3) */ 3 132 3 133 2 word3 bit (18), 3 134 3 135 2 tsr_stat, /* TSR STATUS for 1,2,&3 word instructions */ 3 136 3 tsna, /* Word 1 status */ 3 137 4 prn bit (3), /* Word 1 PR number */ 3 138 4 prv bit (1), /* Word 1 PR valid bit */ 3 139 3 tsnb, /* Word 2 status */ 3 140 4 prn bit (3), /* Word 2 PR number */ 3 141 4 prv bit (1), /* Word 2 PR valid bit */ 3 142 3 tsnc, /* Word 3 status */ 3 143 4 prn bit (3), /* Word 3 PR number */ 3 144 4 prv bit (1), /* Word 3 PR valid bit */ 3 145 3 146 2 tpr_tbr bit (6), /* TPR.TBR field */ 3 147 3 148 3 149 /* WORD (4) */ 3 150 3 151 2 ilc bit (18), /* INSTRUCTION COUNTER */ 3 152 3 153 2 ir, /* INDICATOR REGISTERS */ 3 154 3 zero bit (1), /* zero indicator */ 3 155 3 neg bit (1), /* negative indicator */ 3 156 3 carry bit (1), /* carryry indicator */ 3 157 3 ovfl bit (1), /* overflow indicator */ 3 158 3 eovf bit (1), /* eponent overflow */ 3 159 3 eufl bit (1), /* exponent underflow */ 3 160 3 oflm bit (1), /* overflow mask */ 3 161 3 tro bit (1), /* tally runout */ 3 162 3 par bit (1), /* parity error */ 3 163 3 parm bit (1), /* parity mask */ 3 164 3 bm bit (1), /* ^bar mode */ 3 165 3 tru bit (1), /* truncation mode */ 3 166 3 mif bit (1), /* multi-word instruction mode */ 3 167 3 abs bit (1), /* absolute mode */ 3 168 3 hex bit (1), /* hexadecimal exponent mode */ 3 169 3 pad bit (3), 3 170 3 171 3 172 /* WORD (5) */ 3 173 3 174 2 ca bit (18), /* COMPUTED ADDRESS */ 3 175 3 176 2 cu, /* CONTROL UNIT STATUS */ 3 177 3 rf bit (1), /* on first cycle of repeat instr */ 3 178 3 rpt bit (1), /* repeat instruction */ 3 179 3 rd bit (1), /* repeat double instruction */ 3 180 3 rl bit (1), /* repeat link instruciton */ 3 181 3 pot bit (1), /* IT modification */ 3 182 3 pon bit (1), /* return type instruction */ 3 183 3 xde bit (1), /* XDE from Even location */ 3 184 3 xdo bit (1), /* XDE from Odd location */ 3 185 3 poa bit (1), /* operation preparation */ 3 186 3 rfi bit (1), /* tells CPU to refetch instruction */ 3 187 3 its bit (1), /* ITS modification */ 3 188 3 if bit (1), /* fault occured during instruction fetch */ 3 189 3 190 2 cpu_tag bit (6)) unaligned, /* computed tag field */ 3 191 3 192 3 193 /* WORDS (6,7) */ 3 194 3 195 2 even_inst bit (36), /* even instruction of faulting pair */ 3 196 3 197 2 odd_inst bit (36); /* odd instruction of faulting pair */ 3 198 3 199 3 200 3 201 3 202 3 203 3 204 /* ALTERNATE SCU DECLARATION */ 3 205 3 206 3 207 dcl 1 scux based (scup) aligned, 3 208 3 209 (2 pad0 bit (36), 3 210 3 211 2 fd, /* GROUP II FAULT DATA */ 3 212 3 isn bit (1), /* illegal segment number */ 3 213 3 ioc bit (1), /* illegal op code */ 3 214 3 ia_am bit (1), /* illegal address - modifier */ 3 215 3 isp bit (1), /* illegal slave procedure */ 3 216 3 ipr bit (1), /* illegal procedure */ 3 217 3 nea bit (1), /* non existent address */ 3 218 3 oobb bit (1), /* out of bounds */ 3 219 3 pad bit (29), 3 220 3 221 2 pad2 bit (36), 3 222 3 223 2 pad3a bit (18), 3 224 3 225 2 tsr_stat (0:2), /* TSR STATUS as an ARRAY */ 3 226 3 prn bit (3), /* PR number */ 3 227 3 prv bit (1), /* PR valid bit */ 3 228 3 229 2 pad3b bit (6)) unaligned, 3 230 3 231 2 pad45 (0:1) bit (36), 3 232 3 233 2 instr (0:1) bit (36); /* Instruction ARRAY */ 3 234 3 235 3 236 3 237 /* END INCLUDE FILE mc.incl.pl1 */ 776 777 4 1 /* BEGIN INCLUDE FILE its.incl.pl1 4 2* modified 27 July 79 by JRDavis to add its_unsigned 4 3* Internal format of ITS pointer, including ring-number field for follow-on processor */ 4 4 4 5 dcl 1 its based aligned, /* declaration for ITS type pointer */ 4 6 2 pad1 bit (3) unaligned, 4 7 2 segno bit (15) unaligned, /* segment number within the pointer */ 4 8 2 ringno bit (3) unaligned, /* ring number within the pointer */ 4 9 2 pad2 bit (9) unaligned, 4 10 2 its_mod bit (6) unaligned, /* should be 43(8) */ 4 11 4 12 2 offset bit (18) unaligned, /* word offset within the addressed segment */ 4 13 2 pad3 bit (3) unaligned, 4 14 2 bit_offset bit (6) unaligned, /* bit offset within the word */ 4 15 2 pad4 bit (3) unaligned, 4 16 2 mod bit (6) unaligned; /* further modification */ 4 17 4 18 dcl 1 itp based aligned, /* declaration for ITP type pointer */ 4 19 2 pr_no bit (3) unaligned, /* number of pointer register to use */ 4 20 2 pad1 bit (27) unaligned, 4 21 2 itp_mod bit (6) unaligned, /* should be 41(8) */ 4 22 4 23 2 offset bit (18) unaligned, /* word offset from pointer register word offset */ 4 24 2 pad2 bit (3) unaligned, 4 25 2 bit_offset bit (6) unaligned, /* bit offset relative to new word offset */ 4 26 2 pad3 bit (3) unaligned, 4 27 2 mod bit (6) unaligned; /* further modification */ 4 28 4 29 4 30 dcl 1 its_unsigned based aligned, /* just like its, but with unsigned binary */ 4 31 2 pad1 bit (3) unaligned, 4 32 2 segno fixed bin (15) unsigned unaligned, 4 33 2 ringno fixed bin (3) unsigned unaligned, 4 34 2 pad2 bit (9) unaligned, 4 35 2 its_mod bit (6) unaligned, 4 36 4 37 2 offset fixed bin (18) unsigned unaligned, 4 38 2 pad3 bit (3) unaligned, 4 39 2 bit_offset fixed bin (6) unsigned unaligned, 4 40 2 pad4 bit (3) unaligned, 4 41 2 mod bit (6) unaligned; 4 42 4 43 dcl 1 itp_unsigned based aligned, /* just like itp, but with unsigned binary where appropriate */ 4 44 2 pr_no fixed bin (3) unsigned unaligned, 4 45 2 pad1 bit (27) unaligned, 4 46 2 itp_mod bit (6) unaligned, 4 47 4 48 2 offset fixed bin (18) unsigned unaligned, 4 49 2 pad2 bit (3) unaligned, 4 50 2 bit_offset fixed bin (6) unsigned unaligned, 4 51 2 pad3 bit (3) unaligned, 4 52 2 mod bit (6) unaligned; 4 53 4 54 4 55 dcl ITS_MODIFIER bit (6) unaligned internal static options (constant) init ("43"b3); 4 56 dcl ITP_MODIFIER bit (6) unaligned internal static options (constant) init ("41"b3); 4 57 4 58 /* END INCLUDE FILE its.incl.pl1 */ 778 779 5 1 /* BEGIN INCLUDE FILE amu_info.incl.pl1 */ 5 2 5 3 dcl 1 amu_info aligned based (amu_info_ptr), 5 4 2 version char (8) aligned, /* AMU_INFO_VERSION */ 5 5 2 flags aligned, 5 6 3 early_dump bit(1) unal, 5 7 3 pad bit(35) unal, 5 8 2 type fixed bin unal, /* One of the types below */ 5 9 2 time_created fixed bin (71) aligned, /* time created -- for debugging purposes */ 5 10 2 chain, /* a chain of all the amu_info's which exist */ 5 11 3 prev pointer unaligned, 5 12 3 next pointer unaligned, 5 13 5 14 2 area_ptr pointer, /* pointer to area used for allocating things */ 5 15 5 16 2 translation_table_ptr pointer, /* pointer to address map -- always present */ 5 17 /* SEE: amu_translation.incl.pl1 */ 5 18 2 fdump_info_ptr pointer, 5 19 /* pointer to FDUMP info, present if looking at an FDUMP */ 5 20 /* SEE: amu_fdump_info.incl.pl1 */ 5 21 /* old_uid_table pointer if looking at a SAVED PROC. */ 5 22 /* See: amu_old_uid_table */ 5 23 5 24 5 25 2 hardcore_info_ptr pointer, /* pointer to hardcore information -- always present */ 5 26 /* SEE: amu_hardcore_info.incl.pl1 */ 5 27 2 copy_chain pointer, /* pointer to info about segment copies */ 5 28 /* SEE: amu_copy_info.incl.pl1 */ 5 29 2 process_info_ptr pointer, /* pointer to process info for this translation */ 5 30 /* SEE: amu_process_info.incl.pl1 */ 5 31 2 process_idx fixed bin, /* index of process in translation-specifc process table */ 5 32 5 33 2 proc_idx_hold fixed bin, /* a place to keep the index when a changing to another proc */ 5 34 5 35 2 error_info, /* various info about how amu_error_ is to behave */ 5 36 3 error_flags aligned, 5 37 4 handler_exists bit (1) unaligned, /* set to indicate existence of an amu_error handler */ 5 38 4 in_subsystem bit (1) unaligned, /* This amu_info belongs to an ssu_ maintained subsystem */ 5 39 4 pad bit (34) unaligned, 5 40 3 sci_ptr pointer, /* sci_ptr for subsystem, if in_subsystem = "1"b */ 5 41 2 definitions_info_ptr ptr; 5 42 5 43 dcl amu_area area based (amu_info.area_ptr); 5 44 5 45 dcl amu_info_ptr pointer; 5 46 5 47 dcl (FDUMP_TYPE init (1037), /* the various legitimate types of amu_info's */ 5 48 FDUMP_PROCESS_TYPE init (1038), 5 49 ONLINE_TYPE init (1039), 5 50 ONLINE_PROCESS_TYPE init (1040), 5 51 NETWORK_FDUMP_TYPE init (1041), 5 52 NETWORK_ONLINE_TYPE init (1042), 5 53 SAVED_PROC_TYPE init (1043), 5 54 INDIRECT_TYPE init (1044)) fixed bin internal static options (constant); 5 55 5 56 dcl AMU_INFO_VERSION_1 char (8) internal static options (constant) init ("amu_v1"); 5 57 dcl AMU_INFO_VERSION char (8) internal static options (constant) init ("amu_v1"); 5 58 dcl AMU_INFO_VERSION_2 char (8) internal static options (constant) init ("amu_v2"); 5 59 5 60 dcl PDIR_SUFFIX char(4) init("pdir") int static options(constant); 5 61 5 62 /* END INCLUDE FILE amu_info.incl.pl1 */ 780 781 6 1 /* Begin amu_mc.incl.pl1 */ 6 2 6 3 dcl number_val_args fixed bin (17) init (23) static options (constant); 6 4 6 5 dcl valid_mc_arg (24) char (8) init 6 6 ("-dump", /* mc from bos dump */ 6 7 "-lg", /* all of the info stored at the given pointer */ 6 8 "-scu","-ppr","-tpr","-inst", /* scu data or trs or psr (if scu then not psr nor tsr) */ 6 9 "-reg", /* basic ou regs */ 6 10 "-misc","-code","-flt","-tm", /* misc line of mc data if misc then not others */ 6 11 "-eis", /* eis info if MIF flag in scu_data */ 6 12 "-prs","-pr0","-pr1","-pr2","-pr3","-pr4","-pr5","-pr6","-pr7", /* pointer regs if prs then not the others */ 6 13 "-vbf","-oct","-set") /* control args */ 6 14 static options (constant); 6 15 6 16 /* the next structuers all all the same real data word and a dcl'ed in 6 17* many ways to make the code easer to write and undersand, only time 6 18* will tell if this is the correct end result. If any are changed they 6 19* all must by changed, The bit order must corespond to valid_mc_arg */ 6 20 6 21 6 22 6 23 dcl 1 arg_bits based (arg_bits_ptr) aligned, 6 24 2 request_arg(number_val_args) bit (1) unal; 6 25 6 26 dcl 1 what_prs based (arg_bits_ptr) aligned, 6 27 2 pad bit (13) unal, 6 28 2 pregs (0:7) bit (1) unal, 6 29 2 padr bit (16); 6 30 6 31 6 32 dcl 1 arg_bits_def based (arg_bits_ptr), 6 33 2 dump bit (1) unal, 6 34 2 all bit (1) unal, 6 35 2 scu bit (1) unal, 6 36 2 ppr bit (1) unal, 6 37 2 tpr bit (1) unal, 6 38 2 inst bit (1) unal, 6 39 2 regs bit (1) unal, 6 40 2 xreg (0:7) bit (1) unal, 6 41 2 areg bit (1) unal, 6 42 2 qreg bit (1) unal, 6 43 2 mis bit (1) unal, 6 44 2 mc_err bit (1) unal, 6 45 2 flt bit (1) unal, 6 46 2 tm bit (1) unal, 6 47 2 eis bit (1) unal, 6 48 2 prs bit (1) unal, 6 49 2 pr (0:7) bit (1) unal, 6 50 2 long bit (1) unal, 6 51 2 set_ptr bit (1) unal, 6 52 2 mc_stored bit (1) unal, 6 53 2 rest_bits bit (1) unal; /* bits to fill out the word **/ 6 54 6 55 6 56 6 57 dcl arg_bits_ptr ptr; 6 58 6 59 /* End amu_mc.incl.pl1 */ 782 783 784 end azm_display_mc_; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/15/84 1440.1 azm_display_mc_.pl1 >special_ldd>online>6897-11/15/84>azm_display_mc_.pl1 772 1 05/20/83 1846.4 iocb.incl.pl1 >ldd>include>iocb.incl.pl1 774 2 08/12/81 2025.8 bos_dump.incl.pl1 >ldd>include>bos_dump.incl.pl1 776 3 12/15/83 1100.4 mc.incl.pl1 >ldd>include>mc.incl.pl1 778 4 11/26/79 1320.6 its.incl.pl1 >ldd>include>its.incl.pl1 780 5 11/15/84 1524.3 amu_info.incl.pl1 >special_ldd>online>6897-11/15/84>amu_info.incl.pl1 782 6 09/22/83 1102.5 amu_mc.incl.pl1 >ldd>include>amu_mc.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. APU 001241 constant varying char(6) initial array dcl 141 set ref 632 632 633* CU 001211 constant varying char(3) initial array dcl 145 set ref 641 641 642* EXT_FAULT_TYPES 001632 constant varying char(39) initial array dcl 125 ref 752 FAULT_TYPES 002363 constant varying char(15) initial array dcl 111 ref 710 727 FLT_LN 000424 automatic char(100) unaligned dcl 69 set ref 207* 219* 317* 352* IA 0(16) based bit(4) array level 2 packed unaligned dcl 697 ref 717 719 IA_LN 000455 automatic char(100) unaligned dcl 69 set ref 207* 219* 355* PR_ptr 000526 automatic pointer dcl 78 set ref 593* 594 594 594 600 600 PTR_STR 000520 automatic char(24) dcl 77 set ref 597* 599* P_amu_info_ptr parameter pointer dcl 24 ref 8 279 293 P_arg_bits_ptr parameter pointer dcl 27 ref 8 279 295 P_code parameter fixed bin(35,0) dcl 28 set ref 8 184* 279 286* 298* 765* P_mc_ptr parameter pointer dcl 25 ref 8 279 296 378 P_sci_ptr parameter pointer dcl 26 ref 8 279 294 SC_IA_TYPES 002077 constant varying char(42) initial array dcl 117 ref 719 TAG based structure array level 1 packed unaligned dcl 85 TAG_ptr 000530 automatic pointer dcl 81 set ref 645* 649 TAG_table 002670 constant char(40) initial array unaligned dcl 99 set ref 645 a 24 based bit(36) level 3 in structure "mc" packed unaligned dcl 3-12 in procedure "azm_display_mc_" set ref 409* 424* a parameter bit(1) unaligned dcl 423 in procedure "display_aq_reg" ref 421 424 active 2(32) based bit(1) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" ref 526 active 4(32) based bit(1) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" ref 542 active 6(32) based bit(1) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" ref 555 addr builtin function dcl 89 ref 189 308 523 593 622 631 640 645 686 686 687 687 717 719 addrel builtin function dcl 89 ref 325 668 677 aligned_error_message 000321 automatic char(100) dcl 57 set ref 459* 460 460 all 0(01) based bit(1) level 2 packed unaligned dcl 6-32 ref 200 amu_$get_name 000022 constant entry external dcl 40 ref 599 669 678 amu_info_ptr 000550 automatic pointer dcl 5-45 set ref 293* 599* 669* 678* areg 0(15) based bit(1) level 2 packed unaligned dcl 6-32 ref 239 arg_bits_def based structure level 1 packed unaligned dcl 6-32 arg_bits_ptr 000552 automatic pointer dcl 6-57 set ref 177 180 193 197 200 220 226 230 237 239 240 242 250 251 252 255 261 262 267 270 276 295* 310 568 600 613 at_by_wd 000315 automatic char(2) unaligned dcl 55 set ref 359* 361* 670* bar 3573 based bit(36) level 3 dcl 2-11 set ref 390 390* baseptr builtin function dcl 89 ref 668 677 bin builtin function dcl 89 ref 719 break 000731 automatic fixed bin(17,0) dcl 696 set ref 715* 716 721* by_name 000114 automatic char(168) unaligned dcl 51 set ref 669* 670* byptr 000360 automatic pointer dcl 63 set ref 325* 326 344 622* 624 631* 633 640* 642 668* 669* 670* ca 5 based bit(18) level 2 packed unaligned dcl 3-56 set ref 640 677 char_tally 0(12) based bit(24) level 2 packed unaligned dcl 469 set ref 525 525* cleanup 000534 stack reference condition dcl 93 ref 176 cmodereg 3575 based bit(36) level 3 dcl 2-11 set ref 389 389* code 000354 automatic fixed bin(35,0) dcl 59 in procedure "azm_display_mc_" set ref 183 184 204 206 209 211 214 222 227 233 245 273 283 285 298* 765 code based char(4) array level 2 in structure "TAG" packed unaligned dcl 85 in procedure "azm_display_mc_" ref 649 convert_status_code_ 000024 constant entry external dcl 41 ref 459 cpu_no 2(27) based bit(3) level 2 packed unaligned dcl 3-56 ref 620 620 620 cpu_tag 5(30) based bit(6) level 2 packed unaligned dcl 3-56 ref 646 cpu_type 46(01) based fixed bin(2,0) level 2 packed unsigned unaligned dcl 3-12 ref 264 436 cpul 002666 constant char(1) initial array unaligned dcl 106 set ref 620* cur_bit_off 2(20) based bit(4) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" set ref 535* cur_bit_off 4(20) based bit(4) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" set ref 547* cur_bit_off 6(20) based bit(4) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" set ref 561* cur_char_off 4(18) based bit(2) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" set ref 547* cur_char_off 2(18) based bit(2) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" set ref 535* cur_char_off 6(18) based bit(2) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" set ref 561* cur_wd_off 4 based bit(18) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" set ref 547* cur_wd_off 2 based bit(18) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" set ref 535* cur_wd_off 6 based bit(18) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" set ref 561* cv_bin_$oct 000014 constant entry external dcl 34 ref 339 cvbinbuf 000316 automatic char(12) dcl 56 set ref 339* 340 data_mode 2(25) based bit(2) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" ref 535 535 data_mode 4(25) based bit(2) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" ref 547 547 date_time_$format 000032 constant entry external dcl 448 ref 450 db_print 000010 constant entry external dcl 32 ref 686 687 dbr 3570 based bit(72) level 3 dcl 2-11 ref 386 386 386 386 dec1 2 based structure level 2 packed unaligned dcl 469 dec2 4 based structure level 2 packed unaligned dcl 469 dec3 6 based structure level 2 packed unaligned dcl 469 dt_form 000000 constant char(41) initial unaligned dcl 446 set ref 450* dump based structure level 1 dcl 2-11 in procedure "azm_display_mc_" dump based bit(1) level 2 in structure "arg_bits_def" packed unaligned dcl 6-32 in procedure "azm_display_mc_" ref 177 180 276 310 dump_header based structure level 1 dcl 2-47 dump_misc_registers based structure level 1 dcl 2-69 dump_registers based structure level 1 dcl 2-59 dumpptr 000542 automatic pointer dcl 2-9 set ref 378* 379 380 381 382 383 384 385 386 386 386 386 388 388 389 389 390 390 e 26 based bit(8) level 3 packed unaligned dcl 3-12 set ref 409 409 eis 0(21) based bit(1) level 2 packed unaligned dcl 6-32 ref 270 eis_info 50 based bit(36) array level 2 packed unaligned dcl 3-12 set ref 385* 523 568* 568* 568* 568* 568* 568* 568* 568* eis_info_fmt based structure level 1 packed unaligned dcl 469 eis_info_ptr 000652 automatic pointer dcl 468 set ref 523* 525 525 526 535 535 535 535 535 535 535 535 542 547 547 547 547 547 547 547 553 555 561 561 561 561 561 eis_info_valid 000240 automatic bit(1) unaligned dcl 52 set ref 212 309* 362* 364* errcode 43 based fixed bin(35,0) level 2 packed unaligned dcl 3-12 ref 457 458 error_code_mc 000100 automatic fixed bin(35,0) dcl 48 set ref 458* 459* even_inst 6 based bit(36) level 2 dcl 3-56 set ref 686 686 ext_fault_reg 46(03) based bit(15) level 2 in structure "mc" packed unaligned dcl 3-12 in procedure "azm_display_mc_" set ref 264 264* 384* 436 436* ext_fault_reg 3577 based bit(15) level 3 in structure "dump" packed unaligned dcl 2-11 in procedure "azm_display_mc_" ref 384 ext_fault_reg parameter bit(15) unaligned dcl 747 in procedure "interpret_ext_fault_reg" set ref 744 752 757* fault_index 000371 automatic fixed bin(6,0) unsigned dcl 66 set ref 316* 319 323 330 338 617* fault_no 000730 automatic fixed bin(17,0) dcl 696 set ref 708* 709 710* 716* 717 718 719* 725* 726 727* fault_reg parameter bit(36) unaligned dcl 695 in procedure "interpret_fault_reg" set ref 692 704 709 717 719 726 735* fault_reg 45 based bit(36) level 2 in structure "mc" packed unaligned dcl 3-12 in procedure "azm_display_mc_" set ref 263* 383* 435* fault_time 46(18) based bit(54) level 2 packed unaligned dcl 3-12 set ref 450 450 450* faultreg 3576 based bit(36) level 3 dcl 2-11 ref 383 fi_flag 1(35) based bit(1) level 2 packed unaligned dcl 3-56 ref 316 fi_num 1(30) based bit(5) level 2 packed unaligned dcl 3-56 ref 316 fixed builtin function dcl 89 ref 316 355 355 355 405 405 405 405 405 405 405 405 405 405 405 405 405 405 405 405 409 409 419 419 450 450 529 529 535 535 535 535 544 544 547 547 547 547 557 557 561 561 620 620 620 646 668 668 677 677 flt 0(19) based bit(1) level 2 packed unaligned dcl 6-32 ref 262 flt_bf 000506 automatic varying char(24) dcl 70 set ref 317* 319* 320 324 flt_int_typ 000013 constant varying char(24) initial array dcl 161 ref 319 323 flt_ln 000373 automatic char(100) unaligned dcl 69 set ref 317* 324* 327* 334* 340* 345 345 345* 345* 349* 349* 352 621* 624* 624* 626 627* 628* 629* 633* 633* 635 636* 637* 638* 642* 642* 653 654* 655* flt_lng 000365 automatic fixed bin(17,0) dcl 64 set ref 323* 324 324 327 328 334 335 fltdtab based bit(1) array unaligned dcl 68 ref 326 344 624 633 642 g1and7flts 001210 constant bit(6) initial array unaligned dcl 148 ref 329 330 grp1flt 000774 constant varying char(24) initial array dcl 150 set ref 343 349* grp2flt 000713 constant varying char(24) initial array dcl 157 set ref 345* hbound builtin function dcl 89 ref 329 343 623 632 641 i parameter fixed bin(17,0) dcl 418 in procedure "display_x_reg" set ref 416 419* 419 419 i 000352 automatic fixed bin(17,0) dcl 58 in procedure "azm_display_mc_" set ref 225* 226 226* 236* 237 237* 329* 330* 343* 344 345 345 349* 623* 624 624* 632* 633 633* 641* 642 642* 646* 648 649 i parameter fixed bin(17,0) dcl 592 in procedure "print_pr_reg" set ref 590 593 594* 594 597* 597 597 599 i 000662 automatic fixed bin(17,0) dcl 581 in procedure "display_pr_regs_" set ref 583* 584* ial 1(20) based bit(4) level 3 packed unaligned dcl 3-56 ref 354 355 355 355 ilc 4 based bit(18) level 2 packed unaligned dcl 3-56 set ref 622 668 ill_act 001352 constant varying char(37) initial array dcl 132 set ref 355* illeg_acts based structure level 1 packed unaligned dcl 697 indrs 001316 constant varying char(4) initial array dcl 138 set ref 623 623 624* indx 000740 automatic fixed bin(17,0) dcl 748 set ref 751* 752 752* inst 0(05) based bit(1) level 2 packed unaligned dcl 6-32 ref 252 inst6 000366 automatic fixed bin(17,0) dcl 64 set ref 315* 686* 687 ioa_ 000016 constant entry external dcl 35 ref 194 207 219 377 386 388 389 390 404 405 409 412 419 424 426 432 450 460 521 525 528 529 535 540 543 544 547 551 556 557 561 566 568 582 594 599 600 611 613 617 620 628 637 655 670 679 685 735 757 ioa_$rsnnl 000020 constant entry external dcl 35 ref 345 349 355 597 624 633 642 iocb based structure level 1 dcl 1-6 iocb_name 000101 automatic char(32) unaligned dcl 49 set ref 684* 686* 687* iocbp 000112 automatic pointer dcl 50 set ref 297* 684 686* 687* iox_$user_output 000012 external static pointer dcl 33 ref 297 ir 4(18) based structure level 2 packed unaligned dcl 3-56 its based structure level 1 dcl 4-5 its_mod 0(30) based bit(6) level 2 packed unaligned dcl 4-5 ref 594 j 000353 automatic fixed bin(17,0) dcl 58 set ref 342* 345* 349* 355* 597* 624* 627 633* 636 642* 654 jump_add_ind 6(33) based bit(3) level 3 packed unaligned dcl 469 ref 553 lbound builtin function dcl 89 ref 623 632 641 length builtin function dcl 89 ref 323 732 733 756 level_count 3 based bit(9) level 3 packed unaligned dcl 469 ref 535 535 line1 000241 automatic varying char(80) dcl 53 set ref 706* 710* 710 727* 727 732* 732 732 735* 750* 752* 752 755 756* 756 756 757* line1_sw 000313 automatic bit(1) initial unaligned dcl 54 set ref 54* 711* 728* 732 735* line2 000266 automatic varying char(80) dcl 53 set ref 706* 718* 719* 719 733* 733 733 735* line2_sw 000314 automatic bit(1) initial unaligned dcl 54 set ref 54* 720* 733 735* lnpos 000364 automatic fixed bin(17,0) dcl 64 set ref 328* 335* 340 341* 341 342 long 0(31) based bit(1) level 2 packed unaligned dcl 6-32 ref 568 600 613 mask 40 based bit(72) level 2 packed unaligned dcl 3-12 set ref 382* 432 432 432 432 432 mc based structure level 1 dcl 3-12 mc_err 0(18) based bit(1) level 2 packed unaligned dcl 6-32 ref 261 mc_stored 0(33) based bit(1) level 2 packed unaligned dcl 6-32 set ref 193* 197* mcm 3550 based bit(72) array level 3 dcl 2-11 ref 382 mcp 000544 automatic pointer dcl 3-10 set ref 177* 189 263 264 264 264 276* 296* 308 376* 379 380 381 382 383 384 385 405 405 405 405 405 405 405 405 405 405 405 405 405 405 405 405 409 409 409 409 412 412 419 419 424 426 432 432 432 432 432 435 436 436 436 450 450 450 457 458 523 529 529 544 544 557 557 568 568 568 568 568 568 568 568 593 597 599 613 613 613 613 613 613 613 613 mif 4(30) based bit(1) level 3 packed unaligned dcl 3-56 ref 362 mis 0(17) based bit(1) level 2 packed unaligned dcl 6-32 ref 255 misc_registers 3540 based structure level 2 dcl 2-11 modereg 3574 based bit(36) level 3 dcl 2-11 set ref 388 388* name 1 based char(32) level 2 dcl 1-6 ref 684 no_scu_data 000367 automatic bit(1) unaligned dcl 65 set ref 192 309* 312* non_val_flt 000370 automatic bit(1) unaligned dcl 65 set ref 309* 320* 617 null builtin function dcl 89 ref 686 686 687 687 odd_inst 7 based bit(36) level 2 dcl 3-56 set ref 687 687 port_name 002647 constant char(3) initial array unaligned dcl 109 ref 718 port_stat 1(20) based structure level 2 packed unaligned dcl 3-56 ppr based structure level 2 in structure "scu" packed unaligned dcl 3-56 in procedure "azm_display_mc_" set ref 631 ppr 0(03) based bit(1) level 2 in structure "arg_bits_def" packed unaligned dcl 6-32 in procedure "azm_display_mc_" ref 250 pr 0(23) based bit(1) array level 2 packed unaligned dcl 6-32 ref 226 print_ia 000356 automatic bit(1) unaligned dcl 62 set ref 207* 219* 309* 357* prn 3(22) based bit(3) level 4 in structure "scu" packed unaligned dcl 3-56 in procedure "azm_display_mc_" set ref 544* 544 544 prn 3(26) based bit(3) level 4 in structure "scu" packed unaligned dcl 3-56 in procedure "azm_display_mc_" set ref 557* 557 557 prn 3(18) based bit(3) level 4 in structure "scu" packed unaligned dcl 3-56 in procedure "azm_display_mc_" set ref 529* 529 529 prs based pointer array level 2 in structure "mc" dcl 3-12 in procedure "azm_display_mc_" set ref 379* 529 529 544 544 557 557 593 597* 599* prs 0(22) based bit(1) level 2 in structure "arg_bits_def" packed unaligned dcl 6-32 in procedure "azm_display_mc_" ref 220 prs 3500 based pointer array level 2 in structure "dump" dcl 2-11 in procedure "azm_display_mc_" ref 379 prv 3(21) based bit(1) level 4 in structure "scu" packed unaligned dcl 3-56 in procedure "azm_display_mc_" ref 529 prv 3(25) based bit(1) level 4 in structure "scu" packed unaligned dcl 3-56 in procedure "azm_display_mc_" ref 544 prv 3(29) based bit(1) level 4 in structure "scu" packed unaligned dcl 3-56 in procedure "azm_display_mc_" ref 557 psr 0(03) based bit(15) level 3 packed unaligned dcl 3-56 set ref 668 ptrfmt 002652 constant char(44) initial unaligned dcl 107 ref 594 597 ptrlen 3600 based bit(36) array level 2 dcl 2-11 ref 385 pwrd based structure level 1 dcl 73 q 25 based bit(36) level 3 packed unaligned dcl 3-12 set ref 409* 426* qreg 0(16) based bit(1) level 2 packed unaligned dcl 6-32 ref 240 ralr 27(33) based bit(3) level 3 packed unaligned dcl 3-12 set ref 412* ref_name 000166 automatic char(168) unaligned dcl 51 set ref 678* 679* refptr 000362 automatic pointer dcl 63 set ref 677* 678* 679* regs 0(06) based bit(1) level 2 in structure "arg_bits_def" packed unaligned dcl 6-32 in procedure "azm_display_mc_" ref 230 regs 20 based structure level 2 in structure "mc" packed unaligned dcl 3-12 in procedure "azm_display_mc_" set ref 380* regs 3520 based structure level 2 in structure "dump" dcl 2-11 in procedure "azm_display_mc_" ref 380 residue 5(12) based fixed bin(23,0) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" ref 547 547 residue 3(12) based fixed bin(23,0) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" set ref 535* residue 7(12) based fixed bin(23,0) level 3 in structure "eis_info_fmt" packed unaligned dcl 469 in procedure "display_eis_info_" ref 561 561 rtrim builtin function dcl 89 ref 460 460 sci_ptr 000516 automatic pointer dcl 71 set ref 177* 276* 294* 376* scu 3540 based bit(36) array level 3 in structure "dump" dcl 2-11 in procedure "azm_display_mc_" ref 381 scu 0(02) based bit(1) level 2 in structure "arg_bits_def" packed unaligned dcl 6-32 in procedure "azm_display_mc_" ref 242 scu 30 based bit(36) array level 2 in structure "mc" packed unaligned dcl 3-12 in procedure "azm_display_mc_" set ref 189 308 381* 613* 613* 613* 613* 613* 613* 613* 613* scu based structure level 1 dcl 3-56 in procedure "azm_display_mc_" set ref 310 scup 000546 automatic pointer dcl 3-54 set ref 189* 308* 310 316 316 325 354 355 355 355 362 529 529 529 529 544 544 544 544 557 557 557 557 620 620 620 622 631 640 646 668 668 677 677 686 686 687 687 ssu_$get_temp_segment 000026 constant entry external dcl 42 ref 376 ssu_$release_temp_segment 000030 constant entry external dcl 43 ref 177 276 string builtin function dcl 89 ref 310 substr builtin function dcl 89 set ref 320 324* 324 327* 334* 340* 340 345 345 386 386 386 386 432 432 432 432 529 529 544 544 557 557 627* 636* 654* 709 726 732 733 752 756 t 27 based bit(27) level 3 packed unaligned dcl 3-12 set ref 412* tag_ 000533 automatic char(4) initial unaligned dcl 83 set ref 83* 649* 653 655* tag_prt 000532 automatic bit(1) initial unaligned dcl 82 set ref 82* 650* 655* temp_index 000372 automatic fixed bin(17,0) dcl 67 set ref 338* 339* three_desc 011056 constant bit(3) initial unaligned dcl 519 ref 553 tm 0(20) based bit(1) level 2 packed unaligned dcl 6-32 ref 267 tpr 0(04) based bit(1) level 2 in structure "arg_bits_def" packed unaligned dcl 6-32 in procedure "azm_display_mc_" ref 251 tpr 2 based structure level 2 in structure "scu" packed unaligned dcl 3-56 in procedure "azm_display_mc_" tsna 3(18) based structure level 3 packed unaligned dcl 3-56 tsnb 3(22) based structure level 3 packed unaligned dcl 3-56 tsnc 3(26) based structure level 3 packed unaligned dcl 3-56 tsr 2(03) based bit(15) level 3 packed unaligned dcl 3-56 ref 677 tsr_stat 3(18) based structure level 2 packed unaligned dcl 3-56 tsrpr 000355 automatic bit(1) unaligned dcl 61 set ref 318* 330* 336* 359 619 unspec builtin function dcl 89 set ref 330 379* 379 380* 380 381* 381 382* 382 529 529 544 544 557 557 w1 based fixed bin(35,0) level 2 dcl 73 set ref 594* 600* w2 1 based fixed bin(35,0) level 2 dcl 73 set ref 594* 600* x 20 based bit(18) array level 3 packed unaligned dcl 3-12 set ref 405 405 405 405 405 405 405 405 405 405 405 405 405 405 405 405 419 419 xreg 0(07) based bit(1) array level 2 packed unaligned dcl 6-32 ref 237 NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. AMU_INFO_VERSION internal static char(8) initial unaligned dcl 5-57 AMU_INFO_VERSION_1 internal static char(8) initial unaligned dcl 5-56 AMU_INFO_VERSION_2 internal static char(8) initial unaligned dcl 5-58 DUMP_VERSION_1 internal static fixed bin(17,0) initial dcl 2-120 DUMP_VERSION_2 internal static fixed bin(17,0) initial dcl 2-121 FDUMP_PROCESS_TYPE internal static fixed bin(17,0) initial dcl 5-47 FDUMP_TYPE internal static fixed bin(17,0) initial dcl 5-47 INDIRECT_TYPE internal static fixed bin(17,0) initial dcl 5-47 ITP_MODIFIER internal static bit(6) initial unaligned dcl 4-56 ITS_MODIFIER internal static bit(6) initial unaligned dcl 4-55 NETWORK_FDUMP_TYPE internal static fixed bin(17,0) initial dcl 5-47 NETWORK_ONLINE_TYPE internal static fixed bin(17,0) initial dcl 5-47 ONLINE_PROCESS_TYPE internal static fixed bin(17,0) initial dcl 5-47 ONLINE_TYPE internal static fixed bin(17,0) initial dcl 5-47 PDIR_SUFFIX internal static char(4) initial unaligned dcl 5-60 SAVED_PROC_TYPE internal static fixed bin(17,0) initial dcl 5-47 abx internal static fixed bin(17,0) initial dcl 3-42 amu_area based area(1024) dcl 5-43 amu_info based structure level 1 dcl 5-3 apx internal static fixed bin(17,0) initial dcl 3-42 arg_bits based structure level 1 dcl 6-23 bbx internal static fixed bin(17,0) initial dcl 3-42 bpx internal static fixed bin(17,0) initial dcl 3-42 iox_$iocb_version_sentinel external static char(4) dcl 1-51 itp based structure level 1 dcl 4-18 itp_unsigned based structure level 1 dcl 4-43 its_unsigned based structure level 1 dcl 4-30 lbx internal static fixed bin(17,0) initial dcl 3-42 lpx internal static fixed bin(17,0) initial dcl 3-42 number_val_args internal static fixed bin(17,0) initial dcl 6-3 sbx internal static fixed bin(17,0) initial dcl 3-42 scux based structure level 1 dcl 3-207 spx internal static fixed bin(17,0) initial dcl 3-42 time automatic char(24) unaligned dcl 60 v1_dump based structure level 1 dcl 2-83 valid_mc_arg internal static char(8) initial array unaligned dcl 6-5 what_prs based structure level 1 dcl 6-26 NAMES DECLARED BY EXPLICIT CONTEXT. azm_display_mc_ 003710 constant entry external dcl 8 azm_display_mc_$regs_only 004401 constant entry external dcl 279 by_pass_reg 004236 constant label dcl 242 ref 234 bypass_misc 004350 constant label dcl 270 ref 258 bypass_ppr_tpr 004271 constant label dcl 255 ref 247 bypass_prs 004166 constant label dcl 230 ref 223 display_aq_reg 005547 constant entry internal dcl 421 ref 239 240 display_eis_info_ 006070 constant entry internal dcl 466 ref 213 272 display_mc_code 006003 constant entry internal dcl 455 ref 246 261 434 display_misc_ 005625 constant entry internal dcl 429 ref 210 257 display_pr_regs_ 006743 constant entry internal dcl 578 ref 203 221 282 display_regs_ 005311 constant entry internal dcl 400 ref 205 232 284 display_scu_ 007226 constant entry internal dcl 608 ref 208 244 display_time 005715 constant entry internal dcl 443 ref 267 438 display_x_reg 005507 constant entry internal dcl 416 ref 237 eis_oct 006667 constant label dcl 568 ref 553 error_return 004421 constant label dcl 765 ref 204 206 209 211 214 222 227 233 245 273 283 285 init_dump_display 005061 constant entry internal dcl 374 ref 182 init_scu_data 004451 constant entry internal dcl 304 ref 190 391 interpret_ext_fault_reg 010717 constant entry internal dcl 744 ref 264 436 interpret_fault_reg 010350 constant entry internal dcl 692 ref 263 435 print_inst 010164 constant entry internal dcl 682 ref 252 657 print_ppr 007767 constant entry internal dcl 666 ref 250 618 print_pr_reg 006774 constant entry internal dcl 590 ref 226 584 print_tpr 010070 constant entry internal dcl 675 ref 251 619 setup 004424 constant entry internal dcl 289 ref 175 281 start_display 004024 constant label dcl 200 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 11246 11302 11061 11256 Length 11660 11061 34 342 165 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME azm_display_mc_ 1328 external procedure is an external procedure. on unit on line 176 70 on unit setup internal procedure shares stack frame of external procedure azm_display_mc_. init_scu_data internal procedure shares stack frame of external procedure azm_display_mc_. init_dump_display internal procedure shares stack frame of external procedure azm_display_mc_. display_regs_ internal procedure shares stack frame of external procedure azm_display_mc_. display_x_reg internal procedure shares stack frame of external procedure azm_display_mc_. display_aq_reg internal procedure shares stack frame of external procedure azm_display_mc_. display_misc_ internal procedure shares stack frame of external procedure azm_display_mc_. display_time internal procedure shares stack frame of external procedure azm_display_mc_. display_mc_code internal procedure shares stack frame of external procedure azm_display_mc_. display_eis_info_ internal procedure shares stack frame of external procedure azm_display_mc_. display_pr_regs_ internal procedure shares stack frame of external procedure azm_display_mc_. print_pr_reg internal procedure shares stack frame of external procedure azm_display_mc_. display_scu_ internal procedure shares stack frame of external procedure azm_display_mc_. print_ppr internal procedure shares stack frame of external procedure azm_display_mc_. print_tpr internal procedure shares stack frame of external procedure azm_display_mc_. print_inst internal procedure shares stack frame of external procedure azm_display_mc_. interpret_fault_reg internal procedure shares stack frame of external procedure azm_display_mc_. interpret_ext_fault_reg internal procedure shares stack frame of external procedure azm_display_mc_. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME azm_display_mc_ 000100 error_code_mc azm_display_mc_ 000101 iocb_name azm_display_mc_ 000112 iocbp azm_display_mc_ 000114 by_name azm_display_mc_ 000166 ref_name azm_display_mc_ 000240 eis_info_valid azm_display_mc_ 000241 line1 azm_display_mc_ 000266 line2 azm_display_mc_ 000313 line1_sw azm_display_mc_ 000314 line2_sw azm_display_mc_ 000315 at_by_wd azm_display_mc_ 000316 cvbinbuf azm_display_mc_ 000321 aligned_error_message azm_display_mc_ 000352 i azm_display_mc_ 000353 j azm_display_mc_ 000354 code azm_display_mc_ 000355 tsrpr azm_display_mc_ 000356 print_ia azm_display_mc_ 000360 byptr azm_display_mc_ 000362 refptr azm_display_mc_ 000364 lnpos azm_display_mc_ 000365 flt_lng azm_display_mc_ 000366 inst6 azm_display_mc_ 000367 no_scu_data azm_display_mc_ 000370 non_val_flt azm_display_mc_ 000371 fault_index azm_display_mc_ 000372 temp_index azm_display_mc_ 000373 flt_ln azm_display_mc_ 000424 FLT_LN azm_display_mc_ 000455 IA_LN azm_display_mc_ 000506 flt_bf azm_display_mc_ 000516 sci_ptr azm_display_mc_ 000520 PTR_STR azm_display_mc_ 000526 PR_ptr azm_display_mc_ 000530 TAG_ptr azm_display_mc_ 000532 tag_prt azm_display_mc_ 000533 tag_ azm_display_mc_ 000542 dumpptr azm_display_mc_ 000544 mcp azm_display_mc_ 000546 scup azm_display_mc_ 000550 amu_info_ptr azm_display_mc_ 000552 arg_bits_ptr azm_display_mc_ 000652 eis_info_ptr display_eis_info_ 000662 i display_pr_regs_ 000730 fault_no interpret_fault_reg 000731 break interpret_fault_reg 000740 indx interpret_ext_fault_reg THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. alloc_cs cat_realloc_cs call_ext_out_desc call_ext_out return enable shorten_stack ext_entry int_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. amu_$get_name convert_status_code_ cv_bin_$oct date_time_$format db_print ioa_ ioa_$rsnnl ssu_$get_temp_segment ssu_$release_temp_segment THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. iox_$user_output LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 54 003674 82 003676 83 003677 8 003703 175 003716 176 003717 177 003733 178 003751 180 003752 182 003757 183 003760 184 003762 185 003764 187 003765 189 003766 190 003771 192 003772 193 003774 194 004000 195 004017 197 004020 200 004024 203 004031 204 004032 205 004034 206 004035 207 004037 208 004070 209 004071 210 004073 211 004074 212 004076 213 004100 214 004101 216 004103 219 004104 220 004135 221 004142 222 004143 223 004145 225 004146 226 004153 227 004162 228 004164 230 004166 232 004173 233 004174 234 004176 236 004177 237 004203 238 004212 239 004214 240 004225 242 004236 244 004243 245 004244 246 004246 247 004247 250 004250 251 004255 252 004263 255 004271 257 004276 258 004277 261 004300 262 004305 263 004312 264 004321 267 004342 270 004350 272 004355 273 004356 276 004360 277 004376 279 004377 281 004407 282 004410 283 004411 284 004413 285 004414 286 004416 287 004420 765 004421 767 004423 289 004424 293 004425 294 004431 295 004434 296 004437 297 004442 298 004446 300 004450 304 004451 308 004452 309 004455 310 004462 312 004473 313 004475 315 004476 316 004500 317 004512 318 004521 319 004522 320 004532 323 004542 324 004544 325 004547 326 004552 327 004556 328 004561 329 004563 330 004571 331 004600 332 004602 334 004603 335 004606 336 004610 338 004612 339 004614 340 004625 341 004641 342 004643 343 004645 344 004651 345 004656 348 004726 349 004727 351 004763 352 004765 354 004770 355 004775 357 005037 359 005041 361 005046 362 005050 364 005057 366 005060 374 005061 376 005062 377 005106 378 005122 379 005126 380 005132 381 005135 382 005140 383 005144 384 005146 385 005153 386 005167 388 005216 389 005241 390 005264 391 005307 392 005310 400 005311 404 005312 405 005326 409 005424 412 005457 414 005506 416 005507 419 005511 420 005546 421 005547 424 005551 426 005601 427 005624 429 005625 432 005626 434 005662 435 005663 436 005672 438 005713 441 005714 443 005715 450 005716 452 006002 455 006003 457 006004 458 006007 459 006010 460 006025 461 006066 462 006067 466 006070 521 006071 523 006105 525 006110 526 006136 528 006143 529 006160 535 006222 538 006311 540 006312 542 006327 543 006334 544 006351 547 006413 549 006474 551 006475 553 006512 555 006517 556 006523 557 006540 561 006602 564 006651 566 006652 568 006667 572 006742 578 006743 582 006744 583 006763 584 006767 585 006771 586 006773 590 006774 593 006776 594 007002 597 007052 599 007121 600 007171 602 007225 608 007226 611 007227 613 007244 617 007317 618 007341 619 007342 620 007345 621 007405 622 007410 623 007413 624 007421 625 007462 626 007464 627 007470 628 007474 629 007515 631 007520 632 007522 633 007527 634 007570 635 007572 636 007576 637 007602 638 007623 640 007626 641 007631 642 007637 643 007700 645 007702 646 007704 648 007710 649 007712 650 007716 653 007720 654 007731 655 007735 657 007765 659 007766 666 007767 668 007770 669 010003 670 010034 673 010067 675 010070 677 010071 678 010104 679 010135 680 010163 682 010164 684 010165 685 010171 686 010206 687 010265 688 010347 692 010350 704 010352 706 010360 708 010362 709 010367 710 010375 711 010434 713 010437 715 010441 716 010442 717 010451 718 010462 719 010501 720 010547 721 010552 723 010554 725 010556 726 010563 727 010571 728 010630 730 010633 732 010635 733 010646 735 010657 737 010716 744 010717 750 010721 751 010722 752 010727 753 010774 755 010777 756 011004 757 011012 761 011037 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved