COMPILATION LISTING OF SEGMENT azm_find_mem_box_ Compiled by: Multics PL/I Compiler, Release 28d, of October 4, 1983 Compiled at: Honeywell Multics Op. - System M Compiled on: 11/19/84 1125.8 mst Mon Options: optimize map 1 /* *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Information Systems Inc., 1983 * 4* * * 5* *********************************************************** */ 6 azm_find_mem_box_: 7 proc (P_amu_info_ptr, P_address, P_segno, P_offset, P_code); 8 9 /* format: style4,delnl,insnl,ifthenstmt,indnoniterend,ifthendo,ifthen,^thendo */ 10 11 dcl P_amu_info_ptr ptr; 12 dcl P_address fixed bin (35); 13 dcl P_code fixed bin (35); 14 dcl P_segno fixed bin; 15 dcl P_offset fixed bin (18); 16 dcl code fixed bin (35); 17 18 dcl address fixed bin (35); 19 dcl page_addr fixed bin; 20 dcl (i, offset) fixed bin (17); 21 dcl control_data_ptr ptr; 22 dcl range fixed bin (18); 23 dcl temp_ptr ptr; 24 dcl brief_sw bit (1) init ("0"b); 25 dcl 1 controller_data (0:7) aligned like scs$controller_data; 26 27 dcl amu_$definition_ptr entry (ptr, char (*), char (*), fixed bin (35)) returns (ptr); 28 dcl amu_$do_translation_by_ptr entry (ptr, ptr, fixed bin (18), ptr, fixed bin (35)); 29 dcl amu_$get_name entry (ptr, ptr) returns (char (*)); 30 dcl ioa_ entry () options (variable); 31 dcl (addr, addrel, baseptr, divide, 32 substr, size) builtin; 33 34 go to common; 35 36 37 azm_find_mem_box_$bf: 38 entry (P_amu_info_ptr, P_address, P_segno, P_offset, P_code); 39 40 brief_sw = "1"b; 41 42 common: 43 44 amu_info_ptr = P_amu_info_ptr; 45 address = P_address; 46 page_addr = divide (address, 1024, 17, 0); 47 control_data_ptr = amu_$definition_ptr (amu_info_ptr, "scs", "controller_data", code); 48 if code ^= 0 then do; 49 P_code = code; 50 return; 51 end; 52 range = size (controller_data); 53 call amu_$do_translation_by_ptr (amu_info_ptr, control_data_ptr, range, addr (controller_data), code); 54 if code ^= 0 then do; 55 P_code = code; 56 return; 57 end; 58 do i = 0 to 7; 59 if (page_addr >= controller_data (i).base) then do; 60 if page_addr < (controller_data (i).base + controller_data (i).size) then do; 61 temp_ptr = addrel (baseptr (P_segno), P_offset); 62 offset = (address - (controller_data (i).base * 1024)); 63 if ^brief_sw then 64 call ioa_ ("^a (^p):", amu_$get_name (amu_info_ptr, temp_ptr), temp_ptr); 65 call ioa_ ("Absolute Addr ^o (Word ^o in Mem ^a).", 66 address, offset, substr ("abcdefgh", i + 1, 1)); 67 P_code = 0; 68 return; 69 end; 70 end; 71 end; 72 call ioa_ ("Cannot find address ^o.", address); 73 P_code = 0; 74 return; 75 76 1 1 /* BEGIN INCLUDE FILE amu_info.incl.pl1 */ 1 2 1 3 dcl 1 amu_info aligned based (amu_info_ptr), 1 4 2 version char (8) aligned, /* AMU_INFO_VERSION */ 1 5 2 flags aligned, 1 6 3 early_dump bit(1) unal, 1 7 3 pad bit(35) unal, 1 8 2 type fixed bin unal, /* One of the types below */ 1 9 2 time_created fixed bin (71) aligned, /* time created -- for debugging purposes */ 1 10 2 chain, /* a chain of all the amu_info's which exist */ 1 11 3 prev pointer unaligned, 1 12 3 next pointer unaligned, 1 13 1 14 2 area_ptr pointer, /* pointer to area used for allocating things */ 1 15 1 16 2 translation_table_ptr pointer, /* pointer to address map -- always present */ 1 17 /* SEE: amu_translation.incl.pl1 */ 1 18 2 fdump_info_ptr pointer, 1 19 /* pointer to FDUMP info, present if looking at an FDUMP */ 1 20 /* SEE: amu_fdump_info.incl.pl1 */ 1 21 /* old_uid_table pointer if looking at a SAVED PROC. */ 1 22 /* See: amu_old_uid_table */ 1 23 1 24 1 25 2 hardcore_info_ptr pointer, /* pointer to hardcore information -- always present */ 1 26 /* SEE: amu_hardcore_info.incl.pl1 */ 1 27 2 copy_chain pointer, /* pointer to info about segment copies */ 1 28 /* SEE: amu_copy_info.incl.pl1 */ 1 29 2 process_info_ptr pointer, /* pointer to process info for this translation */ 1 30 /* SEE: amu_process_info.incl.pl1 */ 1 31 2 process_idx fixed bin, /* index of process in translation-specifc process table */ 1 32 1 33 2 proc_idx_hold fixed bin, /* a place to keep the index when a changing to another proc */ 1 34 1 35 2 error_info, /* various info about how amu_error_ is to behave */ 1 36 3 error_flags aligned, 1 37 4 handler_exists bit (1) unaligned, /* set to indicate existence of an amu_error handler */ 1 38 4 in_subsystem bit (1) unaligned, /* This amu_info belongs to an ssu_ maintained subsystem */ 1 39 4 pad bit (34) unaligned, 1 40 3 sci_ptr pointer, /* sci_ptr for subsystem, if in_subsystem = "1"b */ 1 41 2 definitions_info_ptr ptr; 1 42 1 43 dcl amu_area area based (amu_info.area_ptr); 1 44 1 45 dcl amu_info_ptr pointer; 1 46 1 47 dcl (FDUMP_TYPE init (1037), /* the various legitimate types of amu_info's */ 1 48 FDUMP_PROCESS_TYPE init (1038), 1 49 ONLINE_TYPE init (1039), 1 50 ONLINE_PROCESS_TYPE init (1040), 1 51 NETWORK_FDUMP_TYPE init (1041), 1 52 NETWORK_ONLINE_TYPE init (1042), 1 53 SAVED_PROC_TYPE init (1043), 1 54 INDIRECT_TYPE init (1044)) fixed bin internal static options (constant); 1 55 1 56 dcl AMU_INFO_VERSION_1 char (8) internal static options (constant) init ("amu_v1"); 1 57 dcl AMU_INFO_VERSION char (8) internal static options (constant) init ("amu_v1"); 1 58 dcl AMU_INFO_VERSION_2 char (8) internal static options (constant) init ("amu_v2"); 1 59 1 60 dcl PDIR_SUFFIX char(4) init("pdir") int static options(constant); 1 61 1 62 /* END INCLUDE FILE amu_info.incl.pl1 */ 77 78 2 1 /* BEGIN INCLUDE FILE scs.incl.pl1 ... March 1983 */ 2 2 /* format: style4 */ 2 3 2 4 /* Information about system controllers */ 2 5 2 6 dcl 1 scs$controller_data (0:7) aligned ext, /* per-controller info */ 2 7 2 size fixed bin (17) unaligned, /* size (in 1024 word blocks) of this controller */ 2 8 2 base fixed bin (17) unaligned, /* abs address (0 mod 1024) for base of this controller */ 2 9 2 eima_data (4) unaligned, /* EIMA information for this controller */ 2 10 3 mask_available bit (1) unaligned, /* ON if corresponding mask exists */ 2 11 3 mask_assigned bit (1) unaligned, /* ON if mask assigned to a port */ 2 12 3 mbz bit (3) unaligned, 2 13 3 mask_assignment fixed bin (3) unaligned, /* port to which mask is assigned */ 2 14 2 info aligned, 2 15 3 online bit (1) unaligned, /* ON if controller is online */ 2 16 3 offline bit (1) unaligned, /* ON if controller is offline but can be added */ 2 17 3 store_a_online bit (1) unaligned, /* ON if store A is online */ 2 18 3 store_a1_online bit (1) unaligned, /* ON if store A1 is online */ 2 19 3 store_b_online bit (1) unaligned, /* ON if store B is online */ 2 20 3 store_b1_online bit (1) unaligned, /* ON if store B1 is online */ 2 21 3 store_b_is_lower bit (1) unaligned, /* ON if store B is lower */ 2 22 3 ext_interlaced bit (1) unaligned, /* ON if this SCU is interlaced with other SCU */ 2 23 3 int_interlaced bit (1) unaligned, /* ON if this SCU is internally interlaced */ 2 24 3 four_word bit (1) unaligned, /* ON if external interlace is 4-word */ 2 25 3 cyclic_priority (7) bit (1) unaligned, /* Cyclic priority for adjacent ports */ 2 26 3 type bit (4) unaligned, /* Model number for this controller */ 2 27 3 abs_wired bit (1) unaligned, /* ON if controller can have abs_wired pages */ 2 28 3 program bit (1) unaligned, /* PROGRAM/MANUAL switch setting */ 2 29 3 mbz bit (13) unaligned, 2 30 2 lower_store_size fixed bin (17) unaligned, /* size (in 1024 word blocks) of lower store */ 2 31 2 upper_store_size fixed bin (17) unaligned; /* size (in 1024 word blocks) of upper store */ 2 32 2 33 /* Information about CPUs */ 2 34 2 35 dcl 1 scs$processor_data (0:7) aligned ext, /* information about CPUs in the system */ 2 36 ( 2 37 2 online bit (1), /* "1"b if CPU is online */ 2 38 2 offline bit (1), /* "1"b if CPU is offline but can be added */ 2 39 2 release_mask bit (1), /* "1"b is this CPU is to give up its mask */ 2 40 2 accept_mask bit (1), /* "1"b if this CPU is to grap mask in idle loop */ 2 41 2 delete_cpu bit (1), /* "1"b if this CPU is to delete itself */ 2 42 2 interrupt_cpu bit (1), /* "1"b if this CPU takes hardware interrupts */ 2 43 2 halted_cpu bit (1), /* "1"b if this CPU has stopped itself (going to BOS) */ 2 44 2 cpu_type fixed bin (2) unsigned, /* 0 => DPS or L68, 1 => DPS8 */ 2 45 2 mbz1 bit (6), 2 46 2 cache_size fixed bin (3) unsigned, /* 0 = No cache; 1 = L68 2K cache; 2 47* 2 = DPS8 8K cache; 3 = DPS8 VS&SC 8K cache; 2 48* 4 = DPS8 VS&SC 16K cache; 5 = DPS8 VS&SC 32K cache 2 49* 7 = ignore cache size (set by ISOLTS reconfig) */ 2 50 2 mbz2 bit (12), 2 51 2 expanded_port bit (1), /* "1"b = on expanded port */ 2 52 2 expander_port fixed bin (2) unsigned, /* The actual expander port */ 2 53 2 controller_port fixed bin (3) unsigned 2 54 ) unaligned; /* Port on controller */ 2 55 2 56 dcl 1 scs$port_data (0:7) aligned external static, /* Info about what is connected to each SCU port */ 2 57 2 assigned fixed bin (4) unsigned unaligned, /* Type of device on this port */ 2 58 2 expander_port bit (1) unaligned, /* "1"b => this port has a port expander */ 2 59 2 expanded_cpu (0:3) bit (1) unaligned, /* "1"b => this expander port has a CPU attached */ 2 60 2 iom_number fixed bin (3) unsigned unaligned, /* IOM number of IOM attached to this port */ 2 61 2 cpu_number (0:3) fixed bin (3) unsigned unaligned, /* CPU number of CPU(s) attached to this port */ 2 62 /* cpu_number (0) is only one if expander_port is "0"b */ 2 63 2 pad bit (12) unaligned; 2 64 2 65 dcl 1 scs$cow (0:7) aligned external, /* Actual connect words */ 2 66 2 pad bit (36) aligned, /* Expander COW's must be odd-word */ 2 67 2 cow, 2 68 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 2 69 3 mbz1 bit (13) unaligned, 2 70 3 expander_command bit (3) unaligned, /* Expander command. */ 2 71 3 mbz2 bit (2) unaligned, 2 72 3 expanded_port bit (1) unaligned, /* "1"b = on expanded port */ 2 73 3 expander_port fixed bin (3) unsigned unaligned, /* Port on expander for cioc */ 2 74 3 mbz3 bit (3) unaligned, 2 75 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 2 76 2 77 dcl 1 scs$cow_ptrs (0:7) external aligned, /* Pointers to COW's */ 2 78 2 rel_cow_ptr bit (18) unal, /* Relative pointer to COW */ 2 79 2 pad bit (12) unal, 2 80 2 tag bit (6) unal; /* Better be zero. */ 2 81 2 82 dcl 1 scs$reconfig_general_cow aligned external, /* Used during reconfig ops. */ 2 83 2 pad bit (36) aligned, 2 84 2 cow, /* Connect operand word, in odd location. */ 2 85 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */ 2 86 3 mbz1 bit (13) unaligned, 2 87 3 expander_command bit (3) unaligned, /* Expander command. */ 2 88 3 mbz2 bit (9) unaligned, 2 89 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */ 2 90 2 91 /* MASKS and PATTERNS */ 2 92 2 93 dcl scs$sys_level bit (72) aligned ext; /* mask used while handling I/O interrupts */ 2 94 dcl scs$open_level bit (72) aligned ext; /* mask used during normal operation */ 2 95 dcl scs$processor_start_mask bit (72) aligned ext; /* mask used when starting up a CPU */ 2 96 dcl scs$cpu_test_mask bit (72) aligned ext; /* mask used for ISOLTS CPU testing */ 2 97 dcl scs$number_of_masks fixed bin ext; /* number of masks (starting at sys_level) */ 2 98 dcl scs$processor_start_pattern bit (36) aligned ext; /* SMIC pattern used to send processor start interrupt */ 2 99 dcl scs$cpu_test_pattern bit (36) aligned ext; /* SMIC pattern used for ISOLTS processor testing */ 2 100 2 101 /* CAM and CACHE clear info */ 2 102 2 103 dcl scs$cam_pair fixed bin (71) ext; /* instructions XEDd when CAMing and clearing CACHE */ 2 104 dcl scs$cam_wait bit (8) aligned ext; /* Used when evicting pages from main memory */ 2 105 2 106 /* MASKING INSTRUCTIONS & POINTERS */ 2 107 2 108 dcl scs$set_mask (0:7) bit (36) aligned ext; /* instructions to set mask (STAQ or SMCM) */ 2 109 dcl scs$read_mask (0:7) bit (36) aligned ext; /* instructions to read mask (LDAQ or RMCM) */ 2 110 dcl scs$mask_ptr (0:7) ptr unaligned ext; /* pointers for real or simulated masks */ 2 111 2 112 /* MISCELLANEOUS */ 2 113 2 114 dcl 1 scs$processor_test_data aligned ext, /* info used for cpu testing */ 2 115 ( 2 116 2 active bit (1), /* = "1"b if cpu currently under test */ 2 117 2 scu_state bit (2), /* state of scu being used for testing (see definition below) */ 2 118 2 pad1 bit (4), 2 119 2 req_mem fixed bin (10), /* dedicated memory required to test this cpu */ 2 120 2 cpu_tag fixed bin (5), /* tag of cpu under test */ 2 121 2 scu_tag fixed bin (5), /* tag of scu being used for cpu testing */ 2 122 2 mask_cpu fixed bin (5) 2 123 ) unaligned; /* tag of active cpu that has mask asigned to above scu */ 2 124 2 125 /* scu_state = "00"b => SCU defined by scs$processor_test_data.scu_tag not yet effected */ 2 126 /* scu_state = "01"b => all core removed from SCU, port mask not yet changed */ 2 127 /* scu_state = "10"b => all core removed from SCU, port mask changed */ 2 128 /* scu_state = "11"b => only 64k at base of SCU being used for testing, original port mask restored */ 2 129 2 130 dcl scs$idle_aptep (0:7) ptr unaligned ext; /* pointer to idle process APTE for each processor */ 2 131 2 132 dcl scs$connect_lock bit (36) aligned ext; /* lock for sending connects */ 2 133 dcl scs$reconfig_lock bit (36) aligned ext; /* Lock used during reconfiguration */ 2 134 dcl scs$trouble_flags bit (8) aligned ext; /* checkoff flags for sys_trouble stopping */ 2 135 dcl scs$bos_restart_flags bit (8) aligned ext; /* checkoff flags for restarting after sys_trouble */ 2 136 dcl scs$nprocessors fixed bin ext; /* number of runnung processors */ 2 137 dcl scs$bos_processor_tag fixed bin (3) ext; /* CPU tag of processor running BOS */ 2 138 dcl scs$faults_initialized bit (1) aligned ext; /* ON after faults have been enabled */ 2 139 dcl scs$sys_trouble_pending bit (1) aligned ext; /* sys_trouble event is pending in the system */ 2 140 dcl scs$fast_cam_pending (0:7) bit (36) aligned ext; /* checkoff cells for cam connect */ 2 141 dcl scs$interrupt_controller fixed bin (3) ext; /* port number of low order controller */ 2 142 dcl scs$processor_start_int_no fixed bin (5) ext; /* interrupt cell for starting a processor */ 2 143 dcl scs$processor bit (8) aligned ext; /* bits ON for online CPUs */ 2 144 dcl scs$processor_start_wait bit (8) aligned ext; /* checkoff flags for waiting for new processor */ 2 145 2 146 dcl scs$trouble_dbrs (0:7) fixed bin (71); /* DBR values at system crash time */ 2 147 2 148 dcl scs$port_addressing_word (0:7) bit (3) aligned ext; /* active module port number for each controller */ 2 149 2 150 dcl scs$cfg_data (0:7) fixed bin (71) aligned ext; /* RSCR-CFG data from each controller */ 2 151 2 152 dcl scs$cfg_data_save fixed bin (71) aligned ext; /* RSCR-CFG save area for ISOLTS CPU testing */ 2 153 2 154 dcl scs$expanded_ports bit (1) unaligned dim (0:7) external; 2 155 /* Which ports have expanders */ 2 156 2 157 dcl scs$processor_switch_data (0:4) bit (36) aligned ext; /* raw data from RSW 0 thru 4 */ 2 158 dcl scs$processor_switch_template (0:4) bit (36) aligned ext; /* expected data from RSW 0 thru 4 */ 2 159 dcl scs$processor_switch_compare (0:4) bit (36) aligned ext; /* discrepancies from expected data */ 2 160 dcl scs$processor_switch_mask (0:4) bit (36) aligned ext; /* masks for comparing switch data */ 2 161 2 162 dcl scs$processor_data_switch_value bit (36) aligned ext; /* Correct value for CPU data switches */ 2 163 2 164 dcl scs$controller_config_size (0:7) fixed bin (14) aligned ext; 2 165 /* Controller size on config card */ 2 166 2 167 dcl scs$reconfig_locker_id char (32) aligned ext; /* process group ID of process doing reconfiguration */ 2 168 2 169 dcl scs$scas_page_table (0:31) bit (36) aligned external static; 2 170 /* PTWs for SCAS pages */ 2 171 2 172 dcl scs$cycle_priority_template bit (7) aligned ext; /* template for setting anti-hog switches */ 2 173 dcl scs$set_cycle_switches bit (1) aligned ext; /* flag to set ant-hog switches */ 2 174 2 175 2 176 dcl ( 2 177 IOM_PORT init (1), 2 178 CPU_PORT init (2), 2 179 BULK_PORT init (3) 2 180 ) fixed bin int static options (constant); /* values for scs$port_data.assigned */ 2 181 2 182 2 183 /* END INCLUDE FILE scs.incl.pl1 */ 79 80 end azm_find_mem_box_; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/15/84 1440.1 azm_find_mem_box_.pl1 >special_ldd>online>6897-11/15/84>azm_find_mem_box_.pl1 77 1 11/15/84 1524.3 amu_info.incl.pl1 >special_ldd>online>6897-11/15/84>amu_info.incl.pl1 79 2 10/12/83 0943.5 scs.incl.pl1 >ldd>include>scs.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. P_address parameter fixed bin(35,0) dcl 12 ref 6 37 45 P_amu_info_ptr parameter pointer dcl 11 ref 6 37 42 P_code parameter fixed bin(35,0) dcl 13 set ref 6 37 49* 55* 67* 73* P_offset parameter fixed bin(18,0) dcl 15 ref 6 37 61 P_segno parameter fixed bin(17,0) dcl 14 ref 6 37 61 addr builtin function dcl 31 ref 53 53 addrel builtin function dcl 31 ref 61 address 000101 automatic fixed bin(35,0) dcl 18 set ref 45* 46 62 65* 72* amu_$definition_ptr 000010 constant entry external dcl 27 ref 47 amu_$do_translation_by_ptr 000012 constant entry external dcl 28 ref 53 amu_$get_name 000014 constant entry external dcl 29 ref 63 amu_info_ptr 000156 automatic pointer dcl 1-45 set ref 42* 47* 53* 63* base 0(18) 000115 automatic fixed bin(17,0) array level 2 packed unaligned dcl 25 set ref 59 60 62 baseptr builtin function dcl 31 ref 61 brief_sw 000114 automatic bit(1) initial unaligned dcl 24 set ref 24* 40* 63 code 000100 automatic fixed bin(35,0) dcl 16 set ref 47* 48 49 53* 54 55 control_data_ptr 000106 automatic pointer dcl 21 set ref 47* 53* controller_data 000115 automatic structure array level 1 dcl 25 set ref 52 53 53 divide builtin function dcl 31 ref 46 i 000103 automatic fixed bin(17,0) dcl 20 set ref 58* 59 60 60 62 65 65* ioa_ 000016 constant entry external dcl 30 ref 63 65 72 offset 000104 automatic fixed bin(17,0) dcl 20 set ref 62* 65* page_addr 000102 automatic fixed bin(17,0) dcl 19 set ref 46* 59 60 range 000110 automatic fixed bin(18,0) dcl 22 set ref 52* 53* scs$controller_data 000020 external static structure array level 1 dcl 2-6 size 000115 automatic fixed bin(17,0) array level 2 in structure "controller_data" packed unaligned dcl 25 in procedure "azm_find_mem_box_" set ref 60 size builtin function dcl 31 in procedure "azm_find_mem_box_" ref 52 substr builtin function dcl 31 ref 65 65 temp_ptr 000112 automatic pointer dcl 23 set ref 61* 63* 63* NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. AMU_INFO_VERSION internal static char(8) initial unaligned dcl 1-57 AMU_INFO_VERSION_1 internal static char(8) initial unaligned dcl 1-56 AMU_INFO_VERSION_2 internal static char(8) initial unaligned dcl 1-58 BULK_PORT internal static fixed bin(17,0) initial dcl 2-176 CPU_PORT internal static fixed bin(17,0) initial dcl 2-176 FDUMP_PROCESS_TYPE internal static fixed bin(17,0) initial dcl 1-47 FDUMP_TYPE internal static fixed bin(17,0) initial dcl 1-47 INDIRECT_TYPE internal static fixed bin(17,0) initial dcl 1-47 IOM_PORT internal static fixed bin(17,0) initial dcl 2-176 NETWORK_FDUMP_TYPE internal static fixed bin(17,0) initial dcl 1-47 NETWORK_ONLINE_TYPE internal static fixed bin(17,0) initial dcl 1-47 ONLINE_PROCESS_TYPE internal static fixed bin(17,0) initial dcl 1-47 ONLINE_TYPE internal static fixed bin(17,0) initial dcl 1-47 PDIR_SUFFIX internal static char(4) initial unaligned dcl 1-60 SAVED_PROC_TYPE internal static fixed bin(17,0) initial dcl 1-47 amu_area based area(1024) dcl 1-43 amu_info based structure level 1 dcl 1-3 scs$bos_processor_tag external static fixed bin(3,0) dcl 2-137 scs$bos_restart_flags external static bit(8) dcl 2-135 scs$cam_pair external static fixed bin(71,0) dcl 2-103 scs$cam_wait external static bit(8) dcl 2-104 scs$cfg_data external static fixed bin(71,0) array dcl 2-150 scs$cfg_data_save external static fixed bin(71,0) dcl 2-152 scs$connect_lock external static bit(36) dcl 2-132 scs$controller_config_size external static fixed bin(14,0) array dcl 2-164 scs$cow external static structure array level 1 dcl 2-65 scs$cow_ptrs external static structure array level 1 dcl 2-77 scs$cpu_test_mask external static bit(72) dcl 2-96 scs$cpu_test_pattern external static bit(36) dcl 2-99 scs$cycle_priority_template external static bit(7) dcl 2-172 scs$expanded_ports external static bit(1) array unaligned dcl 2-154 scs$fast_cam_pending external static bit(36) array dcl 2-140 scs$faults_initialized external static bit(1) dcl 2-138 scs$idle_aptep external static pointer array unaligned dcl 2-130 scs$interrupt_controller external static fixed bin(3,0) dcl 2-141 scs$mask_ptr external static pointer array unaligned dcl 2-110 scs$nprocessors external static fixed bin(17,0) dcl 2-136 scs$number_of_masks external static fixed bin(17,0) dcl 2-97 scs$open_level external static bit(72) dcl 2-94 scs$port_addressing_word external static bit(3) array dcl 2-148 scs$port_data external static structure array level 1 dcl 2-56 scs$processor external static bit(8) dcl 2-143 scs$processor_data external static structure array level 1 dcl 2-35 scs$processor_data_switch_value external static bit(36) dcl 2-162 scs$processor_start_int_no external static fixed bin(5,0) dcl 2-142 scs$processor_start_mask external static bit(72) dcl 2-95 scs$processor_start_pattern external static bit(36) dcl 2-98 scs$processor_start_wait external static bit(8) dcl 2-144 scs$processor_switch_compare external static bit(36) array dcl 2-159 scs$processor_switch_data external static bit(36) array dcl 2-157 scs$processor_switch_mask external static bit(36) array dcl 2-160 scs$processor_switch_template external static bit(36) array dcl 2-158 scs$processor_test_data external static structure level 1 dcl 2-114 scs$read_mask external static bit(36) array dcl 2-109 scs$reconfig_general_cow external static structure level 1 dcl 2-82 scs$reconfig_lock external static bit(36) dcl 2-133 scs$reconfig_locker_id external static char(32) dcl 2-167 scs$scas_page_table external static bit(36) array dcl 2-169 scs$set_cycle_switches external static bit(1) dcl 2-173 scs$set_mask external static bit(36) array dcl 2-108 scs$sys_level external static bit(72) dcl 2-93 scs$sys_trouble_pending external static bit(1) dcl 2-139 scs$trouble_dbrs automatic fixed bin(71,0) array dcl 2-146 scs$trouble_flags external static bit(8) dcl 2-134 NAMES DECLARED BY EXPLICIT CONTEXT. azm_find_mem_box_ 000055 constant entry external dcl 6 azm_find_mem_box_$bf 000066 constant entry external dcl 37 common 000076 constant label dcl 42 set ref 34 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 514 536 403 524 Length 756 403 22 203 110 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME azm_find_mem_box_ 166 external procedure is an external procedure. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME azm_find_mem_box_ 000100 code azm_find_mem_box_ 000101 address azm_find_mem_box_ 000102 page_addr azm_find_mem_box_ 000103 i azm_find_mem_box_ 000104 offset azm_find_mem_box_ 000106 control_data_ptr azm_find_mem_box_ 000110 range azm_find_mem_box_ 000112 temp_ptr azm_find_mem_box_ 000114 brief_sw azm_find_mem_box_ 000115 controller_data azm_find_mem_box_ 000156 amu_info_ptr azm_find_mem_box_ THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out_desc call_ext_out return shorten_stack ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. amu_$definition_ptr amu_$do_translation_by_ptr amu_$get_name ioa_ THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. scs$controller_data LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 24 000045 6 000050 34 000063 37 000064 40 000074 42 000076 45 000102 46 000104 47 000106 48 000144 49 000146 50 000150 52 000151 53 000153 54 000174 55 000176 56 000200 58 000201 59 000205 60 000215 61 000223 62 000233 63 000244 65 000312 67 000350 68 000352 71 000353 72 000355 73 000400 74 000402 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved