COMPILATION LISTING OF SEGMENT !BBBJNkPCZFwGzf Compiled by: Multics PL/I Compiler, Release 28d, of October 4, 1983 Compiled at: Honeywell Multics Op. - System M Compiled on: 04/26/84 1324.0 mst Thu Options: table map 1 /* *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Information Systems Inc., 1984 * 4* * * 5* *********************************************************** */ 6 7 cache_threshold_defaults_: 8 proc; 9 10 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ 11 /* */ 12 /* cache_threshold_defaults_ - this segment contains the default cache threshold values */ 13 /* as defined by HIS (LCPD HW Eng.) as an acceptable error rate for the cache memory in */ 14 /* the L68, DPS68 and DPS8 processors. */ 15 /* */ 16 /* Created: 2/84 by GA Texada */ 17 /* */ 18 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ 19 20 21 /* format: style1,ind2,^inddcls,ifthenstmt,dclind2,declareind2,ifthendo,ifthen*/ 22 23 dcl code fixed bin (35), 24 1 cdsa aligned like cds_args, 25 1 cache_threshold_defaults_ aligned like cache_threshold_data; 26 27 dcl (addr, null, size, string, unspec) builtin; 28 29 dcl com_err_ entry () options (variable), 30 create_data_segment_ entry (ptr, fixed bin (35)); 31 32 33 unspec (cache_threshold_defaults_) = ""b; /* start clean */ 34 cache_threshold_defaults_.pri_dir_parity = 4; /* L68 use only */ 35 cache_threshold_defaults_.port_buffer(*) = 1; /* HW Eng. said .2, but... */ 36 cache_threshold_defaults_.pri_dir = 2; 37 cache_threshold_defaults_.wno_parity_any_port = 1;/* HW Eng. said .4 but... */ 38 cache_threshold_defaults_.dup_dir_parity(*) = 1; 39 cache_threshold_defaults_.dup_dir_multimatch = 0; /* These are NOT acceptable */ 40 41 cdsa.sections (1).p = addr (cache_threshold_defaults_); 42 cdsa.sections (1).len = size (cache_threshold_defaults_); 43 cdsa.sections (1).struct_name = "cache_threshold_defaults_"; 44 cdsa.seg_name = "cache_threshold_defaults_"; 45 cdsa.num_exclude_names = 0; 46 cdsa.exclude_array_ptr = null (); 47 string (cdsa.switches) = "0"b; 48 cdsa.switches.have_text = "1"b; 49 call create_data_segment_ (addr (cdsa), code); 50 if code ^= 0 then call com_err_ (code, "cache_threshold_defaults_"); 51 return; 52 1 1 /* START OF: cache_threshold_data.incl.pl1 * * * * * * * * * * * * * * * * */ 1 2 1 3 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ 1 4 /* */ 1 5 /* This include file is used by cache_threshold_defaults_ and monitor_cache to provide */ 1 6 /* for comparing the acceptable cache memory error rates. */ 1 7 /* Created: 2/84 by GA Texada */ 1 8 /* */ 1 9 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ 1 10 1 11 1 12 1 13 dcl cache_threshold_datap ptr, 1 14 1 15 1 cache_threshold_data aligned based(cache_threshold_datap), 1 16 1 17 2 pri_dir_parity fixed bin (35), /* All cache types */ 1 18 /* PFR bit 32 */ 1 19 2 port_buffer(4) fixed bin (35), /* DPS8 cache types all 4 ports */ 1 20 /* EFR bits 36-39 */ 1 21 2 pri_dir fixed bin (35), /* DPS8 cache types */ 1 22 /* EFR bit 40 */ 1 23 2 wno_parity_any_port fixed bin (35), /* DPS8 NON VS&SC only */ 1 24 /* EFR bit 41 */ 1 25 2 dup_dir_parity(4) fixed bin (35), /* DPS8 VS&SC only, lvl 0-3 */ 1 26 /* EFR bits 42-45 */ 1 27 2 dup_dir_multimatch fixed bin (35), /* DPS8 cache types */ 1 28 /* EFR bit 46 */ 1 29 2 pad(5) fixed bin(35), /* UNUSED in the error counter array */ 1 30 1 31 cache_threshold_data_array(17) fixed bin(35) aligned based(cache_threshold_datap); 1 32 1 33 1 34 /* END OF: cache_threshold_data.incl.pl1 * * * * * * * * * * * * * * * * */ 53 54 2 1 /* BEGIN INCLUDE FILE cds_args.incl.pl1 */ 2 2 2 3 dcl 1 cds_args based aligned, 2 4 2 sections (2), 2 5 3 p ptr, /* pointer to data for text/static section */ 2 6 3 len fixed bin (18), /* size of text/static section */ 2 7 3 struct_name char (32), /* name of declared structure for this section */ 2 8 2 seg_name char (32), /* name to create segment by */ 2 9 2 num_exclude_names fixed bin, /* number of names in exclude array */ 2 10 2 exclude_array_ptr ptr, /* pointer to array of exclude names */ 2 11 2 switches, /* control switches */ 2 12 3 defs_in_link bit (1) unal, /* says put defs in linkage */ 2 13 3 separate_static bit (1) unal, /* says separate static section is wanted */ 2 14 3 have_text bit (1) unal, /* ON if text section given */ 2 15 3 have_static bit (1) unal, /* ON if static section given */ 2 16 3 pad bit (32) unal; 2 17 2 18 dcl exclude_names (1) char (32) based; /* pointed to be cds_args.exclude_array_ptr */ 2 19 2 20 /* END INCLUDE FILE cds_args.incl.pl1 */ 55 56 end cache_threshold_defaults_; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 04/26/84 1320.0 !BBBJNkPCZFwGzf.pl1 >special_ldd>on>gt>cache_threshold_defaults_.cds 53 1 04/26/84 1322.0 cache_threshold_data.incl.pl1 >special_ldd>on>gt>cache_threshold_data.incl.pl1 55 2 04/01/76 2209.5 cds_args.incl.pl1 >ldd>include>cds_args.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. addr builtin function dcl 27 ref 41 49 49 cache_threshold_data based structure level 1 dcl 1-13 cache_threshold_datap 000170 automatic pointer dcl 1-13 ref 1-13 1-13 1-13 1-13 1-13 1-13 1-13 1-13 cache_threshold_defaults_ 000147 automatic structure level 1 dcl 23 set ref 33* 41 42 cds_args based structure level 1 dcl 2-3 cdsa 000102 automatic structure level 1 dcl 23 set ref 49 49 code 000100 automatic fixed bin(35,0) dcl 23 set ref 49* 50 50* com_err_ 000012 constant entry external dcl 29 ref 50 create_data_segment_ 000014 constant entry external dcl 29 ref 49 dup_dir_multimatch 13 000147 automatic fixed bin(35,0) level 2 dcl 23 set ref 39* dup_dir_parity 7 000147 automatic fixed bin(35,0) array level 2 dcl 23 set ref 38* exclude_array_ptr 42 000102 automatic pointer level 2 dcl 23 set ref 46* have_text 44(02) 000102 automatic bit(1) level 3 packed unaligned dcl 23 set ref 48* len 2 000102 automatic fixed bin(18,0) array level 3 dcl 23 set ref 42* null builtin function dcl 27 ref 46 num_exclude_names 40 000102 automatic fixed bin(17,0) level 2 dcl 23 set ref 45* p 000102 automatic pointer array level 3 dcl 23 set ref 41* port_buffer 1 000147 automatic fixed bin(35,0) array level 2 dcl 23 set ref 35* pri_dir 5 000147 automatic fixed bin(35,0) level 2 dcl 23 set ref 36* pri_dir_parity 000147 automatic fixed bin(35,0) level 2 dcl 23 set ref 34* sections 000102 automatic structure array level 2 dcl 23 seg_name 30 000102 automatic char(32) level 2 dcl 23 set ref 44* size builtin function dcl 27 ref 42 string builtin function dcl 27 set ref 47* struct_name 3 000102 automatic char(32) array level 3 dcl 23 set ref 43* switches 44 000102 automatic structure level 2 dcl 23 set ref 47* unspec builtin function dcl 27 set ref 33* wno_parity_any_port 6 000147 automatic fixed bin(35,0) level 2 dcl 23 set ref 37* NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. cache_threshold_data_array based fixed bin(35,0) array dcl 1-13 exclude_names based char(32) array unaligned dcl 2-18 NAME DECLARED BY EXPLICIT CONTEXT. cache_threshold_defaults_ 000014 constant entry external dcl 7 THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION. STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 212 230 134 222 Length 1430 134 16 1163 56 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME cache_threshold_defaults_ 150 external procedure is an external procedure. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME cache_threshold_defaults_ 000100 code cache_threshold_defaults_ 000102 cdsa cache_threshold_defaults_ 000147 cache_threshold_defaults_ cache_threshold_defaults_ 000170 cache_threshold_datap cache_threshold_defaults_ THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out_desc call_ext_out return ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. com_err_ create_data_segment_ NO EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 7 000013 33 000021 34 000024 35 000026 36 000037 37 000041 38 000043 39 000055 41 000056 42 000060 43 000062 44 000065 45 000070 46 000071 47 000073 48 000074 49 000076 50 000111 51 000133 Object Segment >special_ldd>on>gt>cache_threshold_defaults_ Created on 04/26/84 1324.2 mst Thu by GJohnson.SysMaint.a using create_data_segment_, Version II of Monday, August 15, 1983 Object Text Defs Link Symb Static Start 0 0 22 124 134 134 Length 326 22 102 10 156 0 9 Definitions: segname: cache_threshold_defaults_ text|13 dup_dir_multimatch text|7 dup_dir_parity text|14 pad text|1 port_buffer text|5 pri_dir text|0 pri_dir_parity symb|0 symbol_table text|6 wno_parity_any_port No Links. ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved