COMPILATION LISTING OF SEGMENT hran_dps8_ Compiled by: Multics PL/I Compiler, Release 28d, of October 4, 1983 Compiled at: Honeywell Multics Op. - System M Compiled on: 11/19/84 1114.4 mst Mon Options: optimize map 1 /* *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 4* * * 5* * Copyright (c) 1972 by Massachusetts Institute of * 6* * Technology and Honeywell Information Systems, Inc. * 7* * * 8* *********************************************************** */ 9 10 11 /* Coded August 1980 by Rich Coppola for support of the DPS8M CPU */ 12 13 /* Modified Oct 1982 by Rich Coppola to make 'threading' work properly. 14* Some notes: The 870M CPU does not append on PIAs unless it crosses a page 15* boundary (apuhr1.piapgbsy). Also direct cycles get entered in the APU hregs 16* even though the APU does nothing. This version of the 'threader' attempts to 17* follow these 'rules' so that the 'analyzed' registers are threaded properly. 18* A new feature has been added as well. If the final address (apuhr1.finadd) 19* of the APU does not agree with the address that the CU developed 20* (cuhr.ca_value) a diagnostic message is displayed. These mismatches may 21* be due to REAL address problems or a failure to strobe the address into 22* the appropriate hreg properly. 23* 24* Modified Oct 1982 by Rich Coppola to add entries for the display of hregs 25* in octal and interpreted, but not threaded, hregs. 26* 27* Modified August 83 by B. Braun to change the long format (when lo_sw is on) 28* to fit neatly on a 80 char screen. 29* 30* Modified 01 Oct 84 by B. Braun to change nregs to be 16, not 64 for bce toehold. 31**/ 32 33 hran_dps8_: proc; 34 35 return; /* do not enter here */ 36 37 38 /* PARAMETERS */ 39 40 dcl a_iocbp ptr; 41 dcl lo_sw bit (1); 42 dcl switches bit (5); /* tell what hregs to display and how */ 43 /* must be in this order */ 44 /* expand_sw 45* do_ou 46* do_cu 47* do_au 48* do_du */ 49 50 51 /* EXTERNAL DATA */ 52 53 dcl get_line_length_$switch 54 entry (ptr, fixed bin (35)) returns (fixed bin); 55 dcl ioa_$ioa_switch options (variable), 56 ioa_$ioa_switch_nnl entry options (variable), 57 ioa_$rsnnl entry options (variable); /* default io switch */ 58 59 /* AUTOMATIC STORAGE */ 60 61 dcl a_nregs fixed bin; /* auto copy of number of regs */ 62 63 dcl 1 a_switches based (addr (switches)), 64 (2 expand_sw bit (1), 65 2 do_ou bit (1), 66 2 do_cu bit (1), 67 2 do_au bit (1), 68 2 do_du bit (1)) unal; 69 70 dcl (i, j, foo, cusegno, ausegno) fixed bin; 71 dcl PAD (0:10) char (11) var int static options (constant) init ( 72 "", " ", " ", " ", " ", " ", " ", " ", 73 " ", " ", " "); 74 dcl (OP_pad, TAG_pad) char (4) var; 75 dcl AU_index fixed bin, /* AU1 data index */ 76 au_synched bit (1), 77 au2 bit (1), 78 CU_index fixed bin, /* index into CU data */ 79 CU_ptr ptr, /* pointer to CU data */ 80 CY_print char (1), /* cycle type for output */ 81 DU_mode char (1), /* DU execution mode symbol */ 82 IC_cur fixed bin (18) init (1), /* current IC value for CU entries */ 83 IC_next fixed bin (18) init (1), /* next IC value for CU entries */ 84 IC_last fixed bin (18) init (1), /* last IC value for CU lines */ 85 IC_print bit (1), /* sw to print IC value */ 86 IC_value fixed bin (18), /* IC value for output */ 87 LEVEL (0:3) char (1) init ("A", "B", "C", "D"), /* level of ASS MEM for printing */ 88 NOP_flag bit (1) init ("0"b), /* flag for NOP cycles */ 89 OP_cur bit (10) init ((10)"0"b), /* current opcode for CU lines */ 90 OP_last bit (10) init ((10)"0"b), /* last opcode for CU lines */ 91 OP_print char (5) var, /* opcode string for printing */ 92 tpr_ca char (6), 93 TPR_CA_PR char (8) var, 94 DU_OU_ptr ptr, /* pointer to DU_OU data */ 95 DU_OU_synch fixed bin init (0), /* index value at which DU_OU & CU synchronize */ 96 PTW_print char (3), /* PTWAM level and reg# for printing */ 97 SDW_print char (3), /* SDWAM level and reg# for printing */ 98 SEG_print bit (1), /* switch for printing segno */ 99 AUSEG_pr bit (1), /* same for au regs */ 100 (pr_autag, pr_auop, pr_cuop, pr_cutag) bit (1), 101 TAG_cur fixed bin, /* current TAG table index */ 102 TAG_print char (3) var, /* TAG string for printing */ 103 XD1_flag bit (1) init ("0"b), /* flag for 1st of XED pair */ 104 XD2_flag bit (1) init ("0"b), /* flag for 2nd of XED pair */ 105 XEC_flag bit (1) init ("0"b), /* XEC flag */ 106 XED_flag bit (1) init ("0"b), /* XED flag */ 107 AUOP bit (10), /* for display of OP and tag */ 108 AUOP_PR char (5) var, /* in AU2 */ 109 AUTAG fixed bin, 110 AUTAG_PR char (3) var, 111 (temp_char1, temp_char2) char (2), 112 ll_sw bit(1), 113 null builtin, 114 iocbp ptr, /* output switch name */ 115 iox_$user_output ptr ext, /* default io switch */ 116 fetch_count fixed bin init (0), /* fetch cycle count */ 117 118 pull_count fixed bin init (0); /* index into instruction pull table */ 119 120 dcl au_cycle_done bit (1) init ("0"b); 121 122 dcl repeat_count fixed bin init (0), /* OU instruction repeat count */ 123 tag_chain_flag bit (1); /* tag print control flag */ 124 dcl hr_block bit (36*2*4*16) based; /* #of bits in the prds hr data block */ 125 126 dcl 1 cu_regs (64) based (cuhrp), 127 (2 cu_flags bit (18), 128 2 cu_op bit (18), 129 2 cu_addr bit (24), 130 2 cu_pt_flags bit (12)) unaligned; 131 132 dcl 1 ou_regs (64) based (du_ouhrp), 133 (2 du_regs bit (36), 134 2 ou_ic bit (18), 135 2 ou_rs bit (9), 136 2 ou_inds bit (9)) unaligned; 137 138 dcl 1 apu1_regs (64) based (aphrp1), 139 (2 ap1_segno bit (15), 140 2 ap1_flags1 bit (12), 141 2 ap1_flags2 bit (8), 142 2 ap1_flt bit (1), 143 2 ap1_finadd bit (24), 144 2 ap1_trr bit (3), 145 2 ap1_flags3 bit (9)) unaligned; 146 147 148 dcl 1 apu2_regs (64) based (aphrp2), 149 (2 ap2_ca bit (18), 150 2 ap2_op bit (18), 151 2 ap2_pad bit (36)) unaligned; 152 153 dcl code fixed bin (35); 154 155 hranl_dps8_: entry (hr_data_ptr, a_iocbp, nregs, lo_sw); 156 157 158 159 code = 0; 160 call setup; 161 if code ^= 0 then 162 return; 163 164 165 166 /* History regs should be valid, print heading and initialize */ 167 168 call ioa_$ioa_switch (iocbp, "DPS8 History Register Analysis"); 169 call ioa_$ioa_switch (iocbp, "^/HR ^[^34x^;^10x^]IC or^12xc^3xMemory", lo_sw); 170 171 call ioa_$ioa_switch_nnl (iocbp, 172 "id^[^9thr contents^8x^;^4t^] Seg# [tpr.ca] opcode tag y Address mc ^[^/^7tflags^;flags^/^]", lo_sw, (lo_sw & ll_sw)); 173 174 175 176 /* Merge CU & OU entries up to fault cycle */ 177 178 HRA01: 179 180 IC_last = 0; 181 AU_index = a_nregs + 1; 182 OP_last = "777"b3; 183 au_synched = "0"b; 184 185 186 do CU_index = 1 to a_nregs -1; 187 188 IC_cur = fixed (du_ouhr.ict (CU_index), 18); 189 OP_cur = cuhr.op_code (CU_index); 190 if au_synched = "0"b then call synch_auhr; 191 call cur; 192 OP_last = OP_cur; 193 IC_last = IC_cur; 194 end; 195 196 197 198 /* Do the fault cycles */ 199 200 do_flt_cycle: 201 202 203 IC_cur = fixed (du_ouhr.ict (CU_index), 18); 204 OP_cur = cuhr.op_code (CU_index); 205 call cur; 206 call ioa_$ioa_switch (iocbp, "^/"); 207 return; 208 209 cur: proc; 210 211 212 /* Determine if IC value is to be displayed */ 213 214 215 /* if we are repeating _o_r XEC'ing ... */ 216 217 if cuhr.rpts (CU_index) | XEC_flag then goto cur03; 218 219 cur02: 220 221 if (IC_cur ^= IC_last) then do; /* if IC or OP has changed since last CU line ... */ 222 IC_cur = fixed (du_ouhr.ict (CU_index), 18); 223 IC_value = IC_cur; 224 IC_print = "1"b; 225 end; 226 227 else IC_print = "0"b; /* if IC didn't change, don't print */ 228 229 if XED_flag then do; /* if XEDing ... */ 230 231 if ^XD1_flag then do; /* if 1st of XED pair not been done ... */ 232 XD1_flag = "1"b; /* we are about to do it */ 233 goto cur03; 234 end; 235 236 if ^XD2_flag then do; /* if 2nd of XED pair has not been done ... */ 237 if cuhr.op_code (CU_index) ^= OP_cur then 238 XD2_flag = "1"b; /* we are about to do it */ 239 goto cur03; 240 end; 241 242 if cuhr.op_code (CU_index) ^= OP_cur then 243 XED_flag, XD1_flag, XD2_flag = "0"b; /* XED finished, reset all flags */ 244 end; 245 246 247 248 cur03: 249 if OP_cur = OP_last & IC_print = "0"b then 250 /* if neither IC nor opcode have changed ... */ 251 pr_cuop = "0"b; /* this must be the same instruction */ 252 253 else do; 254 OP_cur = cuhr.op_code (CU_index); 255 OP_print = rtrim (OP.code (fixed (OP_cur, 10)+1)); 256 pr_cuop = "1"b; 257 end; 258 259 cur04: if OP.DUOP (fixed (cuhr.op_code (CU_index), 10)+1) /* if a decimal op ... */ 260 | cuhr.op_code (CU_index) = STCA /* or STCA ... */ 261 | cuhr.op_code (CU_index) = STCQ /* or STCQ ... */ 262 | cuhr.op_code (CU_index) = STBA /* or STBA ... */ 263 | cuhr.op_code (CU_index) = STBQ /* or STBQ ... */ 264 | cuhr.rpts (CU_index) /* or its a repeat */ 265 then do; /* print a blank TAG */ 266 TAG_cur = 0; 267 pr_cutag = "0"b; 268 end; 269 270 else do; 271 TAG_cur = fixed (cuhr.tag (CU_index), 10)+1; 272 TAG_print = rtrim (TAG.code (TAG_cur)); 273 pr_cutag = "1"b; 274 end; 275 276 if TAG_cur > 0 then /* if its a true tag ... */ 277 tag_chain_flag = TAG.chain (TAG_cur); /* set tag chain flag */ 278 279 280 CY_print = "?"; /* set up for don't know */ 281 282 283 if cuhr.pfa (CU_index) then CY_print = "F"; 284 285 else if cuhr.xint (CU_index) then CY_print = "x"; 286 287 else if cuhr.pia (CU_index) then do; 288 CY_print = "i"; 289 if cuhr.op_code (CU_index) ^= XED then do; 290 IC_next = fixed (cuhr.ca_value (CU_index), 24); 291 XED_flag, XD1_flag, XD2_flag = "0"b; /* reset XED flags for transfer */ 292 end; 293 294 else if cuhr.op_code (CU_index) ^= XEC then do; 295 IC_next = fixed (cuhr.ca_value (CU_index), 24); 296 XEC_flag = "0"b; 297 end; 298 299 end; 300 301 else if cuhr.riw (CU_index) | cuhr.siw (CU_index) then 302 CY_print = "n"; 303 304 305 else if (fixed (cuhr.tag (CU_index), 6) = 3) | 306 (fixed (cuhr.tag (CU_index), 6) = 7) 307 then CY_print = "d"; 308 309 310 else if OP.DUOP (fixed (OP_cur, 10)+1) then 311 CY_print = "e"; 312 313 else if OP_cur = NOP 314 | (OP.TR (fixed (OP_cur, 10)+1) & ^cuhr.rtrgo (CU_index)) then do; 315 CY_print = "*"; 316 NOP_flag = "1"b; 317 end; 318 319 else if (^cuhr.pia (CU_index)) & (cuhr.poa (CU_index)) then 320 CY_print = "o"; 321 322 if au_synched = "1"b then 323 if ext_hr.AU1.even (AU_index) ^= "0"b then 324 if apuhr2.opcode (AU_index) = cuhr.op_code (CU_index) then do; 325 cusegno = fixed (apuhr1.esn (AU_index), 15); 326 SEG_print = "1"b; 327 end; 328 329 else SEG_print = "0"b; 330 331 if pr_cuop then do; 332 foo = length (OP_print); /* get proper # of pad chars to right justify */ 333 foo = 5 - foo; 334 OP_pad = PAD (foo); 335 OP_print = OP_pad || OP_print; 336 end; 337 338 if pr_cutag then do; 339 foo = length (TAG_print); /* do same for TAG */ 340 foo = 3 - foo; 341 TAG_pad = PAD (foo); 342 TAG_print = TAG_pad || TAG_print; 343 end; 344 else TAG_print = ""; 345 346 347 call ioa_$ioa_switch_nnl (iocbp, "^/CU ^[^12.3b ^12.3b^;^2s^5t^]^[^5o^;^s^5x^] ^[^6o^;^s^6x^] ^[^a^;^s^5x^] ^[^3a^;^s^3x^] ^1a ^8o ^2o ", 348 lo_sw, ext_hr.CU.even (CU_index), ext_hr.CU.odd (CU_index), 349 SEG_print, cusegno, 350 IC_print, IC_value, 351 pr_cuop, OP_print, 352 pr_cutag, rtrim (TAG_print), 353 CY_print, 354 fixed (cuhr.ca_value (CU_index), 24), 355 2 * fixed (cuhr.pcmd (CU_index), 3)); 356 357 call ioa_$ioa_switch_nnl (iocbp, "^[^/^7t^]^[pia ^]^[poa ^]^[riw ^]^[siw ^]^[pot ^]^[pon ^]", 358 (lo_sw & ll_sw), cuhr (CU_index).pia, cuhr (CU_index).poa, cuhr (CU_index).riw, 359 cuhr (CU_index).siw, cuhr (CU_index).pot, cuhr (CU_index).pon); 360 361 call ioa_$ioa_switch_nnl (iocbp, "^[raw ^]^[saw ^]^[inf ^]^[xde ^]^[xdo ^]^[ic ^]^[rpts ^]", 362 cuhr (CU_index).raw, cuhr (CU_index).saw, cuhr (CU_index).pia, 363 cuhr (CU_index).xde, cuhr (CU_index).xdo, cuhr (CU_index).ic, cuhr (CU_index).rpts); 364 365 call ioa_$ioa_switch_nnl (iocbp, "^[pai ^]^[pfa ^]^[inh ^]^[xint ^]^[pib ^]^[its ^]", 366 cuhr (CU_index).pai, cuhr (CU_index).pfa, cuhr (CU_index).inhib, 367 cuhr (CU_index).xint, cuhr (CU_index).pib, 368 (^OP.DUOP (fixed (OP_cur, 10)+1) & cuhr (CU_index).its_flag)); 369 370 call ioa_$ioa_switch_nnl (iocbp, "^[port ^]^[internal ^]^[cache flush ^]", 371 cuhr (CU_index).portf, cuhr (CU_index).internal, cuhr (CU_index).cache_flush); 372 373 374 if substr (ext_hr.DU_OU.odd (CU_index), 19, 18) ^= "0"b then do; 375 call ioa_$ioa_switch_nnl (iocbp, "^/OU ^[^12.3b ^12.3b^;^2s^4t^]^41x", 376 lo_sw, ext_hr.DU_OU.even (CU_index), ext_hr.DU_OU.odd (CU_index)); 377 call ioa_$ioa_switch_nnl (iocbp, "^[^/^7t^]RS-REG=^a ^[dtrgo ^]", 378 (lo_sw & ll_sw), ltrim (rtrim (OP.code (fixed (du_ouhr (CU_index).rs || "0"b, 10) +1))), 379 du_ouhr (CU_index).dtrgo, du_ouhr (CU_index).dtrgo); 380 381 if ou_regs (CU_index).ou_inds ^= "0"b then do; 382 call ioa_$ioa_switch_nnl (iocbp, "^[zero ^]^[sign ^]^[carry ^]^[ovfl ^]^[eovfl ^]^[eufl ^]^[oflm ^]^[hex ^]", 383 du_ouhr (CU_index).ir_reg.zero_, du_ouhr (CU_index).ir_reg.sign_, du_ouhr (CU_index).ir_reg.carry_, 384 du_ouhr (CU_index).ir_reg.ovfl_, du_ouhr (CU_index).ir_reg.eovfl_, du_ouhr (CU_index).ir_reg.eufl_, 385 du_ouhr (CU_index).ir_reg.oflm_, du_ouhr (CU_index).ir_reg.hex_); 386 end; 387 end; 388 389 if cuhr.op_code (CU_index) = XED then XED_flag = "1"b; 390 if cuhr.op_code (CU_index) = XEC then XEC_flag = "1"b; 391 392 if cuhr.pfa (CU_index) then return; 393 394 if (cuhr.pia (CU_index) & ^(apuhr1.piapgbsy (AU_index) | apuhr1.piaoosb (AU_index))) then 395 go to display_du; 396 397 398 if au_synched = "1"b then 399 if ext_hr.AU1.even (AU_index) ^= "0"b then do; 400 display_apu: call aur; 401 AU_index = AU_index +1; 402 if au_cycle_done = "1"b then 403 go to display_du; 404 goto display_apu; /* keep going till APU cycle finished */ 405 end; 406 407 display_du: 408 if OP.DUOP (fixed (OP_cur, 10)+1) & ^cuhr.pia (CU_index) then 409 call dur; 410 return; 411 end; 412 413 aur: proc; 414 415 if AU_index > a_nregs then go to AU_DONE; 416 if ext_hr.AU1.even (AU_index) = "0"b then return; 417 SDW_print = " "; 418 au_cycle_done = "0"b; 419 420 if substr (ext_hr.AU1.even (AU_index), 16, 10) = "0"b then 421 go to AU_DONE; /* not an APU cycle */ 422 423 if cuhr.op_code (CU_index) ^= apuhr2.opcode (AU_index) then 424 go to AU_DONE; 425 if (cuhr.tag (CU_index) = "03"b3 | cuhr.tag (CU_index) = "07"b3) | 426 (apuhr2.TAG (AU_index) = "03"b3 | apuhr2.TAG (AU_index) = "07"b3) then do; 427 AU_DONE: au_cycle_done = "1"b; 428 return; 429 end; 430 431 if apuhr1.fap (AU_index) = "1"b | apuhr1.fanp (AU_index) = "1"b then 432 au_cycle_done = "1"b; 433 434 435 if apuhr1.sdwmf (AU_index) then do; 436 call ioa_$rsnnl ("^1a", temp_char1, 1, 437 LEVEL (fixed (apuhr1.sdwlvl (AU_index), 2))); 438 call ioa_$rsnnl ("^2o", temp_char2, 2, 439 fixed (substr (apuhr1.esn (AU_index), 12, 4), 4)); 440 SDW_print = ltrim (rtrim (temp_char1)) || ltrim (rtrim (temp_char2)); 441 end; 442 443 444 PTW_print = " "; 445 446 if apuhr1.ptwmf (AU_index) then do; 447 call ioa_$rsnnl ("^1a", temp_char1, 1, 448 LEVEL (fixed (apuhr1.ptwlvl (AU_index), 2))); 449 call ioa_$rsnnl ("^2o", temp_char2, 2, 450 fixed (apuhr1.ptwaddr (AU_index), 4)); 451 PTW_print = ltrim (rtrim (temp_char1)) || ltrim (rtrim (temp_char2)); 452 end; 453 454 if apuhr2.opcode (AU_index) = "0"b then do; /* ^trust au2 so.. */ 455 pr_auop = "0"b; 456 pr_autag = "0"b; 457 au2 = "0"b; 458 go to no_au2; 459 end; 460 461 462 463 pr_auop = "1"b; /* assume display of opcode */ 464 AUOP = apuhr2.opcode (AU_index); 465 AUOP_PR = rtrim (OP.code (fixed (AUOP, 10)+1)); 466 foo = length (AUOP_PR); /* do same thing as we did for CU */ 467 foo = 5 -foo; 468 OP_pad = PAD (foo); 469 AUOP_PR = OP_pad || AUOP_PR; 470 if AUOP_PR = OP_print then 471 pr_auop = "0"b; 472 473 474 pr_autag = "1"b; 475 AUTAG = fixed (apuhr2.TAG (AU_index), 10)+1; 476 AUTAG_PR = rtrim (TAG.code (AUTAG)); 477 foo = length (AUTAG_PR); 478 foo = 3 - foo; 479 TAG_pad = PAD (foo); 480 AUTAG_PR = TAG_pad || AUTAG_PR; 481 if AUTAG_PR = TAG_print then 482 pr_autag = "0"b; 483 484 485 call ioa_$rsnnl ("^6o", tpr_ca, 6, 486 fixed (apuhr2.CA (AU_index), 18)); 487 TPR_CA_PR = "[" || ltrim (rtrim (tpr_ca)) || "]"; 488 foo = length (TPR_CA_PR); 489 foo = 8 - foo; 490 OP_pad = PAD (foo); 491 TPR_CA_PR = OP_pad || TPR_CA_PR; 492 au2 = "1"b; 493 494 495 496 no_au2: 497 ausegno = fixed (apuhr1.esn (AU_index), 15); 498 if ausegno = cusegno then 499 AUSEG_pr = "0"b; 500 else AUSEG_pr = "1"b; 501 502 call ioa_$ioa_switch_nnl (iocbp, "^/AU ^[^12.3b ^12.3b^;^2s^5t^]^[^5o^;^s^5x^] ^[^8a^;^s^8x^] ^[^5a^;^s^5x^] ^[^3a^;^s^3x^]^3x^8o r^1o ", 503 lo_sw, ext_hr.AU1.even (AU_index), ext_hr.AU1.odd (AU_index), 504 AUSEG_pr, ausegno, 505 au2, TPR_CA_PR, 506 pr_auop, AUOP_PR, 507 pr_autag, AUTAG_PR, 508 fixed (apuhr1.finadd (AU_index), 25), 509 fixed (apuhr1.trr (AU_index), 3)); 510 511 call ioa_$ioa_switch_nnl (iocbp, "^[fdsptw ^]^[mdsptw ^]^[fsdw ^]^[fptw ^]^[fptw2 ^]^[mptw ^]", 512 apuhr1 (AU_index).fdsptw, apuhr1 (AU_index).mdsptw, apuhr1 (AU_index).fsdwp, 513 apuhr1 (AU_index).fptw, apuhr1 (AU_index).fptw2, apuhr1 (AU_index).mptw); 514 call ioa_$ioa_switch_nnl (iocbp, "^[^/^7t^]^[fanp ^]^[fap ^]^[sdwm (^a) ^]^[ptwm (^a) ^]^[flt ^]^[flthld ^]^[cache ^]", 515 (lo_sw & ll_sw), apuhr1 (AU_index).fanp, apuhr1 (AU_index).fap, apuhr1 (AU_index).sdwmf, ltrim (rtrim (SDW_print)), 516 apuhr1 (AU_index).ptwmf, ltrim (rtrim (PTW_print)), apuhr1 (AU_index).flt, apuhr1 (AU_index).flthld, apuhr1 (AU_index).cache_used); 517 call ioa_$ioa_switch_nnl (iocbp, "^[piapgbsy ^]^[piaoosb ^]^[*SDWAM-ERR* ^]^[*PTWAM-ERR* ^]", 518 apuhr1 (AU_index).piapgbsy, apuhr1 (AU_index).piaoosb, apuhr1 (AU_index).sdwerr, apuhr1 (AU_index).ptwerr); 519 520 if au_cycle_done = "1"b then 521 if apuhr1.finadd (AU_index) ^= cuhr.ca_value (CU_index) then do; 522 /* allow for ind cycles */ 523 if substr (apuhr1.finadd (AU_index), 16, 9) = 524 substr (cuhr.ca_value (CU_index), 16, 9) then 525 if cuhr.its_flag (CU_index) then return; 526 if substr (apuhr1.finadd (AU_index), 16, 9) = 527 substr (cuhr.ca_value (CU_index -1), 16, 9) then 528 return; 529 if substr (apuhr1.finadd (AU_index), 16, 9) = 530 substr (cuhr.ca_value (CU_index -2), 16, 9) then 531 return; 532 call ioa_$ioa_switch_nnl (iocbp, "^/*****Final Address Mismatch CU <=> AU: CU = ^8o :: AU = ^8o*****", 533 cuhr.ca_value (CU_index), apuhr1.finadd (AU_index)); 534 end; 535 return; 536 end; 537 538 dur: proc; 539 540 if ext_hr.DU_OU.even (CU_index) = "0"b 541 then return; /* no DU entry */ 542 543 if du_ouhr.du_word (CU_index) then DU_mode = "w"; 544 else if du_ouhr.nine (CU_index) then DU_mode = "9"; 545 else if du_ouhr.six (CU_index) then DU_mode = "6"; 546 else if du_ouhr.four (CU_index) then DU_mode = "4"; 547 else if du_ouhr.du_bit (CU_index) then DU_mode = "b"; 548 else DU_mode = "?"; 549 550 551 call ioa_$ioa_switch_nnl (iocbp, "^/DU ^[^12.3b ^12.3b^;^2s^4t^]^37x ^1a ", 552 lo_sw, ext_hr.DU_OU.even (CU_index), ext_hr.DU_OU.odd (CU_index), 553 DU_mode); 554 555 call ioa_$ioa_switch_nnl (iocbp, "^[d1a ^]^[d2a ^]^[anstr ^]^[lrw1 ^]^[lrw2 ^]", 556 ^du_ouhr (CU_index).fanld1, ^du_ouhr (CU_index).fanld2, ^du_ouhr (CU_index).fanstr, 557 ^du_ouhr (CU_index).fldwrt1, ^du_ouhr (CU_index).fldwrt2); 558 559 call ioa_$ioa_switch_nnl (iocbp, "^[d1n ^]^[d2n ^]^[ndsqflg ^]^[dud ^]^[gstr ^]", 560 ^du_ouhr (CU_index).fnld1, ^du_ouhr (CU_index).fnld2, du_ouhr (CU_index).endseqf, 561 ^du_ouhr.fdud (CU_index), ^du_ouhr.fgstr (CU_index)); 562 563 call ioa_$ioa_switch_nnl (iocbp, "^[ndseq ^]^[sp1 ^]^[sp2 ^]^[sp3 ^]^[pop ^]^[addgC ^]", 564 ^du_ouhr (CU_index).endseq, du_ouhr (CU_index).ptr1, du_ouhr (CU_index).ptr2, du_ouhr (CU_index).ptr3, 565 du_ouhr (CU_index).fpop, ^du_ouhr (CU_index).fgeac); 566 567 call ioa_$ioa_switch_nnl (iocbp, "^[addgE ^]^[addgF ^]^[addgH ^]^[ldptr1 ^]^[swdseq ^]", 568 ^du_ouhr (CU_index).fgeae, ^du_ouhr (CU_index).fgeaf, 569 ^du_ouhr (CU_index).fgeah, ^du_ouhr (CU_index).fgldp1, 570 ^du_ouhr (CU_index).fsweq); 571 572 call ioa_$ioa_switch_nnl (iocbp, "^[chrcyc ^]^[dfirst ^]^[exh ^]^[addcyc ^]^[intrptd ^]", 573 ^du_ouhr (CU_index).fgch, du_ouhr (CU_index).dfrst, du_ouhr (CU_index).exh, 574 ^du_ouhr (CU_index).fgadd, du_ouhr (CU_index).intrptd); 575 576 call ioa_$ioa_switch_nnl (iocbp, "^[ldptr2 ^]^[gemC ^]^[btdgA ^]^[shftgt ^]", 577 ^du_ouhr (CU_index).dcode.gldp2, du_ouhr (CU_index).dcode.gemc, 578 du_ouhr (CU_index).dcode.gbda, du_ouhr (CU_index).dcode.gsp5); 579 580 end; /* end dur */ 581 582 583 no_thread: entry (hr_data_ptr, a_iocbp, nregs, switches); 584 585 code = 0; 586 call setup; 587 if code ^= 0 then 588 return; 589 590 if do_du then do_ou = "1"b; 591 592 if ^expand_sw then do; 593 if (do_cu | do_ou) then do; 594 call ioa_$ioa_switch (iocbp, "^/^[CU-FLAGS OPCODE ADDRESS PT^]^[ ^]^[ DU REGS OU-IC RS IND^]^[ OU-IC^]", 595 do_cu, ^do_cu, do_ou, ^do_ou); 596 597 do i = a_nregs to 1 by - 1; 598 call ioa_$ioa_switch (iocbp, "^2d ^[^6.3b ^6.3b ^8.3b ^4.3b^;^4s^]^[^2x^6.3b^;^s^]^[ ^12.3b ^6.3b ^3.3b ^3.3b^]", 599 i, do_cu, cu_regs (i).cu_flags, cu_regs (i).cu_op, 600 cu_regs (i).cu_addr, cu_regs (i).cu_pt_flags, 601 ^do_ou, ou_regs (i).ou_ic, 602 do_ou, ou_regs (i).du_regs, ou_regs (i).ou_ic, 603 ou_regs (i).ou_rs, ou_regs (i).ou_inds); 604 end; 605 end; 606 607 if do_au then do; 608 call ioa_$ioa_switch (iocbp, "^/^3x^10tAPU#1 REGISTERS^40tAPU#2 REGISTERS"); 609 do i = a_nregs to 1 by -1; 610 call ioa_$ioa_switch (iocbp, "^2d ^5.3b ^4.3b ^3.3b ^.1b ^8.3b ^.3b ^3.3b^7x^6.3b ^6.3b", 611 i, ap1_segno (i), ap1_flags1 (i), "0"b || ap1_flags2 (i), ap1_flt (i), 612 ap1_finadd (i), ap1_trr (i), ap1_flags3 (i), ap2_ca (i), ap2_op (i)); 613 end; 614 end; 615 return; 616 end; 617 618 if expand_sw then do; 619 if do_cu then do; 620 call ioa_$ioa_switch_nnl (iocbp, "^2/EXPANDED CU REGS^/^5tOU-IC^11tOP-CODE^23tADDRESS PC FLAGS"); 621 do i = a_nregs to 1 by -1; 622 call ioa_$ioa_switch_nnl (iocbp, "^/^2d ^6o^10t^10a^22t^8o ^2o ", 623 i, fixed (du_ouhr.ict (i), 18), 624 ltrim (rtrim (OP.code (fixed (cuhr.op_code (i), 10) +1)) || 625 " " || ltrim (rtrim (TAG.code (fixed (cuhr.tag (i), 10) +1)))), 626 fixed (cuhr.ca_value (i), 24), 627 2 * fixed (cuhr.pcmd (i), 3)); 628 629 call ioa_$ioa_switch_nnl (iocbp, "^[pia ^]^[poa ^]^[riw ^]^[siw ^]^[pot ^]^[pon ^]", 630 cuhr (i).pia, cuhr (i).poa, cuhr (i).riw, 631 cuhr (i).siw, cuhr (i).pot, cuhr (i).pon); 632 633 call ioa_$ioa_switch_nnl (iocbp, "^[raw ^]^[saw ^]^[inf ^]^[xde ^]^[xdo ^]^[ic ^]^[rpts ^]", 634 cuhr (i).raw, cuhr (i).saw, cuhr (i).pia, 635 cuhr (i).xde, cuhr (i).xdo, cuhr (i).ic, cuhr (i).rpts); 636 637 call ioa_$ioa_switch_nnl (iocbp, "^[pai ^]^[pfa ^]^[inh ^]^[xint ^]^[pib ^]^[its ^]", 638 cuhr (i).pai, cuhr (i).pfa, cuhr (i).inhib, 639 cuhr (i).xint, cuhr (i).pib, 640 (substr (cuhr (i).op_code, 10, 1) = "0"b & cuhr (i).its_flag)); 641 642 call ioa_$ioa_switch_nnl (iocbp, "^[port ^]^[internal ^]^[cache flush ^]", 643 cuhr (i).portf, cuhr (i).internal, cuhr (i).cache_flush); 644 end; 645 end; 646 647 if do_au then do; 648 call ioa_$ioa_switch_nnl (iocbp, "^2/EXPANDED APU REGS^/ SEGNO OFFSET INSTR FINAL ADDR FLAGS"); 649 650 do i = a_nregs to 1 by -1; 651 SDW_print = " "; 652 if apuhr1.sdwmf (i) then do; 653 call ioa_$rsnnl ("^1a", temp_char1, 1, 654 LEVEL (fixed (apuhr1.sdwlvl (i), 2))); 655 call ioa_$rsnnl ("^2o", temp_char2, 2, 656 fixed (substr (apuhr1.esn (i), 12, 4), 4)); 657 SDW_print = ltrim (rtrim (temp_char1)) || ltrim (rtrim (temp_char2)); 658 end; 659 660 661 PTW_print = " "; 662 663 if apuhr1.ptwmf (i) then do; 664 call ioa_$rsnnl ("^1a", temp_char1, 1, 665 LEVEL (fixed (apuhr1.ptwlvl (i), 2))); 666 call ioa_$rsnnl ("^2o", temp_char2, 2, 667 fixed (apuhr1.ptwaddr (i), 4)); 668 PTW_print = ltrim (rtrim (temp_char1)) || ltrim (rtrim (temp_char2)); 669 end; 670 671 672 call ioa_$ioa_switch_nnl (iocbp, "^/^2d ^5.3b ^6o ^10a ^8o ", 673 i, apuhr1.esn (i), apuhr2.CA (i), 674 675 ltrim (rtrim (OP.code (fixed (apuhr2.opcode (i), 10) +1)) || 676 " " || ltrim (rtrim (TAG.code (fixed (apuhr2.TAG (i), 10) +1)))), 677 fixed (apuhr1.finadd (i), 24)); 678 679 call ioa_$ioa_switch_nnl (iocbp, "^[fdsptw ^]^[mdsptw ^]^[fsdw ^]^[fptw ^]^[fptw2 ^]^[mptw ^]", 680 apuhr1 (i).fdsptw, apuhr1 (i).mdsptw, apuhr1 (i).fsdwp, 681 apuhr1 (i).fptw, apuhr1 (i).fptw2, apuhr1 (i).mptw); 682 call ioa_$ioa_switch_nnl (iocbp, "^[fanp ^]^[fap ^]^[sdwm (^a) ^]^[ptwm (^a) ^]^[flt ^]^[flthld ^]^[cache ^]", 683 apuhr1 (i).fanp, apuhr1 (i).fap, apuhr1 (i).sdwmf, ltrim (rtrim (SDW_print)), 684 apuhr1 (i).ptwmf, ltrim (rtrim (PTW_print)), apuhr1 (i).flt, apuhr1 (i).flthld, apuhr1 (i).cache_used); 685 call ioa_$ioa_switch_nnl (iocbp, "^[piapgbsy ^]^[piaoosb ^]^[*SDWAM-ERR* ^]^[*PTWAM-ERR* ^]", 686 apuhr1 (i).piapgbsy, apuhr1 (i).piaoosb, apuhr1 (i).sdwerr, apuhr1 (i).ptwerr); 687 688 end; 689 end; 690 691 692 if do_ou then do; 693 call ioa_$ioa_switch_nnl (iocbp, "^2/EXPANDED DU/OU REGS^/^5tOU-IC RS-REG ^15tDU/OU-INDS"); 694 do i = a_nregs to 1 by -1; 695 call ioa_$ioa_switch_nnl (iocbp, "^/^2d ^6o^10t^a^18t^[zero ^]^[sign ^]^[carry ^]^[ovfl ^]^[eovfl ^]^[eufl ^]^[oflm ^]^[hex ^]^[dtrgo ^]", 696 i, fixed (du_ouhr.ict (i), 18), 697 ltrim (rtrim (OP.code (fixed (du_ouhr (i).rs || "0"b, 10) +1))), 698 du_ouhr (i).ir_reg.zero_, du_ouhr (i).ir_reg.sign_, 699 du_ouhr (i).ir_reg.carry_, du_ouhr (i).ir_reg.ovfl_, 700 du_ouhr (i).ir_reg.eovfl_, du_ouhr (i).ir_reg.eufl_, 701 du_ouhr (i).ir_reg.oflm_, du_ouhr (i).ir_reg.hex_, 702 du_ouhr (i).dtrgo); 703 704 if substr (cuhr.op_code (i), 10, 1) & ^cuhr.pia (i) then do; 705 if du_ouhr.du_word (CU_index) then DU_mode = "w"; 706 else if du_ouhr.nine (CU_index) then DU_mode = "9"; 707 else if du_ouhr.six (CU_index) then DU_mode = "6"; 708 else if du_ouhr.four (CU_index) then DU_mode = "4"; 709 else if du_ouhr.du_bit (CU_index) then DU_mode = "b"; 710 else DU_mode = "?"; 711 712 call ioa_$ioa_switch_nnl (iocbp, "^[d1a ^]^[d2a ^]^[anstr ^]^[lrw1 ^]^[lrw2 ^]", 713 ^du_ouhr (CU_index).fanld1, ^du_ouhr (CU_index).fanld2, ^du_ouhr (CU_index).fanstr, 714 ^du_ouhr (CU_index).fldwrt1, ^du_ouhr (CU_index).fldwrt2); 715 716 call ioa_$ioa_switch_nnl (iocbp, "^[d1n ^]^[d2n ^]^[ndsqflg ^]^[dud ^]^[gstr ^]", 717 ^du_ouhr (CU_index).fnld1, ^du_ouhr (CU_index).fnld2, du_ouhr (CU_index).endseqf, 718 ^du_ouhr.fdud (CU_index), ^du_ouhr.fgstr (CU_index)); 719 720 call ioa_$ioa_switch_nnl (iocbp, "^[ndseq ^]^[sp1 ^]^[sp2 ^]^[sp3 ^]^[pop ^]^[addgC ^]", 721 ^du_ouhr (CU_index).endseq, du_ouhr (CU_index).ptr1, du_ouhr (CU_index).ptr2, du_ouhr (CU_index).ptr3, 722 du_ouhr (CU_index).fpop, ^du_ouhr (CU_index).fgeac); 723 724 call ioa_$ioa_switch_nnl (iocbp, "^[addgE ^]^[addgF ^]^[addgH ^]^[ldptr1 ^]^[swdseq ^]", 725 ^du_ouhr (CU_index).fgeae, ^du_ouhr (CU_index).fgeaf, 726 ^du_ouhr (CU_index).fgeah, ^du_ouhr (CU_index).fgldp1, 727 ^du_ouhr (CU_index).fsweq); 728 729 call ioa_$ioa_switch_nnl (iocbp, "^[chrcyc ^]^[dfirst ^]^[exh ^]^[addcyc ^]^[intrptd ^]", 730 ^du_ouhr (CU_index).fgch, du_ouhr (CU_index).dfrst, du_ouhr (CU_index).exh, 731 ^du_ouhr (CU_index).fgadd, du_ouhr (CU_index).intrptd); 732 733 call ioa_$ioa_switch_nnl (iocbp, "^[ldptr2 ^]^[gemC ^]^[btdgA ^]^[shftgt ^]", 734 ^du_ouhr (CU_index).dcode.gldp2, du_ouhr (CU_index).dcode.gemc, 735 du_ouhr (CU_index).dcode.gbda, du_ouhr (CU_index).dcode.gsp5); 736 737 end; 738 739 740 end; 741 end; 742 743 744 end; 745 return; 746 747 748 749 setup: proc; 750 751 752 753 /* *********************************************************** 754* * check iocbp and long switch, set control accordingly * 755* *********************************************************** */ 756 757 758 if a_iocbp = null then /* called to use default io switch */ 759 iocbp = iox_$user_output; 760 else iocbp = a_iocbp; 761 762 763 if hr_data_ptr = null then do; /* check validity of ptr */ 764 call ioa_$ioa_switch (iocbp, "^/History Register Pointer is Null"); 765 code = -1; 766 return; /* must be a bad call */ 767 end; 768 769 a_nregs = nregs; 770 771 if a_nregs = 64 then do; /* set up proper offsets to hr data */ 772 cu_offset = 128; 773 au_offset2 = 256; 774 au_offset1 = 384; 775 a_nregs = 16; /* we currently only save 16 in bce toehold */ 776 end; 777 778 779 du_ouhrp = addrel (hr_data_ptr, du_ou_offset); /* set pointer to Ops Unit data */ 780 cuhrp = addrel (hr_data_ptr, cu_offset); /* set pointer to Control Unit data */ 781 aphrp2 = addrel (hr_data_ptr, au_offset2); /* set pointer to DU data */ 782 aphrp1 = addrel (hr_data_ptr, au_offset1); /* set pointer to App Unit data */ 783 OP_ptr = addr (OP_table); /* set pointer to opcode table */ 784 TAG_ptr = addr (TAG_table); /* set pointer to tag table */ 785 786 787 788 /* *********************************************************************** 789* * If history registers were not saved, fim will zero the block out. * 790* * So we need to see if the block is valid by checking for zeroes. * 791* *********************************************************************** */ 792 793 if hr_data_ptr -> hr_block = "0"b then do; 794 call ioa_$ioa_switch (iocbp, "^/History Register Buffer is Empty"); 795 code = -1; 796 return; 797 end; 798 /* get terminal line length */ 799 ll_sw = get_line_length_$switch (null (), (0)) <= 80; 800 801 return; 802 end setup; 803 804 805 806 /* This subroutine is used to get the AU hregs in synch with the CU hregs */ 807 808 synch_auhr: proc; 809 810 811 do AU_index = 1 to a_nregs while (au_synched = "0"b); 812 if apuhr2.opcode (AU_index) = cuhr.op_code (CU_index) then 813 if apuhr1.finadd (AU_index) = cuhr.ca_value (CU_index) then 814 if ext_hr.AU1.even (AU_index) ^= "0"b then 815 if (apuhr2.TAG (AU_index) ^= "03"b3 | apuhr2.TAG (AU_index) ^= "07"b3) then 816 au_synched = "1"b; 817 end; 818 819 if au_synched = "0"b then 820 AU_index = a_nregs +1; 821 822 else AU_index = AU_index -1; 823 return; 824 end synch_auhr; 825 1 1 1 2 /* BEGIN INCLUDE FILE ... history_regs_dps8.incl.pl1 1 3* * ... created by R. L. Coppola 8/80. */ 1 4 /* Modified Sept, 1981 by Rich Coppola to reflect changes made in the CPU */ 1 5 1 6 dcl (du_ouhrp, cuhrp, aphrp1, aphrp2, hr_data_ptr) ptr; 1 7 dcl nregs fixed bin; /* number of history registers saved (16/64) */ 1 8 1 9 1 10 dcl 1 ext_hr based (hr_data_ptr), /* History Register data */ 1 11 2 DU_OU (nregs), 1 12 3 even bit (36), 1 13 3 odd bit (36), 1 14 2 CU (nregs), 1 15 3 even bit (36), 1 16 3 odd bit (36), 1 17 2 AU2 (nregs), 1 18 3 even bit (36), 1 19 3 odd bit (36), 1 20 2 AU1 (nregs), 1 21 3 even bit (36), 1 22 3 odd bit (36); 1 23 1 24 1 25 1 26 dcl du_ou_offset fixed bin init (0), /* offsets to hr data within the hr data block */ 1 27 cu_offset fixed bin init (32), 1 28 au_offset2 fixed bin init (64), 1 29 au_offset1 fixed bin init (96); 1 30 1 31 1 32 dcl 1 cuhra (nregs) like cuhr; /* copy of HR data (corrected) */ 1 33 1 34 dcl 1 cuhr (nregs) based (cuhrp) aligned, 1 35 (2 pia bit (1), /* preparing instruction address */ 1 36 2 poa bit (1), /* preparing operand address */ 1 37 2 riw bit (1), /* requesting indirect word */ 1 38 2 siw bit (1), /* restoring indirect word */ 1 39 2 pot bit (1), /* preparing operand tally */ 1 40 2 pon bit (1), /* preparing operand address */ 1 41 2 raw bit (1), /* requesting alter-rewrite word (complemented) */ 1 42 2 saw bit (1), /* restoring alter-rewrite word */ 1 43 2 rtrgo bit (1), /* remember transfer go - condition met */ 1 44 2 xde bit (1), /* XED from even location */ 1 45 2 xdo bit (1), /* XED from odd location */ 1 46 2 ic bit (1), /* even/odd inst. pair */ 1 47 2 rpts bit (1), /* repeat operation */ 1 48 2 portf bit (1), /* memory cycle to port on previous cycle */ 1 49 2 internal bit (1), /* memory cycle to cache or direct on previous cycle */ 1 50 2 pai bit (1), /* prepare interrupt address */ 1 51 2 pfa bit (1), /* prepare FLT address */ 1 52 2 master_mode bit (1), /* in master mode */ 1 53 2 op_code bit (10), /* op code of inst */ 1 54 2 inhib bit (1), /* inhibit int bit */ 1 55 2 its_flag bit (1), /* ar reg mod flag */ 1 56 2 tag bit (6), /* tag field of instr */ 1 57 2 ca_value bit (24), /* 24 bit address field of inst */ 1 58 2 pcmd bit (5), /* processor command register */ 1 59 2 xint bit (1), /* execute interrupt */ 1 60 2 ins_fetch bit (1), /* inst fetch */ 1 61 2 cache_rd bit (1), /* cache read cycle this cycle */ 1 62 2 mem_rd bit (1), /* memory read this cycle */ 1 63 2 mem_sto bit (1), /* memory store this cycle */ 1 64 2 pib bit (1), /* port interface busy */ 1 65 2 cache_flush bit (1)) unaligned; 1 66 1 67 dcl 1 du_ouhr (nregs) based (du_ouhrp) aligned, 1 68 (2 fanld1 bit (1), /* alpha-num load desc 1 (complemented) */ 1 69 2 fanld2 bit (1), /* alpha-num load desc 2 (complemented) */ 1 70 2 fanstr bit (1), /* alpha-num store (complemented) */ 1 71 2 fldwrt1 bit (1), /* load re-write reg 1 (complemented) */ 1 72 2 fldwrt2 bit (1), /* load re-write reg 2 (complemented) */ 1 73 2 fnld1 bit (1), /* numeric load desc 1 (complemented) */ 1 74 2 fnld2 bit (1), /* numeric load desc 2 (complemented) */ 1 75 2 endseqf bit (1), /* end sequence flag */ 1 76 2 fdud bit (1), /* decimal unit idle (complemented) */ 1 77 2 fgstr bit (1), /* general store flag (complemented) */ 1 78 2 endseq bit (1), /* end of sequence (complemented) */ 1 79 2 nine bit (1), /* 9-bit char. operation */ 1 80 2 six bit (1), /* 6-bit char. operation */ 1 81 2 four bit (1), /* 4-bit char operation */ 1 82 2 du_bit bit (1), /* Bit operation */ 1 83 2 du_word bit (1), /* Word operation */ 1 84 2 ptr1 bit (1), /* select ptr 1 */ 1 85 2 ptr2 bit (1), /* select ptr 2 */ 1 86 2 ptr3 bit (1), /* select ptr 3 */ 1 87 2 fpop bit (1), /* prepare operand pointer */ 1 88 2 fgeac bit (1), /* add cycle gate C (complemented) */ 1 89 2 fgeae bit (1), /* add cycle gate E (complemented) */ 1 90 2 fgeaf bit (1), /* add cycle gate F(complemented) */ 1 91 2 fgeah bit (1), /* add cycle gate H (complemented) */ 1 92 2 fgldp1 bit (1), /* load PTR #1 (complemented) */ 1 93 2 fsweq bit (1), /* single word sequence flag (complemented) */ 1 94 2 fgch bit (1), /* character cycle (complemented) */ 1 95 2 dfrst bit (1), /* processing descriptor for first time */ 1 96 2 exh bit (1), /* exhaust */ 1 97 2 fgadd bit (1), /* add cycle (complemented) */ 1 98 2 intrptd bit (1), /* interrupted */ 1 99 2 dcode, 1 100 3 gldp2 bit (1), /* ldp2 (complemented) */ 1 101 3 gemc bit (1), /* exponent control */ 1 102 3 gbda bit (1), /* bin to dec gate A */ 1 103 3 gsp5 bit (1), /* shift timing gate */ 1 104 3 dcode_pad bit (1), 1 105 2 ict bit (18), /* Instruction counter */ 1 106 2 rs bit (9), /* OU op-code register (RS0-8) */ 1 107 2 ir_reg, /* the indicator reg */ 1 108 3 zero_ bit (1), 1 109 3 sign_ bit (1), 1 110 3 carry_ bit (1), 1 111 3 ovfl_ bit (1), 1 112 3 eovfl_ bit (1), 1 113 3 eufl_ bit (1), 1 114 3 oflm_ bit (1), 1 115 3 hex_ bit (1), 1 116 2 dtrgo bit (1)) unaligned; /* transfer go */ 1 117 1 118 1 119 dcl 1 apuhr1 (nregs) based (aphrp1) aligned, 1 120 (2 esn bit (15), /* effective segment number for this cycle */ 1 121 /* bits 11-14 contain the */ 1 122 /* SDWAM addr selected */ 1 123 2 piapgbsy bit (1), /* ins fetch across a page bndry */ 1 124 2 piaoosb bit (1), /* ins fetch OOSB */ 1 125 2 fdsptw bit (1), /* fetch of dseg PTW */ 1 126 2 mdsptw bit (1), /* mod of dseg PTW */ 1 127 2 fsdwp bit (1), /* fetch paged SDW */ 1 128 2 fptw bit (1), /* fetch PTW */ 1 129 2 fptw2 bit (1), /* fetch PTW + 1 */ 1 130 2 mptw bit (1), /* modify PTW */ 1 131 2 fanp bit (1), /* fetch final add from non-paged seg */ 1 132 2 fap bit (1), /* fetch final addr paged */ 1 133 2 mtchsdw bit (1), /* SDW match in AM */ 1 134 2 sdwmf bit (1), /* SDWAM match occurred and used */ 1 135 2 bsy bit (2), /* data source for ESN */ 1 136 /* 00 = from ppr.psr */ 1 137 /* 01 = from prn.tsr */ 1 138 /* 10 = from tpr.snr */ 1 139 /* 11 = from tpr.ca */ 1 140 2 ptwmf bit (1), /* PTW match in AM */ 1 141 2 mtchptw bit (1), /* PTWAM match occurred */ 1 142 2 ptwaddr bit (4), /* addr sel for PTWAM (tpr.ca)4,7 */ 1 143 2 flt bit (1), /* ACV or DF flt caused by this cycle */ 1 144 2 finadd bit (24), /* absolute address of this cycle */ 1 145 2 trr bit (3), /* value of tpr.trr for this cycle */ 1 146 2 sdwerr bit (1), /* multi-mtch or parity err in SDWAM */ 1 147 2 sdwlvl bit (2), /* SDWAM level selected */ 1 148 2 cache_used bit (1), /* CPU used cache for this cycle */ 1 149 2 ptwerr bit (1), /* multi-match or parity err in PTWAM */ 1 150 2 ptwlvl bit (2), /* PTWAM level selected */ 1 151 2 flthld bit (1), /* an ACV or DF flt is waiting to be processed */ 1 152 2 apu_pad2 bit (1))unaligned; 1 153 1 154 dcl 1 apuhr2 (nregs) based (aphrp2) aligned, 1 155 (2 CA bit (18), /* tpr.ca */ 1 156 2 opcode bit (10), /* opcode from cur instr */ 1 157 2 inhibit_bit bit (1), /* interrupt inhib bit */ 1 158 2 pr_flag bit (1), /* PR mod flag */ 1 159 2 TAG bit (6), /* mod. tag field */ 1 160 2 pad1 bit (36))unaligned; 1 161 1 162 1 163 /* END INCLUDE FILE ... history_regs_dpse.incl.pl1 */ 826 827 2 1 2 2 /* BEGIN INCLUDE FILE ... opcode_tag_table.incl.pl1 2 3* * ... created by R. L. Coppola 8/80. */ 2 4 2 5 dcl (OP_ptr, TAG_ptr) ptr; /* pointers to op code and tag tables */ 2 6 2 7 dcl LREG int static options (constant) bit (9) init ("000111011"b), 2 8 NOP int static options (constant) bit (9) init ("000001001"b); 2 9 2 10 dcl OP_table (128) int static options (constant) char (48) unal init ( /* opcode table */ 2 11 "illop@illop@mme1 @illop@drl @illop@illop@illop@", /* 000 */ 2 12 "mme2 @illop@mme3 @illop@illop@illop@mme4 @illop@", 2 13 "illop@illop@nop @illop@puls1@illop@puls2@illop@", /* 010 */ 2 14 "illop@illop@cioc @illop@illop@illop@illop@illop@", 2 15 "adlx0Bmve Aadlx1Billop@adlx2Billop@adlx3Billop@", /* 020 */ 2 16 "adlx4Bmvne Aadlx5Billop@adlx6Billop@adlx7Billop@", 2 17 "illop@illop@illop@illop@ldqc Jillop@adl Billop@", /* 030 */ 2 18 "ldac Jillop@adla Billop@adlq Billop@adlaqBillop@", 2 19 "asx0 Jillop@asx1 Jillop@asx2 Jillop@asx3 Jillop@", /* 040 */ 2 20 "asx4 Jillop@asx5 Jillop@asx6 Jillop@asx7 Jillop@", 2 21 "adwp0Billop@adwp1Billop@adwp2Billop@adwp3Billop@", /* 050 */ 2 22 "aos Jillop@asa Jillop@asq Jillop@sscr Billop@", 2 23 "adx0 Bcsl Aadx1 Bcsr Aadx2 Billop@adx3 Billop@", /* 060 */ 2 24 "adx4 Bsztl Aadx5 Bsztr Aadx6 Bcmpb Aadx7 Billop@", 2 25 "illop@illop@awca Billop@awcq Billop@lreg Billop@", /* 070 */ 2 26 "illop@illop@ada Billop@adq Billop@adaq Billop@", 2 27 "cmpx0Bmlr Acmpx1Bmrl Acmpx2Billop@cmpx3Billop@", /* 100 */ 2 28 "cmpx4Billop@cmpx5Billop@cmpx6Bcmpc Acmpx7Billop@", 2 29 "illop@illop@cwl Billop@illop@illop@illop@illop@", /* 110 */ 2 30 "illop@illop@cmpa Billop@cmpq Billop@cmpaqBillop@", 2 31 "sblx0Bscd Asblx1Bscdr Asblx2Billop@sblx3Billop@", /* 120 */ 2 32 "sblx4Bscm Asblx5Bscmr Asblx6Billop@sblx7Billop@", 2 33 "illop@illop@illop@illop@illop@illop@illop@illop@", /* 130 */ 2 34 "illop@illop@sbla Billop@sblq Billop@sblaqBillop@", 2 35 "ssx0 Jillop@ssx1 Jillop@ssx2 Jillop@ssx3 Jillop@", /* 140 */ 2 36 "ssx4 Jillop@ssx5 Jillop@ssx6 Jillop@ssx7 Jillop@", 2 37 "adwp4Billop@adwp5Billop@adwp6Billop@adwp7Billop@", /* 150 */ 2 38 "sdbr @sptr @ssa Jillop@ssq Jillop@illop@illop@", 2 39 "sbx0 Bmvt Asbx1 Billop@sbx2 Billop@sbx3 Billop@", /* 160 */ 2 40 "sbx4 Btct Asbx5 Btctr Asbx6 Billop@sbx7 Billop@", 2 41 "illop@illop@swca Billop@swcq Billop@lpri @lptr @", /* 170 */ 2 42 "illop@illop@sba Billop@sbq Billop@sbaq Billop@", 2 43 "cnax0Billop@cnax1Billop@cnax2Bad2d Acnax3Bsb2d A", /* 200 */ 2 44 "cnax4Billop@cnax5Billop@cnax6Bmp2d Acnax7Bdv2d A", 2 45 "illop@illop@cmk Billop@absa Billop@epaq Billop@", /* 210 */ 2 46 "sznc Jillop@cnaa Billop@cnaq Billop@cnaaqBillop@", 2 47 "ldx0 Billop@ldx1 Billop@ldx2 Bad3d Aldx3 Bsb3d A", /* 220 */ 2 48 "ldx4 Billop@ldx5 Billop@ldx6 Bmp3d Aldx7 Bdv3d A", 2 49 "lbar @illop@rsw Billop@ldbr @lsdr @rmcm Billop@", /* 230 */ 2 50 "szn Billop@lda Billop@ldq Billop@ldaq Billop@", 2 51 "orsx0Jillop@orsx1Jillop@orsx2Jillop@orsx3Jillop@", /* 240 */ 2 52 "orsx4Jillop@orsx5Jillop@orsx6Jillop@orsx7Jillop@", 2 53 "spri0@spbp0@spbp1@spri1@spri2@spbp2@spbp3@spri3@", /* 250 */ 2 54 "spri @ssdr @orsa Jillop@orsq Jillop@lsdp @lptp @", 2 55 "orx0 Billop@orx1 Billop@orx2 Billop@orx3 Billop@", /* 260 */ 2 56 "orx4 Billop@orx5 Billop@orx6 Billop@orx7 Billop@", 2 57 "tsp0 `illop@tsp1 `illop@tsp2 `illop@tsp3 `illop@", /* 270 */ 2 58 "illop@illop@ora Billop@orq Billop@oraq Billop@", 2 59 "canx0Bmvn Acanx1Bbtd Acanx2Billop@canx3Bcmpn A", /* 300 */ 2 60 "canx4Billop@canx5Bdtb Acanx6Billop@canx7Billop@", 2 61 "eawp0@easp1@easp0@eawp1@eawp2@easp3@easp2@eawp3@", /* 310 */ 2 62 "illop@illop@cana Billop@canq Billop@canaqBillop@", 2 63 "lcx0 Billop@lcx1 Billop@lcx2 Billop@lcx3 Billop@", /* 320 */ 2 64 "lcx4 Billop@lcx5 Billop@lcx6 Billop@lcx7 Billop@", 2 65 "eawp4@easp5@easp4@eawp5@eawp6@easp7@easp6@eawp7@", /* 330 */ 2 66 "illop@illop@lca Billop@lcq Billop@lcaq Billop@", 2 67 "ansx0Jillop@ansx1Jillop@ansx2Jillop@ansx3Jillop@", /* 340 */ 2 68 "ansx4Jillop@ansx5Jillop@ansx6Jillop@ansx7Jdvdr A", 2 69 "epp0 @epbp0@epbp1@epp1 @epp2 @epbp2@epbp3@epp3 @", /* 350 */ 2 70 "stac Jillop@ansa Jillop@ansq Jillop@stcd @illop@", 2 71 "anx0 Billop@anx1 Billop@anx2 Billop@anx3 Billop@", /* 360 */ 2 72 "anx4 Billop@anx5 Billop@anx6 Billop@anx7 Billop@", 2 73 "epp4 @epbp4@epbp5@epp5 @epp6 @epbp6@epbp7@epp7 @", /* 370 */ 2 74 "illop@illop@ana Billop@anq Billop@anaq Billop@", 2 75 "illop@illop@mpf Billop@mpy Billop@illop@illop@", /* 400 */ 2 76 "illop@illop@cmg Billop@illop@illop@illop@illop@", 2 77 "illop@illop@lde Billop@illop@illop@rscr Billop@", /* 410 */ 2 78 "illop@illop@ade Billop@illop@illop@illop@illop@", 2 79 "illop@illop@ufm Billop@illop@illop@dufm Billop@", /* 420 */ 2 80 "illop@illop@fcmg Billop@illop@illop@dfcmgBillop@", 2 81 "fszn Billop@fld Billop@illop@illop@dfld Billop@", /* 430 */ 2 82 "illop@illop@ufa Billop@illop@illop@dufa Billop@", 2 83 "sxl0 Billop@sxl1 Billop@sxl2 Billop@sxl3 BsanA", /* 440 */ 2 84 "sxl4 Billop@sxl5 Billop@sxl6 Billop@sxl7 Bspl A", 2 85 "stz Billop@smic Billop@scpr Billop@illop@illop@", /* 430 */ 2 86 "stt @illop@fst Billop@ste Billop@dfst Billop@", 2 87 "illop@illop@fmp Billop@illop@illop@dfmp BlanA", /* 460 */ 2 88 "illop@illop@illop@illop@illop@illop@illop@lpl A", 2 89 "fstr Billop@frd Billop@dfstrBillop@dfrd Billop@", /* 470 */ 2 90 "illop@illop@fad Billop@illop@illop@dfad Billop@", 2 91 "rpl Pa9bd Aillop@a6bd Aillop@a4bd Aillop@abd A", /* 500 */ 2 92 "illop@illop@bcd Billop@div Billop@dvf Bawd A", 2 93 "illop@illop@illop@illop@illop@illop@fneg Billop@", /* 510 */ 2 94 "illop@illop@fcmp Billop@illop@illop@dfcmpBillop@", 2 95 "rpt Ps9bd Aillop@s6bd Aillop@s4bd Aillop@sbd A", /* 520 */ 2 96 "illop@illop@fdi Billop@illop@illop@dfdi Bswd A", 2 97 "illop@illop@neg Billop@cams @camp @negl Billop@", /* 530 */ 2 98 "illop@illop@ufs Billop@illop@illop@dufs Billop@", 2 99 "sprp0@ara0 Asprp1@ara1 Asprp2@ara2 Asprp3@ara3 A", /* 540 */ 2 100 "sprp4@ara4 Asprp5@ara5 Asprp6@ara6 Asprp7@ara7 A", 2 101 "sbar @illop@stba Billop@stbq Billop@smcm Billop@", /* 550 */ 2 102 "stc1 @illop@illop@illop@illop@illop@ssdp @sptp @", 2 103 "rpd Paar0 Aillop@aar1 Aillop@aar2 Aillop@aar3 A", /* 560 */ 2 104 "illop@aar4 Afdv Baar5 Aillop@aar6 Adfdv Baar7 A", 2 105 "illop@illop@illop@illop@illop@illop@fno Billop@", /* 570 */ 2 106 "illop@illop@fsb Billop@illop@illop@dfsb Billop@", 2 107 "tze dtrtn dtnz dtrtf dtnc dillop@trc dillop@", /* 600 */ 2 108 "tmi dtmoz dtpl dtpnz dillop@ttn dttf dillop@", 2 109 "rtcd `illop@illop@illop@illop@illop@rcu `illop@", /* 610 */ 2 110 "teo dillop@teu dillop@dis @illop@tov dillop@", 2 111 "eax0 Billop@eax1 Billop@eax2 Billop@eax3 Billop@", /* 620 */ 2 112 "eax4 Billop@eax5 Billop@eax6 Billop@eax7 Billop@", 2 113 "ret `illop@illop@illop@illop@illop@rccl Billop@", /* 630 */ 2 114 "ldi @illop@eaa Billop@eaq Billop@ldt @illop@", 2 115 "ersx0Jarn0 @ersx1Jarn1 @ersx2Jarn2 @ersx3Jarn3 @", /* 640 */ 2 116 "ersx4Jarn4 @ersx5Jarn5 @ersx6Jarn6 @ersx7Jarn7 @", 2 117 "spri4@spbp4@spbp5@spri5@spri6@spbp6@spbp7@spri7@", /* 650 */ 2 118 "stacqJillop@ersa Jillop@ersq Jillop@scu @illop@", 2 119 "erx0 Bnar0 @erx1 Bnar1 @erx2 Bnar2 @erx3 Bnar3 @", /* 660 */ 2 120 "erx4 Bnar4 @erx5 Bnar5 @erx6 Bnar6 @erx7 Bnar7 @", 2 121 "tsp4 `illop@tsp5 `illop@tsp6 `illop@tsp7 `illop@", /* 670 */ 2 122 "lcpr @illop@era Billop@erq Billop@eraq Billop@", 2 123 "tsx0 `illop@tsx1 `illop@tsx2 `illop@tsx3 `illop@", /* 700 */ 2 124 "tsx4 `illop@tsx5 `illop@tsx6 `illop@tsx7 `illop@", 2 125 "tra `illop@illop@illop@illop@illop@call6`illop@", /* 710 */ 2 126 "illop@illop@tss `illop@xec @illop@xed @illop@", 2 127 "lxl0 Billop@lxl1 Billop@lxl2 Billop@lxl3 Billop@", /* 720 */ 2 128 "lxl4 Billop@lxl5 Billop@lxl6 Billop@lxl7 Billop@", 2 129 "illop@illop@ars Billop@qrs Billop@lrs Billop@", /* 730 */ 2 130 "illop@illop@als Billop@qls Billop@lls Billop@", 2 131 "stx0 Bsar0 @stx1 Bsar1 @stx2 Bsar2 @stx3 Bsar3 @", /* 740 */ 2 132 "stx4 Bsar4 @stx5 Bsar5 @stx6 Bsar6 @stx7 Bsar7 @", 2 133 "stc2 @illop@stca Billop@stcq Billop@sreg Billop@", /* 750 */ 2 134 "sti @sra @sta Billop@stq Bsptr @staq Billop@", 2 135 "lprp0@lar0 @lprp1@lar1 @lprp2@lar2 @lprp3@lar3 @", /* 760 */ 2 136 "lprp4@lar4 @lprp5@lar5 @lprp6@lar6 @lprp7@lar7 @", 2 137 "illop@illop@arl Billop@qrl Billop@lrl Billop@", /* 770 */ 2 138 "gtb Blra @alr Billop@qlr Billop@llr Billop@"); 2 139 2 140 dcl SREG int static options (constant) bit (9) init ("111101011"b), 2 141 STBA int static options (constant) bit (9) init ("101101001"b), 2 142 STBQ int static options (constant) bit (9) init ("101101010"b), 2 143 STCA int static options (constant) bit (9) init ("111101001"b), 2 144 STCQ int static options (constant) bit (9) init ("111101010"b), 2 145 XEC int static options (constant) bit (9) init ("111001110"b), 2 146 XED int static options (constant) bit (9) init ("111001111"b); 2 147 2 148 dcl TAG_table (8) char (40) int static options (constant)init ( /* tag table */ 2 149 " au qu du ic al ql dl ", 2 150 "x0 x1 x2 x3 x4 x5 x6 x7 ", 2 151 "n* aau* aqu* aill ic* aal* aql* aill ", 2 152 "x0* ax1* ax2* ax3* ax4* ax5* ax6* ax7* a", 2 153 "fi itp ill its sd scr f2 f3 ", 2 154 "ci i sc ad di dic aid idc a", 2 155 "*n *au *qu ill *ic *al *ql ill ", 2 156 "*x0 *x1 *x2 *x3 *x4 *x5 *x6 *x7 "); 2 157 2 158 2 159 dcl 1 OP (1024) based (OP_ptr), 2 160 2 code char (5) unal, 2 161 2 pad bit (3) unal, 2 162 2 TR bit (1), 2 163 2 RPT bit (1), 2 164 2 ALT bit (1), 2 165 2 COND bit (1), 2 166 2 OUOP bit (1), 2 167 2 DUOP bit (1); 2 168 2 169 dcl 1 TAG (64) based (TAG_ptr), 2 170 2 code char (4) unal, 2 171 2 pad bit (8) unal, 2 172 2 chain bit (1); 2 173 2 174 828 829 830 831 end hran_dps8_; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 11/15/84 1440.1 hran_dps8_.pl1 >special_ldd>online>6897-11/15/84>hran_dps8_.pl1 826 1 02/03/82 1702.8 history_regs_dps8.incl.pl1 >ldd>include>history_regs_dps8.incl.pl1 828 2 02/03/82 1702.8 opcode_tag_table.incl.pl1 >ldd>include>opcode_tag_table.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. AU1 based structure array level 2 packed unaligned dcl 1-10 AUOP 000162 automatic bit(10) unaligned dcl 75 set ref 464* 465 AUOP_PR 000163 automatic varying char(5) dcl 75 set ref 465* 466 469* 469 470 502* AUSEG_pr 000145 automatic bit(1) unaligned dcl 75 set ref 498* 500* 502* AUTAG 000166 automatic fixed bin(17,0) dcl 75 set ref 475* 476 AUTAG_PR 000170 automatic varying char(3) dcl 75 set ref 476* 477 480* 480 481 502* AU_index 000112 automatic fixed bin(17,0) dcl 75 set ref 181* 322 322 325 394 394 398 401* 401 415 416 420 423 425 425 431 431 435 436 438 438 446 447 449 449 454 464 475 485 485 496 502 502 502 502 502 502 511 511 511 511 511 511 514 514 514 514 514 514 514 517 517 517 517 520 523 526 529 532 811* 812 812 812 812 812* 819* 822* 822 CA based bit(18) array level 2 packed unaligned dcl 1-154 set ref 485 485 672* CU based structure array level 2 packed unaligned dcl 1-10 CU_index 000115 automatic fixed bin(17,0) dcl 75 set ref 186* 188 189* 200 204 217 222 237 242 254 259 259 259 259 259 259 271 283 285 287 289 290 294 295 301 301 305 305 313 319 319 322 347 347 347 347 347 357 357 357 357 357 357 361 361 361 361 361 361 361 365 365 365 365 365 365 370 370 370 374 375 375 377 377 377 377 381 382 382 382 382 382 382 382 382 389 390 392 394 407 423 425 425 520 523 523 526 529 532 540 543 544 545 546 547 551 551 555 555 555 555 555 559 559 559 559 559 563 563 563 563 563 563 567 567 567 567 567 572 572 572 572 572 576 576 576 576 705 706 707 708 709 712 712 712 712 712 716 716 716 716 716 720 720 720 720 720 720 724 724 724 724 724 729 729 729 729 729 733 733 733 733 812 812 CY_print 000116 automatic char(1) unaligned dcl 75 set ref 280* 283* 285* 288* 301* 305* 310* 315* 319* 347* DUOP 1(17) based bit(1) array level 2 packed unaligned dcl 2-159 ref 259 310 365 407 DU_OU based structure array level 2 packed unaligned dcl 1-10 DU_OU_synch 000141 automatic fixed bin(17,0) initial dcl 75 set ref 75* DU_mode 000117 automatic char(1) unaligned dcl 75 set ref 543* 544* 545* 546* 547* 548* 551* 705* 706* 707* 708* 709* 710* IC_cur 000120 automatic fixed bin(18,0) initial dcl 75 set ref 75* 188* 193 200* 219 222* 223 IC_last 000122 automatic fixed bin(18,0) initial dcl 75 set ref 75* 178* 193* 219 IC_next 000121 automatic fixed bin(18,0) initial dcl 75 set ref 75* 290* 295* IC_print 000123 automatic bit(1) unaligned dcl 75 set ref 224* 227* 248 347* IC_value 000124 automatic fixed bin(18,0) dcl 75 set ref 223* 347* LEVEL 000125 automatic char(1) initial array unaligned dcl 75 set ref 75* 75* 75* 75* 436* 447* 653* 664* NOP constant bit(9) initial unaligned dcl 2-7 ref 313 NOP_flag 000126 automatic bit(1) initial unaligned dcl 75 set ref 75* 316* OP based structure array level 1 packed unaligned dcl 2-159 OP_cur 000127 automatic bit(10) initial unaligned dcl 75 set ref 75* 189* 192 204* 237 242 248 254* 255 310 313 313 365 407 OP_last 000130 automatic bit(10) initial unaligned dcl 75 set ref 75* 182* 192* 248 OP_pad 000106 automatic varying char(4) dcl 74 set ref 334* 335 468* 469 490* 491 OP_print 000131 automatic varying char(5) dcl 75 set ref 255* 332 335* 335 347* 470 OP_ptr 000222 automatic pointer dcl 2-5 set ref 255 259 310 313 365 377 377 407 465 622 622 672 672 695 695 783* OP_table 000120 constant char(48) initial array unaligned dcl 2-10 set ref 783 PAD 003120 constant varying char(11) initial array dcl 71 ref 334 341 468 479 490 PTW_print 000142 automatic char(3) unaligned dcl 75 set ref 444* 451* 514 514 661* 668* 682 682 SDW_print 000143 automatic char(3) unaligned dcl 75 set ref 417* 440* 514 514 651* 657* 682 682 SEG_print 000144 automatic bit(1) unaligned dcl 75 set ref 326* 329* 347* STBA constant bit(9) initial unaligned dcl 2-140 ref 259 STBQ constant bit(9) initial unaligned dcl 2-140 ref 259 STCA constant bit(9) initial unaligned dcl 2-140 ref 259 STCQ constant bit(9) initial unaligned dcl 2-140 ref 259 TAG based structure array level 1 packed unaligned dcl 2-169 in procedure "hran_dps8_" TAG 0(30) based bit(6) array level 2 in structure "apuhr2" packed unaligned dcl 1-154 in procedure "hran_dps8_" ref 425 425 475 672 672 812 812 TAG_cur 000152 automatic fixed bin(17,0) dcl 75 set ref 266* 271* 272 276 276 TAG_pad 000110 automatic varying char(4) dcl 74 set ref 341* 342 479* 480 TAG_print 000154 automatic varying char(3) dcl 75 set ref 272* 339 342* 342 344* 347 347 481 TAG_ptr 000224 automatic pointer dcl 2-5 set ref 272 276 476 622 622 672 672 784* TAG_table 000000 constant char(40) initial array unaligned dcl 2-148 set ref 784 TPR_CA_PR 000136 automatic varying char(8) dcl 75 set ref 487* 488 491* 491 502* TR 1(12) based bit(1) array level 2 packed unaligned dcl 2-159 ref 313 XD1_flag 000156 automatic bit(1) initial unaligned dcl 75 set ref 75* 231 232* 242* 291* XD2_flag 000157 automatic bit(1) initial unaligned dcl 75 set ref 75* 236 237* 242* 291* XEC constant bit(9) initial unaligned dcl 2-140 ref 294 390 XEC_flag 000160 automatic bit(1) initial unaligned dcl 75 set ref 75* 217 296* 390* XED constant bit(9) initial unaligned dcl 2-140 ref 289 389 XED_flag 000161 automatic bit(1) initial unaligned dcl 75 set ref 75* 229 242* 291* 389* a_iocbp parameter pointer dcl 40 ref 155 583 758 760 a_nregs 000100 automatic fixed bin(17,0) dcl 61 set ref 181 186 415 597 609 621 650 694 769* 771 775* 811 819 a_switches based structure level 1 packed unaligned dcl 63 ap1_finadd 1 based bit(24) array level 2 packed unaligned dcl 138 set ref 610* ap1_flags1 0(15) based bit(12) array level 2 packed unaligned dcl 138 set ref 610* ap1_flags2 0(27) based bit(8) array level 2 packed unaligned dcl 138 ref 610 ap1_flags3 1(27) based bit(9) array level 2 packed unaligned dcl 138 set ref 610* ap1_flt 0(35) based bit(1) array level 2 packed unaligned dcl 138 set ref 610* ap1_segno based bit(15) array level 2 packed unaligned dcl 138 set ref 610* ap1_trr 1(24) based bit(3) array level 2 packed unaligned dcl 138 set ref 610* ap2_ca based bit(18) array level 2 packed unaligned dcl 148 set ref 610* ap2_op 0(18) based bit(18) array level 2 packed unaligned dcl 148 set ref 610* aphrp1 000212 automatic pointer dcl 1-6 set ref 325 394 394 431 431 435 436 438 438 446 447 449 449 496 502 502 502 502 511 511 511 511 511 511 514 514 514 514 514 514 514 517 517 517 517 520 523 526 529 532 610 610 610 610 610 610 610 652 653 655 655 663 664 666 666 672 672 672 679 679 679 679 679 679 682 682 682 682 682 682 682 685 685 685 685 782* 812 aphrp2 000214 automatic pointer dcl 1-6 set ref 322 423 425 425 454 464 475 485 485 610 610 672 672 672 672 672 781* 812 812 812 apu1_regs based structure array level 1 packed unaligned dcl 138 apu2_regs based structure array level 1 packed unaligned dcl 148 apuhr1 based structure array level 1 dcl 1-119 apuhr2 based structure array level 1 dcl 1-154 au2 000114 automatic bit(1) unaligned dcl 75 set ref 457* 492* 502* au_cycle_done 000202 automatic bit(1) initial unaligned dcl 120 set ref 120* 402 418* 427* 431* 520 au_offset1 000221 automatic fixed bin(17,0) initial dcl 1-26 set ref 1-26* 774* 782 au_offset2 000220 automatic fixed bin(17,0) initial dcl 1-26 set ref 1-26* 773* 781 au_synched 000113 automatic bit(1) unaligned dcl 75 set ref 183* 190 322 398 811 812* 819 ausegno 000104 automatic fixed bin(17,0) dcl 70 set ref 496* 498 502* ca_value 1 based bit(24) array level 2 packed unaligned dcl 1-34 set ref 290 295 347 347 520 523 526 529 532* 622 622 812 cache_flush 1(35) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 370* 642* cache_used 1(30) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 514* 682* carry_ 1(29) based bit(1) array level 3 packed unaligned dcl 1-67 set ref 382* 695* chain 1(08) based bit(1) array level 2 packed unaligned dcl 2-169 ref 276 code based char(5) array level 2 in structure "OP" packed unaligned dcl 2-159 in procedure "hran_dps8_" ref 255 377 377 465 622 622 672 672 695 695 code 000205 automatic fixed bin(35,0) dcl 153 in procedure "hran_dps8_" set ref 159* 161 585* 587 765* 795* code based char(4) array level 2 in structure "TAG" packed unaligned dcl 2-169 in procedure "hran_dps8_" ref 272 476 622 622 672 672 cu_addr 1 based bit(24) array level 2 packed unaligned dcl 126 set ref 598* cu_flags based bit(18) array level 2 packed unaligned dcl 126 set ref 598* cu_offset 000217 automatic fixed bin(17,0) initial dcl 1-26 set ref 1-26* 772* 780 cu_op 0(18) based bit(18) array level 2 packed unaligned dcl 126 set ref 598* cu_pt_flags 1(24) based bit(12) array level 2 packed unaligned dcl 126 set ref 598* cu_regs based structure array level 1 packed unaligned dcl 126 cuhr based structure array level 1 dcl 1-34 cuhrp 000210 automatic pointer dcl 1-6 set ref 189 204 217 237 242 254 259 259 259 259 259 259 271 283 285 287 289 290 294 295 301 301 305 305 313 319 319 322 347 347 347 357 357 357 357 357 357 361 361 361 361 361 361 361 365 365 365 365 365 365 370 370 370 389 390 392 394 407 423 425 425 520 523 523 526 529 532 598 598 598 598 622 622 622 622 622 622 622 629 629 629 629 629 629 633 633 633 633 633 633 633 637 637 637 637 637 637 637 642 642 642 704 704 780* 812 812 cusegno 000103 automatic fixed bin(17,0) dcl 70 set ref 325* 347* 498 dcode 0(31) based structure array level 2 packed unaligned dcl 1-67 dfrst 0(27) based bit(1) array level 2 packed unaligned dcl 1-67 set ref 572* 729* do_au 0(03) based bit(1) level 2 packed unaligned dcl 63 ref 607 647 do_cu 0(02) based bit(1) level 2 packed unaligned dcl 63 set ref 593 594* 594 598* 619 do_du 0(04) based bit(1) level 2 packed unaligned dcl 63 ref 590 do_ou 0(01) based bit(1) level 2 packed unaligned dcl 63 set ref 590* 593 594* 594 598 598* 692 dtrgo 1(35) based bit(1) array level 2 packed unaligned dcl 1-67 set ref 377* 377* 695* du_bit 0(14) based bit(1) array level 2 packed unaligned dcl 1-67 ref 547 709 du_ou_offset 000216 automatic fixed bin(17,0) initial dcl 1-26 set ref 1-26* 779 du_ouhr based structure array level 1 dcl 1-67 du_ouhrp 000206 automatic pointer dcl 1-6 set ref 188 200 222 377 377 377 377 381 382 382 382 382 382 382 382 382 543 544 545 546 547 555 555 555 555 555 559 559 559 559 559 563 563 563 563 563 563 567 567 567 567 567 572 572 572 572 572 576 576 576 576 598 598 598 598 598 622 622 695 695 695 695 695 695 695 695 695 695 695 695 695 705 706 707 708 709 712 712 712 712 712 716 716 716 716 716 720 720 720 720 720 720 724 724 724 724 724 729 729 729 729 729 733 733 733 733 779* du_regs based bit(36) array level 2 packed unaligned dcl 132 set ref 598* du_word 0(15) based bit(1) array level 2 packed unaligned dcl 1-67 ref 543 705 endseq 0(10) based bit(1) array level 2 packed unaligned dcl 1-67 ref 563 720 endseqf 0(07) based bit(1) array level 2 packed unaligned dcl 1-67 set ref 559* 716* eovfl_ 1(31) based bit(1) array level 3 packed unaligned dcl 1-67 set ref 382* 695* esn based bit(15) array level 2 packed unaligned dcl 1-119 set ref 325 438 438 496 655 655 672* eufl_ 1(32) based bit(1) array level 3 packed unaligned dcl 1-67 set ref 382* 695* even based bit(36) array level 3 in structure "ext_hr" packed unaligned dcl 1-10 in procedure "hran_dps8_" set ref 347* even based bit(36) array level 3 in structure "ext_hr" packed unaligned dcl 1-10 in procedure "hran_dps8_" set ref 322 398 416 420 502* 812 even based bit(36) array level 3 in structure "ext_hr" packed unaligned dcl 1-10 in procedure "hran_dps8_" set ref 375* 540 551* exh 0(28) based bit(1) array level 2 packed unaligned dcl 1-67 set ref 572* 729* expand_sw based bit(1) level 2 packed unaligned dcl 63 ref 592 618 ext_hr based structure level 1 packed unaligned dcl 1-10 fanld1 based bit(1) array level 2 packed unaligned dcl 1-67 ref 555 712 fanld2 0(01) based bit(1) array level 2 packed unaligned dcl 1-67 ref 555 712 fanp 0(23) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 431 514* 682* fanstr 0(02) based bit(1) array level 2 packed unaligned dcl 1-67 ref 555 712 fap 0(24) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 431 514* 682* fdsptw 0(17) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 511* 679* fdud 0(08) based bit(1) array level 2 packed unaligned dcl 1-67 ref 559 716 fetch_count 000200 automatic fixed bin(17,0) initial dcl 75 set ref 75* fgadd 0(29) based bit(1) array level 2 packed unaligned dcl 1-67 ref 572 729 fgch 0(26) based bit(1) array level 2 packed unaligned dcl 1-67 ref 572 729 fgeac 0(20) based bit(1) array level 2 packed unaligned dcl 1-67 ref 563 720 fgeae 0(21) based bit(1) array level 2 packed unaligned dcl 1-67 ref 567 724 fgeaf 0(22) based bit(1) array level 2 packed unaligned dcl 1-67 ref 567 724 fgeah 0(23) based bit(1) array level 2 packed unaligned dcl 1-67 ref 567 724 fgldp1 0(24) based bit(1) array level 2 packed unaligned dcl 1-67 ref 567 724 fgstr 0(09) based bit(1) array level 2 packed unaligned dcl 1-67 ref 559 716 finadd 1 based bit(24) array level 2 packed unaligned dcl 1-119 set ref 502 502 520 523 526 529 532* 672 672 812 fldwrt1 0(03) based bit(1) array level 2 packed unaligned dcl 1-67 ref 555 712 fldwrt2 0(04) based bit(1) array level 2 packed unaligned dcl 1-67 ref 555 712 flt 0(35) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 514* 682* flthld 1(34) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 514* 682* fnld1 0(05) based bit(1) array level 2 packed unaligned dcl 1-67 ref 559 716 fnld2 0(06) based bit(1) array level 2 packed unaligned dcl 1-67 ref 559 716 foo 000102 automatic fixed bin(17,0) dcl 70 set ref 332* 333* 333 334 339* 340* 340 341 466* 467* 467 468 477* 478* 478 479 488* 489* 489 490 four 0(13) based bit(1) array level 2 packed unaligned dcl 1-67 ref 546 708 fpop 0(19) based bit(1) array level 2 packed unaligned dcl 1-67 set ref 563* 720* fptw 0(20) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 511* 679* fptw2 0(21) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 511* 679* fsdwp 0(19) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 511* 679* fsweq 0(25) based bit(1) array level 2 packed unaligned dcl 1-67 ref 567 724 gbda 0(33) based bit(1) array level 3 packed unaligned dcl 1-67 set ref 576* 733* gemc 0(32) based bit(1) array level 3 packed unaligned dcl 1-67 set ref 576* 733* get_line_length_$switch 000010 constant entry external dcl 53 ref 799 gldp2 0(31) based bit(1) array level 3 packed unaligned dcl 1-67 ref 576 733 gsp5 0(34) based bit(1) array level 3 packed unaligned dcl 1-67 set ref 576* 733* hex_ 1(34) based bit(1) array level 3 packed unaligned dcl 1-67 set ref 382* 695* hr_block based bit(4608) unaligned dcl 124 ref 793 hr_data_ptr parameter pointer dcl 1-6 ref 155 322 347 347 374 375 375 398 416 420 502 502 540 551 551 583 763 779 780 781 782 793 812 i 000101 automatic fixed bin(17,0) dcl 70 set ref 597* 598* 598 598 598 598 598 598 598 598 598* 609* 610* 610 610 610 610 610 610 610 610 610* 621* 622* 622 622 622 622 622 622 622 622 622 629 629 629 629 629 629 633 633 633 633 633 633 633 637 637 637 637 637 637 637 642 642 642* 650* 652 653 655 655 663 664 666 666 672* 672 672 672 672 672 672 672 672 679 679 679 679 679 679 682 682 682 682 682 682 682 685 685 685 685* 694* 695* 695 695 695 695 695 695 695 695 695 695 695 695 695 704 704* ic 0(11) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 361* 633* ict 1 based bit(18) array level 2 packed unaligned dcl 1-67 ref 188 200 222 622 622 695 695 inhib 0(28) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 365* 637* internal 0(14) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 370* 642* intrptd 0(30) based bit(1) array level 2 packed unaligned dcl 1-67 set ref 572* 729* ioa_$ioa_switch 000012 constant entry external dcl 55 ref 168 169 206 594 598 608 610 764 794 ioa_$ioa_switch_nnl 000014 constant entry external dcl 55 ref 171 347 357 361 365 370 375 377 382 502 511 514 517 532 551 555 559 563 567 572 576 620 622 629 633 637 642 648 672 679 682 685 693 695 712 716 720 724 729 733 ioa_$rsnnl 000016 constant entry external dcl 55 ref 436 438 447 449 485 653 655 664 666 iocbp 000176 automatic pointer dcl 75 set ref 168* 169* 171* 206* 347* 357* 361* 365* 370* 375* 377* 382* 502* 511* 514* 517* 532* 551* 555* 559* 563* 567* 572* 576* 594* 598* 608* 610* 620* 622* 629* 633* 637* 642* 648* 672* 679* 682* 685* 693* 695* 712* 716* 720* 724* 729* 733* 758* 760* 764* 794* iox_$user_output 000020 external static pointer dcl 75 ref 758 ir_reg 1(27) based structure array level 2 packed unaligned dcl 1-67 its_flag 0(29) based bit(1) array level 2 packed unaligned dcl 1-34 ref 365 523 637 ll_sw 000174 automatic bit(1) unaligned dcl 75 set ref 171 357 377 514 799* lo_sw parameter bit(1) unaligned dcl 41 set ref 155 169* 171* 171 347* 357 375* 377 502* 514 551* mdsptw 0(18) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 511* 679* mptw 0(22) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 511* 679* nine 0(11) based bit(1) array level 2 packed unaligned dcl 1-67 ref 544 706 nregs parameter fixed bin(17,0) dcl 1-7 ref 155 583 1-32 322 322 322 347 347 398 398 398 416 416 416 420 420 420 502 502 502 502 502 502 769 812 812 812 null builtin function dcl 75 ref 758 763 799 799 odd 1 based bit(36) array level 3 in structure "ext_hr" packed unaligned dcl 1-10 in procedure "hran_dps8_" set ref 374 375* 551* odd based bit(36) array level 3 in structure "ext_hr" packed unaligned dcl 1-10 in procedure "hran_dps8_" set ref 502* odd based bit(36) array level 3 in structure "ext_hr" packed unaligned dcl 1-10 in procedure "hran_dps8_" set ref 347* oflm_ 1(33) based bit(1) array level 3 packed unaligned dcl 1-67 set ref 382* 695* op_code 0(18) based bit(10) array level 2 packed unaligned dcl 1-34 ref 189 204 237 242 254 259 259 259 259 259 289 294 322 389 390 423 622 622 637 704 812 opcode 0(18) based bit(10) array level 2 packed unaligned dcl 1-154 ref 322 423 454 464 672 672 812 ou_ic 1 based bit(18) array level 2 packed unaligned dcl 132 set ref 598* 598* ou_inds 1(27) based bit(9) array level 2 packed unaligned dcl 132 set ref 381 598* ou_regs based structure array level 1 packed unaligned dcl 132 ou_rs 1(18) based bit(9) array level 2 packed unaligned dcl 132 set ref 598* ovfl_ 1(30) based bit(1) array level 3 packed unaligned dcl 1-67 set ref 382* 695* pai 0(15) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 365* 637* pcmd 1(24) based bit(5) array level 2 packed unaligned dcl 1-34 ref 347 622 pfa 0(16) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 283 365* 392 637* pia based bit(1) array level 2 packed unaligned dcl 1-34 set ref 287 319 357* 361* 394 407 629* 633* 704 piaoosb 0(16) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 394 517* 685* piapgbsy 0(15) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 394 517* 685* pib 1(34) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 365* 637* poa 0(01) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 319 357* 629* pon 0(05) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 357* 629* portf 0(13) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 370* 642* pot 0(04) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 357* 629* pr_auop 000147 automatic bit(1) unaligned dcl 75 set ref 455* 463* 470* 502* pr_autag 000146 automatic bit(1) unaligned dcl 75 set ref 456* 474* 481* 502* pr_cuop 000150 automatic bit(1) unaligned dcl 75 set ref 248* 256* 331 347* pr_cutag 000151 automatic bit(1) unaligned dcl 75 set ref 267* 273* 338 347* ptr1 0(16) based bit(1) array level 2 packed unaligned dcl 1-67 set ref 563* 720* ptr2 0(17) based bit(1) array level 2 packed unaligned dcl 1-67 set ref 563* 720* ptr3 0(18) based bit(1) array level 2 packed unaligned dcl 1-67 set ref 563* 720* ptwaddr 0(31) based bit(4) array level 2 packed unaligned dcl 1-119 ref 449 449 666 666 ptwerr 1(31) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 517* 685* ptwlvl 1(32) based bit(2) array level 2 packed unaligned dcl 1-119 ref 447 664 ptwmf 0(29) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 446 514* 663 682* pull_count 000201 automatic fixed bin(17,0) initial dcl 75 set ref 75* raw 0(06) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 361* 633* repeat_count 000203 automatic fixed bin(17,0) initial dcl 122 set ref 122* riw 0(02) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 301 357* 629* rpts 0(12) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 217 259 361* 633* rs 1(18) based bit(9) array level 2 packed unaligned dcl 1-67 ref 377 377 695 695 rtrgo 0(08) based bit(1) array level 2 packed unaligned dcl 1-34 ref 313 saw 0(07) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 361* 633* sdwerr 1(27) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 517* 685* sdwlvl 1(28) based bit(2) array level 2 packed unaligned dcl 1-119 ref 436 653 sdwmf 0(26) based bit(1) array level 2 packed unaligned dcl 1-119 set ref 435 514* 652 682* sign_ 1(28) based bit(1) array level 3 packed unaligned dcl 1-67 set ref 382* 695* siw 0(03) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 301 357* 629* six 0(12) based bit(1) array level 2 packed unaligned dcl 1-67 ref 545 707 switches parameter bit(5) unaligned dcl 42 set ref 583 590 590 592 593 593 594 594 594 594 598 598 598 607 618 619 647 692 tag 0(30) based bit(6) array level 2 packed unaligned dcl 1-34 ref 271 305 305 425 425 622 622 tag_chain_flag 000204 automatic bit(1) unaligned dcl 122 set ref 276* temp_char1 000172 automatic char(2) unaligned dcl 75 set ref 436* 440 447* 451 653* 657 664* 668 temp_char2 000173 automatic char(2) unaligned dcl 75 set ref 438* 440 449* 451 655* 657 666* 668 tpr_ca 000134 automatic char(6) unaligned dcl 75 set ref 485* 487 trr 1(24) based bit(3) array level 2 packed unaligned dcl 1-119 ref 502 502 xde 0(09) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 361* 633* xdo 0(10) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 361* 633* xint 1(29) based bit(1) array level 2 packed unaligned dcl 1-34 set ref 285 365* 637* zero_ 1(27) based bit(1) array level 3 packed unaligned dcl 1-67 set ref 382* 695* NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. CU_ptr automatic pointer dcl 75 DU_OU_ptr automatic pointer dcl 75 LREG internal static bit(9) initial unaligned dcl 2-7 SREG internal static bit(9) initial unaligned dcl 2-140 cuhra automatic structure array level 1 packed unaligned dcl 1-32 j automatic fixed bin(17,0) dcl 70 NAMES DECLARED BY EXPLICIT CONTEXT. AU_DONE 012551 constant label dcl 427 ref 415 420 423 HRA01 004550 constant label dcl 178 aur 012447 constant entry internal dcl 413 ref 400 cur 010454 constant entry internal dcl 209 ref 191 205 cur02 010466 constant label dcl 219 cur03 010537 constant label dcl 248 ref 217 233 239 cur04 010602 constant label dcl 259 display_apu 012417 constant label dcl 400 ref 404 display_du 012425 constant label dcl 407 ref 394 402 do_flt_cycle 004614 constant label dcl 200 dur 014453 constant entry internal dcl 538 ref 407 hran_dps8_ 004415 constant entry external dcl 33 hranl_dps8_ 004431 constant entry external dcl 155 no_au2 013573 constant label dcl 496 ref 458 no_thread 004655 constant entry external dcl 583 setup 015330 constant entry internal dcl 749 ref 160 586 synch_auhr 015516 constant entry internal dcl 808 ref 190 NAMES DECLARED BY CONTEXT OR IMPLICATION. addr builtin function ref 590 590 592 593 593 594 594 594 594 598 598 598 607 618 619 647 692 783 784 addrel builtin function ref 779 780 781 782 fixed builtin function ref 188 200 222 255 259 271 290 295 305 305 310 313 325 347 347 347 365 377 377 407 436 438 438 447 449 449 465 475 485 485 496 502 502 502 502 622 622 622 622 622 622 622 622 622 653 655 655 664 666 666 672 672 672 672 672 672 695 695 695 695 length builtin function ref 332 339 466 477 488 ltrim builtin function ref 377 377 440 440 451 451 487 514 514 514 514 622 622 622 622 657 657 668 668 672 672 672 672 682 682 682 682 695 695 rtrim builtin function ref 255 272 347 347 377 377 440 440 451 451 465 476 487 514 514 514 514 622 622 622 622 657 657 668 668 672 672 672 672 682 682 682 682 695 695 substr builtin function ref 374 420 438 438 523 523 526 526 529 529 637 655 655 704 STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 15744 15766 15636 15754 Length 16246 15636 22 243 106 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME hran_dps8_ 750 external procedure is an external procedure. cur internal procedure shares stack frame of external procedure hran_dps8_. aur internal procedure shares stack frame of external procedure hran_dps8_. dur internal procedure shares stack frame of external procedure hran_dps8_. setup internal procedure shares stack frame of external procedure hran_dps8_. synch_auhr internal procedure shares stack frame of external procedure hran_dps8_. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME hran_dps8_ 000100 a_nregs hran_dps8_ 000101 i hran_dps8_ 000102 foo hran_dps8_ 000103 cusegno hran_dps8_ 000104 ausegno hran_dps8_ 000106 OP_pad hran_dps8_ 000110 TAG_pad hran_dps8_ 000112 AU_index hran_dps8_ 000113 au_synched hran_dps8_ 000114 au2 hran_dps8_ 000115 CU_index hran_dps8_ 000116 CY_print hran_dps8_ 000117 DU_mode hran_dps8_ 000120 IC_cur hran_dps8_ 000121 IC_next hran_dps8_ 000122 IC_last hran_dps8_ 000123 IC_print hran_dps8_ 000124 IC_value hran_dps8_ 000125 LEVEL hran_dps8_ 000126 NOP_flag hran_dps8_ 000127 OP_cur hran_dps8_ 000130 OP_last hran_dps8_ 000131 OP_print hran_dps8_ 000134 tpr_ca hran_dps8_ 000136 TPR_CA_PR hran_dps8_ 000141 DU_OU_synch hran_dps8_ 000142 PTW_print hran_dps8_ 000143 SDW_print hran_dps8_ 000144 SEG_print hran_dps8_ 000145 AUSEG_pr hran_dps8_ 000146 pr_autag hran_dps8_ 000147 pr_auop hran_dps8_ 000150 pr_cuop hran_dps8_ 000151 pr_cutag hran_dps8_ 000152 TAG_cur hran_dps8_ 000154 TAG_print hran_dps8_ 000156 XD1_flag hran_dps8_ 000157 XD2_flag hran_dps8_ 000160 XEC_flag hran_dps8_ 000161 XED_flag hran_dps8_ 000162 AUOP hran_dps8_ 000163 AUOP_PR hran_dps8_ 000166 AUTAG hran_dps8_ 000170 AUTAG_PR hran_dps8_ 000172 temp_char1 hran_dps8_ 000173 temp_char2 hran_dps8_ 000174 ll_sw hran_dps8_ 000176 iocbp hran_dps8_ 000200 fetch_count hran_dps8_ 000201 pull_count hran_dps8_ 000202 au_cycle_done hran_dps8_ 000203 repeat_count hran_dps8_ 000204 tag_chain_flag hran_dps8_ 000205 code hran_dps8_ 000206 du_ouhrp hran_dps8_ 000210 cuhrp hran_dps8_ 000212 aphrp1 hran_dps8_ 000214 aphrp2 hran_dps8_ 000216 du_ou_offset hran_dps8_ 000217 cu_offset hran_dps8_ 000220 au_offset2 hran_dps8_ 000221 au_offset1 hran_dps8_ 000222 OP_ptr hran_dps8_ 000224 TAG_ptr hran_dps8_ THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. r_e_as r_le_a alloc_cs cat_realloc_cs call_ext_out_desc call_ext_out return alloc_auto_adj shorten_stack ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. get_line_length_$switch ioa_$ioa_switch ioa_$ioa_switch_nnl ioa_$rsnnl THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. iox_$user_output LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 75 004327 120 004373 122 004374 1 26 004375 1 32 004404 33 004414 35 004423 155 004424 159 004437 160 004440 161 004441 168 004443 169 004463 171 004510 178 004550 181 004551 182 004554 183 004556 186 004557 188 004567 189 004575 190 004602 191 004605 192 004606 193 004610 194 004612 200 004614 204 004622 205 004627 206 004630 207 004647 583 004650 585 004663 586 004664 587 004665 590 004667 592 004700 593 004706 594 004724 597 004774 598 005001 604 005131 607 005134 608 005142 609 005163 610 005171 613 005305 615 005310 618 005311 619 005312 620 005317 621 005340 622 005345 629 005560 633 005656 637 005760 642 006063 644 006133 647 006136 648 006144 650 006165 651 006173 652 006175 653 006203 655 006241 657 006300 658 006374 661 006375 663 006377 664 006404 666 006441 668 006500 669 006574 672 006575 679 007002 682 007102 685 007306 688 007366 692 007371 693 007377 694 007420 695 007425 704 007640 705 007653 706 007665 707 007673 708 007701 709 007707 710 007715 712 007717 716 010010 720 010103 724 010203 729 010276 733 010367 740 010450 745 010453 209 010454 217 010455 219 010466 222 010471 223 010476 224 010477 225 010501 227 010502 229 010504 231 010506 232 010510 233 010512 236 010513 237 010515 239 010525 242 010526 248 010537 254 010547 255 010554 256 010600 259 010602 266 010634 267 010635 268 010636 271 010637 272 010643 273 010666 276 010670 280 010701 283 010703 285 010711 287 010717 288 010723 289 010725 290 010733 291 010736 292 010741 294 010742 295 010744 296 010747 299 010750 301 010751 305 010757 310 010771 313 011006 315 011020 316 011022 317 011024 319 011025 322 011034 325 011077 326 011103 327 011105 329 011106 331 011110 332 011113 333 011115 334 011117 335 011133 336 011156 338 011157 339 011162 340 011164 341 011166 342 011202 343 011225 344 011227 347 011230 357 011415 361 011525 365 011627 370 011742 374 012012 375 012022 377 012062 381 012213 382 012223 389 012335 390 012347 392 012354 394 012360 398 012372 400 012417 401 012420 402 012421 404 012424 407 012425 410 012446 413 012447 415 012450 416 012453 417 012477 418 012501 420 012502 423 012506 425 012527 427 012551 428 012553 431 012554 435 012571 436 012574 438 012631 440 012670 441 012764 444 012765 446 012767 447 012774 449 013031 451 013070 452 013164 454 013165 455 013172 456 013173 457 013174 458 013175 463 013176 464 013200 465 013204 466 013230 467 013232 468 013234 469 013250 470 013273 474 013304 475 013306 476 013312 477 013335 478 013337 479 013341 480 013355 481 013400 485 013411 487 013445 488 013524 489 013527 490 013531 491 013545 492 013570 496 013573 498 013600 500 013604 502 013606 511 013753 514 014050 517 014270 520 014350 523 014366 526 014403 529 014411 532 014417 535 014452 538 014453 540 014454 543 014470 544 014477 545 014505 546 014513 547 014521 548 014527 551 014531 555 014575 559 014667 563 014762 567 015062 572 015155 576 015246 580 015327 749 015330 758 015331 760 015343 763 015346 764 015352 765 015372 766 015374 769 015375 771 015377 772 015401 773 015403 774 015405 775 015407 779 015411 780 015416 781 015423 782 015430 783 015435 784 015437 793 015441 794 015450 795 015470 796 015472 799 015473 801 015515 808 015516 811 015517 812 015531 817 015617 819 015621 822 015627 823 015631 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved