COMPILATION LISTING OF SEGMENT hran_l68_ Compiled by: Multics PL/I Compiler, Release 28d, of October 4, 1983 Compiled at: Honeywell Multics Op. - System M Compiled on: 02/13/85 0924.7 mst Wed Options: optimize map 1 /* *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 4* * * 5* * Copyright (c) 1972 by Massachusetts Institute of * 6* * Technology and Honeywell Information Systems, Inc. * 7* * * 8* *********************************************************** */ 9 10 11 /* Coded by Rich Coppola August 1980, for DPS8 support of history registers. 12* This routine was taken, essentially intact, from the old hranl_. 13* 14* Modified August 83 by B. Braun to change the long format (when lo_sw is on) 15* to fit neatly on a 80 char screen. 16* 17* Modified 01 Nov 83 by B. Braun to correct OU ioa_ string for bos_no_thread 18* entry. 19* Modified 01 Oct 84 by B. Braun to correct display of hregs from the dump 20* header as per K. Loepere change. 21* Modified 19 Nov 84 by B. Braun as per Alf Burnham changes (phx17889): 22* 1: Cure the AU CU synchronization problem with non-paged segments. 23* 2:Cure the AU runoff beyond index 16 when no fap or fanp in last cycle. 24* 3:Stop displaying an AU entry on a conditional transfer not taken. 25* 4:Correct erroneous display of cu store cycle 26**/ 27 28 hran_l68_: proc; 29 30 31 /* PARAMETERS */ 32 33 dcl a_iocbp ptr; 34 dcl lo_sw bit (1); 35 dcl switches bit (5); /* tell what to print and how */ 36 /* must be in this order */ 37 /* expand_sw, ou, cu, au, du */ 38 39 /* EXTERNAL DATA */ 40 41 dcl get_line_length_$switch 42 entry (ptr, fixed bin (35)) returns (fixed bin); 43 dcl ioa_ entry options (variable), 44 ioa_$ioa_switch options (variable), 45 ioa_$ioa_switch_nnl entry options (variable), 46 ioa_$rsnnl entry options (variable), 47 iox_$user_output ptr ext; /* default io switch */ 48 49 50 dcl 1 a_switches based (addr (switches)), 51 (2 expand_sw bit (1), 52 2 do_ou bit (1), 53 2 do_cu bit (1), 54 2 do_au bit (1), 55 2 do_du bit (1)) unal; 56 57 dcl 1 OU_ (16) based (ouhrp), 58 2 even bit (36), 59 2 odd bit (36); 60 61 dcl 1 CU_ (16) based (cuhrp), 62 2 even bit (36), 63 2 odd bit (36); 64 65 dcl 1 DU_ (16) based (duhrp), 66 2 even bit (36), 67 2 odd bit (36); 68 69 dcl 1 AU_ (16) based (aphrp), 70 2 even bit (36), 71 2 odd bit (36); 72 73 74 /* AUTOMATIC STORAGE */ 75 76 dcl AU_index fixed, /* AU data index */ 77 AU_ptr ptr, /* pointer to AU data */ 78 AU_synch fixed, /* AU index for synch */ 79 CU_index fixed, /* index into CU data */ 80 CU_ptr ptr, /* pointer to CU data */ 81 CU_synch fixed, /* index value at which CU & OU synchronize */ 82 CY_print char (1), /* cycle type for output */ 83 DU_index fixed, /* DU entry index */ 84 DU_mode char (1), /* DU execution mode symbol */ 85 EXP_DU_mode char (4), 86 DU_ptr ptr, /* pointer to DU data */ 87 IC_cur fixed (18) init (0), /* current IC value for CU entries */ 88 IC_flag bit (1), /* IC print control flag */ 89 IC_next fixed (18) init (0), /* next =C value for CU lines */ 90 IC_print char (7), /* printed IC value */ 91 IC_synch fixed (18), /* IC tracker value at synchronization */ 92 IC_value fixed (18), /* IC value for output */ 93 NOP_flag bit (1) init ("0"b), /* flag for NOP cycles */ 94 OP_cur bit (10) init ((10)"0"b), /* current opcode for CU lines */ 95 OP_print char (5), /* opcode string for printing */ 96 OU_ptr ptr, /* pointer to OU data */ 97 OU_index fixed bin, /* index into OU data */ 98 OU_synch fixed init (0), /* index value at which OU & CU synchronize */ 99 PTW_print char (2), /* PTWAMR number for printing */ 100 SDW_print char (2), /* SDWAMR number for printing */ 101 SEG_print char (5), /* segment number for printing */ 102 TAG_cur fixed, /* current TAG table index */ 103 TAG_print char (4), /* TAG string for printing */ 104 XD1_flag bit (1) init ("0"b), /* flag for 1st of XED pair */ 105 XD2_flag bit (1) init ("0"b), /* flag for 2nd of XED pair */ 106 XEC_flag bit (1) init ("0"b), /* XEC flag */ 107 XED_flag bit (1) init ("0"b), /* XED flag */ 108 count_diff fixed, /* repeat/repull count difference */ 109 ll_sw bit(1), 110 null builtin, 111 iocbp ptr, /* output switch name */ 112 fetch_count fixed init (0), /* fetch cycle count */ 113 index fixed, /* general loop index */ 114 pull_count fixed init (0), /* index into instruction pull table */ 115 pull_index fixed; /* index into instruction pull table */ 116 117 dcl (i, j) fixed bin; 118 dcl (a_do_du, a_do_cu) bit (1); 119 dcl 1 hr, /* copy of HR data (corrected) */ 120 2 OU (16), 121 3 even bit (36), 122 3 odd bit (36), 123 2 CU (16), 124 3 even bit (36), 125 3 odd bit (36), 126 2 DU (16), 127 3 even bit (36), 128 3 odd bit (36), 129 2 AU (16), 130 3 even bit (36), 131 3 odd bit (36); 132 133 dcl 1 a_ouhra (16) like ouhra; /* auto storage for OU hregs */ 134 dcl 1 a_cuhra (16) like cuhra; /* auto storage for CU hregs */ 135 dcl 1 a_duhra (16) like duhra; /* auto storage for DU hregs */ 136 dcl 1 a_apuhra (16) like apuhra; /* auto storage for AU hregs */ 137 138 dcl au_sync_mod_value(16) fixed; /* table to hold mod values used in AU CU synchronization */ 139 140 dcl 1 pull_table (16), /* instruction pull table */ 141 2 index fixed unal init ((16)0), 142 2 pt_addr bit (18) unal init ((16) (18)"0"b); 143 144 dcl repeat_count fixed init (0), /* OU instruction repeat count */ 145 repull_count fixed, /* instruction repull count for loop checking */ 146 synch_flag bit (1), /* synchronization flag */ 147 tag_chain_flag bit (1); /* tag print control flag */ 148 dcl hr_block bit (36*128) based; /* #of bits in the hr data block */ 149 dcl code fixed bin (35); 150 dcl from_bos bit (1) init ("0"b); 151 152 153 154 hranl_l68_bos: entry (hr_data_ptr, a_iocbp, lo_sw); 155 156 from_bos = "1"b; 157 go to START; 158 159 hranl_l68_: entry (hr_data_ptr, a_iocbp, lo_sw); 160 161 from_bos = "0"b; 162 163 START: 164 code = 0; 165 call setup; 166 if code ^= 0 then return; 167 168 169 /* History regs are valid, print heading and initialize */ 170 171 call ioa_$ioa_switch (iocbp, "L68 History Register Analysis"); 172 call ioa_$ioa_switch (iocbp, "^/ HR^[^5-^;^24x^]c", lo_sw); 173 174 call ioa_$ioa_switch_nnl (iocbp, 175 "id##^[^8xhr contents^-^;^3x^]IC_____ opcd__ tag_ y seg#_ offset__ mc ^[^/^7tflags^;flags^/^]", 176 lo_sw, (lo_sw & ll_sw)); 177 178 179 /* Copy the data. There are cases where the data is inconsistent because of hardware timing 180* delays and these inconsistencies must be removed before analysis can be done. */ 181 182 OU = OU_; /* copy the entire structure */ 183 CU = CU_; 184 DU = DU_; 185 AU = AU_; 186 187 a_ouhra = ouhra; /* and do it again */ 188 a_cuhra = cuhra; 189 a_duhra = duhra; 190 a_apuhra = apuhra; 191 192 193 /* Build the table of mod values used in syncing AU to CU */ 194 195 do AU_index = 1 to 16; 196 if a_apuhra.fap (AU_index) 197 then au_sync_mod_value (AU_index) = 1024; 198 else au_sync_mod_value (AU_index) = 16; 199 /* if not fap then could be non-paged segment. Assume so.*/ 200 end; 201 202 /* Fix up repeated values of IC Tracker. These occur because of differences 203* in timing between the OU, which strobes the data, and the CU, which controls the value */ 204 205 206 207 208 do OU_index = 2 to 16; /* from 2nd to last */ 209 /* if IC Tracker value is the same, then ... */ 210 if a_ouhra.ict (OU_index) = a_ouhra.ict (OU_index-1) then 211 /* if all flags are _n_o_t the same, then ... 212* (If IC Tracker _a_n_d all flags are the same, 213* the OU is in multi-cycle or is repeating) */ 214 if hr.OU.even (OU_index) ^= hr.OU.even (OU_index-1) then 215 /* and if the op is _n_o_t LREG or SREG ... */ 216 if a_ouhra.rp (OU_index) ^= LREG & a_ouhra.rp (OU_index) ^= SREG then 217 /* add one to IC Tracker value */ 218 a_ouhra.ict (OU_index) = bit (add (fixed (a_ouhra.ict (OU_index)), 1, 17, 0), 18); 219 end; 220 221 /* Construct an instruction pull table containing the CU_index and addr 222* for all true instruction pulls . Also count all fetch cycles (including 223* descriptor fetches and dummy fetches */ 224 225 do CU_index = 1 to 16; /* look at all CU entries */ 226 /* if the instruction fetch flag in port 227* data is set, then ... */ 228 if a_cuhra.ins_fetch (CU_index) then do; 229 fetch_count = fetch_count+1; /* count a fetch cycle */ 230 /* if the CU is preparing an instruction 231* address _o_r taking a transfer ... */ 232 if (a_cuhra.pia (CU_index) | a_cuhra.trgo (CU_index)) 233 /* _a_n_d this is not the fault cycle ... */ 234 & a_cuhra.nflt (CU_index) then do; 235 pull_table.index (pull_count+1) = CU_index; /* save CU_index and ... */ 236 /* computed address */ 237 pull_table.pt_addr (pull_count+1) = a_cuhra.ca_value (CU_index); 238 pull_count = pull_count+1; /* count an instruction pull */ 239 end; 240 end; 241 end; 242 243 /* Test instruction pull count. If zero, then ... 244* 245* Hypothesis 1 --- 246* 247* The CU will execute 16 (or more) cycles without an instruction pull only if one of the 248* following conditions obtain ... 249* 250* 1) A long EIS instruction is being executed, 251* 2) There is a very long indirect chain, 252* 3) The CU is in repeat mode. 253* 254* 255* Under this hypothesis, there may be at most four instructions appearing in the CU history 256* register with the fault occuring in the last one. The last instruction pull has been overwritten 257* and the fault occurs before or during the next pull. Thus all instructions appearing are in 258* strictly sequential order and the IC Tracker value in OU17 (fault OU) is the value for CU17. */ 259 260 if pull_count = 0 then do; 261 262 263 264 IC_synch = fixed (a_ouhra.ict (16)); /* set IC synch point to last value */ 265 OU_synch = 16; /* set OU synch index value */ 266 267 HRG01C: do CU_synch = 16 to 2 by -1; /* search CU entries backwards */ 268 /* for the fault opcode */ 269 if a_cuhra.op_code (CU_synch) = a_ouhra.rp (16) then 270 /* found it if OU-load or OU-store are set */ 271 if a_cuhra.oul (CU_synch) | a_cuhra.ous (CU_synch) then goto HRG05C; 272 end; 273 goto HRG05C; /* if no match, must look further */ 274 end; 275 276 /* Pull count is non-zero. Find the first instruction pulled */ 277 278 pull_table.index (pull_count+1) = 16; /* add fault cycle for table control */ 279 do pull_index = 1 to pull_count; /* using all pull table entries */ 280 do CU_index = pull_table.index (pull_index) to 16; /* scan all CU entries */ 281 IC_synch = fixed (pull_table.pt_addr (pull_index), 18); /* tentative IC synch */ 282 if ^a_cuhra.nflt (CU_index) then goto HRG02F; /* if this the fault cycle, the CU 283* failed to complete the instruction pair 284* during which it pulled the next pair. */ 285 if OP.TR (fixed (a_cuhra.op_code (CU_index))+1) & a_cuhra.trgo (CU_index) then do; 286 /* if this is a transfer taken, then ... */ 287 CU_synch = CU_index+1; /* next CU entry is the one */ 288 goto HRG05C; 289 end; 290 /* if IC is odd, then the next even instruction 291* is from this pull */ 292 if a_cuhra.ic (CU_index) then do CU_synch = CU_index to 16; 293 if ^a_cuhra.ic (CU_synch) then goto HRG05C; 294 end; 295 end; /* loop on CU_index values */ 296 HRG02A: end; /* loop on pull_index */ 297 298 299 /* Hypothesis 2 --- 300* 301* The CU will fail to complete the current instruction pair ( or fail to reach the even instruction) if ... 302* 303* 1) The instruction pull is the last (or only) pull _a_n_d one of the condition of Hypothesis 1 304*  applies during the execution of the current pair _a_n_d the CU faults on the instruction pull. 305* 306* or 2) The instruction pull is the only pull and is a "look ahead" pull _a_n_d execution of the 307*  current pair leads to one of the conditions of Hypothesis 1. 308* 309* or 3) The processor is in a lock-up loop. 310* 311* The conditions for this hypothesis are the same as those to Hypothesis 1 with the 312* exception of the single instruction pull allowed. The same procedure may be used. */ 313 314 HRG02F: goto HRG01C; 315 316 /* Check for a program loop by counting repulls of this instruction pair */ 317 318 HRG05C: CU_index = CU_synch; /* save current CU_synch value */ 319 /* if the opcode is LREG or SREG, then ... */ 320 if a_cuhra.op_code (CU_index) = SREG | a_cuhra.op_code (CU_index) = LREG then do 321 CU_synch = CU_index to 16 while /* search for last CU entry with opcode */ 322 (a_cuhra.op_code (CU_synch) = a_cuhra.op_code (CU_index)); 323 end; 324 325 if CU_synch = 1 then goto HRG06; /* if this is the 1st CU entry ... */ 326 327 if OP.OUOP (fixed (a_cuhra.op_code (CU_synch))) then /* if this is an OU OP ... */ 328 do CU_index = CU_synch-1 to 1 by -1; /* search CU entries backwards for oldest 329* entry matching this OU entry */ 330 if CU_index > 1 then do; /* if this is _n_o_t the 1st CU entry ... */ 331 /* and the opcode is the same as the 332* prior entry ... */ 333 if a_cuhra.op_code (CU_index) = a_cuhra.op_code (CU_synch) then 334 /* and it is not lreg or sreg ... */ 335 if a_cuhra.op_code (CU_index) ^= LREG & a_cuhra.op_code (CU_index) ^= SREG 336 /* and the repeat flag is not set ... */ 337 & ^a_cuhra.rpts (CU_index) 338 /* or _n_o_t preparing instruction address, _n_o_t 339* fetching or storing and indirect word, and _n_o_t pulling 340* an instruction */ 341 | (^a_cuhra.pia (CU_index) & ^a_cuhra.riw (CU_index) 342 & ^a_cuhra.siw (CU_index) & ^a_cuhra.wi (CU_index)) then 343 CU_synch = CU_index; 344 end; 345 end; 346 goto HRG06; 347 348 /* Hypothesis 5 --- 349* 350* Because the CU is "busier" than the OU, the OU will always contain at least as many occurences 351* of an OU instruction as the CU. However, during "back-to-back" store operations, the IC Tracker 352* may fall behand by a count. Most of these cases have already been covered by the ICT scan loop 353* at HRG01F but the case of the double store will be covered here. */ 354 355 HRG05H: if OU_synch = 0 then OU_synch = 16; 356 do OU_index = 2 to 16; /* inspect all entries */ 357 if a_ouhra.rp (OU_index) ^= LREG & a_ouhra.rp (OU_index) ^= SREG then 358 if a_ouhra.ict (OU_index) = a_ouhra.ict (OU_index-1) then do; 359 a_ouhra.ict (OU_index) = bit (add (fixed (a_ouhra.ict (OU_index)), 1, 35, 0), 18); 360 if fixed (a_ouhra.ict (OU_index)) = IC_synch then goto HRG05C; 361 end; 362 end; 363 364 /* Output CU entries up to CU_synch */ 365 366 HRG06: IC_value = 0; /* initialize IC value for printout */ 367 synch_flag = "0"b; /* reset synch flag */ 368 tag_chain_flag, IC_flag = "0"b; /* reset control flags */ 369 DU_index = fetch_count+1; /* initialize DU entry index */ 370 AU_index = 0; /* turn off AU lines */ 371 do AU_synch = 1 to 16 while /* synch AU to IC_synch */ 372 ((mod (fixed (a_apuhra.finadd (AU_synch)), au_sync_mod_value(AU_synch)) ^= 373 mod (IC_synch, au_sync_mod_value(AU_synch))) & 374 375 (hr.AU.even (AU_synch) ^= "0"b)); 376 end; 377 do CU_index = 1 to CU_synch-1; 378 if hr.CU.even (CU_index) ^= "0"b then 379 call cur; 380 end; 381 382 /* Merge CU & OU entries up to fault cycle */ 383 384 HRG08: IC_value = IC_synch; 385 IC_flag = "1"b; 386 OU_index = 0; 387 synch_flag = "1"b; 388 if CU_index = 16 then goto HRG09; 389 do CU_index = CU_index to 15; 390 if ^a_cuhra.nflt (CU_index) then 391 go to do_fault_cycle; 392 call cur; 393 if OP.OUOP (fixed (OP_cur)+1) & (a_cuhra.oul (CU_index) | a_cuhra.ous (CU_index)) 394 & ^a_cuhra.saw (CU_index) then do; 395 if OU_synch = 0 then do OU_synch = 1 to 16 while 396 (fixed (a_ouhra.ict (OU_synch), 18) ^= IC_value); 397 end; 398 if OU_synch = 17 then /* no synch found */ 399 OU_synch = 0; /* reset for next time */ 400 else if OU_index = 0 then OU_index = OU_synch; /* setup new found synch */ 401 if OU_index > 0 & OU_index < 16 then do; /* within range */ 402 call our; 403 OU_index = OU_index + 1; 404 end; 405 end; 406 end; 407 408 /* Do the fault cycles */ 409 do_fault_cycle: 410 411 412 HRG09: 413 call cur; 414 415 call ioa_$ioa_switch (iocbp, "^/"); 416 return; 417 418 our: proc; 419 420 if ^synch_flag then do; 421 call ioa_$rsnnl ("^7o", IC_print, 7, fixed (a_ouhra.ict (OU_index))); 422 IC_value = fixed (a_ouhra.ict (OU_index)); 423 end; 424 else IC_print = " "; 425 426 if ^synch_flag then OP_print = OP.code (2*fixed (a_ouhra.rp (OU_index))+1); 427 else OP_print = " "; 428 call ioa_$ioa_switch_nnl (iocbp, "^/OU^2o^[ ^12.3b ^12.3b^;^2s^3x^]^7a ^6a^26x^[^/^7t^]", OU_index, lo_sw, 429 hr.OU.even (OU_index), hr.OU.odd (OU_index), IC_print, OP_print, (lo_sw & ll_sw)); 430 if a_ouhra.dir (OU_index) then 431 if substr (a_cuhra.tag (OU_index), 1, 1) then call ioa_$ioa_switch_nnl (iocbp, "dl "); 432 else call ioa_$ioa_switch_nnl (iocbp, "du "); 433 call ioa_$ioa_switch_nnl (iocbp, "^[rb ^]^[rp ^]^[rs ^]^[in ^]^[os ^]", 434 a_ouhra.opbf (OU_index), a_ouhra.frpf (OU_index), 435 a_ouhra.srf (OU_index), a_ouhra.gin (OU_index), 436 a_ouhra.gos (OU_index)); 437 438 call ioa_$ioa_switch_nnl (iocbp, "^[d1 ^]^[d2 ^]^[oe ^]^[oa ^]^[om ^]^[on ^]", 439 a_ouhra.gd1 (OU_index), a_ouhra.gd2 (OU_index), 440 a_ouhra.goe (OU_index), a_ouhra.goa (OU_index), 441 a_ouhra.gom (OU_index), a_ouhra.gon (OU_index)); 442 443 call ioa_$ioa_switch_nnl (iocbp, "^[of ^]^[sd ^]^[-d ^]^[ar ^]^[qr ^]^[x0 ^]", 444 a_ouhra.gof (OU_index), a_ouhra.fstr (OU_index), 445 a_ouhra.dn (OU_index), ^a_ouhra.an (OU_index), 446 ^a_ouhra.qn (OU_index), ^a_ouhra.x0n (OU_index)); 447 448 call ioa_$ioa_switch_nnl (iocbp, "^[x1 ^]^[x2 ^]^[x3 ^]^[x4 ^]^[x5 ^]^[x6 ^]^[x7^]", 449 ^a_ouhra.x1n (OU_index), ^a_ouhra.x2n (OU_index), 450 ^a_ouhra.x3n (OU_index), ^a_ouhra.x4n (OU_index), 451 ^a_ouhra.x5n (OU_index), ^a_ouhra.x6n (OU_index), 452 ^a_ouhra.x7n (OU_index)); 453 return; 454 end; 455 456 cur: proc; 457 458 459 /* Determine if IC value is to be displayed */ 460 461 if IC_cur ^= IC_value then goto cur02; /* if it has changed since last CU line ... */ 462 /* or if we are repeating _o_r XEC'ing ... */ 463 if a_cuhra.rpts (CU_index) | XEC_flag then goto cur03; 464 465 cur02: if a_cuhra.op_code (CU_index) ^= OP_cur then /* if opcode has changed */ 466 if IC_next ^= 0 then do; 467 IC_value = IC_next; 468 IC_flag = "1"b; 469 IC_next = 0; 470 end; 471 else if IC_flag then IC_value = IC_value+1; 472 473 IC_print = " "; /* reset IC print value */ 474 if XED_flag then do; /* if XEDing ... */ 475 476 if ^XD1_flag then do; /* if 1st of XED pair not been done ... */ 477 XD1_flag = "1"b; /* we are about to do it */ 478 goto cur03; 479 end; 480 481 if ^XD2_flag then do; /* if 2nd of XED pair has not been done ... */ 482 if a_cuhra.op_code (CU_index) ^= OP_cur then 483 XD2_flag = "1"b; /* we are about to do it */ 484 goto cur03; 485 end; 486 487 if a_cuhra.op_code (CU_index) ^= OP_cur then 488 XED_flag, XD1_flag, XD2_flag = "0"b; /* XED finished, reset all flags */ 489 end; 490 491 if IC_flag then do; 492 if a_cuhra.ic (CU_index) then /* force to odd if ic flag is set */ 493 IC_value = 2* divide (IC_value, 2, 18, 0)+1; 494 else IC_value = 2* divide (IC_value, 2, 18, 0); /* else force even */ 495 if IC_cur ^= IC_value then /* if it changed ... */ 496 call ioa_$rsnnl ("^7o", IC_print, 7, IC_value); 497 else IC_print = " "; 498 IC_cur = IC_value; 499 end; 500 501 cur03: if a_cuhra.op_code (CU_index) = OP_cur & IC_print = " " then 502 /* if neither IC nor opcode have changed ... */ 503 OP_print = " """; /* this must be the same instruction */ 504 else do; 505 OP_cur = a_cuhra.op_code (CU_index); 506 OP_print = OP.code (fixed (OP_cur)+1); 507 end; 508 509 cur04: if OP.DUOP (fixed (a_cuhra.op_code (CU_index))+1) /* if a decimal op ... */ 510 | a_cuhra.op_code (CU_index) = STCA /* or STCA ... */ 511 | a_cuhra.op_code (CU_index) = STCQ /* or STCQ ... */ 512 | a_cuhra.op_code (CU_index) = STBA /* or STBA ... */ 513 | a_cuhra.op_code (CU_index) = STBQ /* or STBQ ... */ 514 | a_cuhra.rpts (CU_index) /* or its a repeat */ 515 then do; /* print a blank TAG */ 516 TAG_cur = 0; 517 TAG_print = " "; 518 end; 519 else do; 520 TAG_cur = fixed (a_cuhra.tag (CU_index))+1; 521 TAG_print = TAG.code (TAG_cur); 522 end; 523 524 if TAG_cur > 0 then /* if its a true tag ... */ 525 tag_chain_flag = TAG.chain (TAG_cur); /* set tag chain flag */ 526 527 if ^a_cuhra.nflt (CU_index) then CY_print = "F"; 528 else if ^a_cuhra.nxip (CU_index) then CY_print = "x"; 529 else if a_cuhra.ins_fetch (CU_index) 530 & (a_cuhra.pia (CU_index) | a_cuhra.wi (CU_index)) then do; 531 CY_print = "i"; 532 if a_cuhra.op_code (CU_index) ^= XED then 533 IC_next = fixed (a_cuhra.ca_value (CU_index)); 534 XED_flag, XD1_flag, XD2_flag = "0"b; /* reset XED flags for transfer */ 535 end; 536 else if a_cuhra.riw (CU_index) | a_cuhra.siw (CU_index) then CY_print = "n"; 537 else if a_cuhra.cul (CU_index) then 538 if a_cuhra.dir (CU_index) then CY_print = "d"; 539 else CY_print = "o"; 540 else if a_cuhra.ous (CU_index) then CY_print = "o"; 541 else if OP.DUOP (fixed (OP_cur)+1) then CY_print = "e"; 542 else if OP_cur = NOP 543 | (OP.TR (fixed (OP_cur)+1) & ^a_cuhra.trgo (CU_index)) then do; 544 CY_print = "*"; 545 NOP_flag = "1"b; 546 end; 547 else if a_cuhra.oul (CU_index) | a_cuhra.ous (CU_index) then 548 if a_cuhra.dir (CU_index) then CY_print = "d"; 549 else CY_print = "o"; 550 else CY_print = "?"; 551 if AU_index = 0 & a_cuhra.ca_value (CU_index) = pull_table.pt_addr (1) then AU_index = AU_synch; 552 553 if 0 hr_block = "0"b then do; 944 call ioa_$ioa_switch (iocbp, "^/History Register Buffer is Empty"); 945 code = -1; 946 return; 947 end; 948 return; 949 end setup; 950 951 1 1 1 2 /* BEGIN INCLUDE FILE ... opcode_tag_table.incl.pl1 1 3* * ... created by R. L. Coppola 8/80. */ 1 4 1 5 dcl (OP_ptr, TAG_ptr) ptr; /* pointers to op code and tag tables */ 1 6 1 7 dcl LREG int static options (constant) bit (9) init ("000111011"b), 1 8 NOP int static options (constant) bit (9) init ("000001001"b); 1 9 1 10 dcl OP_table (128) int static options (constant) char (48) unal init ( /* opcode table */ 1 11 "illop@illop@mme1 @illop@drl @illop@illop@illop@", /* 000 */ 1 12 "mme2 @illop@mme3 @illop@illop@illop@mme4 @illop@", 1 13 "illop@illop@nop @illop@puls1@illop@puls2@illop@", /* 010 */ 1 14 "illop@illop@cioc @illop@illop@illop@illop@illop@", 1 15 "adlx0Bmve Aadlx1Billop@adlx2Billop@adlx3Billop@", /* 020 */ 1 16 "adlx4Bmvne Aadlx5Billop@adlx6Billop@adlx7Billop@", 1 17 "illop@illop@illop@illop@ldqc Jillop@adl Billop@", /* 030 */ 1 18 "ldac Jillop@adla Billop@adlq Billop@adlaqBillop@", 1 19 "asx0 Jillop@asx1 Jillop@asx2 Jillop@asx3 Jillop@", /* 040 */ 1 20 "asx4 Jillop@asx5 Jillop@asx6 Jillop@asx7 Jillop@", 1 21 "adwp0Billop@adwp1Billop@adwp2Billop@adwp3Billop@", /* 050 */ 1 22 "aos Jillop@asa Jillop@asq Jillop@sscr Billop@", 1 23 "adx0 Bcsl Aadx1 Bcsr Aadx2 Billop@adx3 Billop@", /* 060 */ 1 24 "adx4 Bsztl Aadx5 Bsztr Aadx6 Bcmpb Aadx7 Billop@", 1 25 "illop@illop@awca Billop@awcq Billop@lreg Billop@", /* 070 */ 1 26 "illop@illop@ada Billop@adq Billop@adaq Billop@", 1 27 "cmpx0Bmlr Acmpx1Bmrl Acmpx2Billop@cmpx3Billop@", /* 100 */ 1 28 "cmpx4Billop@cmpx5Billop@cmpx6Bcmpc Acmpx7Billop@", 1 29 "illop@illop@cwl Billop@illop@illop@illop@illop@", /* 110 */ 1 30 "illop@illop@cmpa Billop@cmpq Billop@cmpaqBillop@", 1 31 "sblx0Bscd Asblx1Bscdr Asblx2Billop@sblx3Billop@", /* 120 */ 1 32 "sblx4Bscm Asblx5Bscmr Asblx6Billop@sblx7Billop@", 1 33 "illop@illop@illop@illop@illop@illop@illop@illop@", /* 130 */ 1 34 "illop@illop@sbla Billop@sblq Billop@sblaqBillop@", 1 35 "ssx0 Jillop@ssx1 Jillop@ssx2 Jillop@ssx3 Jillop@", /* 140 */ 1 36 "ssx4 Jillop@ssx5 Jillop@ssx6 Jillop@ssx7 Jillop@", 1 37 "adwp4Billop@adwp5Billop@adwp6Billop@adwp7Billop@", /* 150 */ 1 38 "sdbr @sptr @ssa Jillop@ssq Jillop@illop@illop@", 1 39 "sbx0 Bmvt Asbx1 Billop@sbx2 Billop@sbx3 Billop@", /* 160 */ 1 40 "sbx4 Btct Asbx5 Btctr Asbx6 Billop@sbx7 Billop@", 1 41 "illop@illop@swca Billop@swcq Billop@lpri @lptr @", /* 170 */ 1 42 "illop@illop@sba Billop@sbq Billop@sbaq Billop@", 1 43 "cnax0Billop@cnax1Billop@cnax2Bad2d Acnax3Bsb2d A", /* 200 */ 1 44 "cnax4Billop@cnax5Billop@cnax6Bmp2d Acnax7Bdv2d A", 1 45 "illop@illop@cmk Billop@absa Billop@epaq Billop@", /* 210 */ 1 46 "sznc Jillop@cnaa Billop@cnaq Billop@cnaaqBillop@", 1 47 "ldx0 Billop@ldx1 Billop@ldx2 Bad3d Aldx3 Bsb3d A", /* 220 */ 1 48 "ldx4 Billop@ldx5 Billop@ldx6 Bmp3d Aldx7 Bdv3d A", 1 49 "lbar @illop@rsw Billop@ldbr @lsdr @rmcm Billop@", /* 230 */ 1 50 "szn Billop@lda Billop@ldq Billop@ldaq Billop@", 1 51 "orsx0Jillop@orsx1Jillop@orsx2Jillop@orsx3Jillop@", /* 240 */ 1 52 "orsx4Jillop@orsx5Jillop@orsx6Jillop@orsx7Jillop@", 1 53 "spri0@spbp0@spbp1@spri1@spri2@spbp2@spbp3@spri3@", /* 250 */ 1 54 "spri @ssdr @orsa Jillop@orsq Jillop@lsdp @lptp @", 1 55 "orx0 Billop@orx1 Billop@orx2 Billop@orx3 Billop@", /* 260 */ 1 56 "orx4 Billop@orx5 Billop@orx6 Billop@orx7 Billop@", 1 57 "tsp0 `illop@tsp1 `illop@tsp2 `illop@tsp3 `illop@", /* 270 */ 1 58 "illop@illop@ora Billop@orq Billop@oraq Billop@", 1 59 "canx0Bmvn Acanx1Bbtd Acanx2Billop@canx3Bcmpn A", /* 300 */ 1 60 "canx4Billop@canx5Bdtb Acanx6Billop@canx7Billop@", 1 61 "eawp0@easp1@easp0@eawp1@eawp2@easp3@easp2@eawp3@", /* 310 */ 1 62 "illop@illop@cana Billop@canq Billop@canaqBillop@", 1 63 "lcx0 Billop@lcx1 Billop@lcx2 Billop@lcx3 Billop@", /* 320 */ 1 64 "lcx4 Billop@lcx5 Billop@lcx6 Billop@lcx7 Billop@", 1 65 "eawp4@easp5@easp4@eawp5@eawp6@easp7@easp6@eawp7@", /* 330 */ 1 66 "illop@illop@lca Billop@lcq Billop@lcaq Billop@", 1 67 "ansx0Jillop@ansx1Jillop@ansx2Jillop@ansx3Jillop@", /* 340 */ 1 68 "ansx4Jillop@ansx5Jillop@ansx6Jillop@ansx7Jdvdr A", 1 69 "epp0 @epbp0@epbp1@epp1 @epp2 @epbp2@epbp3@epp3 @", /* 350 */ 1 70 "stac Jillop@ansa Jillop@ansq Jillop@stcd @illop@", 1 71 "anx0 Billop@anx1 Billop@anx2 Billop@anx3 Billop@", /* 360 */ 1 72 "anx4 Billop@anx5 Billop@anx6 Billop@anx7 Billop@", 1 73 "epp4 @epbp4@epbp5@epp5 @epp6 @epbp6@epbp7@epp7 @", /* 370 */ 1 74 "illop@illop@ana Billop@anq Billop@anaq Billop@", 1 75 "illop@illop@mpf Billop@mpy Billop@illop@illop@", /* 400 */ 1 76 "illop@illop@cmg Billop@illop@illop@illop@illop@", 1 77 "illop@illop@lde Billop@illop@illop@rscr Billop@", /* 410 */ 1 78 "illop@illop@ade Billop@illop@illop@illop@illop@", 1 79 "illop@illop@ufm Billop@illop@illop@dufm Billop@", /* 420 */ 1 80 "illop@illop@fcmg Billop@illop@illop@dfcmgBillop@", 1 81 "fszn Billop@fld Billop@illop@illop@dfld Billop@", /* 430 */ 1 82 "illop@illop@ufa Billop@illop@illop@dufa Billop@", 1 83 "sxl0 Billop@sxl1 Billop@sxl2 Billop@sxl3 BsanA", /* 440 */ 1 84 "sxl4 Billop@sxl5 Billop@sxl6 Billop@sxl7 Bspl A", 1 85 "stz Billop@smic Billop@scpr Billop@illop@illop@", /* 430 */ 1 86 "stt @illop@fst Billop@ste Billop@dfst Billop@", 1 87 "illop@illop@fmp Billop@illop@illop@dfmp BlanA", /* 460 */ 1 88 "illop@illop@illop@illop@illop@illop@illop@lpl A", 1 89 "fstr Billop@frd Billop@dfstrBillop@dfrd Billop@", /* 470 */ 1 90 "illop@illop@fad Billop@illop@illop@dfad Billop@", 1 91 "rpl Pa9bd Aillop@a6bd Aillop@a4bd Aillop@abd A", /* 500 */ 1 92 "illop@illop@bcd Billop@div Billop@dvf Bawd A", 1 93 "illop@illop@illop@illop@illop@illop@fneg Billop@", /* 510 */ 1 94 "illop@illop@fcmp Billop@illop@illop@dfcmpBillop@", 1 95 "rpt Ps9bd Aillop@s6bd Aillop@s4bd Aillop@sbd A", /* 520 */ 1 96 "illop@illop@fdi Billop@illop@illop@dfdi Bswd A", 1 97 "illop@illop@neg Billop@cams @camp @negl Billop@", /* 530 */ 1 98 "illop@illop@ufs Billop@illop@illop@dufs Billop@", 1 99 "sprp0@ara0 Asprp1@ara1 Asprp2@ara2 Asprp3@ara3 A", /* 540 */ 1 100 "sprp4@ara4 Asprp5@ara5 Asprp6@ara6 Asprp7@ara7 A", 1 101 "sbar @illop@stba Billop@stbq Billop@smcm Billop@", /* 550 */ 1 102 "stc1 @illop@illop@illop@illop@illop@ssdp @sptp @", 1 103 "rpd Paar0 Aillop@aar1 Aillop@aar2 Aillop@aar3 A", /* 560 */ 1 104 "illop@aar4 Afdv Baar5 Aillop@aar6 Adfdv Baar7 A", 1 105 "illop@illop@illop@illop@illop@illop@fno Billop@", /* 570 */ 1 106 "illop@illop@fsb Billop@illop@illop@dfsb Billop@", 1 107 "tze dtrtn dtnz dtrtf dtnc dillop@trc dillop@", /* 600 */ 1 108 "tmi dtmoz dtpl dtpnz dillop@ttn dttf dillop@", 1 109 "rtcd `illop@illop@illop@illop@illop@rcu `illop@", /* 610 */ 1 110 "teo dillop@teu dillop@dis @illop@tov dillop@", 1 111 "eax0 Billop@eax1 Billop@eax2 Billop@eax3 Billop@", /* 620 */ 1 112 "eax4 Billop@eax5 Billop@eax6 Billop@eax7 Billop@", 1 113 "ret `illop@illop@illop@illop@illop@rccl Billop@", /* 630 */ 1 114 "ldi @illop@eaa Billop@eaq Billop@ldt @illop@", 1 115 "ersx0Jarn0 @ersx1Jarn1 @ersx2Jarn2 @ersx3Jarn3 @", /* 640 */ 1 116 "ersx4Jarn4 @ersx5Jarn5 @ersx6Jarn6 @ersx7Jarn7 @", 1 117 "spri4@spbp4@spbp5@spri5@spri6@spbp6@spbp7@spri7@", /* 650 */ 1 118 "stacqJillop@ersa Jillop@ersq Jillop@scu @illop@", 1 119 "erx0 Bnar0 @erx1 Bnar1 @erx2 Bnar2 @erx3 Bnar3 @", /* 660 */ 1 120 "erx4 Bnar4 @erx5 Bnar5 @erx6 Bnar6 @erx7 Bnar7 @", 1 121 "tsp4 `illop@tsp5 `illop@tsp6 `illop@tsp7 `illop@", /* 670 */ 1 122 "lcpr @illop@era Billop@erq Billop@eraq Billop@", 1 123 "tsx0 `illop@tsx1 `illop@tsx2 `illop@tsx3 `illop@", /* 700 */ 1 124 "tsx4 `illop@tsx5 `illop@tsx6 `illop@tsx7 `illop@", 1 125 "tra `illop@illop@illop@illop@illop@call6`illop@", /* 710 */ 1 126 "illop@illop@tss `illop@xec @illop@xed @illop@", 1 127 "lxl0 Billop@lxl1 Billop@lxl2 Billop@lxl3 Billop@", /* 720 */ 1 128 "lxl4 Billop@lxl5 Billop@lxl6 Billop@lxl7 Billop@", 1 129 "illop@illop@ars Billop@qrs Billop@lrs Billop@", /* 730 */ 1 130 "illop@illop@als Billop@qls Billop@lls Billop@", 1 131 "stx0 Bsar0 @stx1 Bsar1 @stx2 Bsar2 @stx3 Bsar3 @", /* 740 */ 1 132 "stx4 Bsar4 @stx5 Bsar5 @stx6 Bsar6 @stx7 Bsar7 @", 1 133 "stc2 @illop@stca Billop@stcq Billop@sreg Billop@", /* 750 */ 1 134 "sti @sra @sta Billop@stq Bsptr @staq Billop@", 1 135 "lprp0@lar0 @lprp1@lar1 @lprp2@lar2 @lprp3@lar3 @", /* 760 */ 1 136 "lprp4@lar4 @lprp5@lar5 @lprp6@lar6 @lprp7@lar7 @", 1 137 "illop@illop@arl Billop@qrl Billop@lrl Billop@", /* 770 */ 1 138 "gtb Blra @alr Billop@qlr Billop@llr Billop@"); 1 139 1 140 dcl SREG int static options (constant) bit (9) init ("111101011"b), 1 141 STBA int static options (constant) bit (9) init ("101101001"b), 1 142 STBQ int static options (constant) bit (9) init ("101101010"b), 1 143 STCA int static options (constant) bit (9) init ("111101001"b), 1 144 STCQ int static options (constant) bit (9) init ("111101010"b), 1 145 XEC int static options (constant) bit (9) init ("111001110"b), 1 146 XED int static options (constant) bit (9) init ("111001111"b); 1 147 1 148 dcl TAG_table (8) char (40) int static options (constant)init ( /* tag table */ 1 149 " au qu du ic al ql dl ", 1 150 "x0 x1 x2 x3 x4 x5 x6 x7 ", 1 151 "n* aau* aqu* aill ic* aal* aql* aill ", 1 152 "x0* ax1* ax2* ax3* ax4* ax5* ax6* ax7* a", 1 153 "fi itp ill its sd scr f2 f3 ", 1 154 "ci i sc ad di dic aid idc a", 1 155 "*n *au *qu ill *ic *al *ql ill ", 1 156 "*x0 *x1 *x2 *x3 *x4 *x5 *x6 *x7 "); 1 157 1 158 1 159 dcl 1 OP (1024) based (OP_ptr), 1 160 2 code char (5) unal, 1 161 2 pad bit (3) unal, 1 162 2 TR bit (1), 1 163 2 RPT bit (1), 1 164 2 ALT bit (1), 1 165 2 COND bit (1), 1 166 2 OUOP bit (1), 1 167 2 DUOP bit (1); 1 168 1 169 dcl 1 TAG (64) based (TAG_ptr), 1 170 2 code char (4) unal, 1 171 2 pad bit (8) unal, 1 172 2 chain bit (1); 1 173 1 174 952 953 2 1 /* BEGIN INCLUDE FILE ... history_regs_l68.incl.pl1 ... last modified 10/80 */ 2 2 2 3 2 4 dcl (ouhrp, cuhrp, aphrp, duhrp, hr_data_ptr) ptr; 2 5 2 6 2 7 dcl ou_offset fixed bin init (0), /* offsets to hr data within the hr data block */ 2 8 cu_offset fixed bin init (32), 2 9 du_offset fixed bin init (64), 2 10 au_offset fixed bin init (96); 2 11 2 12 2 13 dcl 1 cuhra (16) based (cuhrp) aligned, 2 14 (2 pia bit (1), /* preparing instruction address */ 2 15 2 poa bit (1), /* preparing operand address */ 2 16 2 riw bit (1), /* requesting indirect word */ 2 17 2 siw bit (1), /* restoring indirect word */ 2 18 2 pot bit (1), /* preparing operand tally */ 2 19 2 pon bit (1), /* preparing operand address */ 2 20 2 raw bit (1), /* requesting alter-rewrite word */ 2 21 2 saw bit (1), /* restoring alter-rewrite word */ 2 22 2 trgo bit (1), /* transfer go - condition met */ 2 23 2 xde bit (1), /* XED from even location */ 2 24 2 xdo bit (1), /* XED from odd location */ 2 25 2 ic bit (1), /* even/odd inst. pair */ 2 26 2 rpts bit (1), /* repeat operation */ 2 27 2 wi bit (1), /* wait for instruction fetch */ 2 28 2 ar bit (1), /* address reg valid */ 2 29 2 nxip bit (1), /* not an xip address */ 2 30 2 nflt bit (1), /* not an FLT address */ 2 31 2 np bit (1), /* not in privilaged mode */ 2 32 2 op_code bit (10), /* op code of inst */ 2 33 2 inhib bit (1), /* inhibit int bit */ 2 34 2 its_flag bit (1), /* ar reg mod flag */ 2 35 2 tag bit (6), /* tag field of instr */ 2 36 2 ca_value bit (18), /* address field of inst */ 2 37 2 pcmd bit (5), /* processor command register */ 2 38 2 psl bit (4), /* port select lines */ 2 39 2 xint bit (1), /* execute interrupt */ 2 40 2 ins_fetch bit (1), /* inst fetch */ 2 41 2 cus bit (1), /* control unit store */ 2 42 2 ous bit (1), /* operations unit store */ 2 43 2 cul bit (1), /* control unit load */ 2 44 2 oul bit (1), /* operations unit load */ 2 45 2 dir bit (1), /* direct cycle */ 2 46 2 npcb bit (1), /* port logic not busy */ 2 47 2 pib bit (1)) unaligned; /* port interface busy */ 2 48 2 49 2 50 dcl 1 ouhra (16) based (ouhrp) aligned, 2 51 (2 nopc bit (9), /* next inst. op code */ 2 52 2 itw bit (1), /* IT tally word 6/9 bit data */ 2 53 2 ntg bit (3), /* next inst tag field */ 2 54 2 cmod bit (1), /* character modification */ 2 55 2 dir bit (1), /* direct modification */ 2 56 2 efad bit (2), /* LREG/SREG effective addr */ 2 57 2 pad0 bit (1), 2 58 2 rp bit (9), /* copy of RP reg */ 2 59 2 opbf bit (1), /* OU op code buffer full */ 2 60 2 frpf bit (1), /* primary register full */ 2 61 2 srf bit (1), /* secondary register full */ 2 62 2 gin bit (1), /* first cycle for all OU */ 2 63 2 gos bit (1), /* second cycle for OU - multiple OP */ 2 64 2 gd1 bit (1), /* first divide cycle */ 2 65 2 gd2 bit (1), /* second divide cycle */ 2 66 2 goe bit (1), /* exponent compare cycle */ 2 67 2 goa bit (1), /* mamtissa alignment cycle */ 2 68 2 gom bit (1), /* general OU cycle */ 2 69 2 gon bit (1), /* normalize cycle */ 2 70 2 gof bit (1), /* final cycle */ 2 71 2 fstr bit (1), /* OU store data available */ 2 72 2 dn bit (1), /* data not available */ 2 73 2 an bit (1), /* A reg not in use */ 2 74 2 qn bit (1), /* Q reg not used */ 2 75 2 x0n bit (1), /* X0 not in use */ 2 76 2 x1n bit (1), /* X1 not in use */ 2 77 2 x2n bit (1), /* X2 not in use */ 2 78 2 x3n bit (1), /* X3 not in use */ 2 79 2 x4n bit (1), /* X4 not in use */ 2 80 2 x5n bit (1), /* X5 not in use */ 2 81 2 x6n bit (1), /* X6 not in use */ 2 82 2 x7n bit (1), /* X7 not in use */ 2 83 2 pad1 bit (3), 2 84 2 ict bit (18)) unaligned; /* address of OU inst */ 2 85 2 86 2 87 dcl 1 apuhra (16) based (aphrp), 2 88 (2 esn bit (15), /* effective segment number for this cycle */ 2 89 2 bsy bit (2), /* source of ESN above */ 2 90 2 fdsptw bit (1), /* fetch of dseg PTW */ 2 91 2 mdsptw bit (1), /* mod of dseg PTW */ 2 92 2 dfsdw bit (1), /* xxxxxx */ 2 93 2 fptw bit (1), /* fetch PTW */ 2 94 2 fptw2 bit (1), /* fetch PTW + 1 */ 2 95 2 mptw bit (1), /* modify PTW */ 2 96 2 fanp bit (1), /* fetch final add from non-paged seg */ 2 97 2 fap bit (1), /* xxxxx */ 2 98 2 sdwmf bit (1), /* SDW match in AM */ 2 99 2 sdwamr bit (4), /* AM register that holds SDW */ 2 100 2 ptwmf bit (1), /* PTW match in AM */ 2 101 2 ptwamr bit (4), /* AM register that holds PTW */ 2 102 2 flt bit (1), /* ACV or DF flt caused by this cycle */ 2 103 2 finadd bit (24), /* absolute address of this cycle */ 2 104 2 trr bit (3), /* value of tpr.trr for this cycle */ 2 105 2 apu_pad1 bit (7), 2 106 2 flthld bit (1), /* an ACV or DF flt is waiting to be processed */ 2 107 2 apu_pad2 bit (1))unaligned; 2 108 2 109 2 110 dcl 1 duhra (16) based (duhrp) aligned, 2 111 (2 pol bit (1), /* preparing operand length */ 2 112 2 pop bit (1), /* preparing pointer */ 2 113 2 ndesc bit (1), /* need descriptor */ 2 114 2 seladr bit (1), /* select address register */ 2 115 2 dlendr bit (1), /* length = direct */ 2 116 2 dfrst bit (1), /* processing desc. for first time */ 2 117 2 exr bit (1), /* extended register modification */ 2 118 2 ldfrst bit (1), /* last cycle of dfrst above */ 2 119 2 dulea bit (1), /* DU load and effective add. */ 2 120 2 dusea bit (1), /* DU store and effective add. */ 2 121 2 redo bit (1), /* redo - no update of ptrs. and lngh. */ 2 122 2 wcws bit (1), /* load word count < word size */ 2 123 2 exh bit (1), /* exhaust */ 2 124 2 eseq bit (1), /* end of sequence */ 2 125 2 einst bit (1), /* end of instruction */ 2 126 2 durw bit (1), /* DU read or write */ 2 127 2 ptra bit (2), /* PR address bits 0 and 1 */ 2 128 2 fai1 bit (1), /* active/inactive desc. 1 */ 2 129 2 fai2 bit (1), /* active/inactive desc. 2 */ 2 130 2 fai3 bit (1), /* active/inactive desc. 3 */ 2 131 2 du_wrd bit (1), /* word type inst. */ 2 132 2 nine bit (1), /* nine bit type inst. */ 2 133 2 six bit (1), /* six bit type inst. */ 2 134 2 four bit (1), /* four bit type inst. */ 2 135 2 one bit (1), /* one bit type inst */ 2 136 2 du_pad1 bit (4), 2 137 2 samplint bit (1), /* sample for mid inst. intrp. */ 2 138 2 sfcsq bit (1), /* specific first count of sequence */ 2 139 2 adjlen bit (1), /* adjust length */ 2 140 2 mif bit (1), /* mid inst. intrp. indicator */ 2 141 2 inhibstc1 bit (1), /* inhibit sct1 inst. */ 2 142 2 du_pad2 bit (1), 2 143 2 duidl bit (1), /* DU idle */ 2 144 2 dcldgta bit (1), /* desc. load gates A */ 2 145 2 dcldgtb bit (1), /* desc. load gates B */ 2 146 2 dcldgtc bit (1), /* desc. load gates C */ 2 147 2 nopl1 bit (1), /* alignment cnt. for 1st numeric op. ld. */ 2 148 2 nopgl1 bit (1), /* numeric op. 1 gate load */ 2 149 2 nopl2 bit (1), /* alignment cnt. for 2nd numeric op. ld. */ 2 150 2 nopgl2 bit (1), /* numeric op. 2 gate load */ 2 151 2 aoplg1 bit (1), /* alphanum. op. 1 gate load */ 2 152 2 aoplg2 bit (1), /* alphanum. op. 2 gate load */ 2 153 2 lrwrg1 bit (1), /* load rewrite reg. gate 1 */ 2 154 2 lrwrg2 bit (1), /* load rewrite reg. gate 2 */ 2 155 2 dataav_du bit (1), /* data available */ 2 156 2 rw1rl bit (1), /* rewrite one reg. loaded */ 2 157 2 numstg bit (1), /* numeric store gate */ 2 158 2 anstg bit (1), /* alpha-numeric store gate */ 2 159 2 opav bit (1), /* operand available */ 2 160 2 endseq_du bit (1), /* end sequence */ 2 161 2 len128 bit (1), /* length < 128 */ 2 162 2 charop bit (1), /* character operation */ 2 163 2 anpk bit (1), /* alphanumeric packing cycle */ 2 164 2 exmop bit (1), /* execute MOP */ 2 165 2 blnk bit (1), /* blanking ind. */ 2 166 2 du_pad3 bit (1), 2 167 2 bde bit (1), /* binary to decimal ind. */ 2 168 2 dbe bit (1), /* decimal to binary ind. */ 2 169 2 shft bit (1), /* shift ind. */ 2 170 2 flt bit (1), /* floating ind. */ 2 171 2 rnd bit (1), /* round ind. */ 2 172 2 addsub bit (1), /* add-subtract ind. */ 2 173 2 multdiv bit (1), /* multiply-divide ind. */ 2 174 2 expon bit (1), /* exponent ind. */ 2 175 2 du_pad4 bit (4))unaligned; 2 176 2 177 2 178 /* END INCLUDE FILE ... history_regs.incl.pl1 */ 954 955 956 957 end hran_l68_; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 02/13/85 0857.3 hran_l68_.pl1 >special_ldd>online>6897>hran_l68_.pl1 952 1 02/03/82 1702.8 opcode_tag_table.incl.pl1 >ldd>include>opcode_tag_table.incl.pl1 954 2 03/16/81 1153.0 history_regs_l68.incl.pl1 >ldd>include>history_regs_l68.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. AU 140 000152 automatic structure array level 2 packed unaligned dcl 119 set ref 185* AU_ based structure array level 1 packed unaligned dcl 69 set ref 185 AU_index 000100 automatic fixed bin(17,0) dcl 76 set ref 195* 196 196 198* 370* 551 551* 553 553 553 553 590 590* 590 590 590* 596 596 599* 599 600 600 600 600 618 621 621 621 623 623 623 626* 626 626 626 626 626 626 630 630 630 630 630 630 635 635 635 635 635 635 AU_synch 000101 automatic fixed bin(17,0) dcl 76 set ref 371* 371 371 371 371* 551 CU 40 000152 automatic structure array level 2 packed unaligned dcl 119 set ref 183* CU_ based structure array level 1 packed unaligned dcl 61 set ref 183 CU_index 000102 automatic fixed bin(17,0) dcl 76 set ref 225* 228 232 232 232 235 237* 280* 282 285 285 287 292 292* 318* 320 320 320 320 327* 330 333 333 333 333 333 333 333 333 333* 377* 378* 388 389* 389* 390 393 393 393* 463 465 482 487 492 501 505 509 509 509 509 509 509 520 527 528 529 529 529 532 532 536 536 537 537 540 542 547 547 547 551 557* 557 557 557 557 557 561 561 561 561 561 561 566 566 566 566 566 566 571 571 571 571 571 571 576 576 576 576 576 576 576 576 576 576 585 587 587 590 600 607 609 618 CU_synch 000103 automatic fixed bin(17,0) dcl 76 set ref 267* 269 269 269* 287* 292* 293* 318 320* 320* 325 327 327 333 333* 377 CY_print 000104 automatic char(1) unaligned dcl 76 set ref 527* 528* 531* 536* 537* 539* 540* 541* 544* 547* 549* 550* 557* DU 100 000152 automatic structure array level 2 packed unaligned dcl 119 set ref 184* DUOP 1(17) based bit(1) array level 2 packed unaligned dcl 1-159 ref 509 541 576 607 609 DU_ based structure array level 1 packed unaligned dcl 65 set ref 184 DU_index 000105 automatic fixed bin(17,0) dcl 76 set ref 369* 607* 607 611* 611 644 646 647 648 649 650 653* 653 653 653 657 657 657 657 657 657 657 663 663 663 663 663 663 663 663 663 670 670 670 670 670 670 670 670 676 676 676 676 676 676 676 676 676 683 683 683 683 683 683 683 683 689 689 689 689 689 689 689 695 695 695 695 695 695 695 DU_mode 000106 automatic char(1) unaligned dcl 76 set ref 646* 647* 648* 649* 650* 651* 653* EXP_DU_mode 000107 automatic char(4) unaligned dcl 76 set ref 808* 809* 810* 811* 812* 813* 815* IC_cur 000110 automatic fixed bin(18,0) initial dcl 76 set ref 76* 461 495 498* IC_flag 000111 automatic bit(1) unaligned dcl 76 set ref 368* 385* 468* 471 491 IC_next 000112 automatic fixed bin(18,0) initial dcl 76 set ref 76* 465 467 469* 532* IC_print 000114 automatic char(7) unaligned dcl 76 set ref 421* 424* 428* 473* 495* 497* 501 557* IC_synch 000116 automatic fixed bin(18,0) dcl 76 set ref 264* 281* 360 371 384 IC_value 000117 automatic fixed bin(18,0) dcl 76 set ref 366* 384* 395 422* 461 467* 471* 471 492* 492 494* 494 495 495* 498 LREG constant bit(9) initial unaligned dcl 1-7 ref 210 320 333 357 NOP constant bit(9) initial unaligned dcl 1-7 ref 542 NOP_flag 000120 automatic bit(1) initial unaligned dcl 76 set ref 76* 545* OP based structure array level 1 packed unaligned dcl 1-159 OP_cur 000121 automatic bit(10) initial unaligned dcl 76 set ref 76* 393 465 482 487 501 505* 506 541 542 542 576 607 609 OP_print 000122 automatic char(5) unaligned dcl 76 set ref 426* 427* 428* 501* 506* 557* OP_ptr 000620 automatic pointer dcl 1-5 set ref 285 327 393 426 506 509 541 542 576 607 609 776 776 916* OP_table 000120 constant char(48) initial array unaligned dcl 1-10 set ref 916 OU 000152 automatic structure array level 2 packed unaligned dcl 119 set ref 182* OUOP 1(16) based bit(1) array level 2 packed unaligned dcl 1-159 ref 327 393 OU_ based structure array level 1 packed unaligned dcl 57 set ref 182 OU_index 000124 automatic fixed bin(17,0) dcl 76 set ref 208* 210 210 210 210 210 210 210 210* 356* 357 357 357 357 359 359 360* 386* 400 400* 401 401 403* 403 421 421 422 426 428* 428 428 430 430 433 433 433 433 433 438 438 438 438 438 438 443 443 443 443 443 443 448 448 448 448 448 448 448 590 OU_synch 000125 automatic fixed bin(17,0) initial dcl 76 set ref 76* 265* 355 355* 395 395* 395* 398 398* 400 PTW_print 000126 automatic char(2) unaligned dcl 76 set ref 623* 624* 626* 874* 875* 882 882 SDW_print 000127 automatic char(2) unaligned dcl 76 set ref 621* 622* 626* 872* 873* 882 882 SEG_print 000130 automatic char(5) unaligned dcl 76 set ref 553* 555* 557* SREG constant bit(9) initial unaligned dcl 1-140 ref 210 320 333 357 STBA constant bit(9) initial unaligned dcl 1-140 ref 509 STBQ constant bit(9) initial unaligned dcl 1-140 ref 509 STCA constant bit(9) initial unaligned dcl 1-140 ref 509 STCQ constant bit(9) initial unaligned dcl 1-140 ref 509 TAG based structure array level 1 packed unaligned dcl 1-169 TAG_cur 000132 automatic fixed bin(17,0) dcl 76 set ref 516* 520* 521 524 524 TAG_print 000133 automatic char(4) unaligned dcl 76 set ref 517* 521* 557* TAG_ptr 000622 automatic pointer dcl 1-5 set ref 521 524 776 776 917* TAG_table 000000 constant char(40) initial array unaligned dcl 1-148 set ref 917 TR 1(12) based bit(1) array level 2 packed unaligned dcl 1-159 ref 285 542 XD1_flag 000134 automatic bit(1) initial unaligned dcl 76 set ref 76* 476 477* 487* 534* XD2_flag 000135 automatic bit(1) initial unaligned dcl 76 set ref 76* 481 482* 487* 534* XEC_flag 000136 automatic bit(1) initial unaligned dcl 76 set ref 76* 463 XED constant bit(9) initial unaligned dcl 1-140 ref 532 585 XED_flag 000137 automatic bit(1) initial unaligned dcl 76 set ref 76* 474 487* 534* 585* a_apuhra 000512 automatic structure array level 1 packed unaligned dcl 136 set ref 190* a_cuhra 000412 automatic structure array level 1 packed unaligned dcl 134 set ref 188* a_do_cu 000151 automatic bit(1) unaligned dcl 118 set ref 738* 741* 773 a_do_du 000150 automatic bit(1) unaligned dcl 118 set ref 739* 740* a_duhra 000452 automatic structure array level 1 packed unaligned dcl 135 set ref 189* a_iocbp parameter pointer dcl 33 ref 154 159 703 707 925 927 a_ouhra 000352 automatic structure array level 1 packed unaligned dcl 133 set ref 187* a_switches based structure level 1 packed unaligned dcl 50 addsub 1(29) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 695* addsub 1(29) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 854* adjlen 0(32) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 829 adjlen 0(32) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 670 an 1(05) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 443 an 1(05) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" ref 760 anpk 1(20) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 848* anpk 1(20) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 689* anstg 1(15) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 842* anstg 1(15) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 683* aoplg1 1(08) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 676* aoplg1 1(08) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 835* aoplg2 1(09) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 842* aoplg2 1(09) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 683* aphrp 000630 automatic pointer dcl 2-4 set ref 185 190 731 731 867 867 867 867 867 867 867 872 872 872 874 874 874 877 877 877 877 877 877 882 882 882 882 882 882 914* apuhra based structure array level 1 packed unaligned dcl 2-87 set ref 190 ar 0(14) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" ref 793 ar 0(14) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 571 587 au_offset 000637 automatic fixed bin(17,0) initial dcl 2-7 set ref 2-7* 908* 914 au_sync_mod_value 000552 automatic fixed bin(17,0) array dcl 138 set ref 196* 198* 371 371 590 590 bde 1(24) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 848* bde 1(24) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 689* blnk 1(22) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 689* blnk 1(22) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 848* bsy 0(15) based bit(2) array level 2 packed unaligned dcl 2-87 ref 867 867 867 867 ca_value 1 000412 automatic bit(18) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 237 532 551 557 557 590 ca_value 1 based bit(18) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 776* chain 1(08) based bit(1) array level 2 packed unaligned dcl 1-169 ref 524 charop 1(19) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 848* charop 1(19) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 689* cmod 0(13) based bit(1) array level 2 packed unaligned dcl 2-50 set ref 745* code based char(4) array level 2 in structure "TAG" packed unaligned dcl 1-169 in procedure "hran_l68_" ref 521 776 776 code 000615 automatic fixed bin(35,0) dcl 149 in procedure "hran_l68_" set ref 163* 166 711* 715 933* 945* code based char(5) array level 2 in structure "OP" packed unaligned dcl 1-159 in procedure "hran_l68_" ref 426 506 776 776 cu_offset 000635 automatic fixed bin(17,0) initial dcl 2-7 set ref 2-7* 906* 912 cuhra based structure array level 1 dcl 2-13 set ref 188 cuhrp 000626 automatic pointer dcl 2-4 set ref 183 188 722 722 776 776 776 776 776 776 776 776 776 776 776 783 783 783 783 783 783 788 788 788 788 788 788 793 793 793 793 793 793 798 798 798 798 798 798 798 798 798 798 798 807 912* cul 1(31) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 798* cul 1(31) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 537 576* cus 1(29) 000412 automatic bit(1) array level 2 packed unaligned dcl 134 set ref 576* dataav_du 1(12) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 683 dataav_du 1(12) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 842 dbe 1(25) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 854* dbe 1(25) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 695* dcldgta 1(01) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 835 dcldgta 1(01) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 676 dcldgtb 1(02) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 835 dcldgtb 1(02) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 676 dcldgtc 1(03) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 676 dcldgtc 1(03) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 835 dfrst 0(05) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 815 dfrst 0(05) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 657 dfsdw 0(19) 000512 automatic bit(1) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 630* dfsdw 0(19) based bit(1) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 877* dir 0(14) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 430 590 dir 1(33) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 798* dir 1(33) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 537 547 576* 600 dir 0(14) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 745* dlendr 0(04) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 657 dlendr 0(04) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 815 dn 1(04) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 760* dn 1(04) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 443* do_au 0(03) based bit(1) level 2 packed unaligned dcl 50 set ref 727 728* 864 do_cu 0(02) based bit(1) level 2 packed unaligned dcl 50 set ref 718 719* 722* 731* 738 740 do_du 0(04) based bit(1) level 2 packed unaligned dcl 50 set ref 727 728* 731* 739 741 do_ou 0(01) based bit(1) level 2 packed unaligned dcl 50 set ref 718 719* 722* 742 du_offset 000636 automatic fixed bin(17,0) initial dcl 2-7 set ref 2-7* 907* 913 du_wrd 0(21) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 808 du_wrd 0(21) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 646 duhra based structure array level 1 dcl 2-110 set ref 189 duhrp 000632 automatic pointer dcl 2-4 set ref 184 189 731 731 808 809 810 811 812 815 815 815 815 815 815 815 822 822 822 822 822 822 822 822 822 829 829 829 829 829 829 829 829 835 835 835 835 835 835 835 835 835 842 842 842 842 842 842 842 842 848 848 848 848 848 848 848 854 854 854 854 854 854 854 913* duidl 1 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 676* duidl 1 based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 835* dulea 0(08) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 822 dulea 0(08) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 663 durw 0(15) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 822 durw 0(15) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 663 dusea 0(09) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 663 dusea 0(09) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 822 efad 0(15) based bit(2) array level 2 packed unaligned dcl 2-50 ref 745 745 einst 0(14) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 663 einst 0(14) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 822 endseq_du 1(17) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 848 endseq_du 1(17) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 689 eseq 0(13) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 663* eseq 0(13) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 822* esn 000512 automatic bit(15) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 553 553 esn based bit(15) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 867* even 000152 automatic bit(36) array level 3 in structure "hr" packed unaligned dcl 119 in procedure "hran_l68_" set ref 210 210 428* even 40 000152 automatic bit(36) array level 3 in structure "hr" packed unaligned dcl 119 in procedure "hran_l68_" set ref 378 557* even based bit(36) array level 2 in structure "DU_" packed unaligned dcl 65 in procedure "hran_l68_" set ref 731* even 100 000152 automatic bit(36) array level 3 in structure "hr" packed unaligned dcl 119 in procedure "hran_l68_" set ref 644 653* even based bit(36) array level 2 in structure "OU_" packed unaligned dcl 57 in procedure "hran_l68_" set ref 722* even based bit(36) array level 2 in structure "AU_" packed unaligned dcl 69 in procedure "hran_l68_" set ref 731* even 140 000152 automatic bit(36) array level 3 in structure "hr" packed unaligned dcl 119 in procedure "hran_l68_" set ref 371 618 626* even based bit(36) array level 2 in structure "CU_" packed unaligned dcl 61 in procedure "hran_l68_" set ref 722* exh 0(12) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 663 exh 0(12) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 822 exmop 1(21) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 848* exmop 1(21) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 689* expand_sw based bit(1) level 2 packed unaligned dcl 50 ref 717 737 expon 1(31) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 854* expon 1(31) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 695* exr 0(06) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 815 exr 0(06) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 657 fai1 0(18) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 829* fai1 0(18) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 670* fai2 0(19) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 670* fai2 0(19) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 829* fai3 0(20) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 670* fai3 0(20) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 829* fanp 0(23) based bit(1) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 882* fanp 0(23) 000512 automatic bit(1) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 600 635* fap 0(24) 000512 automatic bit(1) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 196 600 635* fap 0(24) based bit(1) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 882* fdsptw 0(17) based bit(1) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 877* fdsptw 0(17) 000512 automatic bit(1) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 630* fetch_count 000144 automatic fixed bin(17,0) initial dcl 76 set ref 76* 229* 229 369 finadd 1 based bit(24) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 867* finadd 1 000512 automatic bit(24) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 371 590 626 626 flt 0(35) based bit(1) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 882* flt 1(27) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 854* flt 0(35) 000512 automatic bit(1) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 600 635* flt 1(27) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 695* flthld 1(34) 000512 automatic bit(1) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 635* flthld 1(34) based bit(1) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 882* four 0(24) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 649 four 0(24) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 811 fptw 0(20) based bit(1) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 877* fptw 0(20) 000512 automatic bit(1) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 630* fptw2 0(21) 000512 automatic bit(1) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 630* fptw2 0(21) based bit(1) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 877* from_bos 000616 automatic bit(1) initial unaligned dcl 150 set ref 150* 156* 161* 704* 709* 905 frpf 0(28) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 433* frpf 0(28) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 750* fstr 1(03) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 443* fstr 1(03) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 760* gd1 0(32) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 755* gd1 0(32) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 438* gd2 0(33) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 755* gd2 0(33) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 438* get_line_length_$switch 000010 constant entry external dcl 41 ref 929 gin 0(30) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 750* gin 0(30) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 433* goa 0(35) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 438* goa 0(35) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 755* goe 0(34) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 438* goe 0(34) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 755* gof 1(02) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 443* gof 1(02) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 760* gom 1 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 438* gom 1 based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 755* gon 1(01) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 755* gon 1(01) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 438* gos 0(31) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 433* gos 0(31) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 750* hr 000152 automatic structure level 1 packed unaligned dcl 119 hr_block based bit(4608) unaligned dcl 148 ref 943 hr_data_ptr parameter pointer dcl 2-4 ref 154 159 703 707 911 912 913 914 931 943 i 000147 automatic fixed bin(17,0) dcl 117 set ref 721* 722* 722 722 722 722* 730* 731* 731 731 731 731* 744* 745* 745 745 745 745 745 745 745 745 745 750 750 750 750 750 755 755 755 755 755 755 760 760 760 760 760 760 765 765 765 765 765 765 765* 775* 776* 776 776 776 776 776 776 776 776 776 776 776 783 783 783 783 783 783 788 788 788 788 788 788 793 793 793 793 793 793 798 798 798 798 798 798 798 798 798 798 798 807 808 809 810 811 812 815* 815 815 815 815 815 815 815 822 822 822 822 822 822 822 822 822 829 829 829 829 829 829 829 829 835 835 835 835 835 835 835 835 835 842 842 842 842 842 842 842 842 848 848 848 848 848 848 848 854 854 854 854 854 854 854* 866* 867* 867 867 867 867 867 867 867 872 872 872 874 874 874 877 877 877 877 877 877 882 882 882 882 882 882* ic 0(11) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 292 293 492 566* ic 0(11) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 788* ict 1(18) 000352 automatic bit(18) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 210 210 210* 210 264 357 357 359* 359 360 395 421 421 422 ict 1(18) based bit(18) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 745* index 000572 automatic fixed bin(17,0) initial array level 2 packed unaligned dcl 140 set ref 140* 235* 278* 280 inhib 0(28) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 798* inhib 0(28) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 576* inhibstc1 0(34) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 670 inhibstc1 0(34) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 829 ins_fetch 1(28) 000412 automatic bit(1) array level 2 packed unaligned dcl 134 set ref 228 529 607 609 ioa_$ioa_switch 000012 constant entry external dcl 43 ref 171 172 415 719 722 728 731 771 862 888 932 944 ioa_$ioa_switch_nnl 000014 constant entry external dcl 43 ref 174 428 430 432 433 438 443 448 557 561 566 571 576 626 630 635 653 657 663 670 676 683 689 695 743 745 750 755 760 765 774 776 783 788 793 798 815 822 829 835 842 848 854 865 867 877 882 ioa_$rsnnl 000016 constant entry external dcl 43 ref 421 495 553 621 623 872 874 iocbp 000142 automatic pointer dcl 76 set ref 171* 172* 174* 415* 428* 430* 432* 433* 438* 443* 448* 557* 561* 566* 571* 576* 626* 630* 635* 653* 657* 663* 670* 676* 683* 689* 695* 719* 722* 728* 731* 743* 745* 750* 755* 760* 765* 771* 774* 776* 783* 788* 793* 798* 815* 822* 829* 835* 842* 848* 854* 862* 865* 867* 877* 882* 888* 925* 927* 932* 944* iox_$user_output 000020 external static pointer dcl 43 ref 925 its_flag 0(29) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" ref 798 its_flag 0(29) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 576 itw 0(09) based bit(1) array level 2 packed unaligned dcl 2-50 set ref 745* ldfrst 0(07) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 822 ldfrst 0(07) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 663 len128 1(18) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 848 len128 1(18) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 689 ll_sw 000140 automatic bit(1) unaligned dcl 76 set ref 174 428 557 626 653 929* lo_sw parameter bit(1) unaligned dcl 34 set ref 154 159 172* 174* 174 428* 428 557* 557 626* 626 653* 653 lrwrg1 1(10) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 683* lrwrg1 1(10) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 842* lrwrg2 1(11) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 683* lrwrg2 1(11) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 842* mdsptw 0(18) based bit(1) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 877* mdsptw 0(18) 000512 automatic bit(1) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 630* mif 0(33) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 670 mif 0(33) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 829 mptw 0(22) based bit(1) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 877* mptw 0(22) 000512 automatic bit(1) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 630* multdiv 1(30) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 854* multdiv 1(30) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 695* ndesc 0(02) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 657 ndesc 0(02) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 815 nflt 0(16) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 232 282 390 527 571 618 nflt 0(16) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" ref 793 nine 0(22) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 647 nine 0(22) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 809 nopc based bit(9) array level 2 packed unaligned dcl 2-50 set ref 745* nopgl1 1(05) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 835* nopgl1 1(05) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 676* nopgl2 1(07) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 835* nopgl2 1(07) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 676* nopl1 1(04) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 835* nopl1 1(04) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 676* nopl2 1(06) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 835* nopl2 1(06) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 676* np 0(17) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" ref 793 np 0(17) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 571 npcb 1(34) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 798* npcb 1(34) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 576* ntg 0(10) based bit(3) array level 2 packed unaligned dcl 2-50 set ref 745* null builtin function dcl 76 ref 925 929 929 931 numstg 1(14) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 683* numstg 1(14) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 842* nxip 0(15) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" ref 793 nxip 0(15) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 528 571 odd 101 000152 automatic bit(36) array level 3 in structure "hr" packed unaligned dcl 119 in procedure "hran_l68_" set ref 653* odd 1 based bit(36) array level 2 in structure "CU_" packed unaligned dcl 61 in procedure "hran_l68_" set ref 722* odd 1 based bit(36) array level 2 in structure "OU_" packed unaligned dcl 57 in procedure "hran_l68_" set ref 722* odd 1 based bit(36) array level 2 in structure "AU_" packed unaligned dcl 69 in procedure "hran_l68_" set ref 731* odd 41 000152 automatic bit(36) array level 3 in structure "hr" packed unaligned dcl 119 in procedure "hran_l68_" set ref 557* odd 1 based bit(36) array level 2 in structure "DU_" packed unaligned dcl 65 in procedure "hran_l68_" set ref 731* odd 141 000152 automatic bit(36) array level 3 in structure "hr" packed unaligned dcl 119 in procedure "hran_l68_" set ref 626* odd 1 000152 automatic bit(36) array level 3 in structure "hr" packed unaligned dcl 119 in procedure "hran_l68_" set ref 428* one 0(25) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 650 one 0(25) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 812 op_code 0(18) 000412 automatic bit(10) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 269 285 320 320 320 320 327 333 333 333 333 465 482 487 501 505 509 509 509 509 509 532 585 op_code 0(18) based bit(10) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" ref 776 776 798 807 opav 1(16) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 683* opav 1(16) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 842* opbf 0(27) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 750* opbf 0(27) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 433* ou_offset 000634 automatic fixed bin(17,0) initial dcl 2-7 set ref 2-7* 911 ouhra based structure array level 1 dcl 2-50 set ref 187 ouhrp 000624 automatic pointer dcl 2-4 set ref 182 187 722 722 745 745 745 745 745 745 745 745 745 750 750 750 750 750 755 755 755 755 755 755 760 760 760 760 760 760 765 765 765 765 765 765 765 911* oul 1(32) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 798* oul 1(32) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 269 393 547 576* ous 1(30) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 269 393 540 547 576* ous 1(30) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 798* 798* pcmd 1(18) 000412 automatic bit(5) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 557 pcmd 1(18) based bit(5) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" ref 776 pia based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 783* pia 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 232 333 529 561* 587 pib 1(35) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 798* pib 1(35) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 576* poa 0(01) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 561* poa 0(01) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 783* pol based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 815 pol 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 657 pon 0(05) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 561* pon 0(05) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 783* pop 0(01) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 815 pop 0(01) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 657 pot 0(04) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 561* pot 0(04) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 783* psl 1(23) based bit(4) array level 2 packed unaligned dcl 2-13 ref 776 776 776 776 776 pt_addr 0(18) 000572 automatic bit(18) initial array level 2 packed unaligned dcl 140 set ref 140* 237* 281 551 ptra 0(16) 000452 automatic bit(2) array level 2 packed unaligned dcl 135 set ref 653 ptwamr 0(31) based bit(4) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" ref 874 874 ptwamr 0(31) 000512 automatic bit(4) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 623 623 ptwmf 0(30) 000512 automatic bit(1) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 623 635* ptwmf 0(30) based bit(1) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 874 882* pull_count 000145 automatic fixed bin(17,0) initial dcl 76 set ref 76* 235 237 238* 238 260 278 279 pull_index 000146 automatic fixed bin(17,0) dcl 76 set ref 279* 280 281* pull_table 000572 automatic structure array level 1 packed unaligned dcl 140 qn 1(06) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 443 qn 1(06) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" ref 760 raw 0(06) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 788* raw 0(06) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 566* redo 0(10) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 822 redo 0(10) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 663 repeat_count 000612 automatic fixed bin(17,0) initial dcl 144 set ref 144* riw 0(02) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 783* riw 0(02) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 333 536 561* rnd 1(28) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 854* rnd 1(28) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 695* rp 0(18) based bit(9) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 745* rp 0(18) 000352 automatic bit(9) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 210 210 269 357 357 426 rpts 0(12) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 333 463 509 571* rpts 0(12) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 793* rw1rl 1(13) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 842* rw1rl 1(13) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 683* samplint 0(30) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 670* samplint 0(30) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 829* saw 0(07) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 788* saw 0(07) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 393 566* sdwamr 0(26) 000512 automatic bit(4) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 621 621 sdwamr 0(26) based bit(4) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" ref 872 872 sdwmf 0(25) 000512 automatic bit(1) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 621 635* sdwmf 0(25) based bit(1) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 872 882* seladr 0(03) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 657 seladr 0(03) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 815 sfcsq 0(31) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 670 sfcsq 0(31) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 829 shft 1(26) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" set ref 854* shft 1(26) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 695* siw 0(03) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 333 536 561* siw 0(03) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 783* six 0(23) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 810 six 0(23) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 648 srf 0(29) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 433* srf 0(29) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" set ref 750* switches parameter bit(5) unaligned dcl 35 set ref 703 707 717 718 718 719 719 722 722 727 727 728 728 731 731 737 738 739 740 741 742 864 synch_flag 000613 automatic bit(1) unaligned dcl 144 set ref 367* 387* 420 426 tag 0(30) based bit(6) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" ref 776 776 tag 0(30) 000412 automatic bit(6) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 430 520 tag_chain_flag 000614 automatic bit(1) unaligned dcl 144 set ref 368* 524* trgo 0(08) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 232 285 542 566* trgo 0(08) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 788* trr 1(24) based bit(3) array level 2 in structure "apuhra" packed unaligned dcl 2-87 in procedure "hran_l68_" set ref 867* trr 1(24) 000512 automatic bit(3) array level 2 in structure "a_apuhra" packed unaligned dcl 136 in procedure "hran_l68_" set ref 626 626 wcws 0(11) 000452 automatic bit(1) array level 2 in structure "a_duhra" packed unaligned dcl 135 in procedure "hran_l68_" set ref 663 wcws 0(11) based bit(1) array level 2 in structure "duhra" packed unaligned dcl 2-110 in procedure "hran_l68_" ref 822 wi 0(13) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 793* wi 0(13) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 333 529 571* x0n 1(07) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" ref 760 x0n 1(07) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 443 x1n 1(08) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" ref 765 x1n 1(08) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 448 x2n 1(09) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 448 x2n 1(09) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" ref 765 x3n 1(10) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" ref 765 x3n 1(10) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 448 x4n 1(11) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" ref 765 x4n 1(11) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 448 x5n 1(12) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 448 x5n 1(12) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" ref 765 x6n 1(13) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 448 x6n 1(13) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" ref 765 x7n 1(14) based bit(1) array level 2 in structure "ouhra" packed unaligned dcl 2-50 in procedure "hran_l68_" ref 765 x7n 1(14) 000352 automatic bit(1) array level 2 in structure "a_ouhra" packed unaligned dcl 133 in procedure "hran_l68_" set ref 448 xde 0(09) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 788* xde 0(09) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 566* xdo 0(10) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 788* xdo 0(10) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 566* xint 1(27) based bit(1) array level 2 in structure "cuhra" packed unaligned dcl 2-13 in procedure "hran_l68_" set ref 798* xint 1(27) 000412 automatic bit(1) array level 2 in structure "a_cuhra" packed unaligned dcl 134 in procedure "hran_l68_" set ref 576* NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. AU_ptr automatic pointer dcl 76 CU_ptr automatic pointer dcl 76 DU_ptr automatic pointer dcl 76 OU_ptr automatic pointer dcl 76 XEC internal static bit(9) initial unaligned dcl 1-140 count_diff automatic fixed bin(17,0) dcl 76 index automatic fixed bin(17,0) dcl 76 ioa_ 000000 constant entry external dcl 43 j automatic fixed bin(17,0) dcl 117 repull_count automatic fixed bin(17,0) dcl 144 NAMES DECLARED BY EXPLICIT CONTEXT. HRG01C 005665 constant label dcl 267 ref 314 HRG02A 006021 constant label dcl 296 HRG02F 006023 constant label dcl 314 ref 282 HRG05C 006024 constant label dcl 318 ref 269 273 288 293 360 HRG05H 006160 constant label dcl 355 HRG06 006240 constant label dcl 366 set ref 325 346 HRG08 006313 constant label dcl 384 HRG09 006427 constant label dcl 409 ref 388 START 004305 constant label dcl 163 ref 157 START_NO_THREAD 006476 constant label dcl 711 ref 705 aur 014500 constant entry internal dcl 616 ref 598 bos_no_thread 006454 constant entry external dcl 703 cur 013076 constant entry internal dcl 456 ref 378 392 409 cur02 013111 constant label dcl 465 ref 461 cur03 013241 constant label dcl 501 ref 463 478 484 cur04 013302 constant label dcl 509 cur05 014417 constant label dcl 598 set ref 600 do_fault_cycle 006427 constant label dcl 409 ref 390 dur 015076 constant entry internal dcl 642 ref 610 hran_l68_ 004250 constant entry external dcl 28 hranl_l68_ 004276 constant entry external dcl 159 hranl_l68_bos 004263 constant entry external dcl 154 no_thread 006467 constant entry external dcl 707 our 012272 constant entry internal dcl 418 ref 402 setup 016214 constant entry internal dcl 896 ref 165 714 NAMES DECLARED BY CONTEXT OR IMPLICATION. add builtin function ref 210 359 addr builtin function ref 717 718 718 719 719 722 722 727 727 728 728 731 731 737 738 739 740 741 742 864 916 917 addrel builtin function ref 911 912 913 914 bit builtin function ref 210 359 divide builtin function ref 492 494 fixed builtin function ref 210 264 281 285 327 359 360 371 393 395 421 421 422 426 506 509 520 532 541 542 553 553 557 557 557 576 590 590 607 609 621 621 623 623 626 626 626 626 653 776 776 776 776 872 872 874 874 ltrim builtin function ref 776 776 776 776 882 882 882 882 mod builtin function ref 371 371 590 590 rtrim builtin function ref 776 776 776 776 882 882 882 882 substr builtin function ref 430 798 807 STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 16536 16560 16412 16546 Length 17042 16412 22 245 124 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME hran_l68_ 1002 external procedure is an external procedure. our internal procedure shares stack frame of external procedure hran_l68_. cur internal procedure shares stack frame of external procedure hran_l68_. aur internal procedure shares stack frame of external procedure hran_l68_. dur internal procedure shares stack frame of external procedure hran_l68_. setup internal procedure shares stack frame of external procedure hran_l68_. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME hran_l68_ 000100 AU_index hran_l68_ 000101 AU_synch hran_l68_ 000102 CU_index hran_l68_ 000103 CU_synch hran_l68_ 000104 CY_print hran_l68_ 000105 DU_index hran_l68_ 000106 DU_mode hran_l68_ 000107 EXP_DU_mode hran_l68_ 000110 IC_cur hran_l68_ 000111 IC_flag hran_l68_ 000112 IC_next hran_l68_ 000114 IC_print hran_l68_ 000116 IC_synch hran_l68_ 000117 IC_value hran_l68_ 000120 NOP_flag hran_l68_ 000121 OP_cur hran_l68_ 000122 OP_print hran_l68_ 000124 OU_index hran_l68_ 000125 OU_synch hran_l68_ 000126 PTW_print hran_l68_ 000127 SDW_print hran_l68_ 000130 SEG_print hran_l68_ 000132 TAG_cur hran_l68_ 000133 TAG_print hran_l68_ 000134 XD1_flag hran_l68_ 000135 XD2_flag hran_l68_ 000136 XEC_flag hran_l68_ 000137 XED_flag hran_l68_ 000140 ll_sw hran_l68_ 000142 iocbp hran_l68_ 000144 fetch_count hran_l68_ 000145 pull_count hran_l68_ 000146 pull_index hran_l68_ 000147 i hran_l68_ 000150 a_do_du hran_l68_ 000151 a_do_cu hran_l68_ 000152 hr hran_l68_ 000352 a_ouhra hran_l68_ 000412 a_cuhra hran_l68_ 000452 a_duhra hran_l68_ 000512 a_apuhra hran_l68_ 000552 au_sync_mod_value hran_l68_ 000572 pull_table hran_l68_ 000612 repeat_count hran_l68_ 000613 synch_flag hran_l68_ 000614 tag_chain_flag hran_l68_ 000615 code hran_l68_ 000616 from_bos hran_l68_ 000620 OP_ptr hran_l68_ 000622 TAG_ptr hran_l68_ 000624 ouhrp hran_l68_ 000626 cuhrp hran_l68_ 000630 aphrp hran_l68_ 000632 duhrp hran_l68_ 000634 ou_offset hran_l68_ 000635 cu_offset hran_l68_ 000636 du_offset hran_l68_ 000637 au_offset hran_l68_ THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. r_e_as r_ne_as r_le_a alloc_cs cat_realloc_cs call_ext_out_desc call_ext_out return mpfx2 mod_fx1 mod_fx3 shorten_stack ext_entry THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. get_line_length_$switch ioa_$ioa_switch ioa_$ioa_switch_nnl ioa_$rsnnl THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. iox_$user_output LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 76 004171 140 004204 144 004234 150 004235 2 7 004236 28 004247 154 004256 156 004271 157 004273 159 004274 161 004304 163 004305 165 004306 166 004307 171 004311 172 004331 174 004361 182 004421 183 004426 184 004432 185 004436 187 004442 188 004660 189 005077 190 005515 195 005522 196 005527 198 005537 200 005542 208 005544 210 005551 219 005614 225 005616 228 005623 229 005630 232 005631 235 005637 237 005644 238 005653 241 005654 260 005656 264 005660 265 005663 267 005665 269 005673 272 005712 273 005715 278 005716 279 005721 280 005727 281 005735 282 005741 285 005746 287 005774 288 005777 292 006000 293 006011 294 006015 295 006017 296 006021 314 006023 318 006024 320 006026 323 006062 325 006064 327 006067 330 006117 333 006120 345 006154 346 006157 355 006160 356 006164 357 006171 359 006216 360 006227 362 006236 366 006240 367 006241 368 006242 369 006244 370 006247 371 006250 376 006273 377 006275 378 006305 380 006311 384 006313 385 006315 386 006317 387 006320 388 006321 389 006324 390 006331 392 006335 393 006336 395 006370 397 006404 398 006406 400 006413 401 006417 402 006423 403 006424 406 006425 409 006427 415 006430 416 006447 703 006450 704 006462 705 006464 707 006465 709 006475 711 006476 714 006477 715 006500 717 006502 718 006511 719 006523 721 006556 722 006563 724 006645 727 006650 728 006663 730 006716 731 006723 733 007005 735 007010 737 007011 738 007013 739 007020 740 007024 741 007033 742 007041 743 007045 744 007065 745 007073 750 007207 755 007265 760 007344 765 007437 770 007552 771 007555 773 007574 774 007576 775 007616 776 007623 783 010072 788 010154 793 010235 798 010333 807 010447 808 010456 809 010465 810 010473 811 010501 812 010507 813 010515 815 010517 822 010637 829 010773 835 011103 842 011213 848 011312 854 011407 861 011475 862 011500 864 011517 865 011525 866 011546 867 011553 872 011662 873 011734 874 011736 875 012004 877 012006 882 012067 887 012246 888 012252 957 012271 418 012272 420 012273 421 012277 422 012335 423 012342 424 012343 426 012346 427 012373 428 012376 430 012463 432 012513 433 012532 438 012606 443 012665 448 012761 453 013075 456 013076 461 013077 463 013102 465 013111 467 013124 468 013125 469 013127 470 013130 471 013131 473 013134 474 013136 476 013140 477 013142 478 013144 481 013145 482 013147 484 013154 487 013155 491 013163 492 013165 494 013177 495 013203 498 013237 501 013241 505 013267 506 013271 509 013302 516 013337 517 013340 518 013342 520 013343 521 013347 524 013354 527 013365 528 013374 529 013402 531 013410 532 013412 534 013420 535 013423 536 013424 537 013432 539 013443 540 013446 541 013456 542 013501 544 013514 545 013516 546 013520 547 013521 549 013534 550 013537 551 013541 553 013554 555 013617 557 013622 561 013743 566 014022 571 014103 576 014202 585 014336 587 014350 590 014355 594 014411 596 014413 598 014417 599 014420 600 014421 607 014437 609 014466 610 014475 611 014476 613 014477 616 014500 618 014501 621 014514 622 014556 623 014560 624 014625 626 014627 630 014733 635 015014 639 015075 642 015076 644 015077 646 015105 647 015113 648 015121 649 015127 650 015135 651 015143 653 015145 657 015240 663 015353 670 015505 676 015616 683 015727 689 016027 695 016125 700 016213 896 016214 905 016215 906 016217 907 016221 908 016223 911 016225 912 016233 913 016240 914 016245 916 016252 917 016254 925 016256 927 016267 929 016272 931 016314 932 016321 933 016341 934 016343 943 016344 944 016353 945 016373 946 016375 948 016376 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved