COMPILATION LISTING OF SEGMENT gcos_mme_time_ Compiled by: Multics PL/I Compiler, Release 28b, of April 11, 1983 Compiled at: Honeywell LCPD Phoenix, System M Compiled on: 09/09/83 1156.5 mst Fri Options: optimize map 1 /* *********************************************************** 2* * * 3* * Copyright, (C) Honeywell Information Systems Inc., 1982 * 4* * * 5* *********************************************************** */ 6 gcos_mme_time_: proc (mcp, increment); 7 8 /* ***************************************************************************************** 9* ******************************************************************************************* 10* * 11* * 12* * M M E G E T I M E 13* * 14* * 15* * MME GETIME provides the requesting program with the date and time of day. Results 16* * are returned in the following manner: 17* * 18* * C(A) 0-11 month (BCD digits) 19* * C(A) 12-23 day (BCD) 20* * C(A) 24-35 year (BCD) 21* * 22* * C(Q) 0-35 time of day (1/64 milliseconds past midnight) 23* * 24* * Author: DICK SNYDER NOVEMBER 10,1970 25* * Change: T. CASEY SEPTEMBER 1973 TO RETURN LOCAL TIME INSTEAD OF E.S.T. 26* * Change: Dave Ward 05/29/81 appropiate FP precision. 27* * 28* ******************************************************************************************* 29* ***************************************************************************************** */ 30 increment = 0; /* no param words to skip */ 31 time = clock (); /* get current time */ 32 33 call date_time_ (time, date_time); /* get ascii date and time */ 34 35 36 /* Build string of ascii date with out the slashes and convert to bcd */ 37 38 substr (temp, 1, 2) = substr (date_time, 1, 2); /* get month */ 39 substr (temp, 3, 2) = substr (date_time, 4, 2); /* get day */ 40 substr (temp, 5, 2) = substr (date_time, 7, 2); /* get year */ 41 42 call gcos_cv_ascii_gebcd_ (addr (temp), 6, addr (mc.regs.a), 6); /* put bcd in user's a reg */ 43 44 call decode_clock_value_ (time, m, d, y, i, w, z); /* just to get time since midnight local time, 45* in microseconds, into i */ 46 47 i = divide (i, 1000, 71, 0); /* convert to msecs */ 48 addr (mc.regs.q) -> mc64ths = i*64; /* convert to 64ths of a msec */ 49 return; 50 51 /* Variables for gcos_mme_time_: */ 52 /* IDENTIFIER ATTRIBUTES */ 53 dcl clock builtin; 54 dcl d fixed bin(24); 55 dcl date_time char (24) /* ascii date and time */; 56 dcl date_time_ ext entry (fixed bin(71), char (*)); 57 dcl decode_clock_value_ entry (fixed bin(71), fixed bin(24), fixed bin(24), fixed bin(24), fixed bin(71), fixed bin(24), char(3)); 58 dcl gcos_cv_ascii_gebcd_ ext entry (pointer, fixed bin(24), pointer, fixed bin); 59 dcl i fixed bin(71) /* temp */; 60 dcl increment fixed bin(24)/* no of param words to skip */; 61 dcl m fixed bin(24); 62 dcl mc64ths fixed bin(35)based; 63 dcl temp char (6) aligned /* temp */; 64 dcl time fixed bin(71) /* time in microseconds */; 65 dcl w fixed bin(24); 66 dcl y fixed bin(24); 67 dcl z char (3); 68 1 1 /* */ 1 2 /* BEGIN INCLUDE FILE mc.incl.pl1 Created Dec 72 for 6180 - WSS. */ 1 3 /* Modified 06/07/76 by Greenberg for mc.resignal */ 1 4 /* Modified 07/07/76 by Morris for fault register data */ 1 5 /* Modified 08/28/80 by J. A. Bush for the DPS8/70M CVPU */ 1 6 /* Modified '82 to make values constant */ 1 7 1 8 /* words 0-15 pointer registers */ 1 9 1 10 dcl mcp ptr; 1 11 1 12 dcl 1 mc based (mcp) aligned, 1 13 2 prs (0:7) ptr, /* POINTER REGISTERS */ 1 14 (2 regs, /* registers */ 1 15 3 x (0:7) bit (18), /* index registers */ 1 16 3 a bit (36), /* accumulator */ 1 17 3 q bit (36), /* q-register */ 1 18 3 e bit (8), /* exponent */ 1 19 3 pad1 bit (28), 1 20 3 t bit (27), /* timer register */ 1 21 3 pad2 bit (6), 1 22 3 ralr bit (3), /* ring alarm register */ 1 23 1 24 2 scu (0:7) bit (36), 1 25 1 26 2 mask bit (72), /* mem controller mask at time of fault */ 1 27 2 ips_temp bit (36), /* Temporary storage for IPS info */ 1 28 2 errcode fixed bin (35), /* fault handler's error code */ 1 29 2 fim_temp, 1 30 3 unique_index bit (18) unal, /* unique index for restarting faults */ 1 31 3 resignal bit (1) unal, /* recompute signal name with fcode below */ 1 32 3 fcode bit (17) unal, /* fault code used as index to FIM table and SCT */ 1 33 2 fault_reg bit (36), /* fault register */ 1 34 2 pad2 bit (1), 1 35 2 cpu_type fixed bin (2) unsigned, /* L68 = 0, DPS8/70M = 1 */ 1 36 2 ext_fault_reg bit (15), /* extended fault reg for DPS8/70M CPU */ 1 37 2 fault_time bit (54), /* time of fault */ 1 38 1 39 2 eis_info (0:7) bit (36)) unaligned; 1 40 1 41 1 42 dcl (apx fixed bin init (0), 1 43 abx fixed bin init (1), 1 44 bpx fixed bin init (2), 1 45 bbx fixed bin init (3), 1 46 lpx fixed bin init (4), 1 47 lbx fixed bin init (5), 1 48 spx fixed bin init (6), 1 49 sbx fixed bin init (7)) internal static options (constant); 1 50 1 51 1 52 1 53 1 54 dcl scup ptr; 1 55 1 56 dcl 1 scu based (scup) aligned, /* SCU DATA */ 1 57 1 58 1 59 /* WORD (0) */ 1 60 1 61 (2 ppr, /* PROCEDURE POINTER REGISTER */ 1 62 3 prr bit (3), /* procedure ring register */ 1 63 3 psr bit (15), /* procedure segment register */ 1 64 3 p bit (1), /* procedure privileged bit */ 1 65 1 66 2 apu, /* APPENDING UNIT STATUS */ 1 67 3 xsf bit (1), /* ext seg flag - IT modification */ 1 68 3 sdwm bit (1), /* match in SDW Ass. Mem. */ 1 69 3 sd_on bit (1), /* SDW Ass. Mem. ON */ 1 70 3 ptwm bit (1), /* match in PTW Ass. Mem. */ 1 71 3 pt_on bit (1), /* PTW Ass. Mem. ON */ 1 72 3 pi_ap bit (1), /* Instr Fetch or Append cycle */ 1 73 3 dsptw bit (1), /* Fetch of DSPTW */ 1 74 3 sdwnp bit (1), /* Fetch of SDW non paged */ 1 75 3 sdwp bit (1), /* Fetch of SDW paged */ 1 76 3 ptw bit (1), /* Fetch of PTW */ 1 77 3 ptw2 bit (1), /* Fetch of pre-paged PTW */ 1 78 3 fap bit (1), /* Fetch of final address paged */ 1 79 3 fanp bit (1), /* Fetch of final address non-paged */ 1 80 3 fabs bit (1), /* Fetch of final address absolute */ 1 81 1 82 2 fault_cntr bit (3), /* number of retrys of EIS instructions */ 1 83 1 84 1 85 /* WORD (1) */ 1 86 1 87 2 fd, /* FAULT DATA */ 1 88 3 iro bit (1), /* illegal ring order */ 1 89 3 oeb bit (1), /* out of execute bracket */ 1 90 3 e_off bit (1), /* no execute */ 1 91 3 orb bit (1), /* out of read bracket */ 1 92 3 r_off bit (1), /* no read */ 1 93 3 owb bit (1), /* out of write bracket */ 1 94 3 w_off bit (1), /* no write */ 1 95 3 no_ga bit (1), /* not a gate */ 1 96 3 ocb bit (1), /* out of call bracket */ 1 97 3 ocall bit (1), /* outward call */ 1 98 3 boc bit (1), /* bad outward call */ 1 99 3 inret bit (1), /* inward return */ 1 100 3 crt bit (1), /* cross ring transfer */ 1 101 3 ralr bit (1), /* ring alarm register */ 1 102 3 am_er bit (1), /* associative memory fault */ 1 103 3 oosb bit (1), /* out of segment bounds */ 1 104 3 paru bit (1), /* processor parity upper */ 1 105 3 parl bit (1), /* processor parity lower */ 1 106 3 onc_1 bit (1), /* op not complete type 1 */ 1 107 3 onc_2 bit (1), /* op not complete type 2 */ 1 108 1 109 2 port_stat, /* PORT STATUS */ 1 110 3 ial bit (4), /* illegal action lines */ 1 111 3 iac bit (3), /* illegal action channel */ 1 112 3 con_chan bit (3), /* connect channel */ 1 113 1 114 2 fi_num bit (5), /* (fault/interrupt) number */ 1 115 2 fi_flag bit (1), /* 1 => fault, 0 => interrupt */ 1 116 1 117 1 118 /* WORD (2) */ 1 119 1 120 2 tpr, /* TEMPORARY POINTER REGISTER */ 1 121 3 trr bit (3), /* temporary ring register */ 1 122 3 tsr bit (15), /* temporary segment register */ 1 123 1 124 2 pad2 bit (9), 1 125 1 126 2 cpu_no bit (3), /* CPU number */ 1 127 1 128 2 delta bit (6), /* tally modification DELTA */ 1 129 1 130 1 131 /* WORD (3) */ 1 132 1 133 2 word3 bit (18), 1 134 1 135 2 tsr_stat, /* TSR STATUS for 1,2,&3 word instructions */ 1 136 3 tsna, /* Word 1 status */ 1 137 4 prn bit (3), /* Word 1 PR number */ 1 138 4 prv bit (1), /* Word 1 PR valid bit */ 1 139 3 tsnb, /* Word 2 status */ 1 140 4 prn bit (3), /* Word 2 PR number */ 1 141 4 prv bit (1), /* Word 2 PR valid bit */ 1 142 3 tsnc, /* Word 3 status */ 1 143 4 prn bit (3), /* Word 3 PR number */ 1 144 4 prv bit (1), /* Word 3 PR valid bit */ 1 145 1 146 2 tpr_tbr bit (6), /* TPR.TBR field */ 1 147 1 148 1 149 /* WORD (4) */ 1 150 1 151 2 ilc bit (18), /* INSTRUCTION COUNTER */ 1 152 1 153 2 ir, /* INDICATOR REGISTERS */ 1 154 3 zero bit (1), /* zero indicator */ 1 155 3 neg bit (1), /* negative indicator */ 1 156 3 carry bit (1), /* carryry indicator */ 1 157 3 ovfl bit (1), /* overflow indicator */ 1 158 3 eovf bit (1), /* eponent overflow */ 1 159 3 eufl bit (1), /* exponent underflow */ 1 160 3 oflm bit (1), /* overflow mask */ 1 161 3 tro bit (1), /* tally runout */ 1 162 3 par bit (1), /* parity error */ 1 163 3 parm bit (1), /* parity mask */ 1 164 3 bm bit (1), /* ^bar mode */ 1 165 3 tru bit (1), /* truncation mode */ 1 166 3 mif bit (1), /* multi-word instruction mode */ 1 167 3 abs bit (1), /* absolute mode */ 1 168 3 pad bit (4), 1 169 1 170 1 171 /* WORD (5) */ 1 172 1 173 2 ca bit (18), /* COMPUTED ADDRESS */ 1 174 1 175 2 cu, /* CONTROL UNIT STATUS */ 1 176 3 rf bit (1), /* on first cycle of repeat instr */ 1 177 3 rpt bit (1), /* repeat instruction */ 1 178 3 rd bit (1), /* repeat double instruction */ 1 179 3 rl bit (1), /* repeat link instruciton */ 1 180 3 pot bit (1), /* IT modification */ 1 181 3 pon bit (1), /* return type instruction */ 1 182 3 xde bit (1), /* XDE from Even location */ 1 183 3 xdo bit (1), /* XDE from Odd location */ 1 184 3 poa bit (1), /* operation preparation */ 1 185 3 rfi bit (1), /* tells CPU to refetch instruction */ 1 186 3 its bit (1), /* ITS modification */ 1 187 3 if bit (1), /* fault occured during instruction fetch */ 1 188 1 189 2 cpu_tag bit (6)) unaligned, /* computed tag field */ 1 190 1 191 1 192 /* WORDS (6,7) */ 1 193 1 194 2 even_inst bit (36), /* even instruction of faulting pair */ 1 195 1 196 2 odd_inst bit (36); /* odd instruction of faulting pair */ 1 197 1 198 1 199 1 200 1 201 1 202 1 203 /* ALTERNATE SCU DECLARATION */ 1 204 1 205 1 206 dcl 1 scux based (scup) aligned, 1 207 1 208 (2 pad0 bit (36), 1 209 1 210 2 fd, /* GROUP II FAULT DATA */ 1 211 3 isn bit (1), /* illegal segment number */ 1 212 3 ioc bit (1), /* illegal op code */ 1 213 3 ia_am bit (1), /* illegal address - modifier */ 1 214 3 isp bit (1), /* illegal slave procedure */ 1 215 3 ipr bit (1), /* illegal procedure */ 1 216 3 nea bit (1), /* non existent address */ 1 217 3 oobb bit (1), /* out of bounds */ 1 218 3 pad bit (29), 1 219 1 220 2 pad2 bit (36), 1 221 1 222 2 pad3a bit (18), 1 223 1 224 2 tsr_stat (0:2), /* TSR STATUS as an ARRAY */ 1 225 3 prn bit (3), /* PR number */ 1 226 3 prv bit (1), /* PR valid bit */ 1 227 1 228 2 pad3b bit (6)) unaligned, 1 229 1 230 2 pad45 (0:1) bit (36), 1 231 1 232 2 instr (0:1) bit (36); /* Instruction ARRAY */ 1 233 1 234 1 235 1 236 /* END INCLUDE FILE mc.incl.pl1 */ 69 70 end gcos_mme_time_; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 09/09/83 1007.7 gcos_mme_time_.pl1 >spec>on>09/07/83-gcos>gcos_mme_time_.pl1 69 1 08/17/83 1135.7 mc.incl.pl1 >ldd>include>mc.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. a 24 based bit(36) level 3 packed unaligned dcl 1-12 set ref 42 42 clock builtin function dcl 53 ref 31 d 000100 automatic fixed bin(24,0) dcl 54 set ref 44* date_time 000101 automatic char(24) unaligned dcl 55 set ref 33* 38 39 40 date_time_ 000010 constant entry external dcl 56 ref 33 decode_clock_value_ 000012 constant entry external dcl 57 ref 44 gcos_cv_ascii_gebcd_ 000014 constant entry external dcl 58 ref 42 i 000110 automatic fixed bin(71,0) dcl 59 set ref 44* 47* 47 48 increment parameter fixed bin(24,0) dcl 60 set ref 6 30* m 000112 automatic fixed bin(24,0) dcl 61 set ref 44* mc based structure level 1 dcl 1-12 mc64ths based fixed bin(35,0) dcl 62 set ref 48* mcp parameter pointer dcl 1-10 ref 6 42 42 48 q 25 based bit(36) level 3 packed unaligned dcl 1-12 set ref 48 regs 20 based structure level 2 packed unaligned dcl 1-12 temp 000114 automatic char(6) dcl 63 set ref 38* 39* 40* 42 42 time 000116 automatic fixed bin(71,0) dcl 64 set ref 31* 33* 44* w 000120 automatic fixed bin(24,0) dcl 65 set ref 44* y 000121 automatic fixed bin(24,0) dcl 66 set ref 44* z 000122 automatic char(3) unaligned dcl 67 set ref 44* NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. abx internal static fixed bin(17,0) initial dcl 1-42 apx internal static fixed bin(17,0) initial dcl 1-42 bbx internal static fixed bin(17,0) initial dcl 1-42 bpx internal static fixed bin(17,0) initial dcl 1-42 lbx internal static fixed bin(17,0) initial dcl 1-42 lpx internal static fixed bin(17,0) initial dcl 1-42 sbx internal static fixed bin(17,0) initial dcl 1-42 scu based structure level 1 dcl 1-56 scup automatic pointer dcl 1-54 scux based structure level 1 dcl 1-206 spx internal static fixed bin(17,0) initial dcl 1-42 NAME DECLARED BY EXPLICIT CONTEXT. gcos_mme_time_ 000010 constant entry external dcl 6 NAMES DECLARED BY CONTEXT OR IMPLICATION. addr builtin function ref 42 42 42 42 48 divide builtin function ref 47 substr builtin function set ref 38 38 39* 39 40* 40 STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 214 232 140 224 Length 414 140 16 145 54 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME gcos_mme_time_ 116 external procedure is an external procedure. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME gcos_mme_time_ 000100 d gcos_mme_time_ 000101 date_time gcos_mme_time_ 000110 i gcos_mme_time_ 000112 m gcos_mme_time_ 000114 temp gcos_mme_time_ 000116 time gcos_mme_time_ 000120 w gcos_mme_time_ 000121 y gcos_mme_time_ 000122 z gcos_mme_time_ THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out_desc call_ext_out return mpfx2 ext_entry divide_fx3 clock THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. date_time_ decode_clock_value_ gcos_cv_ascii_gebcd_ NO EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 6 000004 30 000015 31 000017 33 000021 38 000036 39 000040 40 000044 42 000047 44 000077 47 000122 48 000127 49 000136 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved