COMPILATION LISTING OF SEGMENT gtss_drl_snumb_ Compiled by: Multics PL/I Compiler, Release 28d, of October 4, 1983 Compiled at: Honeywell Multics Op. - System M Compiled on: 12/10/84 1246.9 mst Mon Options: optimize map 1 /* *********************************************************** 2* * * 3* * * 4* * Copyright, (C) Honeywell Information Systems Inc., 1981 * 5* * * 6* * * 7* *********************************************************** */ 8 9 gtss_drl_snumb_: proc (mcpp, increment); 10 11 /* * gtss obtain snumb. 12* 13* Author: Mel Wilson 19mar79 14* * */ 15 dcl mcpp ptr parm; 16 dcl increment fixed bin parm; 17 mcp = mcpp; 18 19 /* * 20* 21* DRL SNUMB, OBTAIN SNUMB (octal 20) 22* 23* 24* 8_________1_6_____________________ 25* 26* DRL SNUMB 27* 28* (See TSS SYSTEM PROGRAMMER'S 29* REFERENCE MANUAL DD17C, Rev. 0, July 1976 30* Page 3-25) 31* 32**/ 33 34 increment = 0; /* no argument words */ 35 36 call gtss_get_user_state_ (u_state_ptr); 37 temp_snumb = snumb_sequence || "T0"; 38 call gtss_ascii_bcd_ (addr (temp_snumb), 6, addr (mc.a)); 39 if snumb_sequence = 9999 then snumb_sequence = 0; 40 else snumb_sequence = snumb_sequence + 1; 41 return; 42 43 /* miscellaneous declarations */ 44 dcl temp_snumb char (6); 45 dcl gtss_ascii_bcd_ ext entry (ptr, fixed bin, ptr); 46 dcl gtss_get_user_state_ entry (ptr); 47 1 1 /* BEGIN INCLUDE FILE gtss_snumb_xref_.incl.pl1 */ 1 2 /* 1 3* Created: (MWilson Multics) 03/26/79 1152.0 mst Mon 1 4**/ 1 5 1 6 dcl u_state_ptr ptr; 1 7 dcl 1 gtss_snumb_xref_ based (u_state_ptr), 1 8 3 snumb_sequence pic "9999", 1 9 3 entry_count fixed bin, 1 10 3 snumb_entry (100), 1 11 4 snumb char (5), 1 12 4 jout_id bit (12), 1 13 4 activity fixed bin, 1 14 4 status fixed bin; 1 15 1 16 /* * snumb_entry.status key values * */ 1 17 1 18 dcl (READING_RMT, INITIATED) init(3) static int options(constant); 1 19 dcl EXECUTING init(9) static int options(constant); 1 20 dcl WAIT_MEDIA init(11) static int options(constant); 1 21 dcl TERMINATING init(15) static int options(constant); 1 22 dcl OUTPUT_WAITING init(16) static int options(constant); 1 23 dcl (OUTPUT_COMPLETE, COMPLETE) init(17) static int options(constant); 1 24 1 25 /* END INCLUDE FILE gtss_snumb_xref_.incl.pl1 */ 48 49 2 1 /* */ 2 2 /* BEGIN INCLUDE FILE mc.incl.pl1 Created Dec 72 for 6180 - WSS. */ 2 3 /* Modified 06/07/76 by Greenberg for mc.resignal */ 2 4 /* Modified 07/07/76 by Morris for fault register data */ 2 5 /* Modified 08/28/80 by J. A. Bush for the DPS8/70M CVPU */ 2 6 /* Modified '82 to make values constant */ 2 7 2 8 /* words 0-15 pointer registers */ 2 9 2 10 dcl mcp ptr; 2 11 2 12 dcl 1 mc based (mcp) aligned, 2 13 2 prs (0:7) ptr, /* POINTER REGISTERS */ 2 14 (2 regs, /* registers */ 2 15 3 x (0:7) bit (18), /* index registers */ 2 16 3 a bit (36), /* accumulator */ 2 17 3 q bit (36), /* q-register */ 2 18 3 e bit (8), /* exponent */ 2 19 3 pad1 bit (28), 2 20 3 t bit (27), /* timer register */ 2 21 3 pad2 bit (6), 2 22 3 ralr bit (3), /* ring alarm register */ 2 23 2 24 2 scu (0:7) bit (36), 2 25 2 26 2 mask bit (72), /* mem controller mask at time of fault */ 2 27 2 ips_temp bit (36), /* Temporary storage for IPS info */ 2 28 2 errcode fixed bin (35), /* fault handler's error code */ 2 29 2 fim_temp, 2 30 3 unique_index bit (18) unal, /* unique index for restarting faults */ 2 31 3 resignal bit (1) unal, /* recompute signal name with fcode below */ 2 32 3 fcode bit (17) unal, /* fault code used as index to FIM table and SCT */ 2 33 2 fault_reg bit (36), /* fault register */ 2 34 2 pad2 bit (1), 2 35 2 cpu_type fixed bin (2) unsigned, /* L68 = 0, DPS8/70M = 1 */ 2 36 2 ext_fault_reg bit (15), /* extended fault reg for DPS8/70M CPU */ 2 37 2 fault_time bit (54), /* time of fault */ 2 38 2 39 2 eis_info (0:7) bit (36)) unaligned; 2 40 2 41 2 42 dcl (apx fixed bin init (0), 2 43 abx fixed bin init (1), 2 44 bpx fixed bin init (2), 2 45 bbx fixed bin init (3), 2 46 lpx fixed bin init (4), 2 47 lbx fixed bin init (5), 2 48 spx fixed bin init (6), 2 49 sbx fixed bin init (7)) internal static options (constant); 2 50 2 51 2 52 2 53 2 54 dcl scup ptr; 2 55 2 56 dcl 1 scu based (scup) aligned, /* SCU DATA */ 2 57 2 58 2 59 /* WORD (0) */ 2 60 2 61 (2 ppr, /* PROCEDURE POINTER REGISTER */ 2 62 3 prr bit (3), /* procedure ring register */ 2 63 3 psr bit (15), /* procedure segment register */ 2 64 3 p bit (1), /* procedure privileged bit */ 2 65 2 66 2 apu, /* APPENDING UNIT STATUS */ 2 67 3 xsf bit (1), /* ext seg flag - IT modification */ 2 68 3 sdwm bit (1), /* match in SDW Ass. Mem. */ 2 69 3 sd_on bit (1), /* SDW Ass. Mem. ON */ 2 70 3 ptwm bit (1), /* match in PTW Ass. Mem. */ 2 71 3 pt_on bit (1), /* PTW Ass. Mem. ON */ 2 72 3 pi_ap bit (1), /* Instr Fetch or Append cycle */ 2 73 3 dsptw bit (1), /* Fetch of DSPTW */ 2 74 3 sdwnp bit (1), /* Fetch of SDW non paged */ 2 75 3 sdwp bit (1), /* Fetch of SDW paged */ 2 76 3 ptw bit (1), /* Fetch of PTW */ 2 77 3 ptw2 bit (1), /* Fetch of pre-paged PTW */ 2 78 3 fap bit (1), /* Fetch of final address paged */ 2 79 3 fanp bit (1), /* Fetch of final address non-paged */ 2 80 3 fabs bit (1), /* Fetch of final address absolute */ 2 81 2 82 2 fault_cntr bit (3), /* number of retrys of EIS instructions */ 2 83 2 84 2 85 /* WORD (1) */ 2 86 2 87 2 fd, /* FAULT DATA */ 2 88 3 iro bit (1), /* illegal ring order */ 2 89 3 oeb bit (1), /* out of execute bracket */ 2 90 3 e_off bit (1), /* no execute */ 2 91 3 orb bit (1), /* out of read bracket */ 2 92 3 r_off bit (1), /* no read */ 2 93 3 owb bit (1), /* out of write bracket */ 2 94 3 w_off bit (1), /* no write */ 2 95 3 no_ga bit (1), /* not a gate */ 2 96 3 ocb bit (1), /* out of call bracket */ 2 97 3 ocall bit (1), /* outward call */ 2 98 3 boc bit (1), /* bad outward call */ 2 99 3 inret bit (1), /* inward return */ 2 100 3 crt bit (1), /* cross ring transfer */ 2 101 3 ralr bit (1), /* ring alarm register */ 2 102 3 am_er bit (1), /* associative memory fault */ 2 103 3 oosb bit (1), /* out of segment bounds */ 2 104 3 paru bit (1), /* processor parity upper */ 2 105 3 parl bit (1), /* processor parity lower */ 2 106 3 onc_1 bit (1), /* op not complete type 1 */ 2 107 3 onc_2 bit (1), /* op not complete type 2 */ 2 108 2 109 2 port_stat, /* PORT STATUS */ 2 110 3 ial bit (4), /* illegal action lines */ 2 111 3 iac bit (3), /* illegal action channel */ 2 112 3 con_chan bit (3), /* connect channel */ 2 113 2 114 2 fi_num bit (5), /* (fault/interrupt) number */ 2 115 2 fi_flag bit (1), /* 1 => fault, 0 => interrupt */ 2 116 2 117 2 118 /* WORD (2) */ 2 119 2 120 2 tpr, /* TEMPORARY POINTER REGISTER */ 2 121 3 trr bit (3), /* temporary ring register */ 2 122 3 tsr bit (15), /* temporary segment register */ 2 123 2 124 2 pad2 bit (9), 2 125 2 126 2 cpu_no bit (3), /* CPU number */ 2 127 2 128 2 delta bit (6), /* tally modification DELTA */ 2 129 2 130 2 131 /* WORD (3) */ 2 132 2 133 2 word3 bit (18), 2 134 2 135 2 tsr_stat, /* TSR STATUS for 1,2,&3 word instructions */ 2 136 3 tsna, /* Word 1 status */ 2 137 4 prn bit (3), /* Word 1 PR number */ 2 138 4 prv bit (1), /* Word 1 PR valid bit */ 2 139 3 tsnb, /* Word 2 status */ 2 140 4 prn bit (3), /* Word 2 PR number */ 2 141 4 prv bit (1), /* Word 2 PR valid bit */ 2 142 3 tsnc, /* Word 3 status */ 2 143 4 prn bit (3), /* Word 3 PR number */ 2 144 4 prv bit (1), /* Word 3 PR valid bit */ 2 145 2 146 2 tpr_tbr bit (6), /* TPR.TBR field */ 2 147 2 148 2 149 /* WORD (4) */ 2 150 2 151 2 ilc bit (18), /* INSTRUCTION COUNTER */ 2 152 2 153 2 ir, /* INDICATOR REGISTERS */ 2 154 3 zero bit (1), /* zero indicator */ 2 155 3 neg bit (1), /* negative indicator */ 2 156 3 carry bit (1), /* carryry indicator */ 2 157 3 ovfl bit (1), /* overflow indicator */ 2 158 3 eovf bit (1), /* eponent overflow */ 2 159 3 eufl bit (1), /* exponent underflow */ 2 160 3 oflm bit (1), /* overflow mask */ 2 161 3 tro bit (1), /* tally runout */ 2 162 3 par bit (1), /* parity error */ 2 163 3 parm bit (1), /* parity mask */ 2 164 3 bm bit (1), /* ^bar mode */ 2 165 3 tru bit (1), /* truncation mode */ 2 166 3 mif bit (1), /* multi-word instruction mode */ 2 167 3 abs bit (1), /* absolute mode */ 2 168 3 hex bit (1), /* hexadecimal exponent mode */ 2 169 3 pad bit (3), 2 170 2 171 2 172 /* WORD (5) */ 2 173 2 174 2 ca bit (18), /* COMPUTED ADDRESS */ 2 175 2 176 2 cu, /* CONTROL UNIT STATUS */ 2 177 3 rf bit (1), /* on first cycle of repeat instr */ 2 178 3 rpt bit (1), /* repeat instruction */ 2 179 3 rd bit (1), /* repeat double instruction */ 2 180 3 rl bit (1), /* repeat link instruciton */ 2 181 3 pot bit (1), /* IT modification */ 2 182 3 pon bit (1), /* return type instruction */ 2 183 3 xde bit (1), /* XDE from Even location */ 2 184 3 xdo bit (1), /* XDE from Odd location */ 2 185 3 poa bit (1), /* operation preparation */ 2 186 3 rfi bit (1), /* tells CPU to refetch instruction */ 2 187 3 its bit (1), /* ITS modification */ 2 188 3 if bit (1), /* fault occured during instruction fetch */ 2 189 2 190 2 cpu_tag bit (6)) unaligned, /* computed tag field */ 2 191 2 192 2 193 /* WORDS (6,7) */ 2 194 2 195 2 even_inst bit (36), /* even instruction of faulting pair */ 2 196 2 197 2 odd_inst bit (36); /* odd instruction of faulting pair */ 2 198 2 199 2 200 2 201 2 202 2 203 2 204 /* ALTERNATE SCU DECLARATION */ 2 205 2 206 2 207 dcl 1 scux based (scup) aligned, 2 208 2 209 (2 pad0 bit (36), 2 210 2 211 2 fd, /* GROUP II FAULT DATA */ 2 212 3 isn bit (1), /* illegal segment number */ 2 213 3 ioc bit (1), /* illegal op code */ 2 214 3 ia_am bit (1), /* illegal address - modifier */ 2 215 3 isp bit (1), /* illegal slave procedure */ 2 216 3 ipr bit (1), /* illegal procedure */ 2 217 3 nea bit (1), /* non existent address */ 2 218 3 oobb bit (1), /* out of bounds */ 2 219 3 pad bit (29), 2 220 2 221 2 pad2 bit (36), 2 222 2 223 2 pad3a bit (18), 2 224 2 225 2 tsr_stat (0:2), /* TSR STATUS as an ARRAY */ 2 226 3 prn bit (3), /* PR number */ 2 227 3 prv bit (1), /* PR valid bit */ 2 228 2 229 2 pad3b bit (6)) unaligned, 2 230 2 231 2 pad45 (0:1) bit (36), 2 232 2 233 2 instr (0:1) bit (36); /* Instruction ARRAY */ 2 234 2 235 2 236 2 237 /* END INCLUDE FILE mc.incl.pl1 */ 50 51 end gtss_drl_snumb_; SOURCE FILES USED IN THIS COMPILATION. LINE NUMBER DATE MODIFIED NAME PATHNAME 0 12/10/84 1043.4 gtss_drl_snumb_.pl1 >spec>on>7105>gtss_drl_snumb_.pl1 48 1 09/09/83 1714.2 gtss_snumb_xref_.incl.pl1 >ldd>include>gtss_snumb_xref_.incl.pl1 50 2 12/15/83 1100.4 mc.incl.pl1 >ldd>include>mc.incl.pl1 NAMES DECLARED IN THIS COMPILATION. IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES (* indicates a set context) NAMES DECLARED BY DECLARE STATEMENT. a 24 based bit(36) level 3 packed unaligned dcl 2-12 set ref 38 38 gtss_ascii_bcd_ 000010 constant entry external dcl 45 ref 38 gtss_get_user_state_ 000012 constant entry external dcl 46 ref 36 gtss_snumb_xref_ based structure level 1 unaligned dcl 1-7 increment parameter fixed bin(17,0) dcl 16 set ref 9 34* mc based structure level 1 dcl 2-12 mcp 000104 automatic pointer dcl 2-10 set ref 17* 38 38 mcpp parameter pointer dcl 15 ref 9 17 regs 20 based structure level 2 packed unaligned dcl 2-12 snumb_sequence based picture(4) level 2 packed unaligned dcl 1-7 set ref 37 39 39* 40* 40 temp_snumb 000100 automatic char(6) unaligned dcl 44 set ref 37* 38 38 u_state_ptr 000102 automatic pointer dcl 1-6 set ref 36* 37 39 39 40 40 NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED. COMPLETE internal static fixed bin(17,0) initial dcl 1-23 EXECUTING internal static fixed bin(17,0) initial dcl 1-19 INITIATED internal static fixed bin(17,0) initial dcl 1-18 OUTPUT_COMPLETE internal static fixed bin(17,0) initial dcl 1-23 OUTPUT_WAITING internal static fixed bin(17,0) initial dcl 1-22 READING_RMT internal static fixed bin(17,0) initial dcl 1-18 TERMINATING internal static fixed bin(17,0) initial dcl 1-21 WAIT_MEDIA internal static fixed bin(17,0) initial dcl 1-20 abx internal static fixed bin(17,0) initial dcl 2-42 apx internal static fixed bin(17,0) initial dcl 2-42 bbx internal static fixed bin(17,0) initial dcl 2-42 bpx internal static fixed bin(17,0) initial dcl 2-42 lbx internal static fixed bin(17,0) initial dcl 2-42 lpx internal static fixed bin(17,0) initial dcl 2-42 sbx internal static fixed bin(17,0) initial dcl 2-42 scu based structure level 1 dcl 2-56 scup automatic pointer dcl 2-54 scux based structure level 1 dcl 2-207 spx internal static fixed bin(17,0) initial dcl 2-42 NAME DECLARED BY EXPLICIT CONTEXT. gtss_drl_snumb_ 000012 constant entry external dcl 9 NAME DECLARED BY CONTEXT OR IMPLICATION. addr builtin function ref 38 38 38 38 STORAGE REQUIREMENTS FOR THIS PROGRAM. Object Text Link Symbol Defs Static Start 0 0 164 200 117 174 Length 374 117 14 160 45 0 BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME gtss_drl_snumb_ 90 external procedure is an external procedure. STORAGE FOR AUTOMATIC VARIABLES. STACK FRAME LOC IDENTIFIER BLOCK NAME gtss_drl_snumb_ 000100 temp_snumb gtss_drl_snumb_ 000102 u_state_ptr gtss_drl_snumb_ 000104 mcp gtss_drl_snumb_ THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM. call_ext_out return ext_entry unpack_pic THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM. gtss_ascii_bcd_ gtss_get_user_state_ NO EXTERNAL VARIABLES ARE USED BY THIS PROGRAM. LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC 9 000006 17 000017 34 000023 36 000024 37 000032 38 000035 39 000057 40 000075 41 000111 ----------------------------------------------------------- Historical Background This edition of the Multics software materials and documentation is provided and donated to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc. as a contribution to computer science knowledge. This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL and BULL HN Information Systems Inc. to the development of this operating system. Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for managing computer hardware properly and for executing programs. Many subsequent operating systems incorporated Multics principles. Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . ----------------------------------------------------------- Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without fee is hereby granted,provided that the below copyright notice and historical background appear in all copies and that both the copyright notice and historical background and this permission notice appear in supporting documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining to distribution of the programs without specific prior written permission. Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. Copyright 2006 by BULL HN Information Systems Inc. Copyright 2006 by Bull SAS All Rights Reserved