Sample LaTeX Thesis -- serial.tex (Chapter 2)

\chapter{Serial Data Receiver}

\section{Abstract}

Serial data transmission is widely used for communication.  Once serial data
is received, however, it must be converted to the parallel format that most
devices use\cite{Kay}.  The purpose of this lab is to construct a serial data
receiver that puts the data in a parallel format, checks for errors, stores a
selected block of data, and finally outputs that block.

\section{Overview}

The serial data receiver will be connected to a serial data transmitter in the
lab. The receiver must select one of the four blocks transmitted.  Once the
block is selected, the receiver must store the complete block in memory, then
graphically display the block on an oscilloscope.  A block diagram of the
receiver can be found in figure~\ref{figureblock} on page
\pageref{figureblock}.

\section{Description} 
The attached block diagram shows the three subsystems.  These are:

\begin{enumerate}
\item Serial Data Receiver (SDR)
\item Data Error Detector (DED)
\item Block Selector (BS)
\end{enumerate}

The following descriptions and specifications are a shortened version of the
specifications found in the actual lab handout (see \ref{samplelable} on page
\pageref{samplelable}).

\subsection{Serial Data Receiver}

The serial data receiver (SDU) takes in the serial data and puts it in a
parallel format.  The format of the serial data is shown in figure
\ref{figuretag} on page \pageref{figuretag}.  The serial line is normally
high.  Each transmission of a data word is preceded by one low ``start'' bit,
followed by the eight information bits and at least one stop bit (high level),
indicating the end of the data word.  There is an arbitrary amount of time
(including zero) between data words.

\begin{figure}
\vspace{1.5 in}
\caption{Serial Data Format}
\label{figuretag}
\end{figure}

\begin{figure}
\vspace{15ex}
\caption{Block Diagram of the Receiver}
\label{figureblock}
\end{figure}

\subsection{Data Error Detector}

The DED checks the data word for odd parity and a stop bit.  If neither of
these conditions holds true, an error signal is sent to the controller.  If
any error is detected in the transmission, the block of data must be
discarded.

\subsection{Block Selector}

The BS system uses a J-K flip-flop.  The flip-flop is set whenever the first
word of a block has D[5-4] that match switches s[1-0].  The flip-flop is reset
whenever the controller generates the mistake signal, or when the reset switch
is pushed.

\section{Conclusions}

The serial data receiver is a relatively common device.  Through the use of
three switches, one of the four serial data blocks would generate an
interesting display on the scope.  The debugging was much more difficult
because most of it had to be done in the lab with the transmitter running at
full speed.