Static Timing Analysis

Project : MyFirstProject
Build Time : 01/11/16 13:14:00
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_IntClock(routed) ADC_IntClock(routed) 1.600 MHz 1.600 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 134.953 MHz
Clock_1 CyMASTER_CLK 12.000 MHz 12.000 MHz 89.063 MHz
ADC_IntClock CyMASTER_CLK 1.600 MHz 1.600 MHz 37.480 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 625ns(1.6 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_one_hot_7\/main_0 37.480 MHz 26.681 598.319
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_5 1.940
Route 1 \ADC:ch_addr_5\ \ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 6.009
macrocell1 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 2.296
macrocell3 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_7\/main_0 6.226
macrocell25 U(3,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_7\ SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_one_hot_8\/main_0 37.480 MHz 26.681 598.319
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_5 1.940
Route 1 \ADC:ch_addr_5\ \ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 6.009
macrocell1 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 2.296
macrocell3 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_8\/main_0 6.226
macrocell26 U(3,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_8\ SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_one_hot_17\/main_0 37.480 MHz 26.681 598.319
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_5 1.940
Route 1 \ADC:ch_addr_5\ \ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 6.009
macrocell1 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 2.296
macrocell3 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_17\/main_0 6.226
macrocell35 U(3,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_17\ SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_one_hot_36\/main_0 37.480 MHz 26.681 598.319
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_5 1.940
Route 1 \ADC:ch_addr_5\ \ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 6.009
macrocell1 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 2.296
macrocell3 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_36\/main_0 6.226
macrocell54 U(3,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_36\ SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_one_hot_5\/main_0 37.507 MHz 26.662 598.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_5 1.940
Route 1 \ADC:ch_addr_5\ \ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 6.009
macrocell1 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 2.296
macrocell3 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_5\/main_0 6.207
macrocell23 U(3,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_5\ SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_one_hot_39\/main_0 37.507 MHz 26.662 598.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_5 1.940
Route 1 \ADC:ch_addr_5\ \ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 6.009
macrocell1 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 2.296
macrocell3 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_39\/main_0 6.207
macrocell57 U(3,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_39\ SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_one_hot_47\/main_0 37.507 MHz 26.662 598.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_5 1.940
Route 1 \ADC:ch_addr_5\ \ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 6.009
macrocell1 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 2.296
macrocell3 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_47\/main_0 6.207
macrocell65 U(3,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_47\ SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_one_hot_49\/main_0 37.507 MHz 26.662 598.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_5 1.940
Route 1 \ADC:ch_addr_5\ \ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 6.009
macrocell1 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 2.296
macrocell3 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_49\/main_0 6.207
macrocell67 U(3,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_49\ SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_one_hot_1\/main_0 37.987 MHz 26.325 598.675
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_5 1.940
Route 1 \ADC:ch_addr_5\ \ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 6.009
macrocell1 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 2.296
macrocell3 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_1\/main_0 5.870
macrocell19 U(2,0) 1 \ADC:AMuxHw_2_Decoder_one_hot_1\ SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_one_hot_21\/main_0 37.987 MHz 26.325 598.675
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_5 1.940
Route 1 \ADC:ch_addr_5\ \ADC:bSAR_SEQ:ChannelCounter\/count_5 \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 6.009
macrocell1 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_1 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 2.296
macrocell3 U(2,2) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_21\/main_0 5.870
macrocell39 U(2,0) 1 \ADC:AMuxHw_2_Decoder_one_hot_21\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_428/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_2 135.796 MHz 7.364 34.303
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell82 U(3,2) 1 Net_428 Net_428/clock_0 Net_428/q 1.250
Route 1 Net_428 Net_428/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_2 2.604
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 83.3333ns(12 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:genblk8:stsreg\/status_2 89.063 MHz 11.228 72.105
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \PWM_1:PWMUDB:tc_i\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:status_2\/main_1 2.770
macrocell2 U(2,5) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_1 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.318
statusicell1 U(2,5) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 89.969 MHz 11.115 72.218
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.765
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 91.241 MHz 10.960 72.373
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,4) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:status_2\/main_0 3.542
macrocell2 U(2,5) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_0 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.318
statusicell1 U(2,5) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 92.098 MHz 10.858 72.475
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,4) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.548
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 120.163 MHz 8.322 75.011
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.302
macrocell6 U(2,5) 1 \PWM_1:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 120.163 MHz 8.322 75.011
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.302
macrocell8 U(2,5) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_152/main_1 120.163 MHz 8.322 75.011
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_152/main_1 2.302
macrocell10 U(2,5) 1 Net_152 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_152/main_0 120.831 MHz 8.276 75.057
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,4) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_152/main_0 3.516
macrocell10 U(2,5) 1 Net_152 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 141.523 MHz 7.066 76.267
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(2,5) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.306
macrocell8 U(2,5) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 141.663 MHz 7.059 76.274
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(2,5) 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/clock_0 \PWM_1:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 2.299
macrocell9 U(2,5) 1 \PWM_1:PWMUDB:status_1\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC:bSAR_SEQ:bus_clk_nrq_reg\/q Net_428/main_0 135.943 MHz 7.356 34.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
Route 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q Net_428/main_0 2.596
macrocell82 U(3,2) 1 Net_428 SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:nrq_reg\/main_0 135.943 MHz 7.356 34.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
Route 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:nrq_reg\/main_0 2.596
macrocell84 U(3,2) 1 \ADC:bSAR_SEQ:nrq_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC:Sync:genblk1[0]:INST\/out \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_1 134.953 MHz 7.410 34.257
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 \ADC:Sync:genblk1[0]:INST\ \ADC:Sync:genblk1[0]:INST\/clock \ADC:Sync:genblk1[0]:INST\/out 1.020
Route 1 \ADC:Net_3935\ \ADC:Sync:genblk1[0]:INST\/out \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_1 2.880
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_0 136.054 MHz 7.350 34.317
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_0 2.590
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_428/q \ADC:bSAR_SEQ:EOCSts\/status_0 2.666
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell82 U(3,2) 1 Net_428 Net_428/clock_0 Net_428/q 1.250
Route 1 Net_428 Net_428/q \ADC:bSAR_SEQ:EOCSts\/status_0 3.416
statuscell1 U(3,3) 1 \ADC:bSAR_SEQ:EOCSts\ HOLD -2.000
Clock Skew 0.000
\ADC:bSAR_SEQ:CtrlReg\/control_0 Net_428/clk_en 3.131
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \ADC:bSAR_SEQ:CtrlReg\ \ADC:bSAR_SEQ:CtrlReg\/clock \ADC:bSAR_SEQ:CtrlReg\/control_0 0.360
Route 1 \ADC:bSAR_SEQ:enable\ \ADC:bSAR_SEQ:CtrlReg\/control_0 Net_428/clk_en 2.771
macrocell82 U(3,2) 1 Net_428 HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:CtrlReg\/control_0 \ADC:bSAR_SEQ:nrq_reg\/clk_en 3.131
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \ADC:bSAR_SEQ:CtrlReg\ \ADC:bSAR_SEQ:CtrlReg\/clock \ADC:bSAR_SEQ:CtrlReg\/control_0 0.360
Route 1 \ADC:bSAR_SEQ:enable\ \ADC:bSAR_SEQ:CtrlReg\/control_0 \ADC:bSAR_SEQ:nrq_reg\/clk_en 2.771
macrocell84 U(3,2) 1 \ADC:bSAR_SEQ:nrq_reg\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:CtrlReg\/control_1 \ADC:bSAR_SEQ:ChannelCounter\/load 3.141
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \ADC:bSAR_SEQ:CtrlReg\ \ADC:bSAR_SEQ:CtrlReg\/clock \ADC:bSAR_SEQ:CtrlReg\/control_1 0.360
Route 1 \ADC:bSAR_SEQ:load_period\ \ADC:bSAR_SEQ:CtrlReg\/control_1 \ADC:bSAR_SEQ:ChannelCounter\/load 2.781
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:CtrlReg\/control_0 \ADC:bSAR_SEQ:ChannelCounter\/clk_en 3.143
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \ADC:bSAR_SEQ:CtrlReg\ \ADC:bSAR_SEQ:CtrlReg\/clock \ADC:bSAR_SEQ:CtrlReg\/control_0 0.360
Route 1 \ADC:bSAR_SEQ:enable\ \ADC:bSAR_SEQ:CtrlReg\/control_0 \ADC:bSAR_SEQ:ChannelCounter\/clk_en 2.783
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:nrq_reg\/q Net_428/main_1 3.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell84 U(3,2) 1 \ADC:bSAR_SEQ:nrq_reg\ \ADC:bSAR_SEQ:nrq_reg\/clock_0 \ADC:bSAR_SEQ:nrq_reg\/q 1.250
Route 1 \ADC:bSAR_SEQ:nrq_reg\ \ADC:bSAR_SEQ:nrq_reg\/q Net_428/main_1 2.295
macrocell82 U(3,2) 1 Net_428 HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_1 \ADC:AMuxHw_2_Decoder_old_id_1\/main_0 3.975
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_1 0.620
Route 1 \ADC:ch_addr_1\ \ADC:bSAR_SEQ:ChannelCounter\/count_1 \ADC:AMuxHw_2_Decoder_old_id_1\/main_0 3.355
macrocell16 U(2,3) 1 \ADC:AMuxHw_2_Decoder_old_id_1\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:CtrlReg\/control_0 \ADC:bSAR_SEQ:EOCSts\/clk_en 4.058
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \ADC:bSAR_SEQ:CtrlReg\ \ADC:bSAR_SEQ:CtrlReg\/clock \ADC:bSAR_SEQ:CtrlReg\/control_0 0.360
Route 1 \ADC:bSAR_SEQ:enable\ \ADC:bSAR_SEQ:CtrlReg\/control_0 \ADC:bSAR_SEQ:EOCSts\/clk_en 3.698
statuscell1 U(3,3) 1 \ADC:bSAR_SEQ:EOCSts\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_2 \ADC:AMuxHw_2_Decoder_old_id_2\/main_0 4.183
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_2 0.620
Route 1 \ADC:ch_addr_2\ \ADC:bSAR_SEQ:ChannelCounter\/count_2 \ADC:AMuxHw_2_Decoder_old_id_2\/main_0 3.563
macrocell15 U(2,3) 1 \ADC:AMuxHw_2_Decoder_old_id_2\ HOLD 0.000
Clock Skew 0.000
\ADC:AMuxHw_2_Decoder_old_id_0\/q \ADC:AMuxHw_2_Decoder_one_hot_3\/main_6 4.183
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,3) 1 \ADC:AMuxHw_2_Decoder_old_id_0\ \ADC:AMuxHw_2_Decoder_old_id_0\/clock_0 \ADC:AMuxHw_2_Decoder_old_id_0\/q 1.250
Route 1 \ADC:AMuxHw_2_Decoder_old_id_0\ \ADC:AMuxHw_2_Decoder_old_id_0\/q \ADC:AMuxHw_2_Decoder_one_hot_3\/main_6 2.933
macrocell21 U(2,3) 1 \ADC:AMuxHw_2_Decoder_one_hot_3\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_428/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_2 3.854
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell82 U(3,2) 1 Net_428 Net_428/clock_0 Net_428/q 1.250
Route 1 Net_428 Net_428/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_2 2.604
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\PWM_1:PWMUDB:status_1\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_1 1.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(2,5) 1 \PWM_1:PWMUDB:status_1\ \PWM_1:PWMUDB:status_1\/clock_0 \PWM_1:PWMUDB:status_1\/q 1.250
Route 1 \PWM_1:PWMUDB:status_1\ \PWM_1:PWMUDB:status_1\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_1 2.314
statusicell1 U(2,5) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 1.575
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,5) 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/clock_0 \PWM_1:PWMUDB:status_0\/q 1.250
Route 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 2.325
statusicell1 U(2,5) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.675
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,4) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.315
macrocell5 U(2,4) 1 \PWM_1:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 3.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.302
macrocell6 U(2,5) 1 \PWM_1:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 3.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.302
macrocell8 U(2,5) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_152/main_1 3.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_152/main_1 2.302
macrocell10 U(2,5) 1 Net_152 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_149/main_0 3.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,4) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_149/main_0 2.295
macrocell11 U(2,4) 1 Net_149 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 3.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(2,5) 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/clock_0 \PWM_1:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 2.299
macrocell9 U(2,5) 1 \PWM_1:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(2,5) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.306
macrocell8 U(2,5) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 4.575
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 1.810
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.765
datapathcell1 U(2,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\ADC:bSAR_SEQ:bus_clk_nrq_reg\/q Net_428/main_0 3.846
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
Route 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q Net_428/main_0 2.596
macrocell82 U(3,2) 1 Net_428 HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:nrq_reg\/main_0 3.846
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
Route 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:nrq_reg\/main_0 2.596
macrocell84 U(3,2) 1 \ADC:bSAR_SEQ:nrq_reg\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\ADC:Sync:genblk1[0]:INST\/out \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_1 3.230
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 \ADC:Sync:genblk1[0]:INST\ \ADC:Sync:genblk1[0]:INST\/clock \ADC:Sync:genblk1[0]:INST\/out 0.350
Route 1 \ADC:Net_3935\ \ADC:Sync:genblk1[0]:INST\/out \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_1 2.880
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_0 3.840
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_0 2.590
macrocell83 U(3,2) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_152/q MotorL_A(0)_PAD 24.733
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,5) 1 Net_152 Net_152/clock_0 Net_152/q 1.250
Route 1 Net_152 Net_152/q MotorL_A(0)/pin_input 7.263
iocell2 P12[6] 1 MotorL_A(0) MotorL_A(0)/pin_input MotorL_A(0)/pad_out 16.220
Route 1 MotorL_A(0)_PAD MotorL_A(0)/pad_out MotorL_A(0)_PAD 0.000
Clock Clock path delay 0.000
Net_149/q MotorR_A(0)_PAD 23.662
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,4) 1 Net_149 Net_149/clock_0 Net_149/q 1.250
Route 1 Net_149 Net_149/q MotorR_A(0)/pin_input 6.557
iocell4 P12[0] 1 MotorR_A(0) MotorR_A(0)/pin_input MotorR_A(0)/pad_out 15.855
Route 1 MotorR_A(0)_PAD MotorR_A(0)/pad_out MotorR_A(0)_PAD 0.000
Clock Clock path delay 0.000