Static Timing Analysis

Project : ClassDemo
Build Time : 01/08/16 15:13:22
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_Seq_1_IntClock(routed) ADC_SAR_Seq_1_IntClock(routed) 1.600 MHz 1.600 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 120.207 MHz
ADC_SAR_Seq_1_IntClock CyMASTER_CLK 1.600 MHz 1.600 MHz 34.068 MHz
Clock_1 CyMASTER_CLK 100.000  Hz 100.000  Hz 77.888 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 625ns(1.6 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_1\/main_0 34.068 MHz 29.353 595.647
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/clock_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q 1.250
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_2 5.752
macrocell1 U(0,2) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_2 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 2.908
macrocell3 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_1\/main_0 9.233
macrocell16 U(1,0) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_1\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_5\/main_0 34.068 MHz 29.353 595.647
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/clock_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q 1.250
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_2 5.752
macrocell1 U(0,2) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_2 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 2.908
macrocell3 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_5\/main_0 9.233
macrocell20 U(1,0) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_5\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_17\/main_0 34.068 MHz 29.353 595.647
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/clock_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q 1.250
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_2 5.752
macrocell1 U(0,2) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_2 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 2.908
macrocell3 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_17\/main_0 9.233
macrocell32 U(1,0) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_17\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_1\/main_0 34.069 MHz 29.352 595.648
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,4) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/clock_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q 1.250
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_4 5.751
macrocell1 U(0,2) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_4 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 2.908
macrocell3 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_1\/main_0 9.233
macrocell16 U(1,0) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_1\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_5\/main_0 34.069 MHz 29.352 595.648
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,4) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/clock_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q 1.250
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_4 5.751
macrocell1 U(0,2) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_4 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 2.908
macrocell3 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_5\/main_0 9.233
macrocell20 U(1,0) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_5\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_17\/main_0 34.069 MHz 29.352 595.648
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,4) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/clock_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q 1.250
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_4 5.751
macrocell1 U(0,2) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_4 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 2.908
macrocell3 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_17\/main_0 9.233
macrocell32 U(1,0) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_17\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_34\/main_0 34.084 MHz 29.339 595.661
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/clock_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q 1.250
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_2 5.752
macrocell1 U(0,2) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_2 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 2.908
macrocell3 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_34\/main_0 9.219
macrocell49 U(0,0) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_34\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_59\/main_0 34.084 MHz 29.339 595.661
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/clock_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q 1.250
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_2 5.752
macrocell1 U(0,2) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_2 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 2.908
macrocell3 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_59\/main_0 9.219
macrocell74 U(0,0) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_59\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_34\/main_0 34.085 MHz 29.338 595.662
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,4) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/clock_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q 1.250
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_4 5.751
macrocell1 U(0,2) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_4 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 2.908
macrocell3 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_34\/main_0 9.219
macrocell49 U(0,0) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_34\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_59\/main_0 34.085 MHz 29.338 595.662
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,4) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/clock_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q 1.250
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_4 5.751
macrocell1 U(0,2) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/main_4 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 2.908
macrocell3 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_59\/main_0 9.219
macrocell74 U(0,0) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_59\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_853/q \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/main_2 120.207 MHz 8.319 33.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell79 U(1,2) 1 Net_853 Net_853/clock_0 Net_853/q 1.250
Route 1 Net_853 Net_853/q \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/main_2 3.559
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1e+007ns(100  Hz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 77.888 MHz 12.839 9999987.161
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 4.489
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:genblk8:stsreg\/status_2 83.605 MHz 11.961 9999988.039
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \PWM_1:PWMUDB:tc_i\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:status_2\/main_1 3.508
macrocell2 U(0,5) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_1 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.313
statusicell1 U(0,5) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 97.040 MHz 10.305 9999989.695
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:status_2\/main_0 2.892
macrocell2 U(0,5) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_0 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.313
statusicell1 U(0,5) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 97.934 MHz 10.211 9999989.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.901
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 119.904 MHz 8.340 9999991.660
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.320
macrocell6 U(0,5) 1 \PWM_1:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 119.904 MHz 8.340 9999991.660
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.320
macrocell7 U(0,5) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_474/main_1 119.904 MHz 8.340 9999991.660
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_474/main_1 2.320
macrocell8 U(0,5) 1 Net_474 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_474/main_0 130.634 MHz 7.655 9999992.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_474/main_0 2.895
macrocell8 U(0,5) 1 Net_474 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 141.723 MHz 7.056 9999992.944
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,5) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 1.210
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.336
macrocell5 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 141.824 MHz 7.051 9999992.949
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,5) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.291
macrocell7 U(0,5) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q Net_853/main_0 135.943 MHz 7.356 34.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
Route 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q Net_853/main_0 2.596
macrocell79 U(1,2) 1 Net_853 SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\/main_0 135.943 MHz 7.356 34.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
Route 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\/main_0 2.596
macrocell81 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC_SAR_Seq_1:Sync:genblk1[0]:INST\/out \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/main_1 134.953 MHz 7.410 34.257
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 \ADC_SAR_Seq_1:Sync:genblk1[0]:INST\ \ADC_SAR_Seq_1:Sync:genblk1[0]:INST\/clock \ADC_SAR_Seq_1:Sync:genblk1[0]:INST\/out 1.020
Route 1 \ADC_SAR_Seq_1:Net_3935\ \ADC_SAR_Seq_1:Sync:genblk1[0]:INST\/out \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/main_1 2.880
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/main_0 136.054 MHz 7.350 34.317
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/main_0 2.590
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_0 Net_853/clk_en 3.131
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\ \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/clock \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_0 0.360
Route 1 \ADC_SAR_Seq_1:bSAR_SEQ:enable\ \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_0 Net_853/clk_en 2.771
macrocell79 U(1,2) 1 Net_853 HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_0 \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\/clk_en 3.131
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\ \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/clock \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_0 0.360
Route 1 \ADC_SAR_Seq_1:bSAR_SEQ:enable\ \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_0 \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\/clk_en 2.771
macrocell81 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_1 \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/load 3.141
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\ \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/clock \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_1 0.360
Route 1 \ADC_SAR_Seq_1:bSAR_SEQ:load_period\ \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_1 \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/load 2.781
count7cell U(0,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_0 \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/clk_en 3.143
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\ \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/clock \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_0 0.360
Route 1 \ADC_SAR_Seq_1:bSAR_SEQ:enable\ \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_0 \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/clk_en 2.783
count7cell U(0,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/count_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_0\/main_0 3.397
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\ \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/clock \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/count_0 0.620
Route 1 \ADC_SAR_Seq_1:ch_addr_0\ \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/count_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_0\/main_0 2.777
macrocell14 U(0,2) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_0\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\/q Net_853/main_1 3.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell81 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\/clock_0 \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\/q 1.250
Route 1 \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\/q Net_853/main_1 2.294
macrocell79 U(1,2) 1 Net_853 HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/count_4 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/main_0 3.985
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\ \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/clock \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/count_4 0.620
Route 1 \ADC_SAR_Seq_1:ch_addr_4\ \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/count_4 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\/main_0 3.365
macrocell10 U(0,3) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_4\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/count_1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_1\/main_0 4.024
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\ \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/clock \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/count_1 0.620
Route 1 \ADC_SAR_Seq_1:ch_addr_1\ \ADC_SAR_Seq_1:bSAR_SEQ:ChannelCounter\/count_1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_1\/main_0 3.404
macrocell13 U(0,1) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_1\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_0 \ADC_SAR_Seq_1:bSAR_SEQ:EOCSts\/clk_en 4.058
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\ \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/clock \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_0 0.360
Route 1 \ADC_SAR_Seq_1:bSAR_SEQ:enable\ \ADC_SAR_Seq_1:bSAR_SEQ:CtrlReg\/control_0 \ADC_SAR_Seq_1:bSAR_SEQ:EOCSts\/clk_en 3.698
statuscell1 U(1,3) 1 \ADC_SAR_Seq_1:bSAR_SEQ:EOCSts\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_58\/main_3 4.440
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,4) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/clock_0 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q 1.250
Route 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq_1:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_58\/main_3 3.190
macrocell73 U(0,4) 1 \ADC_SAR_Seq_1:AMuxHw_2_Decoder_one_hot_58\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_853/q \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/main_2 4.809
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell79 U(1,2) 1 Net_853 Net_853/clock_0 Net_853/q 1.250
Route 1 Net_853 Net_853/q \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/main_2 3.559
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 1.580
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,5) 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/clock_0 \PWM_1:PWMUDB:status_0\/q 1.250
Route 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 2.330
statusicell1 U(0,5) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.696
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,5) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.336
macrocell5 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 3.100
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.320
macrocell6 U(0,5) 1 \PWM_1:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 3.100
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.320
macrocell7 U(0,5) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_474/main_1 3.100
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_474/main_1 2.320
macrocell8 U(0,5) 1 Net_474 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 3.541
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,5) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.291
macrocell7 U(0,5) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_474/main_0 4.145
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_474/main_0 2.895
macrocell8 U(0,5) 1 Net_474 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 4.151
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.901
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 6.299
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 1.810
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 4.489
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 7.805
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:status_2\/main_0 2.892
macrocell2 U(0,5) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_0 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.313
statusicell1 U(0,5) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q Net_853/main_0 3.846
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
Route 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q Net_853/main_0 2.596
macrocell79 U(1,2) 1 Net_853 HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\/main_0 3.846
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
Route 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\/main_0 2.596
macrocell81 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:nrq_reg\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\ADC_SAR_Seq_1:Sync:genblk1[0]:INST\/out \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/main_1 3.230
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 \ADC_SAR_Seq_1:Sync:genblk1[0]:INST\ \ADC_SAR_Seq_1:Sync:genblk1[0]:INST\/clock \ADC_SAR_Seq_1:Sync:genblk1[0]:INST\/out 0.350
Route 1 \ADC_SAR_Seq_1:Net_3935\ \ADC_SAR_Seq_1:Sync:genblk1[0]:INST\/out \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/main_1 2.880
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/main_0 3.840
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\/main_0 2.590
macrocell80 U(1,2) 1 \ADC_SAR_Seq_1:bSAR_SEQ:bus_clk_nrq_reg\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_474/q Pin_2(0)_PAD 24.258
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,5) 1 Net_474 Net_474/clock_0 Net_474/q 1.250
Route 1 Net_474 Net_474/q Pin_2(0)/pin_input 7.538
iocell2 P1[2] 1 Pin_2(0) Pin_2(0)/pin_input Pin_2(0)/pad_out 15.470
Route 1 Pin_2(0)_PAD Pin_2(0)/pad_out Pin_2(0)_PAD 0.000
Clock Clock path delay 0.000
Net_474/q Pin_1(0)_PAD 23.971
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,5) 1 Net_474 Net_474/clock_0 Net_474/q 1.250
Route 1 Net_474 Net_474/q Pin_1(0)/pin_input 7.470
iocell1 P0[0] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 15.251
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK
Source Destination Delay (ns)
\Control_Reg_1:Sync:ctrl_reg\/control_1 Pin_4(0)_PAD 27.160
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_1 \Control_Reg_1:Sync:ctrl_reg\/control_1 Pin_4(0)/pin_input 9.549
iocell4 P0[6] 1 Pin_4(0) Pin_4(0)/pin_input Pin_4(0)/pad_out 15.561
Route 1 Pin_4(0)_PAD Pin_4(0)/pad_out Pin_4(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_4 Pin_7(0)_PAD 26.622
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_4 2.050
Route 1 Net_5 \Control_Reg_1:Sync:ctrl_reg\/control_4 Pin_7(0)/pin_input 8.828
iocell7 P0[3] 1 Pin_7(0) Pin_7(0)/pin_input Pin_7(0)/pad_out 15.744
Route 1 Pin_7(0)_PAD Pin_7(0)/pad_out Pin_7(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_2 Pin_5(0)_PAD 26.579
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_2 \Control_Reg_1:Sync:ctrl_reg\/control_2 Pin_5(0)/pin_input 9.506
iocell5 P0[5] 1 Pin_5(0) Pin_5(0)/pin_input Pin_5(0)/pad_out 15.023
Route 1 Pin_5(0)_PAD Pin_5(0)/pad_out Pin_5(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 Pin_3(0)_PAD 26.507
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_4 \Control_Reg_1:Sync:ctrl_reg\/control_0 Pin_3(0)/pin_input 8.962
iocell3 P0[7] 1 Pin_3(0) Pin_3(0)/pin_input Pin_3(0)/pad_out 15.495
Route 1 Pin_3(0)_PAD Pin_3(0)/pad_out Pin_3(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_5 Pin_8(0)_PAD 26.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_5 2.050
Route 1 Net_6 \Control_Reg_1:Sync:ctrl_reg\/control_5 Pin_8(0)/pin_input 8.970
iocell8 P0[2] 1 Pin_8(0) Pin_8(0)/pin_input Pin_8(0)/pad_out 15.459
Route 1 Pin_8(0)_PAD Pin_8(0)/pad_out Pin_8(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_3 Pin_6(0)_PAD 26.432
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_3 \Control_Reg_1:Sync:ctrl_reg\/control_3 Pin_6(0)/pin_input 9.502
iocell6 P0[4] 1 Pin_6(0) Pin_6(0)/pin_input Pin_6(0)/pad_out 14.880
Route 1 Pin_6(0)_PAD Pin_6(0)/pad_out Pin_6(0)_PAD 0.000
Clock Clock path delay 0.000