Infotech Category

Dr. Rajeev Surati

Dr. Rajeev Surati is the President and Founder at Scalable Display Technologies. A founder and inventor, Rajeev has built several successful companies and been granted five patents to date including the core patent for Scalable Display Technologies. Among Rajeev’s many inventions are Enterprise Instant Messaging (for Flash Communications) and the distributed “Application push over HTTP” system (for Nexaweb). At Photo.net Corporation, which Rajeev cofounded, he was responsible for running the first photo-sharing site on the Web. He also cofounded Flash Communications, subsequently sold to Microsoft. Rajeev serves on the Boards of Tao Group and Photo.net. and the advisory board of Prematics and Nexaweb Corporations. Rajeev’s Ph.D. from MIT focused on projector/camera feedback systems.

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Mr. Sumeet Singh

Mr. Sumeet Singh is a perfect example of combining high quality research with entrepreneurship. During his graduate studies at the University of California, San Diego, he worked on enabling scalable processing of packets in routers (and network appliances) for content processing and security applications. His work primarily focused on creating scalable algorithms that can automatically generate precise content based signatures for network worms. His research led to several patents (pending) on automated worm detection and papers in top conferences such as SOGCOMM, OSDI, ISCA, and INFOCOM. On the basis of his research on “Automated Worm Fingerprinting”, he cofounded NetSift, Inc. which was acquired a year later by Cisco systems. Currently, he is a member of the CTO Group at Cisco Systems. His current research focuses on conceptualizing and designing custom high speed processors that will enable line-rate content inspection, fine-grained network analytics, and anomaly detection capabilities on all links going in and coming out of a switch. He was the lead architect of the first wire-speed 20Gbps content processing and network analytics processor developed by Cisco Systems.

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Dr. Ram Kumar Krishnamurthy

Ram K. Krishnamurthy is a Senior Principal Research Engineer with the Microprocessor Technology Labs, Corporate Technology Group, of Intel Corporation, Hillsboro, OR, where he directs the high-performance and low-voltage circuits research group. His research at Intel is focused on development of novel high-performance and energy-efficient digital circuits for next generation microprocessors in deep sub-micron (sub-45nm) CMOS technologies, specializing in the areas of high-speed/low-power data-path design, special-purpose DSP accelerators and on-chip interconnects. His Ph.D. research focused on low-power DSP circuit design. He has been with Intel Corporation since 1998. Since 1999, he is an adjunct faculty of ECE, Oregon State University, where he teaches VLSI System Design. He holds 80 patents issued, has 70 patents pending and has published over 75 conference/journal papers. He has presented over 50 invited papers and lectures at various world-wide industry and academic forums. He serves as Intel´s representative on the SRC Design Sciences Task Force and on the program committees of the ISSCC, CICC, and SOC conferences, and as Guest Editor of the IEEE Journal of Solid-State Circuits. He served as the Technical Program Chair/General Chair for the 2005/2006 IEEE International SOC Conference and presently serves on the Conference’s Steering Committee. He has received over 15 Intel Division Recognition Awards during 1998-2008, the 2002 Outstanding Industry Mentor Award from SRC, the MIT Technology Review TR35 Innovator Award in 2006, Intel Award for most patents filed in 2001, most patents issued in 2003, and the Enterprise Group Recognition Award in 2002 for leading the design of industry´s first 10GHz 32-bit ALU that was presented at ISSCC 2002 and the 2001 Intel Developer Forum. He has received the Intel Achievement Award, Intel Corporation’s highest technical recognition award, twice in 2004 and 2008 for breakthrough research and development of novel high-performance execution core arithmetic technologies. His research interests are in high-performance/low-power datapath, DSP and interconnect circuit design. He is a Senior Member of IEEE.

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