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This invention consists of a tri-channel hetero-structure which has a tensile strained semiconductor layer, a compressively strained layer and a confining layer. The thicknesses and doping concentrations of the first two layers are optimized for wide ranges of performance enhancement. The third layer has a band offset with the second layer to confine carriers, and provides a diffusion barrier to the second layer over a large temperature range. A gate dielectric could be disposed over the first, the second or the third layer to form a MOSFET. A method of forming the above structure is also provided.

Improved Enhancement of P-type/N-type Metal-Oxide-Semiconductor Field Effect Transistors Preserved over a Large Processing Temperature Range

Keywords:
Metal-Oxide-Semiconductor field effect transistors (MOSFET), multi-layer structures, strained layers, semiconductor substrates

Applications:
Various electrical devices such as MOSFETs

Problem:
Need for higher currents in MOSFETs

Advantages:

High hole and electron mobilities

High performance over a large processing temperature range

Inventors:

Professor Eugene A. Fitzgerald(Department of Materials Science and Engineering, MIT)

Minjoo L. Lee (Department of Materials Science and Engineering, MIT)

Gupta Saurabh (Department of Materials Science and Engineering, MIT)

Intellectual Property:
US Patent Number 7,791,107, issued on September 7, 2010

Publications:
N/A

Improved Enhancement of P-type/N-type Metal-Oxide-Semiconductor Field Effect Transistors Preserved over a Large Processing Temperature Range

Keywords: Metal-Oxide-Semiconductor field effect transistors (MOSFET), multi-layer structures, strained layers, semiconductor substrates

Applications: Various electrical devices such as MOSFETs

Problem: Need for higher currents in MOSFETs

Advantages: High hole and electron mobilities High performance over a large processing temperature range

Inventors: Professor Eugene A. Fitzgerald(Department of Materials Science and Engineering, MIT) Minjoo L. Lee (Department of Materials Science and Engineering, MIT) Gupta Saurabh (Department of Materials Science and Engineering, MIT)

Intellectual Property: US Patent Number 7,791,107, issued on September 7, 2010

Publications: N/A