I'm in the third year of my graduate program in Computer Science at MIT. I did my Masters in Electrical Engineering at MIT and my Bachelors in Computer Science at the Indian Institute of Technology Madras (IIT Madras).
1. 'A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs', Proceedings of the 40th IEEE/ACM International Symposium on Microarchitecture (MICRO 2007) pdf
2. 'CAD for 3-Dimensional FPGAs', Master's thesis, Massachusetts Institute of Technology, May 2007 pdf
3. 'Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM-based FPGAs', 2005 Military Applications for Programmable Logic Devices (MAPLD 2005) International Conference, Washington D.C., U.S.A. pdf
4. 'An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs', 19th International Conference on VLSI Design (VLSI 2006), Hyderabad, India pdf
5. 'Efficient Methodology for Detection and Correction of SEU-based Interconnect Errors in FPGAs using Partial Reconfiguration', 2005 ACM/SIGDA Thirteenth International Symposium on Field-Programmable Gate Arrays (FPGA 2005), Monterey, California, U.S.A.
6. 'Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-based FPGAs', Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2005) pdf
7. 'Efficient Methodology for Detection and Correction of SEU-based Interconnect Errors in FPGAs using Partial Reconfiguration', 10th European Test Symposium (ETS 2005), Tallinn, Estonia (submitted with permission of FPGA 2005)
8. 'A CLB Architecture for Online Correction of SEU-based Errors in LUTs of SRAM-based FPGAs', 10th European Test Symposium (ETS 2005), Tallinn, Estonia
9. 'A Function Generator-based Reconfigurable System', Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005), Shanghai, China pdf
10. 'Cluster-based Detection of SEU-caused Errors in LUTs of SRAM-based FPGAs', Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005), Shanghai, China pdf
11. 'A Novel CLB Architecture and Circuit Packing Algorithm for Logic-Area Reduction in SRAM-based FPGAs', Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005), Shanghai, China pdf
12. 'Detection of Routing Errors due to SEUs in SRAM-based FPGAs', 18th International Conference on VLSI Design (VLSI 2005), Kolkata, India pdf
13. 'A Novel CLB Architecture to Detect and Correct SEU in LUTs of SRAM-based FPGAs', 2004 International Conference on Field-Programmable Technology, (FPT 2004), Brisbane, Australia pdf