Received: from PACIFIC-CARRIER-ANNEX.MIT.EDU by po9.MIT.EDU (5.61/4.7) id AA19981; Wed, 24 Nov 99 12:06:41 EST Received: from elch.de.uu.net by MIT.EDU with SMTP id AA25276; Wed, 24 Nov 99 12:07:12 EST Received: from aiolos.camaronet.de (pec-3-191.tnt2.s2.uunet.de [149.225.3.191]) by elch.de.uu.net (5.5.5/5.5.5) with ESMTP id SAA04197 for ; Wed, 24 Nov 1999 18:04:40 +0100 (MET) Received: from aiolos.camaronet.de (aiolos.camaronet.de [192.168.177.2]) by aiolos.camaronet.de (8.9.1b+Sun/8.9.1) with ESMTP id RAA13197 for ; Wed, 24 Nov 1999 17:37:10 +0100 (MET) Date: Wed, 24 Nov 1999 17:37:10 +0100 (MET) From: Michael Kukat To: John Carr Subject: VLC (was Re: VAX 6310) (fwd) Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII And this is Antonios info: ...Michael -- Michael@camaronet.de, Rottweil/Germany, http://www.camaronet.de Visit the german VAXpage: http://www.vaxpower.de ---------- Forwarded message ---------- Subject: VLC (was Re: VAX 6310) "michael@camaronet.de" "Michael Kukat" wrote on 4-MAY-1999 16:51:34.03 >Hmmm. Maybe. If i find the time. But first i want to complete my VS 4000 >VLC port (cache still doesn't work, don't know about initialization, and >uninitialized, the machine doesn't run very long). Well VLC uses the SOC chip and only has the primary on-chip cache i.e. there is no other cache in the system. Any document that describes the SOC chip will do nicely, just in case you don't have one here is a summary: IPR 0x25: Cache Control register (CCR) bit 2: enable cache bit 1: flush cache bit 0: diag mode When diag mode is on you can write to the cache data happen in the range 0x20150400-0x201507ff and tags in the range 0x2015000 to 0x201503ff BEHR (0x20150800) (LW access only) bits 0:7 - enable each of 8 banks (turn all on) bits 8:15 - read only bank hit bits used for testing To turn on the cache do something like: a) Set CCR bit 0 to 1 to enable diag mode b) enable all banks in BEHR c) write all tags with V=0 This has now effectively flushed the cache d) turn off diag mode and turn on the cache (I think you can do this in one go by writing 0x04 to IPR 0x25. If you need more detail pick up EK-KA660-TM KA660 CPU Module Technical Manual. This is for the VAX 4000-200 ignore references to a backup cache since the VLC doesn't have one but the VAX 4000-200 uses the same SOC chip as the VLC so the primary cache organisation must be the same and the relevant control registers must also be the same (I guess ...) Antonio