Liquid Metal aims to exploit the increasing availability of FPGAs to offer end-to-end high-performance and low-power solutions for a broad range of applications. The challenge is that FPGA programming remains a difficult, time-consuming task and resources are often left under-utilized. The project aims to create a single unified programming language and environment that allows (all) portions of a system to move fluidly between hardware and software, dynamically and adaptively.

For more information, visit the Liquid Metal webpage.

The StreamIt project involves the design and evaluation of a novel language for streaming and signal processing applications, and a powerful optimizing compiler for commercial off-the-shelf DSP architectures, conventional CPUs, server farms, and emerging tiled-processor architectures. The ultimate goal of the StreamIt project is to develop a practical, high-level stream language that is easy to use but achieves the performance of hand-coded C and assembly code for DSP applications.

For more information, visit the StreamIt webpage.

StreamBit is a compiler that aims to increase productivity in the development of applications that process streams at the bit level. Such bit-stream programs occur in several domains such as cryptography and coding, and they are characterized by strong performance requirements and huge performance differences between highly tuned implementations and more naively written ones. For this reason, widely used implementations often combine clever high-level optimizations with careful low-level coding. StreamBit combines StreamIt with optimization sketches to allow for separation of concerns between the algorithm specification and the implementation details, greatly simplifying the development process.

For more information, visit the StreamBit webpage.

Understanding the behavior and characteristics of an applications is central to architecture design, auto-configuration and evaluation, as well as modern compilation infrastructures. Much of the work on understanding the behavior of a running program has focused on the discovery of "phases" or logical boundaries of program execution. Toward this goal, modern architectures have begun to offer various performance counters intended to aid performance monitoring environments in the hope they can lead to better understanding of the application behavior. This project has three goals. The first is to understand how program behavior varies with its input workload. The second is to deliver a set of robust algorithms for the discovery of program phases. The third goal is to use the program characteristics to drive the investigation of various high-impact and low-cost architecture and ISA modifications.

For more information, visit the VersaBench webpage.

Adaptive and Cooperative Execution (ACE) allows a program to adapt its behavior to runtime information communicated to it by the architecture. ACE relies on the compiler to orchestrate and embed within a program a set of precomputation chains that lead to runtime speculation geared toward faster (and more efficient) program execution. This project aims to extend the ACE prototype and build on its early success to tackle challenging problems in modern systems.

For more information, read our recent papers in ASPLOS 2004 and WBIA 2005.

The Reptile project is focused on innovating compilation techniques to effectively parallelize C programs for the emerging class of tiled-processor architectures. Our immediate emphasis is on the MIT Raw processor, an architecture designed to address the challenges that limit the scalability of current monolithic systems. Raw is a distributed and wired-exposed processors, with sixteen simple cores and compiled-controlled interconnect. Raw affords massive levels of parallelism and bandwidth, but as with any tiled-processor, it increases the burden on the compiler to effectively parallelize programs implemented in the traditional von Neumann model of computation (e.g., C programs).

Stay tuned for more information.

Trimaran is a publicly available compilation and simulation framework for VLIW research. It is based on the HPL-PD parameterized processor architecture which supports novel features such as predication, control and data speculation, and compiler controlled management of the memory hierarchy. The HPL-PD is a precursor to the Intel Itanium Processor Family. Trimaran consists of a full suite of analysis and optimization modules, as well as a graph-based intermediate language. Optimizations and analysis modules can be easily added, deleted or bypassed, thus facilitating compiler optimization research. Similarly, computer architecture research can be conducted by varying the HPL-PD configuration via a machine description language, or through extension to the detailed simulation environment.

For more information, visit the Trimaran webpage.