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//*****************************************************************************


//   ____  ____


//  /   /\/   /


// /___/  \  /    Vendor             : Xilinx


// \   \   \/     Version            : 4.2


//  \   \         Application        : MIG


//  /   /         Filename           : mig_7series_0.v


// /___/   /\     Date Last Modified : $Date: 2011/06/02 08:35:03 $


// \   \  /  \    Date Created       : Fri Oct 14 2011


//  \___\/\___\


//


// Device           : 7 Series


// Design Name      : DDR2 SDRAM


// Purpose          :


//   Wrapper module for the user design top level file. This module can be 


//   instantiated in the system and interconnect as shown in example design 


//   (example_top module).


// Reference        :


// Revision History :


//*****************************************************************************





`timescale 1ps/1ps





module mig_7series_0 (


   // Inouts


   inout [15:0]                         ddr2_dq,


   inout [1:0]                        ddr2_dqs_n,


   inout [1:0]                        ddr2_dqs_p,


   // Outputs


   output [12:0]                       ddr2_addr,


   output [2:0]                      ddr2_ba,


   output                                       ddr2_ras_n,


   output                                       ddr2_cas_n,


   output                                       ddr2_we_n,


   output [0:0]                        ddr2_ck_p,


   output [0:0]                        ddr2_ck_n,


   output [0:0]                       ddr2_cke,


   output [0:0]           ddr2_cs_n,


   output [1:0]                        ddr2_dm,


   output [0:0]                       ddr2_odt,


   // Inputs


   // Single-ended system clock


   input                                        sys_clk_i,


   // user interface signals


   input [26:0]                       app_addr,


   input [2:0]                                  app_cmd,


   input                                        app_en,


   input [127:0]    app_wdf_data,


   input                                        app_wdf_end,


   input [15:0]  app_wdf_mask,


   input                                        app_wdf_wren,


   output [127:0]   app_rd_data,


   output                                       app_rd_data_end,


   output                                       app_rd_data_valid,


   output                                       app_rdy,


   output                                       app_wdf_rdy,


   input                                        app_sr_req,


   input                                        app_ref_req,


   input                                        app_zq_req,


   output                                       app_sr_active,


   output                                       app_ref_ack,


   output                                       app_zq_ack,


   output                                       ui_clk,


   output                                       ui_clk_sync_rst,


   output                                       init_calib_complete,


   input  [11:0]                                device_temp_i,


                      // The 12 MSB bits of the temperature sensor transfer


                      // function need to be connected to this port. This port


                      // will be synchronized w.r.t. to fabric clock internally.


  input			sys_rst


  );





// Start of IP top instance


  mig_7series_0_mig u_mig_7series_0_mig (





    // Memory interface ports


    .ddr2_addr                      (ddr2_addr),


    .ddr2_ba                        (ddr2_ba),


    .ddr2_cas_n                     (ddr2_cas_n),


    .ddr2_ck_n                      (ddr2_ck_n),


    .ddr2_ck_p                      (ddr2_ck_p),


    .ddr2_cke                       (ddr2_cke),


    .ddr2_ras_n                     (ddr2_ras_n),


    .ddr2_we_n                      (ddr2_we_n),


    .ddr2_dq                        (ddr2_dq),


    .ddr2_dqs_n                     (ddr2_dqs_n),


    .ddr2_dqs_p                     (ddr2_dqs_p),


    .init_calib_complete            (init_calib_complete),


      


    .ddr2_cs_n                      (ddr2_cs_n),


    .ddr2_dm                        (ddr2_dm),


    .ddr2_odt                       (ddr2_odt),


    // Application interface ports


    .app_addr                       (app_addr),


    .app_cmd                        (app_cmd),


    .app_en                         (app_en),


    .app_wdf_data                   (app_wdf_data),


    .app_wdf_end                    (app_wdf_end),


    .app_wdf_wren                   (app_wdf_wren),


    .app_rd_data                    (app_rd_data),


    .app_rd_data_end                (app_rd_data_end),


    .app_rd_data_valid              (app_rd_data_valid),


    .app_rdy                        (app_rdy),


    .app_wdf_rdy                    (app_wdf_rdy),


    .app_sr_req                     (app_sr_req),


    .app_ref_req                    (app_ref_req),


    .app_zq_req                     (app_zq_req),


    .app_sr_active                  (app_sr_active),


    .app_ref_ack                    (app_ref_ack),


    .app_zq_ack                     (app_zq_ack),


    .ui_clk                         (ui_clk),


    .ui_clk_sync_rst                (ui_clk_sync_rst),


      


    .app_wdf_mask                   (app_wdf_mask),


      


    // System Clock Ports


    .sys_clk_i                       (sys_clk_i),


    .device_temp_i                  (device_temp_i),


    .sys_rst                        (sys_rst)


    );


// End of IP top instance





endmodule







