-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
-- Date        : Sat Oct 31 11:28:53 2020
-- Host        : I5-TWO running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               D:/f2020_6111/looper/looper_speed3/looper_speed3.srcs/sources_1/ip/mig_7series_0/mig_7series_0_sim_netlist.vhdl
-- Design      : mig_7series_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a100tcsg324-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_arb_select is
  port (
    \col_mux.col_periodic_rd_r\ : out STD_LOGIC;
    col_rd_wr_r : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    rnk_config_r : out STD_LOGIC;
    DIC : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    col_rd_wr : in STD_LOGIC;
    cke_r_reg_0 : in STD_LOGIC;
    cke_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_arb_select : entity is "mig_7series_v4_2_arb_select";
end mig_7series_0_mig_7series_v4_2_arb_select;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_arb_select is
begin
cke_r_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => cke_r_reg_1(0),
      Q => D(0),
      S => cke_r_reg_0
    );
\col_mux.col_periodic_rd_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => DIC(0),
      Q => \col_mux.col_periodic_rd_r\,
      R => '0'
    );
\col_mux.col_rd_wr_r_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => col_rd_wr,
      Q => col_rd_wr_r,
      R => '0'
    );
\rnk_config_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in,
      Q => rnk_config_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_bank_common is
  port (
    accept_internal_r : out STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : out STD_LOGIC;
    was_wr : out STD_LOGIC;
    \generate_maint_cmds.insert_maint_r_lcl_reg_0\ : out STD_LOGIC;
    maint_wip_r : out STD_LOGIC;
    periodic_rd_cntr_r_reg_0 : out STD_LOGIC;
    was_priority : out STD_LOGIC;
    hi_priority : out STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_1 : out STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_2 : out STD_LOGIC;
    periodic_rd_insert : out STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_0\ : out STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_3 : out STD_LOGIC;
    rb_hit_busy_r_reg : out STD_LOGIC;
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_4 : out STD_LOGIC;
    accept_r_reg_0 : out STD_LOGIC;
    \generate_maint_cmds.insert_maint_r_lcl_reg_1\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__12\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    p_9_in : in STD_LOGIC;
    CLK : in STD_LOGIC;
    periodic_rd_ack_ns : in STD_LOGIC;
    accept_ns : in STD_LOGIC;
    was_wr0 : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    periodic_rd_cntr_r_reg_1 : in STD_LOGIC;
    req_periodic_rd_r_lcl_reg : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    was_priority_reg_0 : in STD_LOGIC;
    app_en_r2 : in STD_LOGIC;
    \q_entry_r_reg[1]\ : in STD_LOGIC;
    p_13_out : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_1\ : in STD_LOGIC;
    rb_hit_busy_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    inhbt_act_faw_r : in STD_LOGIC;
    \grant_r[3]_i_2__1\ : in STD_LOGIC;
    \grant_r[3]_i_2__1_0\ : in STD_LOGIC;
    \grant_r[3]_i_2__1_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r[3]_i_2__1_2\ : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_bank_common : entity is "mig_7series_v4_2_bank_common";
end mig_7series_0_mig_7series_v4_2_bank_common;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_bank_common is
  signal accept_r_reg_n_0 : STD_LOGIC;
  signal \generate_maint_cmds.insert_maint_ns\ : STD_LOGIC;
  signal \^generate_maint_cmds.insert_maint_r_lcl_reg_0\ : STD_LOGIC;
  signal \^hi_priority\ : STD_LOGIC;
  signal \maint_controller.maint_rdy\ : STD_LOGIC;
  signal \maint_controller.maint_rdy_r1\ : STD_LOGIC;
  signal \maint_controller.maint_rdy_r1_i_2_n_0\ : STD_LOGIC;
  signal \maint_controller.maint_srx_r1\ : STD_LOGIC;
  signal \maint_controller.maint_wip_ns\ : STD_LOGIC;
  signal \^maint_controller.maint_wip_r_lcl_reg_0\ : STD_LOGIC;
  signal \^maint_wip_r\ : STD_LOGIC;
  signal \^periodic_rd_ack_r_lcl_reg_0\ : STD_LOGIC;
  signal periodic_rd_cntr_r_i_1_n_0 : STD_LOGIC;
  signal \^periodic_rd_cntr_r_reg_0\ : STD_LOGIC;
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0\ : STD_LOGIC;
  signal \^was_priority\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \maint_controller.maint_rdy_r1_i_2\ : label is "soft_lutpair594";
  attribute SOFT_HLUTNM of \maint_controller.maint_wip_r_lcl_i_2\ : label is "soft_lutpair594";
  attribute SOFT_HLUTNM of periodic_rd_cntr_r_i_1 : label is "soft_lutpair595";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_5__1\ : label is "soft_lutpair591";
  attribute SOFT_HLUTNM of q_has_priority_r_i_2 : label is "soft_lutpair591";
  attribute SOFT_HLUTNM of req_periodic_rd_r_lcl_i_1 : label is "soft_lutpair595";
  attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1\ : label is "soft_lutpair592";
  attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2\ : label is "soft_lutpair592";
  attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1\ : label is "soft_lutpair593";
  attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1\ : label is "soft_lutpair593";
begin
  \generate_maint_cmds.insert_maint_r_lcl_reg_0\ <= \^generate_maint_cmds.insert_maint_r_lcl_reg_0\;
  hi_priority <= \^hi_priority\;
  \maint_controller.maint_wip_r_lcl_reg_0\ <= \^maint_controller.maint_wip_r_lcl_reg_0\;
  maint_wip_r <= \^maint_wip_r\;
  periodic_rd_ack_r_lcl_reg_0 <= \^periodic_rd_ack_r_lcl_reg_0\;
  periodic_rd_cntr_r_reg_0 <= \^periodic_rd_cntr_r_reg_0\;
  was_priority <= \^was_priority\;
accept_internal_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_9_in,
      Q => accept_internal_r,
      R => '0'
    );
accept_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => accept_ns,
      Q => accept_r_reg_n_0,
      R => '0'
    );
\generate_maint_cmds.insert_maint_r_lcl_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maint_controller.maint_rdy_r1\,
      I1 => \maint_controller.maint_rdy\,
      I2 => \maint_controller.maint_srx_r1\,
      I3 => maint_srx_r,
      O => \generate_maint_cmds.insert_maint_ns\
    );
\generate_maint_cmds.insert_maint_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \generate_maint_cmds.insert_maint_ns\,
      Q => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      R => '0'
    );
\grant_r[3]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000100000000000"
    )
        port map (
      I0 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I1 => inhbt_act_faw_r,
      I2 => \grant_r[3]_i_2__1\,
      I3 => \grant_r[3]_i_2__1_0\,
      I4 => \grant_r[3]_i_2__1_1\(0),
      I5 => \grant_r[3]_i_2__1_2\,
      O => \generate_maint_cmds.insert_maint_r_lcl_reg_1\
    );
\maint_controller.maint_hit_busies_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => Q(0),
      R => '0'
    );
\maint_controller.maint_hit_busies_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => Q(1),
      R => '0'
    );
\maint_controller.maint_hit_busies_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(2),
      Q => Q(2),
      R => '0'
    );
\maint_controller.maint_hit_busies_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(3),
      Q => Q(3),
      R => '0'
    );
\maint_controller.maint_rdy_r1_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \maint_controller.maint_rdy_r1_i_2_n_0\,
      I1 => D(1),
      I2 => D(2),
      I3 => D(3),
      I4 => D(0),
      O => \maint_controller.maint_rdy\
    );
\maint_controller.maint_rdy_r1_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => \^periodic_rd_cntr_r_reg_0\,
      I1 => maint_req_r,
      I2 => \^maint_wip_r\,
      O => \maint_controller.maint_rdy_r1_i_2_n_0\
    );
\maint_controller.maint_rdy_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maint_controller.maint_rdy\,
      Q => \maint_controller.maint_rdy_r1\,
      R => '0'
    );
\maint_controller.maint_srx_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => maint_srx_r,
      Q => \maint_controller.maint_srx_r1\,
      R => '0'
    );
\maint_controller.maint_wip_r_lcl_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0000"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0\,
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2),
      I4 => \^maint_controller.maint_wip_r_lcl_reg_0\,
      O => \maint_controller.maint_wip_ns\
    );
\maint_controller.maint_wip_r_lcl_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => \^maint_wip_r\,
      I1 => maint_req_r,
      I2 => \^periodic_rd_cntr_r_reg_0\,
      I3 => \maint_controller.maint_wip_r_lcl_reg_1\,
      O => \^maint_controller.maint_wip_r_lcl_reg_0\
    );
\maint_controller.maint_wip_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maint_controller.maint_wip_ns\,
      Q => \^maint_wip_r\,
      R => '0'
    );
\pass_open_bank_r_lcl_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAA0000"
    )
        port map (
      I0 => \^periodic_rd_ack_r_lcl_reg_0\,
      I1 => was_priority_reg_0,
      I2 => app_en_r2,
      I3 => accept_r_reg_n_0,
      I4 => rb_hit_busy_r(0),
      O => periodic_rd_ack_r_lcl_reg_4
    );
\pass_open_bank_r_lcl_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAA0000"
    )
        port map (
      I0 => \^periodic_rd_ack_r_lcl_reg_0\,
      I1 => was_priority_reg_0,
      I2 => app_en_r2,
      I3 => accept_r_reg_n_0,
      I4 => rb_hit_busy_r(3),
      O => periodic_rd_ack_r_lcl_reg_3
    );
\pass_open_bank_r_lcl_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => rb_hit_busy_r(2),
      I1 => \^periodic_rd_ack_r_lcl_reg_0\,
      I2 => was_priority_reg_0,
      I3 => app_en_r2,
      I4 => accept_r_reg_n_0,
      O => rb_hit_busy_r_reg
    );
\pass_open_bank_r_lcl_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => rb_hit_busy_r(1),
      I1 => \^periodic_rd_ack_r_lcl_reg_0\,
      I2 => was_priority_reg_0,
      I3 => app_en_r2,
      I4 => accept_r_reg_n_0,
      O => rb_hit_busy_r_reg_0
    );
periodic_rd_ack_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => periodic_rd_ack_ns,
      Q => \^periodic_rd_ack_r_lcl_reg_0\,
      R => '0'
    );
periodic_rd_cntr_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => req_periodic_rd_r_lcl_reg,
      I1 => \^periodic_rd_ack_r_lcl_reg_0\,
      I2 => \^periodic_rd_cntr_r_reg_0\,
      O => periodic_rd_cntr_r_i_1_n_0
    );
periodic_rd_cntr_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => periodic_rd_cntr_r_i_1_n_0,
      Q => \^periodic_rd_cntr_r_reg_0\,
      R => periodic_rd_cntr_r_reg_1
    );
\q_entry_r[1]_i_5__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EAAA"
    )
        port map (
      I0 => \^periodic_rd_ack_r_lcl_reg_0\,
      I1 => was_priority_reg_0,
      I2 => app_en_r2,
      I3 => accept_r_reg_n_0,
      I4 => \q_entry_r_reg[1]\,
      O => periodic_rd_ack_r_lcl_reg_1
    );
\q_entry_r[1]_i_5__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => p_13_out,
      I1 => \^periodic_rd_ack_r_lcl_reg_0\,
      I2 => was_priority_reg_0,
      I3 => app_en_r2,
      I4 => accept_r_reg_n_0,
      O => periodic_rd_ack_r_lcl_reg_2
    );
q_has_priority_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => accept_r_reg_n_0,
      I1 => app_en_r2,
      I2 => was_priority_reg_0,
      I3 => \^periodic_rd_ack_r_lcl_reg_0\,
      O => accept_r_reg_0
    );
req_periodic_rd_r_lcl_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \^periodic_rd_ack_r_lcl_reg_0\,
      I1 => \^periodic_rd_cntr_r_reg_0\,
      I2 => req_periodic_rd_r_lcl_reg,
      O => periodic_rd_insert
    );
req_priority_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^was_priority\,
      I1 => was_priority_reg_0,
      O => \^hi_priority\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      I1 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(0)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AAAACECDAAAA"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\,
      I2 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      I5 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\,
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E1"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1),
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2),
      I3 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AAAACCDEAAAA"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\,
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2_n_0\,
      I3 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      I5 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\,
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF00D2000000D2"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2_n_0\,
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3),
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      I4 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I5 => maint_zq_r,
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(4)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1),
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0201"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0\,
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      I2 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(5)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000E0001"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0\,
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      I3 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(6)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1),
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3),
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1),
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2),
      I3 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      I5 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0\,
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3),
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(7),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010101010101001"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      I1 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\,
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(7),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6),
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      I5 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0\,
      O => \rstdiv0_sync_r1_reg_rep__12\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(0),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1_n_0\,
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1_n_0\,
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1_n_0\,
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(4),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(5),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(6),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\(0),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(7),
      R => '0'
    );
was_priority_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^hi_priority\,
      Q => \^was_priority\,
      R => '0'
    );
was_wr_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => was_wr0,
      Q => was_wr,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_bank_compare is
  port (
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    req_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_priority_r : out STD_LOGIC;
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    row_hit_r : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    req_wr_r_lcl_reg_0 : out STD_LOGIC;
    req_wr_r_lcl_reg_1 : out STD_LOGIC;
    start_wtp_timer0 : out STD_LOGIC;
    \req_row_r_lcl_reg[12]_0\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \req_data_buf_addr_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    periodic_rd_insert : in STD_LOGIC;
    CLK : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    p_28_out : in STD_LOGIC;
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \order_q_r_reg[1]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    ordered_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r_reg : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    req_bank_rdy_r_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    row : in STD_LOGIC_VECTOR ( 12 downto 0 );
    \req_data_buf_addr_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_data_buf_addr_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_bank_compare : entity is "mig_7series_v4_2_bank_compare";
end mig_7series_0_mig_7series_v4_2_bank_compare;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_bank_compare is
  signal rd_wr_ns : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \^req_row_r_lcl_reg[12]_0\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \^req_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^req_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal row_hit_ns : STD_LOGIC;
  signal \row_hit_ns_carry_i_1__2_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_2__2_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_3__2_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_4__2_n_0\ : STD_LOGIC;
  signal row_hit_ns_carry_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_1 : STD_LOGIC;
  signal row_hit_ns_carry_n_2 : STD_LOGIC;
  signal row_hit_ns_carry_n_3 : STD_LOGIC;
  signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of demand_priority_r_i_5 : label is "soft_lutpair582";
  attribute SOFT_HLUTNM of \rd_wr_r_lcl_i_1__0\ : label is "soft_lutpair582";
begin
  rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\;
  \req_row_r_lcl_reg[12]_0\(12 downto 0) <= \^req_row_r_lcl_reg[12]_0\(12 downto 0);
  req_wr_r(0) <= \^req_wr_r\(0);
  req_wr_r_lcl_reg_0 <= \^req_wr_r_lcl_reg_0\;
demand_priority_r_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => \^req_wr_r\(0),
      I1 => \^rd_wr_r_lcl_reg_0\,
      I2 => Q(0),
      O => req_wr_r_lcl_reg_1
    );
\order_q_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BDD4D442"
    )
        port map (
      I0 => \^req_wr_r_lcl_reg_0\,
      I1 => \order_q_r_reg[1]\(0),
      I2 => \order_q_r_reg[1]\(1),
      I3 => \order_q_r_reg[1]\(2),
      I4 => ordered_r(0),
      O => ordered_r_lcl_reg
    );
rb_hit_busy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_28_out,
      Q => rb_hit_busy_r_reg_0,
      R => '0'
    );
\rd_wr_r_lcl_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      I1 => Q(0),
      I2 => rd_wr_r_lcl_reg_1,
      I3 => rd_wr_r_lcl_reg_2,
      O => rd_wr_ns
    );
rd_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_ns,
      Q => \^rd_wr_r_lcl_reg_0\,
      R => '0'
    );
\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(0),
      Q => \req_bank_r_lcl_reg[2]_0\(0),
      R => '0'
    );
\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(1),
      Q => \req_bank_r_lcl_reg[2]_0\(1),
      R => '0'
    );
\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(2),
      Q => \req_bank_r_lcl_reg[2]_0\(2),
      R => '0'
    );
req_bank_rdy_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F55FFFFFFFFFFFF"
    )
        port map (
      I0 => req_bank_rdy_r_reg,
      I1 => \^req_wr_r\(0),
      I2 => \^rd_wr_r_lcl_reg_0\,
      I3 => Q(0),
      I4 => req_bank_rdy_r_reg_0,
      I5 => req_bank_rdy_r_reg_1,
      O => \^req_wr_r_lcl_reg_0\
    );
\req_col_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(0),
      Q => \req_col_r_reg[9]_0\(0),
      R => '0'
    );
\req_col_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(1),
      Q => \req_col_r_reg[9]_0\(1),
      R => '0'
    );
\req_col_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(2),
      Q => \req_col_r_reg[9]_0\(2),
      R => '0'
    );
\req_col_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(3),
      Q => \req_col_r_reg[9]_0\(3),
      R => '0'
    );
\req_col_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(4),
      Q => \req_col_r_reg[9]_0\(4),
      R => '0'
    );
\req_col_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(5),
      Q => \req_col_r_reg[9]_0\(5),
      R => '0'
    );
\req_col_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(6),
      Q => \req_col_r_reg[9]_0\(6),
      R => '0'
    );
\req_col_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(7),
      Q => \req_col_r_reg[9]_0\(7),
      R => '0'
    );
\req_col_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(8),
      Q => \req_col_r_reg[9]_0\(8),
      R => '0'
    );
\req_col_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(9),
      Q => \req_col_r_reg[9]_0\(9),
      R => '0'
    );
\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(0),
      Q => \req_data_buf_addr_r_reg[3]_0\(0),
      R => '0'
    );
\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(1),
      Q => \req_data_buf_addr_r_reg[3]_0\(1),
      R => '0'
    );
\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(2),
      Q => \req_data_buf_addr_r_reg[3]_0\(2),
      R => '0'
    );
\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(3),
      Q => \req_data_buf_addr_r_reg[3]_0\(3),
      R => '0'
    );
req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => periodic_rd_insert,
      Q => req_periodic_rd_r(0),
      R => '0'
    );
req_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => hi_priority,
      Q => req_priority_r,
      R => '0'
    );
\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(0),
      Q => \^req_row_r_lcl_reg[12]_0\(0),
      R => '0'
    );
\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(10),
      Q => \^req_row_r_lcl_reg[12]_0\(10),
      R => '0'
    );
\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(11),
      Q => \^req_row_r_lcl_reg[12]_0\(11),
      R => '0'
    );
\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(12),
      Q => \^req_row_r_lcl_reg[12]_0\(12),
      R => '0'
    );
\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(1),
      Q => \^req_row_r_lcl_reg[12]_0\(1),
      R => '0'
    );
\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(2),
      Q => \^req_row_r_lcl_reg[12]_0\(2),
      R => '0'
    );
\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(3),
      Q => \^req_row_r_lcl_reg[12]_0\(3),
      R => '0'
    );
\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(4),
      Q => \^req_row_r_lcl_reg[12]_0\(4),
      R => '0'
    );
\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(5),
      Q => \^req_row_r_lcl_reg[12]_0\(5),
      R => '0'
    );
\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(6),
      Q => \^req_row_r_lcl_reg[12]_0\(6),
      R => '0'
    );
\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(7),
      Q => \^req_row_r_lcl_reg[12]_0\(7),
      R => '0'
    );
\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(8),
      Q => \^req_row_r_lcl_reg[12]_0\(8),
      R => '0'
    );
\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(9),
      Q => \^req_row_r_lcl_reg[12]_0\(9),
      R => '0'
    );
req_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => req_wr_r_lcl0,
      Q => \^req_wr_r\(0),
      R => '0'
    );
row_hit_ns_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => row_hit_ns_carry_n_0,
      CO(2) => row_hit_ns_carry_n_1,
      CO(1) => row_hit_ns_carry_n_2,
      CO(0) => row_hit_ns_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0),
      S(3) => \row_hit_ns_carry_i_1__2_n_0\,
      S(2) => \row_hit_ns_carry_i_2__2_n_0\,
      S(1) => \row_hit_ns_carry_i_3__2_n_0\,
      S(0) => \row_hit_ns_carry_i_4__2_n_0\
    );
\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => row_hit_ns_carry_n_0,
      CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => row_hit_ns,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => row_hit_r_reg_0(0)
    );
\row_hit_ns_carry_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(10),
      I1 => row(10),
      I2 => \^req_row_r_lcl_reg[12]_0\(11),
      I3 => row(11),
      I4 => \^req_row_r_lcl_reg[12]_0\(9),
      I5 => row(9),
      O => \row_hit_ns_carry_i_1__2_n_0\
    );
\row_hit_ns_carry_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(7),
      I1 => row(7),
      I2 => \^req_row_r_lcl_reg[12]_0\(8),
      I3 => row(8),
      I4 => \^req_row_r_lcl_reg[12]_0\(6),
      I5 => row(6),
      O => \row_hit_ns_carry_i_2__2_n_0\
    );
\row_hit_ns_carry_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(4),
      I1 => row(4),
      I2 => \^req_row_r_lcl_reg[12]_0\(5),
      I3 => row(5),
      I4 => \^req_row_r_lcl_reg[12]_0\(3),
      I5 => row(3),
      O => \row_hit_ns_carry_i_3__2_n_0\
    );
\row_hit_ns_carry_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(1),
      I1 => row(1),
      I2 => \^req_row_r_lcl_reg[12]_0\(2),
      I3 => row(2),
      I4 => \^req_row_r_lcl_reg[12]_0\(0),
      I5 => row(0),
      O => \row_hit_ns_carry_i_4__2_n_0\
    );
row_hit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => row_hit_ns,
      Q => row_hit_r,
      R => '0'
    );
\wr_this_rank_r[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      O => start_wtp_timer0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_bank_compare_0 is
  port (
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    req_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_priority_r : out STD_LOGIC;
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    row_hit_r : out STD_LOGIC;
    rb_hit_busy_r_reg_1 : out STD_LOGIC;
    req_wr_r_lcl_reg_0 : out STD_LOGIC;
    start_wtp_timer0 : out STD_LOGIC;
    \req_row_r_lcl_reg[12]_0\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \req_data_buf_addr_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    periodic_rd_insert : in STD_LOGIC;
    CLK : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    p_67_out : in STD_LOGIC;
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \q_entry_r_reg[0]_0\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    row : in STD_LOGIC_VECTOR ( 12 downto 0 );
    \req_data_buf_addr_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_data_buf_addr_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_bank_compare_0 : entity is "mig_7series_v4_2_bank_compare";
end mig_7series_0_mig_7series_v4_2_bank_compare_0;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_bank_compare_0 is
  signal \^rb_hit_busy_r_reg_0\ : STD_LOGIC;
  signal rd_wr_ns : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \^req_row_r_lcl_reg[12]_0\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \^req_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal row_hit_ns : STD_LOGIC;
  signal \row_hit_ns_carry_i_1__1_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_2__1_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_3__1_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_4__1_n_0\ : STD_LOGIC;
  signal row_hit_ns_carry_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_1 : STD_LOGIC;
  signal row_hit_ns_carry_n_2 : STD_LOGIC;
  signal row_hit_ns_carry_n_3 : STD_LOGIC;
  signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rd_wr_r_lcl_i_1__1\ : label is "soft_lutpair572";
  attribute SOFT_HLUTNM of req_bank_rdy_r_i_5 : label is "soft_lutpair572";
begin
  rb_hit_busy_r_reg_0 <= \^rb_hit_busy_r_reg_0\;
  rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\;
  \req_row_r_lcl_reg[12]_0\(12 downto 0) <= \^req_row_r_lcl_reg[12]_0\(12 downto 0);
  req_wr_r(0) <= \^req_wr_r\(0);
\q_entry_r[0]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \q_entry_r_reg[0]\(2),
      I1 => \q_entry_r_reg[0]\(1),
      I2 => \^rb_hit_busy_r_reg_0\,
      I3 => \q_entry_r_reg[0]\(0),
      I4 => \q_entry_r_reg[0]_0\,
      O => rb_hit_busy_r_reg_1
    );
rb_hit_busy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_67_out,
      Q => \^rb_hit_busy_r_reg_0\,
      R => '0'
    );
\rd_wr_r_lcl_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      I1 => rd_wr_r_lcl_reg_1(0),
      I2 => rd_wr_r_lcl_reg_2,
      I3 => rd_wr_r_lcl_reg_3,
      O => rd_wr_ns
    );
rd_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_ns,
      Q => \^rd_wr_r_lcl_reg_0\,
      R => '0'
    );
\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(0),
      Q => \req_bank_r_lcl_reg[2]_0\(0),
      R => '0'
    );
\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(1),
      Q => \req_bank_r_lcl_reg[2]_0\(1),
      R => '0'
    );
\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(2),
      Q => \req_bank_r_lcl_reg[2]_0\(2),
      R => '0'
    );
req_bank_rdy_r_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => \^req_wr_r\(0),
      I1 => \^rd_wr_r_lcl_reg_0\,
      I2 => rd_wr_r_lcl_reg_1(0),
      O => req_wr_r_lcl_reg_0
    );
\req_col_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(0),
      Q => \req_col_r_reg[9]_0\(0),
      R => '0'
    );
\req_col_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(1),
      Q => \req_col_r_reg[9]_0\(1),
      R => '0'
    );
\req_col_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(2),
      Q => \req_col_r_reg[9]_0\(2),
      R => '0'
    );
\req_col_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(3),
      Q => \req_col_r_reg[9]_0\(3),
      R => '0'
    );
\req_col_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(4),
      Q => \req_col_r_reg[9]_0\(4),
      R => '0'
    );
\req_col_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(5),
      Q => \req_col_r_reg[9]_0\(5),
      R => '0'
    );
\req_col_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(6),
      Q => \req_col_r_reg[9]_0\(6),
      R => '0'
    );
\req_col_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(7),
      Q => \req_col_r_reg[9]_0\(7),
      R => '0'
    );
\req_col_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(8),
      Q => \req_col_r_reg[9]_0\(8),
      R => '0'
    );
\req_col_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(9),
      Q => \req_col_r_reg[9]_0\(9),
      R => '0'
    );
\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(0),
      Q => \req_data_buf_addr_r_reg[3]_0\(0),
      R => '0'
    );
\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(1),
      Q => \req_data_buf_addr_r_reg[3]_0\(1),
      R => '0'
    );
\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(2),
      Q => \req_data_buf_addr_r_reg[3]_0\(2),
      R => '0'
    );
\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(3),
      Q => \req_data_buf_addr_r_reg[3]_0\(3),
      R => '0'
    );
req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => periodic_rd_insert,
      Q => req_periodic_rd_r(0),
      R => '0'
    );
req_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => hi_priority,
      Q => req_priority_r,
      R => '0'
    );
\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(0),
      Q => \^req_row_r_lcl_reg[12]_0\(0),
      R => '0'
    );
\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(10),
      Q => \^req_row_r_lcl_reg[12]_0\(10),
      R => '0'
    );
\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(11),
      Q => \^req_row_r_lcl_reg[12]_0\(11),
      R => '0'
    );
\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(12),
      Q => \^req_row_r_lcl_reg[12]_0\(12),
      R => '0'
    );
\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(1),
      Q => \^req_row_r_lcl_reg[12]_0\(1),
      R => '0'
    );
\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(2),
      Q => \^req_row_r_lcl_reg[12]_0\(2),
      R => '0'
    );
\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(3),
      Q => \^req_row_r_lcl_reg[12]_0\(3),
      R => '0'
    );
\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(4),
      Q => \^req_row_r_lcl_reg[12]_0\(4),
      R => '0'
    );
\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(5),
      Q => \^req_row_r_lcl_reg[12]_0\(5),
      R => '0'
    );
\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(6),
      Q => \^req_row_r_lcl_reg[12]_0\(6),
      R => '0'
    );
\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(7),
      Q => \^req_row_r_lcl_reg[12]_0\(7),
      R => '0'
    );
\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(8),
      Q => \^req_row_r_lcl_reg[12]_0\(8),
      R => '0'
    );
\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(9),
      Q => \^req_row_r_lcl_reg[12]_0\(9),
      R => '0'
    );
req_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => req_wr_r_lcl0,
      Q => \^req_wr_r\(0),
      R => '0'
    );
row_hit_ns_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => row_hit_ns_carry_n_0,
      CO(2) => row_hit_ns_carry_n_1,
      CO(1) => row_hit_ns_carry_n_2,
      CO(0) => row_hit_ns_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0),
      S(3) => \row_hit_ns_carry_i_1__1_n_0\,
      S(2) => \row_hit_ns_carry_i_2__1_n_0\,
      S(1) => \row_hit_ns_carry_i_3__1_n_0\,
      S(0) => \row_hit_ns_carry_i_4__1_n_0\
    );
\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => row_hit_ns_carry_n_0,
      CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => row_hit_ns,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => row_hit_r_reg_0(0)
    );
\row_hit_ns_carry_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(10),
      I1 => row(10),
      I2 => \^req_row_r_lcl_reg[12]_0\(11),
      I3 => row(11),
      I4 => \^req_row_r_lcl_reg[12]_0\(9),
      I5 => row(9),
      O => \row_hit_ns_carry_i_1__1_n_0\
    );
\row_hit_ns_carry_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(7),
      I1 => row(7),
      I2 => \^req_row_r_lcl_reg[12]_0\(8),
      I3 => row(8),
      I4 => \^req_row_r_lcl_reg[12]_0\(6),
      I5 => row(6),
      O => \row_hit_ns_carry_i_2__1_n_0\
    );
\row_hit_ns_carry_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(3),
      I1 => row(3),
      I2 => \^req_row_r_lcl_reg[12]_0\(5),
      I3 => row(5),
      I4 => \^req_row_r_lcl_reg[12]_0\(4),
      I5 => row(4),
      O => \row_hit_ns_carry_i_3__1_n_0\
    );
\row_hit_ns_carry_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(1),
      I1 => row(1),
      I2 => \^req_row_r_lcl_reg[12]_0\(2),
      I3 => row(2),
      I4 => \^req_row_r_lcl_reg[12]_0\(0),
      I5 => row(0),
      O => \row_hit_ns_carry_i_4__1_n_0\
    );
row_hit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => row_hit_ns,
      Q => row_hit_r,
      R => '0'
    );
\wr_this_rank_r[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      O => start_wtp_timer0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_bank_compare_1 is
  port (
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    req_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_priority_r : out STD_LOGIC;
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    row_hit_r : out STD_LOGIC;
    req_wr_r_lcl_reg_0 : out STD_LOGIC;
    start_wtp_timer0 : out STD_LOGIC;
    \req_row_r_lcl_reg[12]_0\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \req_data_buf_addr_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    periodic_rd_insert : in STD_LOGIC;
    CLK : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    p_106_out : in STD_LOGIC;
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    row : in STD_LOGIC_VECTOR ( 12 downto 0 );
    \req_data_buf_addr_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_data_buf_addr_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_bank_compare_1 : entity is "mig_7series_v4_2_bank_compare";
end mig_7series_0_mig_7series_v4_2_bank_compare_1;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_bank_compare_1 is
  signal rd_wr_ns : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \^req_row_r_lcl_reg[12]_0\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \^req_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal row_hit_ns : STD_LOGIC;
  signal \row_hit_ns_carry_i_1__0_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_2__0_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_3__0_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_4__0_n_0\ : STD_LOGIC;
  signal row_hit_ns_carry_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_1 : STD_LOGIC;
  signal row_hit_ns_carry_n_2 : STD_LOGIC;
  signal row_hit_ns_carry_n_3 : STD_LOGIC;
  signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rd_wr_r_lcl_i_1__2\ : label is "soft_lutpair561";
  attribute SOFT_HLUTNM of req_bank_rdy_r_i_4 : label is "soft_lutpair561";
begin
  rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\;
  \req_row_r_lcl_reg[12]_0\(12 downto 0) <= \^req_row_r_lcl_reg[12]_0\(12 downto 0);
  req_wr_r(0) <= \^req_wr_r\(0);
rb_hit_busy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_106_out,
      Q => rb_hit_busy_r_reg_0,
      R => '0'
    );
\rd_wr_r_lcl_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      I1 => Q(0),
      I2 => rd_wr_r_lcl_reg_1,
      I3 => rd_wr_r_lcl_reg_2,
      O => rd_wr_ns
    );
rd_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_ns,
      Q => \^rd_wr_r_lcl_reg_0\,
      R => '0'
    );
\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(0),
      Q => \req_bank_r_lcl_reg[2]_0\(0),
      R => '0'
    );
\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(1),
      Q => \req_bank_r_lcl_reg[2]_0\(1),
      R => '0'
    );
\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(2),
      Q => \req_bank_r_lcl_reg[2]_0\(2),
      R => '0'
    );
req_bank_rdy_r_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => \^req_wr_r\(0),
      I1 => \^rd_wr_r_lcl_reg_0\,
      I2 => Q(0),
      O => req_wr_r_lcl_reg_0
    );
\req_col_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(0),
      Q => \req_col_r_reg[9]_0\(0),
      R => '0'
    );
\req_col_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(1),
      Q => \req_col_r_reg[9]_0\(1),
      R => '0'
    );
\req_col_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(2),
      Q => \req_col_r_reg[9]_0\(2),
      R => '0'
    );
\req_col_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(3),
      Q => \req_col_r_reg[9]_0\(3),
      R => '0'
    );
\req_col_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(4),
      Q => \req_col_r_reg[9]_0\(4),
      R => '0'
    );
\req_col_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(5),
      Q => \req_col_r_reg[9]_0\(5),
      R => '0'
    );
\req_col_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(6),
      Q => \req_col_r_reg[9]_0\(6),
      R => '0'
    );
\req_col_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(7),
      Q => \req_col_r_reg[9]_0\(7),
      R => '0'
    );
\req_col_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(8),
      Q => \req_col_r_reg[9]_0\(8),
      R => '0'
    );
\req_col_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(9),
      Q => \req_col_r_reg[9]_0\(9),
      R => '0'
    );
\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(0),
      Q => \req_data_buf_addr_r_reg[3]_0\(0),
      R => '0'
    );
\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(1),
      Q => \req_data_buf_addr_r_reg[3]_0\(1),
      R => '0'
    );
\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(2),
      Q => \req_data_buf_addr_r_reg[3]_0\(2),
      R => '0'
    );
\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(3),
      Q => \req_data_buf_addr_r_reg[3]_0\(3),
      R => '0'
    );
req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => periodic_rd_insert,
      Q => req_periodic_rd_r(0),
      R => '0'
    );
req_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => hi_priority,
      Q => req_priority_r,
      R => '0'
    );
\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(0),
      Q => \^req_row_r_lcl_reg[12]_0\(0),
      R => '0'
    );
\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(10),
      Q => \^req_row_r_lcl_reg[12]_0\(10),
      R => '0'
    );
\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(11),
      Q => \^req_row_r_lcl_reg[12]_0\(11),
      R => '0'
    );
\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(12),
      Q => \^req_row_r_lcl_reg[12]_0\(12),
      R => '0'
    );
\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(1),
      Q => \^req_row_r_lcl_reg[12]_0\(1),
      R => '0'
    );
\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(2),
      Q => \^req_row_r_lcl_reg[12]_0\(2),
      R => '0'
    );
\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(3),
      Q => \^req_row_r_lcl_reg[12]_0\(3),
      R => '0'
    );
\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(4),
      Q => \^req_row_r_lcl_reg[12]_0\(4),
      R => '0'
    );
\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(5),
      Q => \^req_row_r_lcl_reg[12]_0\(5),
      R => '0'
    );
\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(6),
      Q => \^req_row_r_lcl_reg[12]_0\(6),
      R => '0'
    );
\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(7),
      Q => \^req_row_r_lcl_reg[12]_0\(7),
      R => '0'
    );
\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(8),
      Q => \^req_row_r_lcl_reg[12]_0\(8),
      R => '0'
    );
\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(9),
      Q => \^req_row_r_lcl_reg[12]_0\(9),
      R => '0'
    );
req_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => req_wr_r_lcl0,
      Q => \^req_wr_r\(0),
      R => '0'
    );
row_hit_ns_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => row_hit_ns_carry_n_0,
      CO(2) => row_hit_ns_carry_n_1,
      CO(1) => row_hit_ns_carry_n_2,
      CO(0) => row_hit_ns_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0),
      S(3) => \row_hit_ns_carry_i_1__0_n_0\,
      S(2) => \row_hit_ns_carry_i_2__0_n_0\,
      S(1) => \row_hit_ns_carry_i_3__0_n_0\,
      S(0) => \row_hit_ns_carry_i_4__0_n_0\
    );
\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => row_hit_ns_carry_n_0,
      CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => row_hit_ns,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => row_hit_r_reg_0(0)
    );
\row_hit_ns_carry_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(10),
      I1 => row(10),
      I2 => \^req_row_r_lcl_reg[12]_0\(11),
      I3 => row(11),
      I4 => \^req_row_r_lcl_reg[12]_0\(9),
      I5 => row(9),
      O => \row_hit_ns_carry_i_1__0_n_0\
    );
\row_hit_ns_carry_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(7),
      I1 => row(7),
      I2 => \^req_row_r_lcl_reg[12]_0\(8),
      I3 => row(8),
      I4 => \^req_row_r_lcl_reg[12]_0\(6),
      I5 => row(6),
      O => \row_hit_ns_carry_i_2__0_n_0\
    );
\row_hit_ns_carry_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(4),
      I1 => row(4),
      I2 => \^req_row_r_lcl_reg[12]_0\(5),
      I3 => row(5),
      I4 => \^req_row_r_lcl_reg[12]_0\(3),
      I5 => row(3),
      O => \row_hit_ns_carry_i_3__0_n_0\
    );
\row_hit_ns_carry_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(1),
      I1 => row(1),
      I2 => \^req_row_r_lcl_reg[12]_0\(2),
      I3 => row(2),
      I4 => \^req_row_r_lcl_reg[12]_0\(0),
      I5 => row(0),
      O => \row_hit_ns_carry_i_4__0_n_0\
    );
row_hit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => row_hit_ns,
      Q => row_hit_r,
      R => '0'
    );
\wr_this_rank_r[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      O => start_wtp_timer0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_bank_compare_2 is
  port (
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    req_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_priority_r : out STD_LOGIC;
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    row_hit_r : out STD_LOGIC;
    req_wr_r_lcl_reg_0 : out STD_LOGIC;
    start_wtp_timer0 : out STD_LOGIC;
    \req_row_r_lcl_reg[12]_0\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    rb_hit_busy_r_reg_1 : out STD_LOGIC;
    rb_hit_busy_r_reg_2 : out STD_LOGIC;
    \req_data_buf_addr_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    periodic_rd_insert : in STD_LOGIC;
    CLK : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    p_145_out : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 2 downto 0 );
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    row : in STD_LOGIC_VECTOR ( 12 downto 0 );
    \head_r_lcl_i_2__1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_data_buf_addr_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_data_buf_addr_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_bank_compare_2 : entity is "mig_7series_v4_2_bank_compare";
end mig_7series_0_mig_7series_v4_2_bank_compare_2;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_bank_compare_2 is
  signal \^rb_hit_busy_r_reg_0\ : STD_LOGIC;
  signal rd_wr_ns : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \^req_row_r_lcl_reg[12]_0\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \^req_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal row_hit_ns : STD_LOGIC;
  signal row_hit_ns_carry_i_1_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_1 : STD_LOGIC;
  signal row_hit_ns_carry_n_2 : STD_LOGIC;
  signal row_hit_ns_carry_n_3 : STD_LOGIC;
  signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \head_r_lcl_i_4__1\ : label is "soft_lutpair548";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_8__1\ : label is "soft_lutpair548";
  attribute SOFT_HLUTNM of rd_wr_r_lcl_i_1 : label is "soft_lutpair547";
  attribute SOFT_HLUTNM of req_bank_rdy_r_i_3 : label is "soft_lutpair547";
begin
  rb_hit_busy_r_reg_0 <= \^rb_hit_busy_r_reg_0\;
  rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\;
  \req_row_r_lcl_reg[12]_0\(12 downto 0) <= \^req_row_r_lcl_reg[12]_0\(12 downto 0);
  req_wr_r(0) <= \^req_wr_r\(0);
\head_r_lcl_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7EE8"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg_0\,
      I1 => \head_r_lcl_i_2__1\(2),
      I2 => \head_r_lcl_i_2__1\(0),
      I3 => \head_r_lcl_i_2__1\(1),
      O => rb_hit_busy_r_reg_1
    );
\q_entry_r[1]_i_8__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg_0\,
      I1 => \head_r_lcl_i_2__1\(1),
      I2 => \head_r_lcl_i_2__1\(0),
      I3 => \head_r_lcl_i_2__1\(2),
      O => rb_hit_busy_r_reg_2
    );
rb_hit_busy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_145_out,
      Q => \^rb_hit_busy_r_reg_0\,
      R => '0'
    );
rd_wr_r_lcl_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      I1 => Q(0),
      I2 => rd_wr_r_lcl_reg_1,
      I3 => rd_wr_r_lcl_reg_2,
      O => rd_wr_ns
    );
rd_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_ns,
      Q => \^rd_wr_r_lcl_reg_0\,
      R => '0'
    );
\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(0),
      Q => \req_bank_r_lcl_reg[2]_0\(0),
      R => '0'
    );
\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(1),
      Q => \req_bank_r_lcl_reg[2]_0\(1),
      R => '0'
    );
\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \req_bank_r_lcl_reg[2]_1\(2),
      Q => \req_bank_r_lcl_reg[2]_0\(2),
      R => '0'
    );
req_bank_rdy_r_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => \^req_wr_r\(0),
      I1 => \^rd_wr_r_lcl_reg_0\,
      I2 => Q(0),
      O => req_wr_r_lcl_reg_0
    );
\req_col_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(0),
      Q => \req_col_r_reg[9]_0\(0),
      R => '0'
    );
\req_col_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(1),
      Q => \req_col_r_reg[9]_0\(1),
      R => '0'
    );
\req_col_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(2),
      Q => \req_col_r_reg[9]_0\(2),
      R => '0'
    );
\req_col_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(3),
      Q => \req_col_r_reg[9]_0\(3),
      R => '0'
    );
\req_col_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(4),
      Q => \req_col_r_reg[9]_0\(4),
      R => '0'
    );
\req_col_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(5),
      Q => \req_col_r_reg[9]_0\(5),
      R => '0'
    );
\req_col_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(6),
      Q => \req_col_r_reg[9]_0\(6),
      R => '0'
    );
\req_col_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(7),
      Q => \req_col_r_reg[9]_0\(7),
      R => '0'
    );
\req_col_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(8),
      Q => \req_col_r_reg[9]_0\(8),
      R => '0'
    );
\req_col_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \req_col_r_reg[9]_1\(9),
      Q => \req_col_r_reg[9]_0\(9),
      R => '0'
    );
\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(0),
      Q => \req_data_buf_addr_r_reg[3]_0\(0),
      R => '0'
    );
\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(1),
      Q => \req_data_buf_addr_r_reg[3]_0\(1),
      R => '0'
    );
\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(2),
      Q => \req_data_buf_addr_r_reg[3]_0\(2),
      R => '0'
    );
\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \req_data_buf_addr_r_reg[0]_0\(0),
      D => \req_data_buf_addr_r_reg[3]_1\(3),
      Q => \req_data_buf_addr_r_reg[3]_0\(3),
      R => '0'
    );
req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => periodic_rd_insert,
      Q => req_periodic_rd_r(0),
      R => '0'
    );
req_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => hi_priority,
      Q => req_priority_r,
      R => '0'
    );
\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(0),
      Q => \^req_row_r_lcl_reg[12]_0\(0),
      R => '0'
    );
\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(10),
      Q => \^req_row_r_lcl_reg[12]_0\(10),
      R => '0'
    );
\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(11),
      Q => \^req_row_r_lcl_reg[12]_0\(11),
      R => '0'
    );
\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(12),
      Q => \^req_row_r_lcl_reg[12]_0\(12),
      R => '0'
    );
\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(1),
      Q => \^req_row_r_lcl_reg[12]_0\(1),
      R => '0'
    );
\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(2),
      Q => \^req_row_r_lcl_reg[12]_0\(2),
      R => '0'
    );
\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(3),
      Q => \^req_row_r_lcl_reg[12]_0\(3),
      R => '0'
    );
\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(4),
      Q => \^req_row_r_lcl_reg[12]_0\(4),
      R => '0'
    );
\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(5),
      Q => \^req_row_r_lcl_reg[12]_0\(5),
      R => '0'
    );
\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(6),
      Q => \^req_row_r_lcl_reg[12]_0\(6),
      R => '0'
    );
\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(7),
      Q => \^req_row_r_lcl_reg[12]_0\(7),
      R => '0'
    );
\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(8),
      Q => \^req_row_r_lcl_reg[12]_0\(8),
      R => '0'
    );
\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => row(9),
      Q => \^req_row_r_lcl_reg[12]_0\(9),
      R => '0'
    );
req_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => req_wr_r_lcl0,
      Q => \^req_wr_r\(0),
      R => '0'
    );
row_hit_ns_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => row_hit_ns_carry_n_0,
      CO(2) => row_hit_ns_carry_n_1,
      CO(1) => row_hit_ns_carry_n_2,
      CO(0) => row_hit_ns_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0),
      S(3) => row_hit_ns_carry_i_1_n_0,
      S(2 downto 0) => S(2 downto 0)
    );
\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => row_hit_ns_carry_n_0,
      CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => row_hit_ns,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => row_hit_r_reg_0(0)
    );
row_hit_ns_carry_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^req_row_r_lcl_reg[12]_0\(9),
      I1 => row(9),
      I2 => row(11),
      I3 => \^req_row_r_lcl_reg[12]_0\(11),
      I4 => \^req_row_r_lcl_reg[12]_0\(10),
      I5 => row(10),
      O => row_hit_ns_carry_i_1_n_0
    );
row_hit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => row_hit_ns,
      Q => row_hit_r,
      R => '0'
    );
\wr_this_rank_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      O => start_wtp_timer0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_bank_queue is
  port (
    idle_r_lcl_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    wait_for_maint_r : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    pass_open_bank_ns : out STD_LOGIC;
    q_has_rd : out STD_LOGIC;
    tail_r : out STD_LOGIC;
    head_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    ordered_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    demand_priority_ns : out STD_LOGIC;
    \order_q_r_reg[0]_0\ : out STD_LOGIC;
    idle_r_lcl_reg_2 : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__10\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__10_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_9_in : out STD_LOGIC;
    pre_bm_end_r_reg_1 : out STD_LOGIC;
    q_entry_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_2 : out STD_LOGIC;
    pre_bm_end_r_reg_3 : out STD_LOGIC;
    idle_r_lcl_reg_3 : out STD_LOGIC;
    idle_r_lcl_reg_4 : out STD_LOGIC;
    idle_r_lcl_reg_5 : out STD_LOGIC;
    idle_r_lcl_reg_6 : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    CLK : in STD_LOGIC;
    pre_bm_end_ns : in STD_LOGIC;
    pre_passing_open_bank_ns : in STD_LOGIC;
    \q_entry_r_reg[0]_1\ : in STD_LOGIC;
    \q_entry_r_reg[1]_1\ : in STD_LOGIC;
    \q_entry_r_reg[1]_2\ : in STD_LOGIC;
    \q_entry_r_reg[1]_3\ : in STD_LOGIC;
    q_entry_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[1]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_reg : in STD_LOGIC;
    req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    col_wait_ns : in STD_LOGIC;
    demand_priority_r_reg : in STD_LOGIC;
    req_priority_r : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    demand_priority_r_reg_0 : in STD_LOGIC;
    demand_priority_r_reg_1 : in STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    \grant_r[3]_i_12\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    q_has_priority_r_reg_0 : in STD_LOGIC;
    q_has_priority_r_reg_1 : in STD_LOGIC;
    was_priority : in STD_LOGIC;
    was_wr : in STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    row_hit_r : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    pre_wait_r : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[0]\ : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    p_106_out : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ : in STD_LOGIC;
    p_67_out : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : in STD_LOGIC;
    p_28_out : in STD_LOGIC;
    p_13_out : in STD_LOGIC;
    accept_internal_r_reg : in STD_LOGIC;
    accept_internal_r_reg_0 : in STD_LOGIC;
    accept_internal_r_reg_1 : in STD_LOGIC;
    accept_internal_r_reg_2 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \q_entry_r_reg[1]_4\ : in STD_LOGIC;
    \q_entry_r_reg[1]_5\ : in STD_LOGIC;
    maint_sre_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    maint_rank_r : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    \q_entry_r[1]_i_2__0_0\ : in STD_LOGIC;
    accept_internal_r : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_2 : in STD_LOGIC;
    app_en_r2 : in STD_LOGIC;
    \act_wait_r_lcl_i_4__1_0\ : in STD_LOGIC;
    \act_wait_r_lcl_i_4__1_1\ : in STD_LOGIC;
    \act_wait_r_lcl_i_4__1_2\ : in STD_LOGIC;
    \q_entry_r_reg[0]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \grant_r[2]_i_3__0\ : in STD_LOGIC;
    ras_timer_zero_r : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    \order_q_r_reg[1]_0\ : in STD_LOGIC;
    \order_q_r_reg[0]_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_bank_queue : entity is "mig_7series_v4_2_bank_queue";
end mig_7series_0_mig_7series_v4_2_bank_queue;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_bank_queue is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \act_wait_r_lcl_i_5__1_n_0\ : STD_LOGIC;
  signal auto_pre_r_lcl_i_1_n_0 : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg_0\ : STD_LOGIC;
  signal \compute_tail.tail_r_lcl_i_1_n_0\ : STD_LOGIC;
  signal \^head_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal head_r_lcl_i_1_n_0 : STD_LOGIC;
  signal \head_r_lcl_i_2__0_n_0\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^idle_r_lcl_reg_1\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_2\ : STD_LOGIC;
  signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \order_q_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \order_q_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \^order_q_r_reg[0]_0\ : STD_LOGIC;
  signal \^ordered_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ordered_r_lcl_i_1_n_0 : STD_LOGIC;
  signal \^pass_open_bank_ns\ : STD_LOGIC;
  signal pass_open_bank_r_lcl_i_3_n_0 : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg_0\ : STD_LOGIC;
  signal pre_bm_end_r : STD_LOGIC;
  signal \^pre_bm_end_r_reg_0\ : STD_LOGIC;
  signal pre_passing_open_bank_r : STD_LOGIC;
  signal q_entry_ns_0 : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \q_entry_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_4__2_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_4__1_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_4__2_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_5__0_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_6__1_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_7__1_n_0\ : STD_LOGIC;
  signal q_entry_r_1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^q_entry_r_reg[0]_0\ : STD_LOGIC;
  signal q_has_priority : STD_LOGIC;
  signal q_has_priority_ns : STD_LOGIC;
  signal \^q_has_rd\ : STD_LOGIC;
  signal q_has_rd_ns : STD_LOGIC;
  signal \ras_timer_r[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_ns\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal rb_hit_busies_r : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \^rstdiv0_sync_r1_reg_rep__10\ : STD_LOGIC;
  signal set_order_q : STD_LOGIC;
  signal \^tail_r\ : STD_LOGIC;
  signal wait_for_maint_ns : STD_LOGIC;
  signal \^wait_for_maint_r\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \head_r_lcl_i_3__0\ : label is "soft_lutpair552";
  attribute SOFT_HLUTNM of idle_r_lcl_i_1 : label is "soft_lutpair549";
  attribute SOFT_HLUTNM of \maint_controller.maint_hit_busies_r[0]_i_1\ : label is "soft_lutpair549";
  attribute SOFT_HLUTNM of \q_entry_r[0]_i_3__0\ : label is "soft_lutpair554";
  attribute SOFT_HLUTNM of \q_entry_r[0]_i_3__1\ : label is "soft_lutpair554";
  attribute SOFT_HLUTNM of \q_entry_r[0]_i_3__2\ : label is "soft_lutpair551";
  attribute SOFT_HLUTNM of \q_entry_r[0]_i_4__2\ : label is "soft_lutpair550";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_10\ : label is "soft_lutpair555";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_3__0\ : label is "soft_lutpair550";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_3__2\ : label is "soft_lutpair553";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_4__0\ : label is "soft_lutpair555";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_4__2\ : label is "soft_lutpair551";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_6__1\ : label is "soft_lutpair552";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_9\ : label is "soft_lutpair553";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_1__2\ : label is "soft_lutpair556";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_1__2\ : label is "soft_lutpair556";
begin
  E(0) <= \^e\(0);
  auto_pre_r_lcl_reg_0 <= \^auto_pre_r_lcl_reg_0\;
  head_r(0) <= \^head_r\(0);
  idle_r_lcl_reg_0(0) <= \^idle_r_lcl_reg_0\(0);
  idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\;
  idle_r_lcl_reg_2 <= \^idle_r_lcl_reg_2\;
  \order_q_r_reg[0]_0\ <= \^order_q_r_reg[0]_0\;
  ordered_r(0) <= \^ordered_r\(0);
  pass_open_bank_ns <= \^pass_open_bank_ns\;
  pass_open_bank_r_lcl_reg_0 <= \^pass_open_bank_r_lcl_reg_0\;
  pre_bm_end_r_reg_0 <= \^pre_bm_end_r_reg_0\;
  \q_entry_r_reg[0]_0\ <= \^q_entry_r_reg[0]_0\;
  q_has_rd <= \^q_has_rd\;
  \rstdiv0_sync_r1_reg_rep__10\ <= \^rstdiv0_sync_r1_reg_rep__10\;
  tail_r <= \^tail_r\;
  wait_for_maint_r <= \^wait_for_maint_r\;
accept_internal_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => accept_internal_r_reg,
      I1 => \^idle_r_lcl_reg_2\,
      I2 => accept_internal_r_reg_0,
      I3 => accept_internal_r_reg_1,
      I4 => accept_internal_r_reg_2,
      O => p_9_in
    );
accept_internal_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000D"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => set_order_q,
      I2 => \^pre_bm_end_r_reg_0\,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      O => \^idle_r_lcl_reg_2\
    );
act_wait_r_lcl_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAEAEAEA"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => Q(0),
      I3 => bm_end_r1_reg,
      I4 => req_wr_r(0),
      I5 => pre_bm_end_r,
      O => \^rstdiv0_sync_r1_reg_rep__10\
    );
\act_wait_r_lcl_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => q_entry_r_1(0),
      I1 => q_entry_r_1(1),
      I2 => \^idle_r_lcl_reg_0\(0),
      I3 => \act_wait_r_lcl_i_5__1_n_0\,
      O => \^q_entry_r_reg[0]_0\
    );
\act_wait_r_lcl_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00808080"
    )
        port map (
      I0 => \grant_r[3]_i_12\(0),
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => Q(0),
      I3 => bm_end_r1_reg,
      I4 => req_wr_r(0),
      I5 => pre_passing_open_bank_r,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\
    );
\act_wait_r_lcl_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22F2FFFF22F222F2"
    )
        port map (
      I0 => rb_hit_busies_r(2),
      I1 => \act_wait_r_lcl_i_4__1_0\,
      I2 => rb_hit_busies_r(1),
      I3 => \act_wait_r_lcl_i_4__1_1\,
      I4 => \act_wait_r_lcl_i_4__1_2\,
      I5 => rb_hit_busies_r(3),
      O => \act_wait_r_lcl_i_5__1_n_0\
    );
auto_pre_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AEAEAEEE"
    )
        port map (
      I0 => \^auto_pre_r_lcl_reg_0\,
      I1 => auto_pre_r_lcl_reg_1,
      I2 => row_hit_r,
      I3 => \^wait_for_maint_r\,
      I4 => auto_pre_r_lcl_reg_2,
      I5 => \^rstdiv0_sync_r1_reg_rep__10\,
      O => auto_pre_r_lcl_i_1_n_0
    );
auto_pre_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => auto_pre_r_lcl_i_1_n_0,
      Q => \^auto_pre_r_lcl_reg_0\,
      R => '0'
    );
bm_end_r1_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAAAAAA"
    )
        port map (
      I0 => pre_bm_end_r,
      I1 => req_wr_r(0),
      I2 => bm_end_r1_reg,
      I3 => Q(0),
      I4 => \^pass_open_bank_r_lcl_reg_0\,
      O => \^pre_bm_end_r_reg_0\
    );
\compute_tail.tail_r_lcl_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF1F5F1FFF0F0F0"
    )
        port map (
      I0 => pass_open_bank_r_lcl_reg_1,
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => set_order_q,
      I3 => \compute_tail.tail_r_lcl_reg_0\,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => \^tail_r\,
      O => \compute_tail.tail_r_lcl_i_1_n_0\
    );
\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \compute_tail.tail_r_lcl_i_1_n_0\,
      Q => \^tail_r\,
      R => \q_entry_r_reg[0]_1\
    );
\demand_priority_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A2A2A000000000"
    )
        port map (
      I0 => col_wait_ns,
      I1 => \^order_q_r_reg[0]_0\,
      I2 => demand_priority_r_reg,
      I3 => req_priority_r,
      I4 => q_has_priority,
      I5 => \^idle_r_lcl_reg_2\,
      O => demand_priority_ns
    );
\demand_priority_r_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => demand_priority_r_reg_0,
      I1 => demand_priority_r_reg_1,
      I2 => demand_priority_r_reg_2,
      I3 => demand_priority_r_reg_3,
      I4 => order_q_r(0),
      I5 => order_q_r(1),
      O => \^order_q_r_reg[0]_0\
    );
\grant_r[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFF"
    )
        port map (
      I0 => \^head_r\(0),
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => \grant_r[2]_i_3__0\,
      I3 => ras_timer_zero_r,
      I4 => \^wait_for_maint_r\,
      O => head_r_lcl_reg_0
    );
granted_col_r_i_9: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40555555"
    )
        port map (
      I0 => pre_passing_open_bank_r,
      I1 => req_wr_r(0),
      I2 => bm_end_r1_reg,
      I3 => Q(0),
      I4 => \^pass_open_bank_r_lcl_reg_0\,
      O => pre_passing_open_bank_r_reg_0
    );
head_r_lcl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAFFEA00"
    )
        port map (
      I0 => \head_r_lcl_i_2__0_n_0\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => \^idle_r_lcl_reg_1\,
      I3 => \q_entry_r[1]_i_3__0_n_0\,
      I4 => \^head_r\(0),
      O => head_r_lcl_i_1_n_0
    );
\head_r_lcl_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000404F00004040"
    )
        port map (
      I0 => q_entry_r_1(1),
      I1 => q_entry_r_1(0),
      I2 => \q_entry_r[0]_i_4__2_n_0\,
      I3 => head_r_lcl_reg_1,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => \q_entry_r[0]_i_2__2_n_0\,
      O => \head_r_lcl_i_2__0_n_0\
    );
\head_r_lcl_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01168001"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => head_r_lcl_reg_2(0),
      I2 => head_r_lcl_reg_2(1),
      I3 => head_r_lcl_reg_2(2),
      I4 => q_has_priority_r_reg_1,
      O => \^idle_r_lcl_reg_1\
    );
head_r_lcl_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => head_r_lcl_i_1_n_0,
      Q => \^head_r\(0),
      S => \q_entry_r_reg[0]_1\
    );
idle_r_lcl_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^idle_r_lcl_reg_2\,
      O => \^e\(0)
    );
idle_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^e\(0),
      Q => \^idle_r_lcl_reg_0\(0),
      R => '0'
    );
\maint_controller.maint_hit_busies_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000F0002"
    )
        port map (
      I0 => \^idle_r_lcl_reg_2\,
      I1 => \maint_controller.maint_hit_busies_r_reg[0]\,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I3 => \^pre_bm_end_r_reg_0\,
      I4 => \maint_controller.maint_hit_busies_r_reg[0]_0\(0),
      O => \rstdiv0_sync_r1_reg_rep__10_0\(0)
    );
\order_q_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00470047FF444444"
    )
        port map (
      I0 => \order_q_r_reg[0]_1\,
      I1 => set_order_q,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I3 => req_bank_rdy_r_reg_0,
      I4 => order_q_r(1),
      I5 => order_q_r(0),
      O => \order_q_r[0]_i_1_n_0\
    );
\order_q_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF8B0088008B8888"
    )
        port map (
      I0 => \order_q_r_reg[1]_0\,
      I1 => set_order_q,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I3 => req_bank_rdy_r_reg_0,
      I4 => order_q_r(1),
      I5 => order_q_r(0),
      O => \order_q_r[1]_i_1_n_0\
    );
\order_q_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[0]_i_1_n_0\,
      Q => order_q_r(0),
      R => '0'
    );
\order_q_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[1]_i_1_n_0\,
      Q => order_q_r(1),
      R => '0'
    );
ordered_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454005400540054"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I1 => set_order_q,
      I2 => \^ordered_r\(0),
      I3 => Q(0),
      I4 => bm_end_r1_reg,
      I5 => req_wr_r(0),
      O => ordered_r_lcl_i_1_n_0
    );
ordered_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ordered_r_lcl_i_1_n_0,
      Q => \^ordered_r\(0),
      R => '0'
    );
pass_open_bank_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00000800"
    )
        port map (
      I0 => pass_open_bank_r_lcl_reg_1,
      I1 => \^tail_r\,
      I2 => pre_wait_r,
      I3 => pass_open_bank_r_lcl_i_3_n_0,
      I4 => \^rstdiv0_sync_r1_reg_rep__10\,
      I5 => \^pass_open_bank_r_lcl_reg_0\,
      O => \^pass_open_bank_ns\
    );
pass_open_bank_r_lcl_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => auto_pre_r_lcl_reg_2,
      I1 => \^wait_for_maint_r\,
      I2 => row_hit_r,
      O => pass_open_bank_r_lcl_i_3_n_0
    );
pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^pass_open_bank_ns\,
      Q => \^pass_open_bank_r_lcl_reg_0\,
      R => '0'
    );
pre_bm_end_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_bm_end_ns,
      Q => pre_bm_end_r,
      R => '0'
    );
pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_passing_open_bank_ns,
      Q => pre_passing_open_bank_r,
      R => '0'
    );
\q_entry_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCC440FCCCC44C0"
    )
        port map (
      I0 => \q_entry_r[0]_i_2__2_n_0\,
      I1 => \q_entry_r[0]_i_3_n_0\,
      I2 => \q_entry_r[0]_i_4__2_n_0\,
      I3 => set_order_q,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => q_entry_r_1(0),
      O => \q_entry_r[0]_i_1_n_0\
    );
\q_entry_r[0]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \q_entry_r[1]_i_7__1_n_0\,
      I1 => \q_entry_r_reg[0]_2\(2),
      I2 => \q_entry_r_reg[0]_2\(0),
      I3 => \q_entry_r_reg[0]_2\(1),
      I4 => q_has_priority_r_reg_0,
      O => \q_entry_r[0]_i_2__2_n_0\
    );
\q_entry_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"96696996FFFFFFFF"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => head_r_lcl_reg_2(0),
      I2 => head_r_lcl_reg_2(1),
      I3 => head_r_lcl_reg_2(2),
      I4 => q_has_priority_r_reg_1,
      I5 => \^pre_bm_end_r_reg_0\,
      O => \q_entry_r[0]_i_3_n_0\
    );
\q_entry_r[0]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9669"
    )
        port map (
      I0 => \q_entry_r[1]_i_4__2_n_0\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      O => idle_r_lcl_reg_3
    );
\q_entry_r[0]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00009669"
    )
        port map (
      I0 => \q_entry_r[1]_i_4__2_n_0\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I3 => q_has_priority_r_reg_1,
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      O => idle_r_lcl_reg_5
    );
\q_entry_r[0]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_0\,
      I1 => head_r_lcl_reg_2(2),
      I2 => head_r_lcl_reg_2(1),
      I3 => head_r_lcl_reg_2(0),
      I4 => \^idle_r_lcl_reg_0\(0),
      O => idle_r_lcl_reg_6
    );
\q_entry_r[0]_i_4__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"404F"
    )
        port map (
      I0 => set_order_q,
      I1 => q_has_priority_r_reg_1,
      I2 => \^idle_r_lcl_reg_0\(0),
      I3 => \q_entry_r[1]_i_7__1_n_0\,
      O => \q_entry_r[0]_i_4__2_n_0\
    );
\q_entry_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => q_entry_ns_0(1),
      I1 => \q_entry_r[1]_i_3__0_n_0\,
      I2 => q_entry_r_1(1),
      O => \q_entry_r[1]_i_1_n_0\
    );
\q_entry_r[1]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4DB2"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I3 => \q_entry_r[1]_i_6__1_n_0\,
      O => pre_bm_end_r_reg_1
    );
\q_entry_r[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3CAAFFFF3CAA0000"
    )
        port map (
      I0 => \q_entry_r[1]_i_2__2_n_0\,
      I1 => \q_entry_r_reg[1]_1\,
      I2 => \q_entry_r[1]_i_4__1_n_0\,
      I3 => \q_entry_r_reg[1]_2\,
      I4 => \q_entry_r_reg[1]_3\,
      I5 => q_entry_r(0),
      O => \q_entry_r_reg[1]_0\
    );
\q_entry_r[1]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8CBF4073"
    )
        port map (
      I0 => \q_entry_r[1]_i_4__2_n_0\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => q_has_priority_r_reg_1,
      I3 => \q_entry_r[1]_i_5__0_n_0\,
      I4 => \q_entry_r[1]_i_6__1_n_0\,
      O => q_entry_ns_0(1)
    );
\q_entry_r[1]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBBB8B8B8888B8"
    )
        port map (
      I0 => \q_entry_r_reg[1]_4\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I2 => q_has_priority_r_reg_1,
      I3 => \^pre_bm_end_r_reg_0\,
      I4 => \q_entry_r[1]_i_4__2_n_0\,
      I5 => \q_entry_r[1]_i_6__1_n_0\,
      O => q_entry_ns(0)
    );
\q_entry_r[1]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF6A5600006A56"
    )
        port map (
      I0 => \q_entry_r[1]_i_6__1_n_0\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => \q_entry_r[1]_i_4__2_n_0\,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I5 => \q_entry_r_reg[1]_5\,
      O => \q_entry_r[1]_i_2__2_n_0\
    );
\q_entry_r[1]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEAEF"
    )
        port map (
      I0 => set_order_q,
      I1 => q_has_priority_r_reg_1,
      I2 => \^idle_r_lcl_reg_0\(0),
      I3 => \q_entry_r[1]_i_7__1_n_0\,
      I4 => \^pre_bm_end_r_reg_0\,
      O => \q_entry_r[1]_i_3__0_n_0\
    );
\q_entry_r[1]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78888777"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I2 => \^pre_bm_end_r_reg_0\,
      I3 => \q_entry_r[1]_i_4__2_n_0\,
      I4 => \q_entry_r[1]_i_6__1_n_0\,
      O => pre_bm_end_r_reg_3
    );
\q_entry_r[1]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9FF9"
    )
        port map (
      I0 => \q_entry_r[1]_i_4__2_n_0\,
      I1 => \^pre_bm_end_r_reg_0\,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      O => idle_r_lcl_reg_4
    );
\q_entry_r[1]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1441411428828228"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_0\,
      I1 => head_r_lcl_reg_2(2),
      I2 => head_r_lcl_reg_2(1),
      I3 => head_r_lcl_reg_2(0),
      I4 => \^idle_r_lcl_reg_0\(0),
      I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      O => \q_entry_r[1]_i_4__1_n_0\
    );
\q_entry_r[1]_i_4__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => head_r_lcl_reg_2(0),
      I2 => head_r_lcl_reg_2(1),
      I3 => head_r_lcl_reg_2(2),
      O => \q_entry_r[1]_i_4__2_n_0\
    );
\q_entry_r[1]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5656565600FFFF00"
    )
        port map (
      I0 => head_r_lcl_reg_1,
      I1 => \q_entry_r[1]_i_2__0_0\,
      I2 => \q_entry_r[1]_i_7__1_n_0\,
      I3 => q_entry_r_1(0),
      I4 => q_entry_r_1(1),
      I5 => set_order_q,
      O => \q_entry_r[1]_i_5__0_n_0\
    );
\q_entry_r[1]_i_6__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7EE8"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => head_r_lcl_reg_2(2),
      I2 => head_r_lcl_reg_2(1),
      I3 => head_r_lcl_reg_2(0),
      O => \q_entry_r[1]_i_6__1_n_0\
    );
\q_entry_r[1]_i_7__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0BBB00000BBB0BBB"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I1 => rb_hit_busies_r(2),
      I2 => p_13_out,
      I3 => rb_hit_busies_r(3),
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I5 => rb_hit_busies_r(1),
      O => \q_entry_r[1]_i_7__1_n_0\
    );
\q_entry_r[1]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9060"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I2 => \q_entry_r[1]_i_4__2_n_0\,
      I3 => \^pre_bm_end_r_reg_0\,
      O => pre_bm_end_r_reg_2
    );
\q_entry_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[0]_i_1_n_0\,
      Q => q_entry_r_1(0),
      R => \q_entry_r_reg[0]_1\
    );
\q_entry_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[1]_i_1_n_0\,
      Q => q_entry_r_1(1),
      R => \q_entry_r_reg[0]_1\
    );
q_has_priority_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF00000080"
    )
        port map (
      I0 => q_has_priority_r_reg_0,
      I1 => q_has_priority_r_reg_1,
      I2 => was_priority,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => q_has_priority,
      O => q_has_priority_ns
    );
q_has_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_priority_ns,
      Q => q_has_priority,
      R => '0'
    );
q_has_rd_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00BA00BA00BA00FF"
    )
        port map (
      I0 => \^q_has_rd\,
      I1 => was_wr,
      I2 => pass_open_bank_r_lcl_reg_1,
      I3 => \^rstdiv0_sync_r1_reg_rep__10\,
      I4 => q_has_rd_r_reg_0,
      I5 => \^idle_r_lcl_reg_0\(0),
      O => q_has_rd_ns
    );
q_has_rd_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_rd_ns,
      Q => \^q_has_rd\,
      R => '0'
    );
\ras_timer_r[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[0]_i_2__2_n_0\,
      I1 => \^q_entry_r_reg[0]_0\,
      I2 => \ras_timer_r_reg[0]\,
      O => D(0)
    );
\ras_timer_r[0]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => rb_hit_busies_r(1),
      I1 => rb_hit_busies_r(2),
      I2 => \ras_timer_r_reg[0]_0\,
      I3 => \ras_timer_r_reg[0]_1\,
      I4 => rb_hit_busies_r(3),
      I5 => \ras_timer_r_reg[0]_2\,
      O => \ras_timer_r[0]_i_2__2_n_0\
    );
\ras_timer_r[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[1]_i_2__2_n_0\,
      I1 => \^q_entry_r_reg[0]_0\,
      I2 => \ras_timer_r_reg[1]\,
      O => D(1)
    );
\ras_timer_r[1]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => rb_hit_busies_r(1),
      I1 => rb_hit_busies_r(2),
      I2 => \ras_timer_r_reg[1]_0\,
      I3 => \ras_timer_r_reg[1]_1\,
      I4 => rb_hit_busies_r(3),
      I5 => \ras_timer_r_reg[1]_2\,
      O => \ras_timer_r[1]_i_2__2_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000B800"
    )
        port map (
      I0 => rb_hit_busies_r(1),
      I1 => \^idle_r_lcl_reg_2\,
      I2 => p_106_out,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      O => \rb_hit_busies.rb_hit_busies_ns\(1)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000B800"
    )
        port map (
      I0 => rb_hit_busies_r(2),
      I1 => \^idle_r_lcl_reg_2\,
      I2 => p_67_out,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      O => \rb_hit_busies.rb_hit_busies_ns\(2)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000B8"
    )
        port map (
      I0 => rb_hit_busies_r(3),
      I1 => \^idle_r_lcl_reg_2\,
      I2 => p_28_out,
      I3 => p_13_out,
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      O => \rb_hit_busies.rb_hit_busies_ns\(3)
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_ns\(1),
      Q => rb_hit_busies_r(1),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_ns\(2),
      Q => rb_hit_busies_r(2),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_ns\(3),
      Q => rb_hit_busies_r(3),
      R => '0'
    );
\req_bank_rdy_r_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2202"
    )
        port map (
      I0 => req_bank_rdy_r_reg,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_bank_rdy_r_reg_0,
      O => req_bank_rdy_ns
    );
\wait_for_maint_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFA8AA00000000"
    )
        port map (
      I0 => set_order_q,
      I1 => maint_sre_r,
      I2 => maint_zq_r,
      I3 => maint_rank_r,
      I4 => \^wait_for_maint_r\,
      I5 => wait_for_maint_r_lcl_reg_0,
      O => wait_for_maint_ns
    );
\wait_for_maint_r_lcl_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080800080008000"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => \^head_r\(0),
      I2 => accept_internal_r,
      I3 => wait_for_maint_r_lcl_reg_1,
      I4 => wait_for_maint_r_lcl_reg_2,
      I5 => app_en_r2,
      O => set_order_q
    );
wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wait_for_maint_ns,
      Q => \^wait_for_maint_r\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_bank_queue__parameterized0\ is
  port (
    idle_r_lcl_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    wait_for_maint_r : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    pass_open_bank_ns : out STD_LOGIC;
    q_has_rd : out STD_LOGIC;
    tail_r : out STD_LOGIC;
    head_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    ordered_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    col_wait_r_reg : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    demand_priority_ns : out STD_LOGIC;
    \order_q_r_reg[0]_0\ : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    periodic_rd_ack_ns : out STD_LOGIC;
    accept_ns : out STD_LOGIC;
    idle_r_lcl_reg_2 : out STD_LOGIC;
    pre_bm_end_r_reg_1 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : out STD_LOGIC;
    p_91_out : out STD_LOGIC;
    pre_bm_end_r_reg_2 : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11_0\ : out STD_LOGIC;
    demand_act_priority_r_reg : out STD_LOGIC;
    CLK : in STD_LOGIC;
    pre_bm_end_ns : in STD_LOGIC;
    pre_passing_open_bank_ns : in STD_LOGIC;
    \q_entry_r_reg[0]_1\ : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC;
    \grant_r_reg[2]\ : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    \grant_r_reg[2]_0\ : in STD_LOGIC;
    \grant_r_reg[2]_1\ : in STD_LOGIC;
    col_wait_r_0 : in STD_LOGIC;
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    \ras_timer_r_reg[1]\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    col_wait_ns : in STD_LOGIC;
    demand_priority_r_reg : in STD_LOGIC;
    req_priority_r : in STD_LOGIC;
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    demand_priority_r_reg_0 : in STD_LOGIC;
    demand_priority_r_reg_1 : in STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    granted_col_r_i_2_0 : in STD_LOGIC;
    granted_col_r_i_2_1 : in STD_LOGIC;
    granted_col_r_i_2_2 : in STD_LOGIC;
    p_145_out : in STD_LOGIC;
    p_130_out : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_1 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_2 : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    idle_r : in STD_LOGIC_VECTOR ( 2 downto 0 );
    p_13_out : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_reg : in STD_LOGIC;
    req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    head_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    \q_entry_r_reg[0]_2\ : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    rb_hit_busy_r : in STD_LOGIC_VECTOR ( 2 downto 0 );
    q_has_priority_r_reg_1 : in STD_LOGIC;
    \q_entry_r[1]_i_2__1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : in STD_LOGIC;
    p_28_out : in STD_LOGIC;
    q_has_priority_r_reg_2 : in STD_LOGIC;
    p_67_out : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[1]\ : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    maint_sre_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    maint_rank_r : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    accept_internal_r : in STD_LOGIC;
    ordered_r_lcl_reg_0 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    app_en_r2 : in STD_LOGIC;
    \grant_r[3]_i_12\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    was_priority : in STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    was_wr : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    row_hit_r : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    pre_wait_r : in STD_LOGIC;
    \grant_r_reg[2]_2\ : in STD_LOGIC;
    demand_act_priority_r : in STD_LOGIC;
    \grant_r_reg[2]_3\ : in STD_LOGIC;
    \grant_r_reg[2]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    demand_act_priority_r_1 : in STD_LOGIC;
    \grant_r[3]_i_2__1_0\ : in STD_LOGIC;
    ras_timer_zero_r : in STD_LOGIC;
    \q_entry_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \order_q_r_reg[1]_0\ : in STD_LOGIC;
    \order_q_r_reg[0]_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_bank_queue__parameterized0\ : entity is "mig_7series_v4_2_bank_queue";
end \mig_7series_0_mig_7series_v4_2_bank_queue__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_bank_queue__parameterized0\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \auto_pre_r_lcl_i_1__0_n_0\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg_0\ : STD_LOGIC;
  signal \compute_tail.tail_r_lcl_i_1__0_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_6__0_n_0\ : STD_LOGIC;
  signal granted_col_r_i_4_n_0 : STD_LOGIC;
  signal \^head_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \head_r_lcl_i_1__0_n_0\ : STD_LOGIC;
  signal \head_r_lcl_i_2__1_n_0\ : STD_LOGIC;
  signal \head_r_lcl_i_3__2_n_0\ : STD_LOGIC;
  signal \head_r_lcl_i_4__0_n_0\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^idle_r_lcl_reg_1\ : STD_LOGIC;
  signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \order_q_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \order_q_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \^order_q_r_reg[0]_0\ : STD_LOGIC;
  signal \^ordered_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \ordered_r_lcl_i_1__2_n_0\ : STD_LOGIC;
  signal \^pass_open_bank_ns\ : STD_LOGIC;
  signal \pass_open_bank_r_lcl_i_2__1_n_0\ : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg_0\ : STD_LOGIC;
  signal pre_bm_end_r : STD_LOGIC;
  signal \^pre_bm_end_r_reg_0\ : STD_LOGIC;
  signal pre_passing_open_bank_r : STD_LOGIC;
  signal q_entry_ns : STD_LOGIC_VECTOR ( 0 to 0 );
  signal q_entry_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \q_entry_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_3__1_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[0]_0\ : STD_LOGIC;
  signal q_has_priority : STD_LOGIC;
  signal q_has_priority_ns : STD_LOGIC;
  signal \^q_has_rd\ : STD_LOGIC;
  signal q_has_rd_ns : STD_LOGIC;
  signal \ras_timer_r[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_ns\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal rb_hit_busies_r : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \^rstdiv0_sync_r1_reg_rep__11_0\ : STD_LOGIC;
  signal set_order_q : STD_LOGIC;
  signal \^tail_r\ : STD_LOGIC;
  signal wait_for_maint_ns : STD_LOGIC;
  signal \^wait_for_maint_r\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \bm_end_r1_i_1__0\ : label is "soft_lutpair564";
  attribute SOFT_HLUTNM of \compute_tail.tail_r_lcl_i_2__1\ : label is "soft_lutpair567";
  attribute SOFT_HLUTNM of \compute_tail.tail_r_lcl_i_2__2\ : label is "soft_lutpair567";
  attribute SOFT_HLUTNM of granted_col_r_i_2 : label is "soft_lutpair565";
  attribute SOFT_HLUTNM of \head_r_lcl_i_3__2\ : label is "soft_lutpair565";
  attribute SOFT_HLUTNM of \head_r_lcl_i_4__0\ : label is "soft_lutpair563";
  attribute SOFT_HLUTNM of \idle_r_lcl_i_1__2\ : label is "soft_lutpair562";
  attribute SOFT_HLUTNM of \maint_controller.maint_hit_busies_r[1]_i_2\ : label is "soft_lutpair564";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_3__1\ : label is "soft_lutpair563";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_1__1\ : label is "soft_lutpair566";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_1__1\ : label is "soft_lutpair566";
  attribute SOFT_HLUTNM of \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1\ : label is "soft_lutpair562";
begin
  E(0) <= \^e\(0);
  auto_pre_r_lcl_reg_0 <= \^auto_pre_r_lcl_reg_0\;
  head_r(0) <= \^head_r\(0);
  idle_r_lcl_reg_0(0) <= \^idle_r_lcl_reg_0\(0);
  idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\;
  \order_q_r_reg[0]_0\ <= \^order_q_r_reg[0]_0\;
  ordered_r(0) <= \^ordered_r\(0);
  pass_open_bank_ns <= \^pass_open_bank_ns\;
  pass_open_bank_r_lcl_reg_0 <= \^pass_open_bank_r_lcl_reg_0\;
  pre_bm_end_r_reg_0 <= \^pre_bm_end_r_reg_0\;
  \q_entry_r_reg[0]_0\ <= \^q_entry_r_reg[0]_0\;
  q_has_rd <= \^q_has_rd\;
  \rstdiv0_sync_r1_reg_rep__11_0\ <= \^rstdiv0_sync_r1_reg_rep__11_0\;
  tail_r <= \^tail_r\;
  wait_for_maint_r <= \^wait_for_maint_r\;
accept_internal_r_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D0"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => set_order_q,
      I2 => \^pre_bm_end_r_reg_0\,
      I3 => q_has_priority_r_reg_2,
      O => \^idle_r_lcl_reg_1\
    );
accept_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF0000"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      I1 => periodic_rd_ack_r_lcl_reg,
      I2 => periodic_rd_ack_r_lcl_reg_0,
      I3 => periodic_rd_ack_r_lcl_reg_1,
      I4 => periodic_rd_ack_r_lcl_reg_2,
      I5 => periodic_rd_insert,
      O => accept_ns
    );
\act_wait_r_lcl_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAEAEAEA"
    )
        port map (
      I0 => q_has_priority_r_reg_2,
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => Q(0),
      I3 => bm_end_r1_reg,
      I4 => req_wr_r(0),
      I5 => pre_bm_end_r,
      O => \^rstdiv0_sync_r1_reg_rep__11_0\
    );
act_wait_r_lcl_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40555555"
    )
        port map (
      I0 => pre_passing_open_bank_r,
      I1 => req_wr_r(0),
      I2 => bm_end_r1_reg,
      I3 => Q(0),
      I4 => \^pass_open_bank_r_lcl_reg_0\,
      O => pre_passing_open_bank_r_reg_0
    );
act_wait_r_lcl_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00808080"
    )
        port map (
      I0 => \grant_r[3]_i_12\(0),
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => Q(0),
      I3 => bm_end_r1_reg,
      I4 => req_wr_r(0),
      I5 => pre_passing_open_bank_r,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\
    );
\auto_pre_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AEAEAEEE"
    )
        port map (
      I0 => \^auto_pre_r_lcl_reg_0\,
      I1 => auto_pre_r_lcl_reg_1,
      I2 => row_hit_r,
      I3 => \^wait_for_maint_r\,
      I4 => auto_pre_r_lcl_reg_2,
      I5 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      O => \auto_pre_r_lcl_i_1__0_n_0\
    );
auto_pre_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \auto_pre_r_lcl_i_1__0_n_0\,
      Q => \^auto_pre_r_lcl_reg_0\,
      R => '0'
    );
\bm_end_r1_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0888"
    )
        port map (
      I0 => \^pass_open_bank_r_lcl_reg_0\,
      I1 => Q(0),
      I2 => bm_end_r1_reg,
      I3 => req_wr_r(0),
      I4 => pre_bm_end_r,
      O => p_91_out
    );
\compute_tail.tail_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5F1FFF1F0F0FFF0"
    )
        port map (
      I0 => pass_open_bank_r_lcl_reg_2,
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => set_order_q,
      I3 => \compute_tail.tail_r_lcl_reg_0\,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => \^tail_r\,
      O => \compute_tail.tail_r_lcl_i_1__0_n_0\
    );
\compute_tail.tail_r_lcl_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_0\,
      I1 => p_130_out,
      I2 => p_13_out,
      O => pre_bm_end_r_reg_1
    );
\compute_tail.tail_r_lcl_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_0\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I2 => p_13_out,
      O => pre_bm_end_r_reg_2
    );
\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \compute_tail.tail_r_lcl_i_1__0_n_0\,
      Q => \^tail_r\,
      R => \q_entry_r_reg[0]_1\
    );
\demand_priority_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A2A2A000000000"
    )
        port map (
      I0 => col_wait_ns,
      I1 => \^order_q_r_reg[0]_0\,
      I2 => demand_priority_r_reg,
      I3 => req_priority_r,
      I4 => q_has_priority,
      I5 => \^idle_r_lcl_reg_1\,
      O => demand_priority_ns
    );
\demand_priority_r_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => demand_priority_r_reg_0,
      I1 => demand_priority_r_reg_1,
      I2 => demand_priority_r_reg_2,
      I3 => demand_priority_r_reg_3,
      I4 => order_q_r(0),
      I5 => order_q_r(1),
      O => \^order_q_r_reg[0]_0\
    );
\grant_r[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CDCD0000CDCD00CD"
    )
        port map (
      I0 => \^q_entry_r_reg[0]_0\,
      I1 => \grant_r_reg[2]\,
      I2 => req_bank_rdy_r_reg,
      I3 => \grant_r_reg[2]_0\,
      I4 => \grant_r_reg[2]_1\,
      I5 => col_wait_r_0,
      O => col_wait_r_reg
    );
\grant_r[3]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4440404044404440"
    )
        port map (
      I0 => \grant_r[3]_i_6__0_n_0\,
      I1 => \grant_r_reg[2]_2\,
      I2 => demand_act_priority_r,
      I3 => \grant_r_reg[2]_3\,
      I4 => \grant_r_reg[2]_4\(0),
      I5 => demand_act_priority_r_1,
      O => demand_act_priority_r_reg
    );
\grant_r[3]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFF"
    )
        port map (
      I0 => \^head_r\(0),
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => \grant_r[3]_i_2__1_0\,
      I3 => ras_timer_zero_r,
      I4 => \^wait_for_maint_r\,
      O => \grant_r[3]_i_6__0_n_0\
    );
granted_col_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => q_entry_r(0),
      I1 => q_entry_r(1),
      I2 => \^idle_r_lcl_reg_0\(0),
      I3 => granted_col_r_i_4_n_0,
      O => \^q_entry_r_reg[0]_0\
    );
granted_col_r_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22F2FFFF22F222F2"
    )
        port map (
      I0 => rb_hit_busies_r(4),
      I1 => granted_col_r_i_2_0,
      I2 => rb_hit_busies_r(2),
      I3 => granted_col_r_i_2_1,
      I4 => granted_col_r_i_2_2,
      I5 => rb_hit_busies_r(3),
      O => granted_col_r_i_4_n_0
    );
\head_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAEFAAAAEAE0AAAA"
    )
        port map (
      I0 => \head_r_lcl_i_2__1_n_0\,
      I1 => \head_r_lcl_i_3__2_n_0\,
      I2 => \head_r_lcl_i_4__0_n_0\,
      I3 => set_order_q,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => \^head_r\(0),
      O => \head_r_lcl_i_1__0_n_0\
    );
\head_r_lcl_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"010101010000FF00"
    )
        port map (
      I0 => \head_r_lcl_i_4__0_n_0\,
      I1 => head_r_lcl_reg_0,
      I2 => \q_entry_r[0]_i_4_n_0\,
      I3 => head_r_lcl_reg_1,
      I4 => p_130_out,
      I5 => \^pre_bm_end_r_reg_0\,
      O => \head_r_lcl_i_2__1_n_0\
    );
\head_r_lcl_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => q_entry_r(0),
      I1 => q_entry_r(1),
      O => \head_r_lcl_i_3__2_n_0\
    );
head_r_lcl_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAEAEAEA"
    )
        port map (
      I0 => p_130_out,
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => Q(0),
      I3 => bm_end_r1_reg,
      I4 => req_wr_r(0),
      I5 => pre_bm_end_r,
      O => pass_open_bank_r_lcl_reg_1
    );
\head_r_lcl_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"404F"
    )
        port map (
      I0 => set_order_q,
      I1 => q_has_priority_r_reg_0,
      I2 => \^idle_r_lcl_reg_0\(0),
      I3 => \q_entry_r[1]_i_5_n_0\,
      O => \head_r_lcl_i_4__0_n_0\
    );
head_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \head_r_lcl_i_1__0_n_0\,
      Q => \^head_r\(0),
      R => \q_entry_r_reg[0]_1\
    );
\idle_r_lcl_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      O => \^e\(0)
    );
idle_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^e\(0),
      Q => \^idle_r_lcl_reg_0\(0),
      R => '0'
    );
\maint_controller.maint_hit_busies_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F000200"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      I1 => \maint_controller.maint_hit_busies_r_reg[1]\,
      I2 => q_has_priority_r_reg_2,
      I3 => \^pre_bm_end_r_reg_0\,
      I4 => \maint_controller.maint_hit_busies_r_reg[1]_0\(0),
      O => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\maint_controller.maint_hit_busies_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40555555"
    )
        port map (
      I0 => pre_bm_end_r,
      I1 => req_wr_r(0),
      I2 => bm_end_r1_reg,
      I3 => Q(0),
      I4 => \^pass_open_bank_r_lcl_reg_0\,
      O => \^pre_bm_end_r_reg_0\
    );
\order_q_r[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00470047FF444444"
    )
        port map (
      I0 => \order_q_r_reg[0]_1\,
      I1 => set_order_q,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I3 => req_bank_rdy_r_reg_0,
      I4 => order_q_r(1),
      I5 => order_q_r(0),
      O => \order_q_r[0]_i_1__0_n_0\
    );
\order_q_r[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF8B0088008B8888"
    )
        port map (
      I0 => \order_q_r_reg[1]_0\,
      I1 => set_order_q,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I3 => req_bank_rdy_r_reg_0,
      I4 => order_q_r(1),
      I5 => order_q_r(0),
      O => \order_q_r[1]_i_1__0_n_0\
    );
\order_q_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[0]_i_1__0_n_0\,
      Q => order_q_r(0),
      R => '0'
    );
\order_q_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[1]_i_1__0_n_0\,
      Q => order_q_r(1),
      R => '0'
    );
\ordered_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454005400540054"
    )
        port map (
      I0 => q_has_priority_r_reg_2,
      I1 => set_order_q,
      I2 => \^ordered_r\(0),
      I3 => Q(0),
      I4 => bm_end_r1_reg,
      I5 => req_wr_r(0),
      O => \ordered_r_lcl_i_1__2_n_0\
    );
ordered_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ordered_r_lcl_i_1__2_n_0\,
      Q => \^ordered_r\(0),
      R => '0'
    );
\pass_open_bank_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00000080"
    )
        port map (
      I0 => \pass_open_bank_r_lcl_i_2__1_n_0\,
      I1 => pass_open_bank_r_lcl_reg_2,
      I2 => \^tail_r\,
      I3 => pre_wait_r,
      I4 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      I5 => \^pass_open_bank_r_lcl_reg_0\,
      O => \^pass_open_bank_ns\
    );
\pass_open_bank_r_lcl_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => auto_pre_r_lcl_reg_2,
      I1 => \^wait_for_maint_r\,
      I2 => row_hit_r,
      O => \pass_open_bank_r_lcl_i_2__1_n_0\
    );
pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^pass_open_bank_ns\,
      Q => \^pass_open_bank_r_lcl_reg_0\,
      R => '0'
    );
periodic_rd_ack_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF000000000000"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      I1 => periodic_rd_ack_r_lcl_reg,
      I2 => periodic_rd_ack_r_lcl_reg_0,
      I3 => periodic_rd_ack_r_lcl_reg_1,
      I4 => periodic_rd_ack_r_lcl_reg_2,
      I5 => periodic_rd_insert,
      O => periodic_rd_ack_ns
    );
pre_bm_end_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_bm_end_ns,
      Q => pre_bm_end_r,
      R => '0'
    );
pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_passing_open_bank_ns,
      Q => pre_passing_open_bank_r,
      R => '0'
    );
\q_entry_r[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => q_entry_ns(0),
      I1 => \q_entry_r[1]_i_3__1_n_0\,
      I2 => q_entry_r(0),
      O => \q_entry_r[0]_i_1__0_n_0\
    );
\q_entry_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0553355F0AA33AA"
    )
        port map (
      I0 => \q_entry_r_reg[0]_2\,
      I1 => q_entry_r(0),
      I2 => \q_entry_r[0]_i_4_n_0\,
      I3 => \^pre_bm_end_r_reg_0\,
      I4 => set_order_q,
      I5 => q_has_priority_r_reg_0,
      O => q_entry_ns(0)
    );
\q_entry_r[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969669"
    )
        port map (
      I0 => \q_entry_r[1]_i_5_n_0\,
      I1 => rb_hit_busy_r(2),
      I2 => q_has_priority_r_reg_1,
      I3 => rb_hit_busy_r(1),
      I4 => rb_hit_busy_r(0),
      O => \q_entry_r[0]_i_4_n_0\
    );
\q_entry_r[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \q_entry_r_reg[1]_1\(0),
      I1 => \q_entry_r[1]_i_3__1_n_0\,
      I2 => q_entry_r(1),
      O => \q_entry_r[1]_i_1__0_n_0\
    );
\q_entry_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2DDDDDD2DDD2D222"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_0\,
      I1 => p_130_out,
      I2 => \^idle_r_lcl_reg_0\(0),
      I3 => idle_r(1),
      I4 => idle_r(2),
      I5 => idle_r(0),
      O => idle_r_lcl_reg_2
    );
\q_entry_r[1]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEFFFFF"
    )
        port map (
      I0 => set_order_q,
      I1 => q_has_priority_r_reg_0,
      I2 => \^idle_r_lcl_reg_0\(0),
      I3 => \q_entry_r[1]_i_5_n_0\,
      I4 => \^pre_bm_end_r_reg_0\,
      O => \q_entry_r[1]_i_3__1_n_0\
    );
\q_entry_r[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A9A9A9A9FF0000FF"
    )
        port map (
      I0 => head_r_lcl_reg_0,
      I1 => \q_entry_r[1]_i_2__1\,
      I2 => \q_entry_r[1]_i_5_n_0\,
      I3 => q_entry_r(1),
      I4 => q_entry_r(0),
      I5 => set_order_q,
      O => \q_entry_r_reg[1]_0\
    );
\q_entry_r[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777000007770777"
    )
        port map (
      I0 => rb_hit_busies_r(3),
      I1 => p_13_out,
      I2 => p_130_out,
      I3 => rb_hit_busies_r(4),
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I5 => rb_hit_busies_r(2),
      O => \q_entry_r[1]_i_5_n_0\
    );
\q_entry_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[0]_i_1__0_n_0\,
      Q => q_entry_r(0),
      S => \q_entry_r_reg[0]_1\
    );
\q_entry_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[1]_i_1__0_n_0\,
      Q => q_entry_r(1),
      R => \q_entry_r_reg[0]_1\
    );
\q_has_priority_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000000800000"
    )
        port map (
      I0 => q_has_priority_r_reg_0,
      I1 => q_has_priority_r_reg_1,
      I2 => was_priority,
      I3 => q_has_priority_r_reg_2,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => q_has_priority,
      O => q_has_priority_ns
    );
q_has_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_priority_ns,
      Q => q_has_priority,
      R => '0'
    );
\q_has_rd_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AB00AB00FF00AB"
    )
        port map (
      I0 => \^q_has_rd\,
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => q_has_rd_r_reg_0,
      I3 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      I4 => pass_open_bank_r_lcl_reg_2,
      I5 => was_wr,
      O => q_has_rd_ns
    );
q_has_rd_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_rd_ns,
      Q => \^q_has_rd\,
      R => '0'
    );
\ras_timer_r[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[0]_i_2__1_n_0\,
      I1 => \^q_entry_r_reg[0]_0\,
      I2 => \ras_timer_r_reg[0]\,
      O => D(0)
    );
\ras_timer_r[0]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => rb_hit_busies_r(2),
      I1 => rb_hit_busies_r(3),
      I2 => \ras_timer_r_reg[0]_0\,
      I3 => \ras_timer_r_reg[0]_1\,
      I4 => rb_hit_busies_r(4),
      I5 => \ras_timer_r_reg[0]_2\,
      O => \ras_timer_r[0]_i_2__1_n_0\
    );
\ras_timer_r[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[1]_i_2__1_n_0\,
      I1 => \^q_entry_r_reg[0]_0\,
      I2 => \ras_timer_r_reg[1]\,
      O => D(1)
    );
\ras_timer_r[1]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => rb_hit_busies_r(2),
      I1 => rb_hit_busies_r(3),
      I2 => \ras_timer_r_reg[1]_0\,
      I3 => \ras_timer_r_reg[1]_1\,
      I4 => rb_hit_busies_r(4),
      I5 => \ras_timer_r_reg[1]_2\,
      O => \ras_timer_r[1]_i_2__1_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AC00"
    )
        port map (
      I0 => rb_hit_busies_r(2),
      I1 => p_67_out,
      I2 => \^idle_r_lcl_reg_1\,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I4 => q_has_priority_r_reg_2,
      O => \rb_hit_busies.rb_hit_busies_ns\(2)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000AC"
    )
        port map (
      I0 => rb_hit_busies_r(3),
      I1 => p_28_out,
      I2 => \^idle_r_lcl_reg_1\,
      I3 => p_13_out,
      I4 => q_has_priority_r_reg_2,
      O => \rb_hit_busies.rb_hit_busies_ns\(3)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000A000C"
    )
        port map (
      I0 => rb_hit_busies_r(4),
      I1 => p_145_out,
      I2 => p_130_out,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I4 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_ns\(4)
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_ns\(2),
      Q => rb_hit_busies_r(2),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_ns\(3),
      Q => rb_hit_busies_r(3),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_ns\(4),
      Q => rb_hit_busies_r(4),
      R => '0'
    );
\req_bank_rdy_r_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2202"
    )
        port map (
      I0 => req_bank_rdy_r_reg,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_bank_rdy_r_reg_0,
      O => req_bank_rdy_ns
    );
\wait_for_maint_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFA8AA00000000"
    )
        port map (
      I0 => set_order_q,
      I1 => maint_sre_r,
      I2 => maint_zq_r,
      I3 => maint_rank_r,
      I4 => \^wait_for_maint_r\,
      I5 => wait_for_maint_r_lcl_reg_0,
      O => wait_for_maint_ns
    );
\wait_for_maint_r_lcl_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080800080008000"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => \^head_r\(0),
      I2 => accept_internal_r,
      I3 => ordered_r_lcl_reg_0,
      I4 => ordered_r_lcl_reg_1,
      I5 => app_en_r2,
      O => set_order_q
    );
wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wait_for_maint_ns,
      Q => \^wait_for_maint_r\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_bank_queue__parameterized1\ is
  port (
    idle_r_lcl_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    wait_for_maint_r : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    pass_open_bank_ns : out STD_LOGIC;
    tail_r : out STD_LOGIC;
    head_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    ordered_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    idle_r_lcl_reg_1 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    demand_priority_ns : out STD_LOGIC;
    \order_q_r_reg[0]_0\ : out STD_LOGIC;
    idle_r_lcl_reg_2 : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    idle_r_lcl_reg_3 : out STD_LOGIC;
    pre_bm_end_r_reg_1 : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : out STD_LOGIC;
    idle_r_lcl_reg_4 : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    pre_passing_open_bank_r_reg_0 : out STD_LOGIC;
    p_52_out : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11_0\ : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    q_has_rd_r_reg_0 : out STD_LOGIC;
    CLK : in STD_LOGIC;
    pre_bm_end_ns : in STD_LOGIC;
    pre_passing_open_bank_ns : in STD_LOGIC;
    \q_entry_r_reg[0]_1\ : in STD_LOGIC;
    \q_entry_r_reg[1]_1\ : in STD_LOGIC;
    \q_entry_r_reg[0]_2\ : in STD_LOGIC;
    \q_entry_r_reg[0]_3\ : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    \ras_timer_r_reg[1]\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    col_wait_ns : in STD_LOGIC;
    demand_priority_r_reg : in STD_LOGIC;
    req_priority_r : in STD_LOGIC;
    col_wait_r : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    demand_priority_r_reg_0 : in STD_LOGIC;
    demand_priority_r_reg_1 : in STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    \ras_timer_r_reg[0]_3\ : in STD_LOGIC;
    \grant_r[3]_i_5\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_4\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_5\ : in STD_LOGIC;
    p_145_out : in STD_LOGIC;
    p_130_out : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC;
    head_r_lcl_reg_3 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC;
    \q_entry_r[1]_i_2__2\ : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    p_13_out : in STD_LOGIC;
    p_28_out : in STD_LOGIC;
    q_has_priority_r_reg_1 : in STD_LOGIC;
    p_106_out : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[2]\ : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    maint_sre_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    maint_rank_r : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    bm_end_r1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_reg_0 : in STD_LOGIC;
    req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    accept_internal_r : in STD_LOGIC;
    ordered_r_lcl_reg_0 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    app_en_r2 : in STD_LOGIC;
    rb_hit_busy_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    was_priority : in STD_LOGIC;
    q_has_rd_r_reg_1 : in STD_LOGIC;
    was_wr : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    row_hit_r : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    pre_wait_r : in STD_LOGIC;
    \grant_r[3]_i_3__2\ : in STD_LOGIC;
    ras_timer_zero_r : in STD_LOGIC;
    req_bank_rdy_r : in STD_LOGIC;
    \demand_priority_r_i_4__1\ : in STD_LOGIC;
    \order_q_r_reg[1]_0\ : in STD_LOGIC;
    \order_q_r_reg[0]_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_bank_queue__parameterized1\ : entity is "mig_7series_v4_2_bank_queue";
end \mig_7series_0_mig_7series_v4_2_bank_queue__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_bank_queue__parameterized1\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \auto_pre_r_lcl_i_1__1_n_0\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg_0\ : STD_LOGIC;
  signal \compute_tail.tail_r_lcl_i_1__1_n_0\ : STD_LOGIC;
  signal \^head_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \head_r_lcl_i_1__1_n_0\ : STD_LOGIC;
  signal head_r_lcl_i_2_n_0 : STD_LOGIC;
  signal \head_r_lcl_i_3__1_n_0\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^idle_r_lcl_reg_1\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_2\ : STD_LOGIC;
  signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \order_q_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \order_q_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \^order_q_r_reg[0]_0\ : STD_LOGIC;
  signal \^ordered_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \ordered_r_lcl_i_1__1_n_0\ : STD_LOGIC;
  signal \^pass_open_bank_ns\ : STD_LOGIC;
  signal \pass_open_bank_r_lcl_i_2__0_n_0\ : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg_0\ : STD_LOGIC;
  signal pre_bm_end_r : STD_LOGIC;
  signal \^pre_bm_end_r_reg_0\ : STD_LOGIC;
  signal pre_passing_open_bank_r : STD_LOGIC;
  signal q_entry_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \q_entry_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal q_has_priority : STD_LOGIC;
  signal q_has_priority_ns : STD_LOGIC;
  signal q_has_rd : STD_LOGIC;
  signal q_has_rd_ns : STD_LOGIC;
  signal \ras_timer_r[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_ns\ : STD_LOGIC_VECTOR ( 5 downto 3 );
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : STD_LOGIC;
  signal \^rstdiv0_sync_r1_reg_rep__11_0\ : STD_LOGIC;
  signal set_order_q : STD_LOGIC;
  signal \^tail_r\ : STD_LOGIC;
  signal wait_for_maint_ns : STD_LOGIC;
  signal \^wait_for_maint_r\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \bm_end_r1_i_1__1\ : label is "soft_lutpair574";
  attribute SOFT_HLUTNM of \idle_r_lcl_i_1__1\ : label is "soft_lutpair573";
  attribute SOFT_HLUTNM of \maint_controller.maint_hit_busies_r[2]_i_1\ : label is "soft_lutpair573";
  attribute SOFT_HLUTNM of \maint_controller.maint_hit_busies_r[2]_i_2\ : label is "soft_lutpair574";
  attribute SOFT_HLUTNM of \q_entry_r[0]_i_4__0\ : label is "soft_lutpair575";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_6\ : label is "soft_lutpair575";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_1__0\ : label is "soft_lutpair576";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_1__0\ : label is "soft_lutpair576";
begin
  E(0) <= \^e\(0);
  Q(2 downto 0) <= \^q\(2 downto 0);
  auto_pre_r_lcl_reg_0 <= \^auto_pre_r_lcl_reg_0\;
  head_r(0) <= \^head_r\(0);
  idle_r_lcl_reg_0(0) <= \^idle_r_lcl_reg_0\(0);
  idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\;
  idle_r_lcl_reg_2 <= \^idle_r_lcl_reg_2\;
  \order_q_r_reg[0]_0\ <= \^order_q_r_reg[0]_0\;
  ordered_r(0) <= \^ordered_r\(0);
  pass_open_bank_ns <= \^pass_open_bank_ns\;
  pass_open_bank_r_lcl_reg_0 <= \^pass_open_bank_r_lcl_reg_0\;
  pre_bm_end_r_reg_0 <= \^pre_bm_end_r_reg_0\;
  \q_entry_r_reg[1]_0\(0) <= \^q_entry_r_reg[1]_0\(0);
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\;
  \rstdiv0_sync_r1_reg_rep__11_0\ <= \^rstdiv0_sync_r1_reg_rep__11_0\;
  tail_r <= \^tail_r\;
  wait_for_maint_r <= \^wait_for_maint_r\;
accept_internal_r_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D0"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => set_order_q,
      I2 => \^pre_bm_end_r_reg_0\,
      I3 => q_has_priority_r_reg_1,
      O => \^idle_r_lcl_reg_2\
    );
\act_wait_r_lcl_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAEAEAEA"
    )
        port map (
      I0 => q_has_priority_r_reg_1,
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => bm_end_r1_reg(0),
      I3 => bm_end_r1_reg_0,
      I4 => req_wr_r(0),
      I5 => pre_bm_end_r,
      O => \^rstdiv0_sync_r1_reg_rep__11_0\
    );
\act_wait_r_lcl_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444440444040"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => \head_r_lcl_i_3__1_n_0\,
      I2 => \ras_timer_r_reg[0]_4\,
      I3 => \ras_timer_r_reg[0]_5\,
      I4 => \^q\(0),
      I5 => \ras_timer_r_reg[0]_3\,
      O => \^idle_r_lcl_reg_1\
    );
\auto_pre_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AEAEAEEE"
    )
        port map (
      I0 => \^auto_pre_r_lcl_reg_0\,
      I1 => auto_pre_r_lcl_reg_1,
      I2 => row_hit_r,
      I3 => \^wait_for_maint_r\,
      I4 => auto_pre_r_lcl_reg_2,
      I5 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      O => \auto_pre_r_lcl_i_1__1_n_0\
    );
auto_pre_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \auto_pre_r_lcl_i_1__1_n_0\,
      Q => \^auto_pre_r_lcl_reg_0\,
      R => '0'
    );
\bm_end_r1_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0888"
    )
        port map (
      I0 => \^pass_open_bank_r_lcl_reg_0\,
      I1 => bm_end_r1_reg(0),
      I2 => bm_end_r1_reg_0,
      I3 => req_wr_r(0),
      I4 => pre_bm_end_r,
      O => p_52_out
    );
\compute_tail.tail_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5F1FFF1F0F0FFF0"
    )
        port map (
      I0 => pass_open_bank_r_lcl_reg_1,
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => set_order_q,
      I3 => \compute_tail.tail_r_lcl_reg_0\,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => \^tail_r\,
      O => \compute_tail.tail_r_lcl_i_1__1_n_0\
    );
\compute_tail.tail_r_lcl_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_0\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I2 => p_130_out,
      O => pre_bm_end_r_reg_1
    );
\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \compute_tail.tail_r_lcl_i_1__1_n_0\,
      Q => \^tail_r\,
      R => \q_entry_r_reg[0]_1\
    );
\demand_priority_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A2A2A000000000"
    )
        port map (
      I0 => col_wait_ns,
      I1 => \^order_q_r_reg[0]_0\,
      I2 => demand_priority_r_reg,
      I3 => req_priority_r,
      I4 => q_has_priority,
      I5 => \^idle_r_lcl_reg_2\,
      O => demand_priority_ns
    );
\demand_priority_r_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => demand_priority_r_reg_0,
      I1 => demand_priority_r_reg_1,
      I2 => demand_priority_r_reg_2,
      I3 => demand_priority_r_reg_3,
      I4 => order_q_r(0),
      I5 => order_q_r(1),
      O => \^order_q_r_reg[0]_0\
    );
\demand_priority_r_i_5__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF4FFFFF"
    )
        port map (
      I0 => q_has_rd,
      I1 => req_wr_r(0),
      I2 => req_bank_rdy_r,
      I3 => bm_end_r1_reg(0),
      I4 => \demand_priority_r_i_4__1\,
      O => q_has_rd_r_reg_0
    );
\grant_r[3]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFF"
    )
        port map (
      I0 => \^head_r\(0),
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => \grant_r[3]_i_3__2\,
      I3 => ras_timer_zero_r,
      I4 => \^wait_for_maint_r\,
      O => head_r_lcl_reg_0
    );
\grant_r[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF01FF"
    )
        port map (
      I0 => \ras_timer_r_reg[0]_3\,
      I1 => \grant_r[3]_i_5\,
      I2 => \ras_timer_r_reg[0]_4\,
      I3 => \head_r_lcl_i_3__1_n_0\,
      I4 => \^idle_r_lcl_reg_0\(0),
      I5 => col_wait_r,
      O => idle_r_lcl_reg_3
    );
granted_col_r_i_10: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40555555"
    )
        port map (
      I0 => pre_passing_open_bank_r,
      I1 => req_wr_r(0),
      I2 => bm_end_r1_reg_0,
      I3 => bm_end_r1_reg(0),
      I4 => \^pass_open_bank_r_lcl_reg_0\,
      O => pre_passing_open_bank_r_reg_0
    );
\head_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAEFAAAAEAE0AAAA"
    )
        port map (
      I0 => head_r_lcl_i_2_n_0,
      I1 => \head_r_lcl_i_3__1_n_0\,
      I2 => \q_entry_r[0]_i_4__0_n_0\,
      I3 => set_order_q,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => \^head_r\(0),
      O => \head_r_lcl_i_1__1_n_0\
    );
head_r_lcl_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"101010100000FF00"
    )
        port map (
      I0 => \q_entry_r[0]_i_4__0_n_0\,
      I1 => head_r_lcl_reg_1,
      I2 => \q_entry_r_reg[0]_2\,
      I3 => head_r_lcl_reg_2,
      I4 => head_r_lcl_reg_3,
      I5 => \^pre_bm_end_r_reg_0\,
      O => head_r_lcl_i_2_n_0
    );
\head_r_lcl_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => q_entry_r(0),
      I1 => \^q_entry_r_reg[1]_0\(0),
      O => \head_r_lcl_i_3__1_n_0\
    );
head_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \head_r_lcl_i_1__1_n_0\,
      Q => \^head_r\(0),
      R => \q_entry_r_reg[0]_1\
    );
\idle_r_lcl_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^idle_r_lcl_reg_2\,
      O => \^e\(0)
    );
idle_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^e\(0),
      Q => \^idle_r_lcl_reg_0\(0),
      R => '0'
    );
\maint_controller.maint_hit_busies_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F000200"
    )
        port map (
      I0 => \^idle_r_lcl_reg_2\,
      I1 => \maint_controller.maint_hit_busies_r_reg[2]\,
      I2 => q_has_priority_r_reg_1,
      I3 => \^pre_bm_end_r_reg_0\,
      I4 => \maint_controller.maint_hit_busies_r_reg[2]_0\(0),
      O => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\maint_controller.maint_hit_busies_r[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40555555"
    )
        port map (
      I0 => pre_bm_end_r,
      I1 => req_wr_r(0),
      I2 => bm_end_r1_reg_0,
      I3 => bm_end_r1_reg(0),
      I4 => \^pass_open_bank_r_lcl_reg_0\,
      O => \^pre_bm_end_r_reg_0\
    );
\order_q_r[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00470047FF444444"
    )
        port map (
      I0 => \order_q_r_reg[0]_1\,
      I1 => set_order_q,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      I3 => req_bank_rdy_r_reg,
      I4 => order_q_r(1),
      I5 => order_q_r(0),
      O => \order_q_r[0]_i_1__1_n_0\
    );
\order_q_r[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF8B0088008B8888"
    )
        port map (
      I0 => \order_q_r_reg[1]_0\,
      I1 => set_order_q,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      I3 => req_bank_rdy_r_reg,
      I4 => order_q_r(1),
      I5 => order_q_r(0),
      O => \order_q_r[1]_i_1__1_n_0\
    );
\order_q_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[0]_i_1__1_n_0\,
      Q => order_q_r(0),
      R => '0'
    );
\order_q_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[1]_i_1__1_n_0\,
      Q => order_q_r(1),
      R => '0'
    );
\ordered_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454005400540054"
    )
        port map (
      I0 => q_has_priority_r_reg_1,
      I1 => set_order_q,
      I2 => \^ordered_r\(0),
      I3 => bm_end_r1_reg(0),
      I4 => bm_end_r1_reg_0,
      I5 => req_wr_r(0),
      O => \ordered_r_lcl_i_1__1_n_0\
    );
ordered_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ordered_r_lcl_i_1__1_n_0\,
      Q => \^ordered_r\(0),
      R => '0'
    );
\pass_open_bank_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00000080"
    )
        port map (
      I0 => \pass_open_bank_r_lcl_i_2__0_n_0\,
      I1 => pass_open_bank_r_lcl_reg_1,
      I2 => \^tail_r\,
      I3 => pre_wait_r,
      I4 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      I5 => \^pass_open_bank_r_lcl_reg_0\,
      O => \^pass_open_bank_ns\
    );
\pass_open_bank_r_lcl_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => auto_pre_r_lcl_reg_2,
      I1 => \^wait_for_maint_r\,
      I2 => row_hit_r,
      O => \pass_open_bank_r_lcl_i_2__0_n_0\
    );
pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^pass_open_bank_ns\,
      Q => \^pass_open_bank_r_lcl_reg_0\,
      R => '0'
    );
pre_bm_end_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_bm_end_ns,
      Q => pre_bm_end_r,
      R => '0'
    );
pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_passing_open_bank_ns,
      Q => pre_passing_open_bank_r,
      R => '0'
    );
\q_entry_r[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDCFCCCCDDF0CCCC"
    )
        port map (
      I0 => \q_entry_r_reg[0]_2\,
      I1 => \q_entry_r_reg[0]_3\,
      I2 => \q_entry_r[0]_i_4__0_n_0\,
      I3 => set_order_q,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => q_entry_r(0),
      O => \q_entry_r[0]_i_1__1_n_0\
    );
\q_entry_r[0]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"404F"
    )
        port map (
      I0 => set_order_q,
      I1 => q_has_priority_r_reg_0,
      I2 => \^idle_r_lcl_reg_0\(0),
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      O => \q_entry_r[0]_i_4__0_n_0\
    );
\q_entry_r[1]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEFFFFF"
    )
        port map (
      I0 => set_order_q,
      I1 => q_has_priority_r_reg_0,
      I2 => \^idle_r_lcl_reg_0\(0),
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I4 => \^pre_bm_end_r_reg_0\,
      O => idle_r_lcl_reg_4
    );
\q_entry_r[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF09999000F9999"
    )
        port map (
      I0 => q_entry_r(0),
      I1 => \^q_entry_r_reg[1]_0\(0),
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      I3 => \q_entry_r[1]_i_2__2\,
      I4 => set_order_q,
      I5 => head_r_lcl_reg_1,
      O => \q_entry_r_reg[0]_0\
    );
\q_entry_r[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000707770777077"
    )
        port map (
      I0 => \^q\(1),
      I1 => p_130_out,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I3 => \^q\(2),
      I4 => p_13_out,
      I5 => \^q\(0),
      O => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\
    );
\q_entry_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[0]_i_1__1_n_0\,
      Q => q_entry_r(0),
      R => \q_entry_r_reg[0]_1\
    );
\q_entry_r_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r_reg[1]_1\,
      Q => \^q_entry_r_reg[1]_0\(0),
      S => \q_entry_r_reg[0]_1\
    );
\q_has_priority_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000000800000"
    )
        port map (
      I0 => q_has_priority_r_reg_0,
      I1 => rb_hit_busy_r(0),
      I2 => was_priority,
      I3 => q_has_priority_r_reg_1,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => q_has_priority,
      O => q_has_priority_ns
    );
q_has_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_priority_ns,
      Q => q_has_priority,
      R => '0'
    );
\q_has_rd_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AB00AB00FF00AB"
    )
        port map (
      I0 => q_has_rd,
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => q_has_rd_r_reg_1,
      I3 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      I4 => pass_open_bank_r_lcl_reg_1,
      I5 => was_wr,
      O => q_has_rd_ns
    );
q_has_rd_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_rd_ns,
      Q => q_has_rd,
      R => '0'
    );
\ras_timer_r[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[0]_i_2__0_n_0\,
      I1 => \^idle_r_lcl_reg_1\,
      I2 => \ras_timer_r_reg[0]\,
      O => D(0)
    );
\ras_timer_r[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \ras_timer_r_reg[0]_0\,
      I3 => \ras_timer_r_reg[0]_1\,
      I4 => \^q\(2),
      I5 => \ras_timer_r_reg[0]_2\,
      O => \ras_timer_r[0]_i_2__0_n_0\
    );
\ras_timer_r[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[1]_i_2__0_n_0\,
      I1 => \^idle_r_lcl_reg_1\,
      I2 => \ras_timer_r_reg[1]\,
      O => D(1)
    );
\ras_timer_r[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \ras_timer_r_reg[1]_0\,
      I3 => \ras_timer_r_reg[1]_1\,
      I4 => \^q\(2),
      I5 => \ras_timer_r_reg[1]_2\,
      O => \ras_timer_r[1]_i_2__0_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000AC"
    )
        port map (
      I0 => \^q\(0),
      I1 => p_28_out,
      I2 => \^idle_r_lcl_reg_2\,
      I3 => p_13_out,
      I4 => q_has_priority_r_reg_1,
      O => \rb_hit_busies.rb_hit_busies_ns\(3)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000A000C"
    )
        port map (
      I0 => \^q\(1),
      I1 => p_145_out,
      I2 => p_130_out,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      I4 => \^idle_r_lcl_reg_2\,
      O => \rb_hit_busies.rb_hit_busies_ns\(4)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AC00"
    )
        port map (
      I0 => \^q\(2),
      I1 => p_106_out,
      I2 => \^idle_r_lcl_reg_2\,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I4 => q_has_priority_r_reg_1,
      O => \rb_hit_busies.rb_hit_busies_ns\(5)
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_ns\(3),
      Q => \^q\(0),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_ns\(4),
      Q => \^q\(1),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_ns\(5),
      Q => \^q\(2),
      R => '0'
    );
\req_bank_rdy_r_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2202"
    )
        port map (
      I0 => col_wait_r,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_bank_rdy_r_reg,
      O => req_bank_rdy_ns
    );
\wait_for_maint_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFA8AA00000000"
    )
        port map (
      I0 => set_order_q,
      I1 => maint_sre_r,
      I2 => maint_zq_r,
      I3 => maint_rank_r,
      I4 => \^wait_for_maint_r\,
      I5 => wait_for_maint_r_lcl_reg_0,
      O => wait_for_maint_ns
    );
\wait_for_maint_r_lcl_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080800080008000"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => \^head_r\(0),
      I2 => accept_internal_r,
      I3 => ordered_r_lcl_reg_0,
      I4 => ordered_r_lcl_reg_1,
      I5 => app_en_r2,
      O => set_order_q
    );
wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wait_for_maint_ns,
      Q => \^wait_for_maint_r\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_bank_queue__parameterized2\ is
  port (
    idle_r_lcl_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    wait_for_maint_r : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    pass_open_bank_ns : out STD_LOGIC;
    q_has_rd : out STD_LOGIC;
    tail_r : out STD_LOGIC;
    head_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    ordered_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC;
    demand_priority_ns : out STD_LOGIC;
    \order_q_r_reg[0]_0\ : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    pre_bm_end_r_reg_1 : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11_0\ : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    CLK : in STD_LOGIC;
    pre_bm_end_ns : in STD_LOGIC;
    pre_passing_open_bank_ns : in STD_LOGIC;
    \q_entry_r_reg[0]_1\ : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC;
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    \ras_timer_r_reg[1]\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    \order_q_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    req_bank_rdy_r_reg : in STD_LOGIC;
    col_wait_ns : in STD_LOGIC;
    demand_priority_r_reg : in STD_LOGIC;
    req_priority_r : in STD_LOGIC;
    col_wait_r : in STD_LOGIC;
    demand_priority_r_reg_0 : in STD_LOGIC;
    demand_priority_r_reg_1 : in STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    act_wait_r_lcl_i_4_0 : in STD_LOGIC;
    act_wait_r_lcl_i_4_1 : in STD_LOGIC;
    act_wait_r_lcl_i_4_2 : in STD_LOGIC;
    p_145_out : in STD_LOGIC;
    p_130_out : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\ : in STD_LOGIC;
    \q_entry_r_reg[1]_0\ : in STD_LOGIC;
    \q_entry_r_reg[1]_1\ : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    \q_entry_r_reg[0]_2\ : in STD_LOGIC;
    head_r_lcl_reg_3 : in STD_LOGIC;
    q_has_priority_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC;
    p_106_out : in STD_LOGIC;
    p_67_out : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]\ : in STD_LOGIC;
    q_has_priority_r_reg_2 : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    maint_sre_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    maint_rank_r : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_reg : in STD_LOGIC;
    req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    accept_internal_r : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    ordered_r_lcl_reg_2 : in STD_LOGIC;
    app_en_r2 : in STD_LOGIC;
    \grant_r[3]_i_12\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    was_priority : in STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    was_wr : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    row_hit_r : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    pre_wait_r : in STD_LOGIC;
    \grant_r[3]_i_4__0\ : in STD_LOGIC;
    ras_timer_zero_r : in STD_LOGIC;
    \q_entry_r_reg[1]_2\ : in STD_LOGIC;
    \q_entry_r_reg[1]_3\ : in STD_LOGIC;
    \q_entry_r_reg[1]_4\ : in STD_LOGIC;
    \order_q_r_reg[1]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_bank_queue__parameterized2\ : entity is "mig_7series_v4_2_bank_queue";
end \mig_7series_0_mig_7series_v4_2_bank_queue__parameterized2\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_bank_queue__parameterized2\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal act_wait_r_lcl_i_5_n_0 : STD_LOGIC;
  signal \auto_pre_r_lcl_i_1__2_n_0\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg_0\ : STD_LOGIC;
  signal \compute_tail.tail_r_lcl_i_1__2_n_0\ : STD_LOGIC;
  signal \^head_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \head_r_lcl_i_1__2_n_0\ : STD_LOGIC;
  signal \head_r_lcl_i_2__2_n_0\ : STD_LOGIC;
  signal head_r_lcl_i_3_n_0 : STD_LOGIC;
  signal \^idle_r_lcl_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^idle_r_lcl_reg_1\ : STD_LOGIC;
  signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \order_q_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \order_q_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \^order_q_r_reg[0]_0\ : STD_LOGIC;
  signal \^ordered_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \ordered_r_lcl_i_1__0_n_0\ : STD_LOGIC;
  signal \^ordered_r_lcl_reg_0\ : STD_LOGIC;
  signal \^pass_open_bank_ns\ : STD_LOGIC;
  signal pass_open_bank_r_lcl_i_2_n_0 : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg_0\ : STD_LOGIC;
  signal pre_bm_end_r : STD_LOGIC;
  signal \^pre_bm_end_r_reg_0\ : STD_LOGIC;
  signal pre_passing_open_bank_r : STD_LOGIC;
  signal q_entry_ns : STD_LOGIC_VECTOR ( 0 to 0 );
  signal q_entry_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \q_entry_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_4__1_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_11_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_6__0_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_7__0_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_8__0_n_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[0]_0\ : STD_LOGIC;
  signal q_has_priority : STD_LOGIC;
  signal q_has_priority_ns : STD_LOGIC;
  signal \^q_has_rd\ : STD_LOGIC;
  signal q_has_rd_ns : STD_LOGIC;
  signal \ras_timer_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \rb_hit_busies.rb_hit_busies_ns\ : STD_LOGIC_VECTOR ( 6 downto 4 );
  signal rb_hit_busies_r : STD_LOGIC_VECTOR ( 6 downto 4 );
  signal \^rstdiv0_sync_r1_reg_rep__11_0\ : STD_LOGIC;
  signal set_order_q : STD_LOGIC;
  signal \^tail_r\ : STD_LOGIC;
  signal wait_for_maint_ns : STD_LOGIC;
  signal \^wait_for_maint_r\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of head_r_lcl_i_3 : label is "soft_lutpair583";
  attribute SOFT_HLUTNM of \idle_r_lcl_i_1__0\ : label is "soft_lutpair584";
  attribute SOFT_HLUTNM of \maint_controller.maint_hit_busies_r[3]_i_1\ : label is "soft_lutpair584";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_6__0\ : label is "soft_lutpair583";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_1\ : label is "soft_lutpair585";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_1\ : label is "soft_lutpair585";
begin
  E(0) <= \^e\(0);
  auto_pre_r_lcl_reg_0 <= \^auto_pre_r_lcl_reg_0\;
  head_r(0) <= \^head_r\(0);
  idle_r_lcl_reg_0(0) <= \^idle_r_lcl_reg_0\(0);
  idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\;
  \order_q_r_reg[0]_0\ <= \^order_q_r_reg[0]_0\;
  ordered_r(0) <= \^ordered_r\(0);
  ordered_r_lcl_reg_0 <= \^ordered_r_lcl_reg_0\;
  pass_open_bank_ns <= \^pass_open_bank_ns\;
  pass_open_bank_r_lcl_reg_0 <= \^pass_open_bank_r_lcl_reg_0\;
  pre_bm_end_r_reg_0 <= \^pre_bm_end_r_reg_0\;
  \q_entry_r_reg[0]_0\ <= \^q_entry_r_reg[0]_0\;
  q_has_rd <= \^q_has_rd\;
  \rstdiv0_sync_r1_reg_rep__11_0\ <= \^rstdiv0_sync_r1_reg_rep__11_0\;
  tail_r <= \^tail_r\;
  wait_for_maint_r <= \^wait_for_maint_r\;
accept_internal_r_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000D"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => set_order_q,
      I2 => \^pre_bm_end_r_reg_0\,
      I3 => q_has_priority_r_reg_2,
      O => \^idle_r_lcl_reg_1\
    );
\act_wait_r_lcl_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAEAEAEA"
    )
        port map (
      I0 => q_has_priority_r_reg_2,
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => Q(0),
      I3 => bm_end_r1_reg,
      I4 => req_wr_r(0),
      I5 => pre_bm_end_r,
      O => \^rstdiv0_sync_r1_reg_rep__11_0\
    );
act_wait_r_lcl_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => q_entry_r(0),
      I1 => q_entry_r(1),
      I2 => \^idle_r_lcl_reg_0\(0),
      I3 => act_wait_r_lcl_i_5_n_0,
      O => \^q_entry_r_reg[0]_0\
    );
act_wait_r_lcl_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22F2FFFF22F222F2"
    )
        port map (
      I0 => rb_hit_busies_r(5),
      I1 => act_wait_r_lcl_i_4_0,
      I2 => rb_hit_busies_r(6),
      I3 => act_wait_r_lcl_i_4_1,
      I4 => act_wait_r_lcl_i_4_2,
      I5 => rb_hit_busies_r(4),
      O => act_wait_r_lcl_i_5_n_0
    );
\act_wait_r_lcl_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40555555"
    )
        port map (
      I0 => pre_passing_open_bank_r,
      I1 => req_wr_r(0),
      I2 => bm_end_r1_reg,
      I3 => Q(0),
      I4 => \^pass_open_bank_r_lcl_reg_0\,
      O => pre_passing_open_bank_r_reg_0
    );
\auto_pre_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AEAEAEEE"
    )
        port map (
      I0 => \^auto_pre_r_lcl_reg_0\,
      I1 => auto_pre_r_lcl_reg_1,
      I2 => row_hit_r,
      I3 => \^wait_for_maint_r\,
      I4 => auto_pre_r_lcl_reg_2,
      I5 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      O => \auto_pre_r_lcl_i_1__2_n_0\
    );
auto_pre_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \auto_pre_r_lcl_i_1__2_n_0\,
      Q => \^auto_pre_r_lcl_reg_0\,
      R => '0'
    );
\bm_end_r1_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAAAAAA"
    )
        port map (
      I0 => pre_bm_end_r,
      I1 => req_wr_r(0),
      I2 => bm_end_r1_reg,
      I3 => Q(0),
      I4 => \^pass_open_bank_r_lcl_reg_0\,
      O => \^pre_bm_end_r_reg_0\
    );
\compute_tail.tail_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF1F5F1FFF0F0F0"
    )
        port map (
      I0 => pass_open_bank_r_lcl_reg_1,
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => set_order_q,
      I3 => head_r_lcl_reg_1,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => \^tail_r\,
      O => \compute_tail.tail_r_lcl_i_1__2_n_0\
    );
\compute_tail.tail_r_lcl_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_0\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\,
      I2 => p_130_out,
      O => pre_bm_end_r_reg_1
    );
\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \compute_tail.tail_r_lcl_i_1__2_n_0\,
      Q => \^tail_r\,
      R => \q_entry_r_reg[0]_1\
    );
demand_priority_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A2A2A000000000"
    )
        port map (
      I0 => col_wait_ns,
      I1 => \^order_q_r_reg[0]_0\,
      I2 => demand_priority_r_reg,
      I3 => req_priority_r,
      I4 => q_has_priority,
      I5 => \^idle_r_lcl_reg_1\,
      O => demand_priority_ns
    );
demand_priority_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => demand_priority_r_reg_0,
      I1 => demand_priority_r_reg_1,
      I2 => demand_priority_r_reg_2,
      I3 => demand_priority_r_reg_3,
      I4 => order_q_r(0),
      I5 => order_q_r(1),
      O => \^order_q_r_reg[0]_0\
    );
\grant_r[3]_i_12__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFF"
    )
        port map (
      I0 => \^head_r\(0),
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => \grant_r[3]_i_4__0\,
      I3 => ras_timer_zero_r,
      I4 => \^wait_for_maint_r\,
      O => head_r_lcl_reg_0
    );
\grant_r[3]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00808080"
    )
        port map (
      I0 => \grant_r[3]_i_12\(0),
      I1 => \^pass_open_bank_r_lcl_reg_0\,
      I2 => Q(0),
      I3 => bm_end_r1_reg,
      I4 => req_wr_r(0),
      I5 => pre_passing_open_bank_r,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\
    );
\head_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAFFFFEAAA0000"
    )
        port map (
      I0 => \head_r_lcl_i_2__2_n_0\,
      I1 => head_r_lcl_reg_1,
      I2 => head_r_lcl_reg_2,
      I3 => \^pre_bm_end_r_reg_0\,
      I4 => \q_entry_r[1]_i_6__0_n_0\,
      I5 => \^head_r\(0),
      O => \head_r_lcl_i_1__2_n_0\
    );
\head_r_lcl_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"004000400040004F"
    )
        port map (
      I0 => q_entry_r(1),
      I1 => q_entry_r(0),
      I2 => head_r_lcl_i_3_n_0,
      I3 => \^pre_bm_end_r_reg_0\,
      I4 => head_r_lcl_reg_3,
      I5 => \q_entry_r[0]_i_4__1_n_0\,
      O => \head_r_lcl_i_2__2_n_0\
    );
head_r_lcl_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"404F"
    )
        port map (
      I0 => set_order_q,
      I1 => q_has_priority_r_reg_0,
      I2 => \^idle_r_lcl_reg_0\(0),
      I3 => \q_entry_r[1]_i_11_n_0\,
      O => head_r_lcl_i_3_n_0
    );
head_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \head_r_lcl_i_1__2_n_0\,
      Q => \^head_r\(0),
      R => \q_entry_r_reg[0]_1\
    );
\idle_r_lcl_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      O => \^e\(0)
    );
idle_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^e\(0),
      Q => \^idle_r_lcl_reg_0\(0),
      R => '0'
    );
\maint_controller.maint_hit_busies_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000F0002"
    )
        port map (
      I0 => \^idle_r_lcl_reg_1\,
      I1 => \maint_controller.maint_hit_busies_r_reg[3]\,
      I2 => q_has_priority_r_reg_2,
      I3 => \^pre_bm_end_r_reg_0\,
      I4 => \maint_controller.maint_hit_busies_r_reg[3]_0\(0),
      O => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\order_q_r[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00470047FF444444"
    )
        port map (
      I0 => \^ordered_r_lcl_reg_0\,
      I1 => set_order_q,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      I3 => req_bank_rdy_r_reg,
      I4 => order_q_r(1),
      I5 => order_q_r(0),
      O => \order_q_r[0]_i_1__2_n_0\
    );
\order_q_r[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969669"
    )
        port map (
      I0 => \order_q_r_reg[0]_1\(0),
      I1 => \order_q_r_reg[0]_1\(1),
      I2 => \order_q_r_reg[0]_1\(2),
      I3 => \^ordered_r\(0),
      I4 => req_bank_rdy_r_reg,
      O => \^ordered_r_lcl_reg_0\
    );
\order_q_r[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF8B0088008B8888"
    )
        port map (
      I0 => \order_q_r_reg[1]_0\,
      I1 => set_order_q,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      I3 => req_bank_rdy_r_reg,
      I4 => order_q_r(1),
      I5 => order_q_r(0),
      O => \order_q_r[1]_i_1__2_n_0\
    );
\order_q_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[0]_i_1__2_n_0\,
      Q => order_q_r(0),
      R => '0'
    );
\order_q_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[1]_i_1__2_n_0\,
      Q => order_q_r(1),
      R => '0'
    );
\ordered_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454005400540054"
    )
        port map (
      I0 => q_has_priority_r_reg_2,
      I1 => set_order_q,
      I2 => \^ordered_r\(0),
      I3 => Q(0),
      I4 => bm_end_r1_reg,
      I5 => req_wr_r(0),
      O => \ordered_r_lcl_i_1__0_n_0\
    );
ordered_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ordered_r_lcl_i_1__0_n_0\,
      Q => \^ordered_r\(0),
      R => '0'
    );
\pass_open_bank_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00000080"
    )
        port map (
      I0 => pass_open_bank_r_lcl_i_2_n_0,
      I1 => pass_open_bank_r_lcl_reg_1,
      I2 => \^tail_r\,
      I3 => pre_wait_r,
      I4 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      I5 => \^pass_open_bank_r_lcl_reg_0\,
      O => \^pass_open_bank_ns\
    );
pass_open_bank_r_lcl_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => auto_pre_r_lcl_reg_2,
      I1 => \^wait_for_maint_r\,
      I2 => row_hit_r,
      O => pass_open_bank_r_lcl_i_2_n_0
    );
pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^pass_open_bank_ns\,
      Q => \^pass_open_bank_r_lcl_reg_0\,
      R => '0'
    );
pre_bm_end_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_bm_end_ns,
      Q => pre_bm_end_r,
      R => '0'
    );
pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_passing_open_bank_ns,
      Q => pre_passing_open_bank_r,
      R => '0'
    );
\q_entry_r[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => q_entry_ns(0),
      I1 => \q_entry_r[1]_i_6__0_n_0\,
      I2 => q_entry_r(0),
      O => \q_entry_r[0]_i_1__2_n_0\
    );
\q_entry_r[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D782D7D7828282D7"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_0\,
      I1 => q_has_priority_r_reg_0,
      I2 => \q_entry_r_reg[0]_2\,
      I3 => set_order_q,
      I4 => q_entry_r(0),
      I5 => \q_entry_r[0]_i_4__1_n_0\,
      O => q_entry_ns(0)
    );
\q_entry_r[0]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969669"
    )
        port map (
      I0 => \q_entry_r[1]_i_11_n_0\,
      I1 => q_has_priority_r_reg_1,
      I2 => rb_hit_busy_r(1),
      I3 => rb_hit_busy_r(2),
      I4 => rb_hit_busy_r(0),
      O => \q_entry_r[0]_i_4__1_n_0\
    );
\q_entry_r[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7077000070777077"
    )
        port map (
      I0 => rb_hit_busies_r(4),
      I1 => p_130_out,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\,
      I3 => rb_hit_busies_r(6),
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I5 => rb_hit_busies_r(5),
      O => \q_entry_r[1]_i_11_n_0\
    );
\q_entry_r[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3CAAFFFF3CAA0000"
    )
        port map (
      I0 => \q_entry_r[1]_i_2_n_0\,
      I1 => \q_entry_r_reg[1]_2\,
      I2 => \q_entry_r_reg[1]_3\,
      I3 => \q_entry_r_reg[1]_4\,
      I4 => \q_entry_r[1]_i_6__0_n_0\,
      I5 => q_entry_r(1),
      O => \q_entry_r[1]_i_1__2_n_0\
    );
\q_entry_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F11F1111"
    )
        port map (
      I0 => \q_entry_r[1]_i_7__0_n_0\,
      I1 => \q_entry_r[1]_i_8__0_n_0\,
      I2 => \q_entry_r_reg[1]_0\,
      I3 => \q_entry_r_reg[1]_1\,
      I4 => \^pre_bm_end_r_reg_0\,
      O => \q_entry_r[1]_i_2_n_0\
    );
\q_entry_r[1]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEAEF"
    )
        port map (
      I0 => set_order_q,
      I1 => q_has_priority_r_reg_0,
      I2 => \^idle_r_lcl_reg_0\(0),
      I3 => \q_entry_r[1]_i_11_n_0\,
      I4 => \^pre_bm_end_r_reg_0\,
      O => \q_entry_r[1]_i_6__0_n_0\
    );
\q_entry_r[1]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8117177E00000000"
    )
        port map (
      I0 => \q_entry_r[1]_i_11_n_0\,
      I1 => q_has_priority_r_reg_1,
      I2 => rb_hit_busy_r(1),
      I3 => rb_hit_busy_r(2),
      I4 => rb_hit_busy_r(0),
      I5 => set_order_q,
      O => \q_entry_r[1]_i_7__0_n_0\
    );
\q_entry_r[1]_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABBA"
    )
        port map (
      I0 => \^pre_bm_end_r_reg_0\,
      I1 => set_order_q,
      I2 => q_entry_r(0),
      I3 => q_entry_r(1),
      O => \q_entry_r[1]_i_8__0_n_0\
    );
\q_entry_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[0]_i_1__2_n_0\,
      Q => q_entry_r(0),
      S => \q_entry_r_reg[0]_1\
    );
\q_entry_r_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[1]_i_1__2_n_0\,
      Q => q_entry_r(1),
      S => \q_entry_r_reg[0]_1\
    );
\q_has_priority_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF00000080"
    )
        port map (
      I0 => q_has_priority_r_reg_1,
      I1 => q_has_priority_r_reg_0,
      I2 => was_priority,
      I3 => q_has_priority_r_reg_2,
      I4 => \^pre_bm_end_r_reg_0\,
      I5 => q_has_priority,
      O => q_has_priority_ns
    );
q_has_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_priority_ns,
      Q => q_has_priority,
      R => '0'
    );
\q_has_rd_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AB00AB00FF00AB"
    )
        port map (
      I0 => \^q_has_rd\,
      I1 => \^idle_r_lcl_reg_0\(0),
      I2 => q_has_rd_r_reg_0,
      I3 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      I4 => pass_open_bank_r_lcl_reg_1,
      I5 => was_wr,
      O => q_has_rd_ns
    );
q_has_rd_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_rd_ns,
      Q => \^q_has_rd\,
      R => '0'
    );
\ras_timer_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[0]_i_2_n_0\,
      I1 => \^q_entry_r_reg[0]_0\,
      I2 => \ras_timer_r_reg[0]\,
      O => D(0)
    );
\ras_timer_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => rb_hit_busies_r(4),
      I1 => rb_hit_busies_r(5),
      I2 => \ras_timer_r_reg[0]_0\,
      I3 => \ras_timer_r_reg[0]_1\,
      I4 => rb_hit_busies_r(6),
      I5 => \ras_timer_r_reg[0]_2\,
      O => \ras_timer_r[0]_i_2_n_0\
    );
\ras_timer_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[1]_i_2_n_0\,
      I1 => \^q_entry_r_reg[0]_0\,
      I2 => \ras_timer_r_reg[1]\,
      O => D(1)
    );
\ras_timer_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => rb_hit_busies_r(4),
      I1 => rb_hit_busies_r(5),
      I2 => \ras_timer_r_reg[1]_0\,
      I3 => \ras_timer_r_reg[1]_1\,
      I4 => rb_hit_busies_r(6),
      I5 => \ras_timer_r_reg[1]_2\,
      O => \ras_timer_r[1]_i_2_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000A000C"
    )
        port map (
      I0 => rb_hit_busies_r(4),
      I1 => p_145_out,
      I2 => p_130_out,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      I4 => \^idle_r_lcl_reg_1\,
      O => \rb_hit_busies.rb_hit_busies_ns\(4)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AC00"
    )
        port map (
      I0 => rb_hit_busies_r(5),
      I1 => p_106_out,
      I2 => \^idle_r_lcl_reg_1\,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      O => \rb_hit_busies.rb_hit_busies_ns\(5)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AC00"
    )
        port map (
      I0 => rb_hit_busies_r(6),
      I1 => p_67_out,
      I2 => \^idle_r_lcl_reg_1\,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\,
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      O => \rb_hit_busies.rb_hit_busies_ns\(6)
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_ns\(4),
      Q => rb_hit_busies_r(4),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_ns\(5),
      Q => rb_hit_busies_r(5),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_ns\(6),
      Q => rb_hit_busies_r(6),
      R => '0'
    );
req_bank_rdy_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2202"
    )
        port map (
      I0 => col_wait_r,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_bank_rdy_r_reg,
      O => req_bank_rdy_ns
    );
wait_for_maint_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFA8AA00000000"
    )
        port map (
      I0 => set_order_q,
      I1 => maint_sre_r,
      I2 => maint_zq_r,
      I3 => maint_rank_r,
      I4 => \^wait_for_maint_r\,
      I5 => wait_for_maint_r_lcl_reg_0,
      O => wait_for_maint_ns
    );
wait_for_maint_r_lcl_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080800080008000"
    )
        port map (
      I0 => \^idle_r_lcl_reg_0\(0),
      I1 => \^head_r\(0),
      I2 => accept_internal_r,
      I3 => ordered_r_lcl_reg_1,
      I4 => ordered_r_lcl_reg_2,
      I5 => app_en_r2,
      O => set_order_q
    );
wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wait_for_maint_ns,
      Q => \^wait_for_maint_r\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_bank_state is
  port (
    bm_end_r1 : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    ras_timer_zero_r : out STD_LOGIC;
    pre_wait_r : out STD_LOGIC;
    demand_act_priority_r : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r_reg_0 : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_wait_r_reg_0 : out STD_LOGIC;
    col_wait_r_reg_1 : out STD_LOGIC;
    act_wait_r_lcl_reg_1 : out STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    demand_priority_r_reg_1 : out STD_LOGIC;
    pre_bm_end_ns : out STD_LOGIC;
    pre_passing_open_bank_ns : out STD_LOGIC;
    col_wait_ns : out STD_LOGIC;
    act_wait_r_lcl_reg_2 : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    ras_timer_zero_r_reg_1 : out STD_LOGIC;
    ras_timer_zero_r_reg_2 : out STD_LOGIC;
    demand_priority_r_reg_2 : out STD_LOGIC;
    \grant_r_reg[0]_0\ : out STD_LOGIC;
    \grant_r_reg[0]_1\ : out STD_LOGIC;
    p_130_out : in STD_LOGIC;
    CLK : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    demand_priority_ns : in STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC;
    ofs_rdy_r0 : in STD_LOGIC;
    start_wtp_timer0 : in STD_LOGIC;
    \rd_this_rank_r_reg[0]_0\ : in STD_LOGIC;
    col_wait_r_reg_2 : in STD_LOGIC;
    \grant_r_reg[0]_2\ : in STD_LOGIC;
    col_wait_r_reg_3 : in STD_LOGIC;
    ras_timer_zero_r_reg_3 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pre_wait_r_reg_0 : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_1\ : in STD_LOGIC;
    act_wait_r_lcl_reg_3 : in STD_LOGIC;
    act_wait_r_lcl_reg_4 : in STD_LOGIC;
    col_wait_r_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    \rtp_timer_r_reg[0]_0\ : in STD_LOGIC;
    \rtp_timer_r_reg[0]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[23]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_address_reg[23]_0\ : in STD_LOGIC;
    wait_for_maint_r : in STD_LOGIC;
    idle_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    head_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    tail_r : in STD_LOGIC;
    auto_pre_r_lcl_reg : in STD_LOGIC;
    rb_hit_busy_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[1]\ : in STD_LOGIC;
    \grant_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[1]_1\ : in STD_LOGIC;
    \grant_r_reg[1]_2\ : in STD_LOGIC;
    \grant_r_reg[1]_3\ : in STD_LOGIC;
    demand_priority_r_0 : in STD_LOGIC;
    demanded_prior_r_1 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    demand_priority_r_2 : in STD_LOGIC;
    override_demand_r : in STD_LOGIC;
    granted_col_r_i_3 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    q_has_rd : in STD_LOGIC;
    req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_bank_state : entity is "mig_7series_v4_2_bank_state";
end mig_7series_0_mig_7series_v4_2_bank_state;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_bank_state is
  signal act_wait_ns : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_1\ : STD_LOGIC;
  signal \^bm_end_r1\ : STD_LOGIC;
  signal \col_wait_r_i_1__2_n_0\ : STD_LOGIC;
  signal \^col_wait_r_reg_0\ : STD_LOGIC;
  signal demand_act_priority_ns : STD_LOGIC;
  signal \^demand_act_priority_r\ : STD_LOGIC;
  signal demand_priority_r_i_6_n_0 : STD_LOGIC;
  signal \^demand_priority_r_reg_0\ : STD_LOGIC;
  signal demanded_prior_ns : STD_LOGIC;
  signal \^demanded_prior_r_reg_0\ : STD_LOGIC;
  signal \^pre_passing_open_bank_ns\ : STD_LOGIC;
  signal pre_wait_ns : STD_LOGIC;
  signal \^pre_wait_r\ : STD_LOGIC;
  signal pre_wait_r_i_2_n_0 : STD_LOGIC;
  signal ras_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ras_timer_zero_ns : STD_LOGIC;
  signal \^ras_timer_zero_r\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_1\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_2\ : STD_LOGIC;
  signal req_bank_rdy_r : STD_LOGIC;
  signal rtp_timer_r : STD_LOGIC;
  signal \rtp_timer_r[0]_i_1_n_0\ : STD_LOGIC;
  signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal starve_limit_cntr_r0 : STD_LOGIC;
  signal \starve_limit_cntr_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[2]_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \col_wait_r_i_1__2\ : label is "soft_lutpair557";
  attribute SOFT_HLUTNM of \grant_r[1]_i_3\ : label is "soft_lutpair560";
  attribute SOFT_HLUTNM of \grant_r[2]_i_2__2\ : label is "soft_lutpair558";
  attribute SOFT_HLUTNM of pre_bm_end_r_i_1 : label is "soft_lutpair558";
  attribute SOFT_HLUTNM of ras_timer_zero_r_i_2 : label is "soft_lutpair557";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[0]_i_1\ : label is "soft_lutpair560";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1\ : label is "soft_lutpair559";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1\ : label is "soft_lutpair559";
begin
  act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\;
  act_wait_r_lcl_reg_1 <= \^act_wait_r_lcl_reg_1\;
  bm_end_r1 <= \^bm_end_r1\;
  col_wait_r_reg_0 <= \^col_wait_r_reg_0\;
  demand_act_priority_r <= \^demand_act_priority_r\;
  demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\;
  demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\;
  pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\;
  pre_wait_r <= \^pre_wait_r\;
  ras_timer_zero_r <= \^ras_timer_zero_r\;
  ras_timer_zero_r_reg_1 <= \^ras_timer_zero_r_reg_1\;
  ras_timer_zero_r_reg_2 <= \^ras_timer_zero_r_reg_2\;
\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^act_wait_r_lcl_reg_0\,
      Q => act_this_rank_r(0),
      R => '0'
    );
\act_wait_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAEAEFFAEAEAEAE"
    )
        port map (
      I0 => \^bm_end_r1\,
      I1 => act_wait_r_lcl_reg_3,
      I2 => act_wait_r_lcl_reg_4,
      I3 => col_wait_r_reg_3,
      I4 => col_wait_r_reg_4(0),
      I5 => \^act_wait_r_lcl_reg_0\,
      O => act_wait_ns
    );
act_wait_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => act_wait_ns,
      Q => \^act_wait_r_lcl_reg_0\,
      R => '0'
    );
\auto_pre_r_lcl_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000800080808000"
    )
        port map (
      I0 => tail_r,
      I1 => auto_pre_r_lcl_reg,
      I2 => rb_hit_busy_r(0),
      I3 => \^act_wait_r_lcl_reg_0\,
      I4 => \^col_wait_r_reg_0\,
      I5 => Q(0),
      O => \compute_tail.tail_r_lcl_reg\
    );
bm_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_130_out,
      Q => \^bm_end_r1\,
      R => '0'
    );
\cmd_pipe_plus.mc_address[23]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => col_wait_r_reg_4(0),
      I2 => \cmd_pipe_plus.mc_address_reg[23]\(0),
      I3 => \cmd_pipe_plus.mc_address_reg[23]_0\,
      O => act_wait_r_lcl_reg_2
    );
\col_wait_r_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAFFEAEA"
    )
        port map (
      I0 => col_wait_r_reg_3,
      I1 => col_wait_r_reg_4(0),
      I2 => \^act_wait_r_lcl_reg_0\,
      I3 => Q(0),
      I4 => \^col_wait_r_reg_0\,
      O => \col_wait_r_i_1__2_n_0\
    );
col_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \col_wait_r_i_1__2_n_0\,
      Q => \^col_wait_r_reg_0\,
      R => col_wait_r_reg_2
    );
demand_act_priority_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \^demand_act_priority_r\,
      I1 => wait_for_maint_r,
      I2 => \^ras_timer_zero_r\,
      I3 => \^act_wait_r_lcl_reg_0\,
      I4 => idle_r(0),
      I5 => head_r(0),
      O => demand_act_priority_ns
    );
demand_act_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demand_act_priority_ns,
      Q => \^demand_act_priority_r\,
      R => '0'
    );
\demand_priority_r_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EAFFEAEA"
    )
        port map (
      I0 => col_wait_r_reg_3,
      I1 => col_wait_r_reg_4(0),
      I2 => \^act_wait_r_lcl_reg_0\,
      I3 => Q(0),
      I4 => \^col_wait_r_reg_0\,
      I5 => \rtp_timer_r_reg[0]_1\,
      O => col_wait_ns
    );
demand_priority_r_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1000"
    )
        port map (
      I0 => demand_priority_r_i_6_n_0,
      I1 => Q(0),
      I2 => demand_priority_r_reg_3,
      I3 => req_bank_rdy_r,
      I4 => \^demand_priority_r_reg_0\,
      O => \grant_r_reg[0]_1\
    );
demand_priority_r_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4FFFFFFF"
    )
        port map (
      I0 => q_has_rd,
      I1 => req_wr_r(0),
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => starve_limit_cntr_r(2),
      O => demand_priority_r_i_6_n_0
    );
demand_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demand_priority_ns,
      Q => \^demand_priority_r_reg_0\,
      R => '0'
    );
demanded_prior_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000D00DDDDDDDD"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r_reg_0\,
      I2 => Q(1),
      I3 => demand_priority_r_0,
      I4 => demanded_prior_r_1,
      I5 => demanded_prior_r_reg_1,
      O => demanded_prior_ns
    );
demanded_prior_r_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => Q(0),
      I1 => \^demand_priority_r_reg_0\,
      I2 => \^demanded_prior_r_reg_0\,
      O => \grant_r_reg[0]_0\
    );
demanded_prior_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demanded_prior_ns,
      Q => \^demanded_prior_r_reg_0\,
      R => '0'
    );
\grant_r[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000800088888"
    )
        port map (
      I0 => \grant_r_reg[1]\,
      I1 => \^ras_timer_zero_r_reg_1\,
      I2 => \grant_r_reg[1]_0\(0),
      I3 => \grant_r_reg[1]_0\(1),
      I4 => \grant_r_reg[1]_1\,
      I5 => \^ras_timer_zero_r_reg_2\,
      O => ras_timer_zero_r_reg_0(0)
    );
\grant_r[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"32"
    )
        port map (
      I0 => \^col_wait_r_reg_0\,
      I1 => \grant_r_reg[0]_2\,
      I2 => col_wait_r_reg_3,
      O => col_wait_r_reg_1
    );
\grant_r[2]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \^ras_timer_zero_r\,
      I1 => \^pre_wait_r\,
      I2 => pre_bm_end_r_reg_0,
      I3 => pre_bm_end_r_reg(0),
      O => \^ras_timer_zero_r_reg_2\
    );
\grant_r[2]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000E00"
    )
        port map (
      I0 => \rnk_config_strobe_r_reg[0]\,
      I1 => \^demand_priority_r_reg_0\,
      I2 => \rnk_config_strobe_r_reg[0]_0\,
      I3 => \^col_wait_r_reg_0\,
      I4 => \rnk_config_strobe_r_reg[0]_1\,
      O => demand_priority_r_reg_1
    );
\grant_r[3]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF0000FFF7"
    )
        port map (
      I0 => \^ras_timer_zero_r\,
      I1 => \^pre_wait_r\,
      I2 => pre_bm_end_r_reg_0,
      I3 => pre_bm_end_r_reg(0),
      I4 => \grant_r_reg[1]_2\,
      I5 => \grant_r_reg[1]_3\,
      O => \^ras_timer_zero_r_reg_1\
    );
granted_col_r_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010011111111"
    )
        port map (
      I0 => demand_priority_r_2,
      I1 => override_demand_r,
      I2 => Q(0),
      I3 => \^demand_priority_r_reg_0\,
      I4 => \^demanded_prior_r_reg_0\,
      I5 => granted_col_r_i_3,
      O => demand_priority_r_reg_2
    );
ofs_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofs_rdy_r0,
      Q => ofs_rdy_r,
      R => ofs_rdy_r_reg_0
    );
pre_bm_end_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEAAAAAA"
    )
        port map (
      I0 => \^pre_passing_open_bank_ns\,
      I1 => pre_bm_end_r_reg(0),
      I2 => pre_bm_end_r_reg_0,
      I3 => \^pre_wait_r\,
      I4 => \^ras_timer_zero_r\,
      O => pre_bm_end_ns
    );
pre_passing_open_bank_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAA20"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => rtp_timer_r,
      I4 => Q(0),
      O => \^pre_passing_open_bank_ns\
    );
pre_wait_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020F00000202"
    )
        port map (
      I0 => \^pre_wait_r\,
      I1 => pre_wait_r_i_2_n_0,
      I2 => pass_open_bank_ns,
      I3 => \rtp_timer_r_reg[0]_0\,
      I4 => pre_wait_r_reg_0,
      I5 => rtp_timer_r,
      O => pre_wait_ns
    );
pre_wait_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => \^ras_timer_zero_r\,
      I1 => \^pre_wait_r\,
      I2 => pre_bm_end_r_reg_0,
      I3 => pre_bm_end_r_reg(0),
      O => pre_wait_r_i_2_n_0
    );
pre_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_wait_ns,
      Q => \^pre_wait_r\,
      R => '0'
    );
\ras_timer_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002F22"
    )
        port map (
      I0 => ras_timer_r(1),
      I1 => ras_timer_r(0),
      I2 => \rd_this_rank_r_reg[0]_0\,
      I3 => Q(0),
      I4 => pre_wait_r_reg_0,
      I5 => \^bm_end_r1\,
      O => \ras_timer_r_reg[1]_0\
    );
\ras_timer_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0202020F02020F0"
    )
        port map (
      I0 => Q(0),
      I1 => \rd_this_rank_r_reg[0]_0\,
      I2 => ras_timer_zero_r_reg_3,
      I3 => ras_timer_r(1),
      I4 => ras_timer_r(0),
      I5 => \^act_wait_r_lcl_reg_1\,
      O => \grant_r_reg[0]\
    );
\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => ras_timer_r(0),
      R => '0'
    );
\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => ras_timer_r(1),
      R => '0'
    );
ras_timer_zero_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0EFF00FF0EFF0EFF"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_1\,
      I1 => ras_timer_r(0),
      I2 => ras_timer_r(1),
      I3 => ras_timer_zero_r_reg_3,
      I4 => \rd_this_rank_r_reg[0]_0\,
      I5 => Q(0),
      O => ras_timer_zero_ns
    );
ras_timer_zero_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => col_wait_r_reg_4(0),
      O => \^act_wait_r_lcl_reg_1\
    );
ras_timer_zero_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ras_timer_zero_ns,
      Q => \^ras_timer_zero_r\,
      R => '0'
    );
\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_this_rank_r_reg[0]_0\,
      Q => rd_this_rank_r(0),
      R => '0'
    );
req_bank_rdy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => req_bank_rdy_ns,
      Q => req_bank_rdy_r,
      R => '0'
    );
\rtp_timer_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => rtp_timer_r,
      I1 => Q(0),
      I2 => \rtp_timer_r_reg[0]_0\,
      I3 => \rtp_timer_r_reg[0]_1\,
      O => \rtp_timer_r[0]_i_1_n_0\
    );
\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtp_timer_r[0]_i_1_n_0\,
      Q => rtp_timer_r,
      R => '0'
    );
\starve_limit_cntr_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r0,
      I2 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[0]_i_1_n_0\
    );
\starve_limit_cntr_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => starve_limit_cntr_r(1),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[1]_i_1_n_0\
    );
\starve_limit_cntr_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[2]_i_1_n_0\
    );
\starve_limit_cntr_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007F000000"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => req_bank_rdy_r,
      I4 => demand_priority_r_reg_3,
      I5 => Q(0),
      O => starve_limit_cntr_r0
    );
\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[0]_i_1_n_0\,
      Q => starve_limit_cntr_r(0),
      R => '0'
    );
\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[1]_i_1_n_0\,
      Q => starve_limit_cntr_r(1),
      R => '0'
    );
\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[2]_i_1_n_0\,
      Q => starve_limit_cntr_r(2),
      R => '0'
    );
\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_wtp_timer0,
      Q => wr_this_rank_r(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_bank_state__parameterized0\ is
  port (
    bm_end_r1_0 : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    ras_timer_zero_r : out STD_LOGIC;
    pre_wait_r : out STD_LOGIC;
    demand_act_priority_r : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r_reg_0 : out STD_LOGIC;
    demanded_prior_r : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_wait_r_reg_0 : out STD_LOGIC;
    rnk_config_valid_ns : out STD_LOGIC;
    demand_priority_r_reg_1 : out STD_LOGIC;
    rnk_config_strobe_ns : out STD_LOGIC;
    col_wait_r_reg_1 : out STD_LOGIC;
    col_wait_ns : out STD_LOGIC;
    pre_bm_end_ns : out STD_LOGIC;
    pre_passing_open_bank_ns : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : out STD_LOGIC;
    rd_wr_r_lcl_reg : out STD_LOGIC;
    demand_priority_r_reg_2 : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    p_91_out : in STD_LOGIC;
    CLK : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    demand_priority_ns : in STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC;
    ofs_rdy_r0 : in STD_LOGIC;
    start_wtp_timer0 : in STD_LOGIC;
    \rd_this_rank_r_reg[0]_0\ : in STD_LOGIC;
    col_wait_r_reg_2 : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_1\ : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    rnk_config_valid_r : in STD_LOGIC;
    \grant_r_reg[1]_0\ : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    demanded_prior_r_reg_0 : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_2\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_3\ : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r_reg_3 : in STD_LOGIC;
    act_wait_r_lcl_reg_3 : in STD_LOGIC;
    act_wait_r_lcl_reg_4 : in STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    \rtp_timer_r_reg[0]_0\ : in STD_LOGIC;
    \rtp_timer_r_reg[0]_1\ : in STD_LOGIC;
    tail_r : in STD_LOGIC;
    auto_pre_r_lcl_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r : in STD_LOGIC;
    demand_act_priority_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    head_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    demanded_prior_r_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_4 : in STD_LOGIC;
    q_has_rd : in STD_LOGIC;
    req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_bank_state__parameterized0\ : entity is "mig_7series_v4_2_bank_state";
end \mig_7series_0_mig_7series_v4_2_bank_state__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_bank_state__parameterized0\ is
  signal act_wait_ns : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC;
  signal \^bm_end_r1_0\ : STD_LOGIC;
  signal \col_wait_r_i_1__0_n_0\ : STD_LOGIC;
  signal \^col_wait_r_reg_0\ : STD_LOGIC;
  signal demand_act_priority_ns : STD_LOGIC;
  signal \^demand_act_priority_r\ : STD_LOGIC;
  signal \demand_priority_r_i_5__0_n_0\ : STD_LOGIC;
  signal \^demand_priority_r_reg_0\ : STD_LOGIC;
  signal \^demand_priority_r_reg_1\ : STD_LOGIC;
  signal demanded_prior_ns : STD_LOGIC;
  signal \^demanded_prior_r\ : STD_LOGIC;
  signal \^pre_passing_open_bank_ns\ : STD_LOGIC;
  signal pre_wait_ns : STD_LOGIC;
  signal \^pre_wait_r\ : STD_LOGIC;
  signal \pre_wait_r_i_2__0_n_0\ : STD_LOGIC;
  signal ras_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ras_timer_zero_ns : STD_LOGIC;
  signal \^ras_timer_zero_r\ : STD_LOGIC;
  signal \ras_timer_zero_r_i_2__0_n_0\ : STD_LOGIC;
  signal req_bank_rdy_r : STD_LOGIC;
  signal rtp_timer_r : STD_LOGIC;
  signal \rtp_timer_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal starve_limit_cntr_r0 : STD_LOGIC;
  signal \starve_limit_cntr_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[2]_i_1__0_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \col_wait_r_i_1__0\ : label is "soft_lutpair568";
  attribute SOFT_HLUTNM of \grant_r[3]_i_5__2\ : label is "soft_lutpair569";
  attribute SOFT_HLUTNM of \grant_r[3]_i_6\ : label is "soft_lutpair571";
  attribute SOFT_HLUTNM of \pre_bm_end_r_i_1__0\ : label is "soft_lutpair569";
  attribute SOFT_HLUTNM of \ras_timer_zero_r_i_2__0\ : label is "soft_lutpair568";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[0]_i_1__0\ : label is "soft_lutpair571";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1__0\ : label is "soft_lutpair570";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1__0\ : label is "soft_lutpair570";
begin
  act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\;
  bm_end_r1_0 <= \^bm_end_r1_0\;
  col_wait_r_reg_0 <= \^col_wait_r_reg_0\;
  demand_act_priority_r <= \^demand_act_priority_r\;
  demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\;
  demand_priority_r_reg_1 <= \^demand_priority_r_reg_1\;
  demanded_prior_r <= \^demanded_prior_r\;
  pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\;
  pre_wait_r <= \^pre_wait_r\;
  ras_timer_zero_r <= \^ras_timer_zero_r\;
\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^act_wait_r_lcl_reg_0\,
      Q => act_this_rank_r(0),
      R => '0'
    );
\act_wait_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAEAEFFAEAEAEAE"
    )
        port map (
      I0 => \^bm_end_r1_0\,
      I1 => act_wait_r_lcl_reg_3,
      I2 => act_wait_r_lcl_reg_4,
      I3 => act_wait_r_lcl_reg_1,
      I4 => act_wait_r_lcl_reg_2(0),
      I5 => \^act_wait_r_lcl_reg_0\,
      O => act_wait_ns
    );
act_wait_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => act_wait_ns,
      Q => \^act_wait_r_lcl_reg_0\,
      R => '0'
    );
\auto_pre_r_lcl_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000800080808000"
    )
        port map (
      I0 => tail_r,
      I1 => auto_pre_r_lcl_reg(0),
      I2 => auto_pre_r_lcl_reg_0,
      I3 => \^act_wait_r_lcl_reg_0\,
      I4 => \^col_wait_r_reg_0\,
      I5 => Q(0),
      O => \compute_tail.tail_r_lcl_reg\
    );
bm_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_91_out,
      Q => \^bm_end_r1_0\,
      R => '0'
    );
\col_wait_r_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAFFEAEA"
    )
        port map (
      I0 => act_wait_r_lcl_reg_1,
      I1 => act_wait_r_lcl_reg_2(0),
      I2 => \^act_wait_r_lcl_reg_0\,
      I3 => Q(0),
      I4 => \^col_wait_r_reg_0\,
      O => \col_wait_r_i_1__0_n_0\
    );
col_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \col_wait_r_i_1__0_n_0\,
      Q => \^col_wait_r_reg_0\,
      R => col_wait_r_reg_2
    );
\demand_act_priority_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \^demand_act_priority_r\,
      I1 => wait_for_maint_r,
      I2 => \^ras_timer_zero_r\,
      I3 => \^act_wait_r_lcl_reg_0\,
      I4 => demand_act_priority_r_reg_0(0),
      I5 => head_r(0),
      O => demand_act_priority_ns
    );
demand_act_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demand_act_priority_ns,
      Q => \^demand_act_priority_r\,
      R => '0'
    );
\demand_priority_r_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EAFFEAEA"
    )
        port map (
      I0 => act_wait_r_lcl_reg_1,
      I1 => act_wait_r_lcl_reg_2(0),
      I2 => \^act_wait_r_lcl_reg_0\,
      I3 => Q(0),
      I4 => \^col_wait_r_reg_0\,
      I5 => demand_priority_r_reg_3,
      O => col_wait_ns
    );
\demand_priority_r_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1000"
    )
        port map (
      I0 => \demand_priority_r_i_5__0_n_0\,
      I1 => Q(0),
      I2 => demand_priority_r_reg_4,
      I3 => req_bank_rdy_r,
      I4 => \^demand_priority_r_reg_0\,
      O => \grant_r_reg[1]\
    );
\demand_priority_r_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4FFFFFFF"
    )
        port map (
      I0 => q_has_rd,
      I1 => req_wr_r(0),
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => starve_limit_cntr_r(2),
      O => \demand_priority_r_i_5__0_n_0\
    );
demand_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demand_priority_ns,
      Q => \^demand_priority_r_reg_0\,
      R => '0'
    );
\demanded_prior_r_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r\,
      I2 => demanded_prior_r_reg_0,
      O => demanded_prior_ns
    );
\demanded_prior_r_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD000000"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r\,
      I2 => Q(0),
      I3 => demanded_prior_r_reg_1,
      I4 => demanded_prior_r_reg_2,
      O => demand_priority_r_reg_2
    );
demanded_prior_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demanded_prior_ns,
      Q => \^demanded_prior_r\,
      R => '0'
    );
\grant_r[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000E00"
    )
        port map (
      I0 => demanded_prior_r_reg_0,
      I1 => \^demand_priority_r_reg_0\,
      I2 => \rnk_config_strobe_r_reg[0]_2\,
      I3 => \^col_wait_r_reg_0\,
      I4 => \rnk_config_strobe_r_reg[0]_3\,
      O => \^demand_priority_r_reg_1\
    );
\grant_r[3]_i_5__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \^ras_timer_zero_r\,
      I1 => \^pre_wait_r\,
      I2 => pre_bm_end_r_reg_0,
      I3 => pre_bm_end_r_reg(0),
      O => ras_timer_zero_r_reg_0
    );
\grant_r[3]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"32"
    )
        port map (
      I0 => \^col_wait_r_reg_0\,
      I1 => \grant_r_reg[1]_0\,
      I2 => act_wait_r_lcl_reg_1,
      O => col_wait_r_reg_1
    );
ofs_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofs_rdy_r0,
      Q => ofs_rdy_r,
      R => ofs_rdy_r_reg_0
    );
\pre_bm_end_r_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEAAAAAA"
    )
        port map (
      I0 => \^pre_passing_open_bank_ns\,
      I1 => pre_bm_end_r_reg(0),
      I2 => pre_bm_end_r_reg_0,
      I3 => \^pre_wait_r\,
      I4 => \^ras_timer_zero_r\,
      O => pre_bm_end_ns
    );
\pre_passing_open_bank_r_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAA20"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => rtp_timer_r,
      I4 => Q(0),
      O => \^pre_passing_open_bank_ns\
    );
\pre_wait_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020F00000202"
    )
        port map (
      I0 => \^pre_wait_r\,
      I1 => \pre_wait_r_i_2__0_n_0\,
      I2 => pass_open_bank_ns,
      I3 => \rtp_timer_r_reg[0]_0\,
      I4 => \rtp_timer_r_reg[0]_1\,
      I5 => rtp_timer_r,
      O => pre_wait_ns
    );
\pre_wait_r_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => \^ras_timer_zero_r\,
      I1 => \^pre_wait_r\,
      I2 => pre_bm_end_r_reg_0,
      I3 => pre_bm_end_r_reg(0),
      O => \pre_wait_r_i_2__0_n_0\
    );
pre_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_wait_ns,
      Q => \^pre_wait_r\,
      R => '0'
    );
\ras_timer_r[0]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00020002000F0002"
    )
        port map (
      I0 => ras_timer_r(1),
      I1 => ras_timer_r(0),
      I2 => \rtp_timer_r_reg[0]_1\,
      I3 => \^bm_end_r1_0\,
      I4 => Q(0),
      I5 => \rd_this_rank_r_reg[0]_0\,
      O => \ras_timer_r_reg[1]_0\
    );
\ras_timer_r[1]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0404040F04040F0"
    )
        port map (
      I0 => \rd_this_rank_r_reg[0]_0\,
      I1 => Q(0),
      I2 => ras_timer_zero_r_reg_1,
      I3 => ras_timer_r(1),
      I4 => ras_timer_r(0),
      I5 => \ras_timer_zero_r_i_2__0_n_0\,
      O => rd_wr_r_lcl_reg
    );
\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => ras_timer_r(0),
      R => '0'
    );
\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => ras_timer_r(1),
      R => '0'
    );
\ras_timer_zero_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0EFF0EFF00FF0EFF"
    )
        port map (
      I0 => \ras_timer_zero_r_i_2__0_n_0\,
      I1 => ras_timer_r(0),
      I2 => ras_timer_r(1),
      I3 => ras_timer_zero_r_reg_1,
      I4 => Q(0),
      I5 => \rd_this_rank_r_reg[0]_0\,
      O => ras_timer_zero_ns
    );
\ras_timer_zero_r_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => act_wait_r_lcl_reg_2(0),
      O => \ras_timer_zero_r_i_2__0_n_0\
    );
ras_timer_zero_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ras_timer_zero_ns,
      Q => \^ras_timer_zero_r\,
      R => '0'
    );
\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_this_rank_r_reg[0]_0\,
      Q => rd_this_rank_r(0),
      R => '0'
    );
req_bank_rdy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => req_bank_rdy_ns,
      Q => req_bank_rdy_r,
      R => '0'
    );
\rnk_config_strobe_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFB"
    )
        port map (
      I0 => \^demand_priority_r_reg_1\,
      I1 => \rnk_config_strobe_r_reg[0]\,
      I2 => \rnk_config_strobe_r_reg[0]_0\,
      I3 => \rnk_config_strobe_r_reg[0]_1\,
      O => rnk_config_strobe_ns
    );
rnk_config_valid_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF0000FFFB"
    )
        port map (
      I0 => \^demand_priority_r_reg_1\,
      I1 => \rnk_config_strobe_r_reg[0]\,
      I2 => \rnk_config_strobe_r_reg[0]_0\,
      I3 => \rnk_config_strobe_r_reg[0]_1\,
      I4 => rnk_config_valid_r_lcl_reg,
      I5 => rnk_config_valid_r,
      O => rnk_config_valid_ns
    );
\rtp_timer_r[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => rtp_timer_r,
      I1 => Q(0),
      I2 => \rtp_timer_r_reg[0]_0\,
      I3 => \rtp_timer_r_reg[0]_1\,
      O => \rtp_timer_r[0]_i_1__0_n_0\
    );
\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtp_timer_r[0]_i_1__0_n_0\,
      Q => rtp_timer_r,
      R => '0'
    );
\starve_limit_cntr_r[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r0,
      I2 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[0]_i_1__0_n_0\
    );
\starve_limit_cntr_r[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => starve_limit_cntr_r(1),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[1]_i_1__0_n_0\
    );
\starve_limit_cntr_r[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => \^col_wait_r_reg_0\,
      O => \starve_limit_cntr_r[2]_i_1__0_n_0\
    );
\starve_limit_cntr_r[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007F000000"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => req_bank_rdy_r,
      I4 => demand_priority_r_reg_4,
      I5 => Q(0),
      O => starve_limit_cntr_r0
    );
\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[0]_i_1__0_n_0\,
      Q => starve_limit_cntr_r(0),
      R => '0'
    );
\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[1]_i_1__0_n_0\,
      Q => starve_limit_cntr_r(1),
      R => '0'
    );
\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[2]_i_1__0_n_0\,
      Q => starve_limit_cntr_r(2),
      R => '0'
    );
\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_wtp_timer0,
      Q => wr_this_rank_r(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_bank_state__parameterized1\ is
  port (
    bm_end_r1_2 : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    ras_timer_zero_r : out STD_LOGIC;
    pre_wait_r : out STD_LOGIC;
    demand_act_priority_r : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    demanded_prior_r : out STD_LOGIC;
    override_demand_r : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_wait_r : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    ofs_rdy_r0 : out STD_LOGIC;
    ofs_rdy_r0_0 : out STD_LOGIC;
    ofs_rdy_r0_1 : out STD_LOGIC;
    demand_priority_r_reg_1 : out STD_LOGIC;
    col_wait_ns : out STD_LOGIC;
    pre_bm_end_ns : out STD_LOGIC;
    pre_passing_open_bank_ns : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC;
    ras_timer_zero_r_reg_1 : out STD_LOGIC;
    act_wait_r_lcl_reg_1 : out STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : out STD_LOGIC;
    rd_wr_r_lcl_reg : out STD_LOGIC;
    demand_priority_r_reg_2 : out STD_LOGIC;
    demand_priority_r_reg_3 : out STD_LOGIC;
    \starve_limit_cntr_r_reg[2]_0\ : out STD_LOGIC;
    p_52_out : in STD_LOGIC;
    CLK : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    demand_priority_ns : in STD_LOGIC;
    override_demand_ns : in STD_LOGIC;
    phy_mc_ctl_full_r_reg_0 : in STD_LOGIC;
    start_wtp_timer0 : in STD_LOGIC;
    \rd_this_rank_r_reg[0]_0\ : in STD_LOGIC;
    phy_mc_cmd_full : in STD_LOGIC;
    phy_mc_ctl_full : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg_0\ : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pre_4_1_1T_arb.granted_pre_r_reg_2\ : in STD_LOGIC;
    phy_mc_data_full : in STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC;
    demanded_prior_r_reg_0 : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC;
    col_wait_r_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    ras_timer_zero_r_reg_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    demand_priority_r_reg_4 : in STD_LOGIC;
    act_wait_r_lcl_reg_3 : in STD_LOGIC;
    act_wait_r_lcl_reg_4 : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    \rtp_timer_r_reg[0]_0\ : in STD_LOGIC;
    \rtp_timer_r_reg[0]_1\ : in STD_LOGIC;
    tail_r : in STD_LOGIC;
    rb_hit_busy_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg : in STD_LOGIC;
    wait_for_maint_r : in STD_LOGIC;
    idle_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    head_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    ras_timer_zero_r_reg_3 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    demanded_prior_r_reg_2 : in STD_LOGIC;
    demand_priority_r_2 : in STD_LOGIC;
    demanded_prior_r_3 : in STD_LOGIC;
    \grant_r[3]_i_5\ : in STD_LOGIC;
    demand_priority_r_reg_5 : in STD_LOGIC;
    \starve_limit_cntr_r_reg[0]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_bank_state__parameterized1\ : entity is "mig_7series_v4_2_bank_state";
end \mig_7series_0_mig_7series_v4_2_bank_state__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_bank_state__parameterized1\ is
  signal act_wait_ns : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_1\ : STD_LOGIC;
  signal \^bm_end_r1_2\ : STD_LOGIC;
  signal \^col_wait_r\ : STD_LOGIC;
  signal \col_wait_r_i_1__1_n_0\ : STD_LOGIC;
  signal demand_act_priority_ns : STD_LOGIC;
  signal \^demand_act_priority_r\ : STD_LOGIC;
  signal \^demand_priority_r_reg_0\ : STD_LOGIC;
  signal demanded_prior_ns : STD_LOGIC;
  signal \^demanded_prior_r\ : STD_LOGIC;
  signal ofs_rdy_r0_2 : STD_LOGIC;
  signal \^override_demand_r\ : STD_LOGIC;
  signal phy_mc_cmd_full_r : STD_LOGIC;
  signal phy_mc_ctl_full_r : STD_LOGIC;
  signal \^pre_passing_open_bank_ns\ : STD_LOGIC;
  signal pre_wait_ns : STD_LOGIC;
  signal \^pre_wait_r\ : STD_LOGIC;
  signal \pre_wait_r_i_2__1_n_0\ : STD_LOGIC;
  signal ras_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ras_timer_zero_ns : STD_LOGIC;
  signal \^ras_timer_zero_r\ : STD_LOGIC;
  signal \^req_bank_rdy_r\ : STD_LOGIC;
  signal rtp_timer_r : STD_LOGIC;
  signal \rtp_timer_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal starve_limit_cntr_r0 : STD_LOGIC;
  signal \starve_limit_cntr_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[2]_i_1__1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \col_wait_r_i_1__1\ : label is "soft_lutpair577";
  attribute SOFT_HLUTNM of \grant_r[3]_i_4__1\ : label is "soft_lutpair578";
  attribute SOFT_HLUTNM of ofs_rdy_r_i_1 : label is "soft_lutpair580";
  attribute SOFT_HLUTNM of \ofs_rdy_r_i_1__0\ : label is "soft_lutpair580";
  attribute SOFT_HLUTNM of \ofs_rdy_r_i_1__1\ : label is "soft_lutpair581";
  attribute SOFT_HLUTNM of \ofs_rdy_r_i_1__2\ : label is "soft_lutpair581";
  attribute SOFT_HLUTNM of \pre_bm_end_r_i_1__1\ : label is "soft_lutpair578";
  attribute SOFT_HLUTNM of \ras_timer_zero_r_i_2__1\ : label is "soft_lutpair577";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1__1\ : label is "soft_lutpair579";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1__1\ : label is "soft_lutpair579";
begin
  act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\;
  act_wait_r_lcl_reg_1 <= \^act_wait_r_lcl_reg_1\;
  bm_end_r1_2 <= \^bm_end_r1_2\;
  col_wait_r <= \^col_wait_r\;
  demand_act_priority_r <= \^demand_act_priority_r\;
  demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\;
  demanded_prior_r <= \^demanded_prior_r\;
  override_demand_r <= \^override_demand_r\;
  pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\;
  pre_wait_r <= \^pre_wait_r\;
  ras_timer_zero_r <= \^ras_timer_zero_r\;
  req_bank_rdy_r <= \^req_bank_rdy_r\;
\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^act_wait_r_lcl_reg_0\,
      Q => act_this_rank_r(0),
      R => '0'
    );
\act_wait_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAEAEFFAEAEAEAE"
    )
        port map (
      I0 => \^bm_end_r1_2\,
      I1 => act_wait_r_lcl_reg_3,
      I2 => act_wait_r_lcl_reg_4,
      I3 => col_wait_r_reg_1,
      I4 => act_wait_r_lcl_reg_2(0),
      I5 => \^act_wait_r_lcl_reg_0\,
      O => act_wait_ns
    );
act_wait_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => act_wait_ns,
      Q => \^act_wait_r_lcl_reg_0\,
      R => '0'
    );
\auto_pre_r_lcl_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000800080808000"
    )
        port map (
      I0 => tail_r,
      I1 => rb_hit_busy_r(0),
      I2 => auto_pre_r_lcl_reg,
      I3 => \^act_wait_r_lcl_reg_0\,
      I4 => \^col_wait_r\,
      I5 => ras_timer_zero_r_reg_2(1),
      O => \compute_tail.tail_r_lcl_reg\
    );
bm_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_52_out,
      Q => \^bm_end_r1_2\,
      R => '0'
    );
\col_wait_r_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAFFEAEA"
    )
        port map (
      I0 => col_wait_r_reg_1,
      I1 => act_wait_r_lcl_reg_2(0),
      I2 => \^act_wait_r_lcl_reg_0\,
      I3 => ras_timer_zero_r_reg_2(1),
      I4 => \^col_wait_r\,
      O => \col_wait_r_i_1__1_n_0\
    );
col_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \col_wait_r_i_1__1_n_0\,
      Q => \^col_wait_r\,
      R => col_wait_r_reg_0
    );
\demand_act_priority_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \^demand_act_priority_r\,
      I1 => wait_for_maint_r,
      I2 => \^ras_timer_zero_r\,
      I3 => \^act_wait_r_lcl_reg_0\,
      I4 => idle_r(0),
      I5 => head_r(0),
      O => demand_act_priority_ns
    );
demand_act_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demand_act_priority_ns,
      Q => \^demand_act_priority_r\,
      R => '0'
    );
\demand_priority_r_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EAFFEAEA"
    )
        port map (
      I0 => col_wait_r_reg_1,
      I1 => act_wait_r_lcl_reg_2(0),
      I2 => \^act_wait_r_lcl_reg_0\,
      I3 => ras_timer_zero_r_reg_2(1),
      I4 => \^col_wait_r\,
      I5 => demand_priority_r_reg_4,
      O => col_wait_ns
    );
\demand_priority_r_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4000"
    )
        port map (
      I0 => demand_priority_r_reg_5,
      I1 => starve_limit_cntr_r(2),
      I2 => starve_limit_cntr_r(1),
      I3 => starve_limit_cntr_r(0),
      I4 => \^demand_priority_r_reg_0\,
      O => \starve_limit_cntr_r_reg[2]_0\
    );
demand_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demand_priority_ns,
      Q => \^demand_priority_r_reg_0\,
      R => '0'
    );
\demanded_prior_r_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r\,
      I2 => demanded_prior_r_reg_0,
      O => demanded_prior_ns
    );
demanded_prior_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD000000"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r\,
      I2 => ras_timer_zero_r_reg_2(1),
      I3 => demanded_prior_r_reg_1,
      I4 => demanded_prior_r_reg_2,
      O => demand_priority_r_reg_2
    );
demanded_prior_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demanded_prior_ns,
      Q => \^demanded_prior_r\,
      R => '0'
    );
\grant_r[3]_i_13__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010011111111"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^override_demand_r\,
      I2 => ras_timer_zero_r_reg_2(0),
      I3 => demand_priority_r_2,
      I4 => demanded_prior_r_3,
      I5 => \grant_r[3]_i_5\,
      O => demand_priority_r_reg_3
    );
\grant_r[3]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFABFF"
    )
        port map (
      I0 => \rnk_config_strobe_r_reg[0]\,
      I1 => \^demand_priority_r_reg_0\,
      I2 => demanded_prior_r_reg_0,
      I3 => \^col_wait_r\,
      I4 => \rnk_config_strobe_r_reg[0]_0\,
      O => demand_priority_r_reg_1
    );
\grant_r[3]_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \^ras_timer_zero_r\,
      I1 => \^pre_wait_r\,
      I2 => \pre_4_1_1T_arb.granted_pre_r_reg_0\,
      I3 => \pre_4_1_1T_arb.granted_pre_r_reg_1\(0),
      O => ras_timer_zero_r_reg_1
    );
ofs_rdy_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1101"
    )
        port map (
      I0 => phy_mc_cmd_full_r,
      I1 => phy_mc_ctl_full_r,
      I2 => phy_mc_data_full,
      I3 => ofs_rdy_r_reg_0(0),
      O => ofs_rdy_r0
    );
\ofs_rdy_r_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1101"
    )
        port map (
      I0 => phy_mc_cmd_full_r,
      I1 => phy_mc_ctl_full_r,
      I2 => phy_mc_data_full,
      I3 => ofs_rdy_r_reg_0(1),
      O => ofs_rdy_r0_0
    );
\ofs_rdy_r_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1101"
    )
        port map (
      I0 => phy_mc_cmd_full_r,
      I1 => phy_mc_ctl_full_r,
      I2 => phy_mc_data_full,
      I3 => \rd_this_rank_r_reg[0]_0\,
      O => ofs_rdy_r0_2
    );
\ofs_rdy_r_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1101"
    )
        port map (
      I0 => phy_mc_cmd_full_r,
      I1 => phy_mc_ctl_full_r,
      I2 => phy_mc_data_full,
      I3 => ofs_rdy_r_reg_0(2),
      O => ofs_rdy_r0_1
    );
ofs_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofs_rdy_r0_2,
      Q => ofs_rdy_r,
      R => phy_mc_ctl_full_r_reg_0
    );
override_demand_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => override_demand_ns,
      Q => \^override_demand_r\,
      R => '0'
    );
phy_mc_cmd_full_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => phy_mc_cmd_full,
      Q => phy_mc_cmd_full_r,
      R => phy_mc_ctl_full_r_reg_0
    );
phy_mc_ctl_full_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => phy_mc_ctl_full,
      Q => phy_mc_ctl_full_r,
      R => phy_mc_ctl_full_r_reg_0
    );
\pre_4_1_1T_arb.granted_pre_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAEAFFFFFFFF"
    )
        port map (
      I0 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => \pre_4_1_1T_arb.granted_pre_r_reg_0\,
      I4 => \pre_4_1_1T_arb.granted_pre_r_reg_1\(0),
      I5 => \pre_4_1_1T_arb.granted_pre_r_reg_2\,
      O => ras_timer_zero_r_reg_0
    );
\pre_bm_end_r_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEAAAAAA"
    )
        port map (
      I0 => \^pre_passing_open_bank_ns\,
      I1 => \pre_4_1_1T_arb.granted_pre_r_reg_1\(0),
      I2 => \pre_4_1_1T_arb.granted_pre_r_reg_0\,
      I3 => \^pre_wait_r\,
      I4 => \^ras_timer_zero_r\,
      O => pre_bm_end_ns
    );
\pre_passing_open_bank_r_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAA20"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => rtp_timer_r,
      I4 => ras_timer_zero_r_reg_2(1),
      O => \^pre_passing_open_bank_ns\
    );
\pre_wait_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020F00000202"
    )
        port map (
      I0 => \^pre_wait_r\,
      I1 => \pre_wait_r_i_2__1_n_0\,
      I2 => pass_open_bank_ns,
      I3 => \rtp_timer_r_reg[0]_0\,
      I4 => \rtp_timer_r_reg[0]_1\,
      I5 => rtp_timer_r,
      O => pre_wait_ns
    );
\pre_wait_r_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => \^ras_timer_zero_r\,
      I1 => \^pre_wait_r\,
      I2 => \pre_4_1_1T_arb.granted_pre_r_reg_0\,
      I3 => \pre_4_1_1T_arb.granted_pre_r_reg_1\(0),
      O => \pre_wait_r_i_2__1_n_0\
    );
pre_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_wait_ns,
      Q => \^pre_wait_r\,
      R => '0'
    );
\ras_timer_r[0]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00020002000F0002"
    )
        port map (
      I0 => ras_timer_r(1),
      I1 => ras_timer_r(0),
      I2 => \rtp_timer_r_reg[0]_1\,
      I3 => \^bm_end_r1_2\,
      I4 => ras_timer_zero_r_reg_2(1),
      I5 => \rd_this_rank_r_reg[0]_0\,
      O => \ras_timer_r_reg[1]_0\
    );
\ras_timer_r[1]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0404040F04040F0"
    )
        port map (
      I0 => \rd_this_rank_r_reg[0]_0\,
      I1 => ras_timer_zero_r_reg_2(1),
      I2 => ras_timer_zero_r_reg_3,
      I3 => ras_timer_r(1),
      I4 => ras_timer_r(0),
      I5 => \^act_wait_r_lcl_reg_1\,
      O => rd_wr_r_lcl_reg
    );
\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => ras_timer_r(0),
      R => '0'
    );
\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => ras_timer_r(1),
      R => '0'
    );
\ras_timer_zero_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0EFF0EFF00FF0EFF"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_1\,
      I1 => ras_timer_r(0),
      I2 => ras_timer_r(1),
      I3 => ras_timer_zero_r_reg_3,
      I4 => ras_timer_zero_r_reg_2(1),
      I5 => \rd_this_rank_r_reg[0]_0\,
      O => ras_timer_zero_ns
    );
\ras_timer_zero_r_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => act_wait_r_lcl_reg_2(0),
      O => \^act_wait_r_lcl_reg_1\
    );
ras_timer_zero_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ras_timer_zero_ns,
      Q => \^ras_timer_zero_r\,
      R => '0'
    );
\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_this_rank_r_reg[0]_0\,
      Q => rd_this_rank_r(0),
      R => '0'
    );
req_bank_rdy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => req_bank_rdy_ns,
      Q => \^req_bank_rdy_r\,
      R => '0'
    );
\rtp_timer_r[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => rtp_timer_r,
      I1 => ras_timer_zero_r_reg_2(1),
      I2 => \rtp_timer_r_reg[0]_0\,
      I3 => \rtp_timer_r_reg[0]_1\,
      O => \rtp_timer_r[0]_i_1__1_n_0\
    );
\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtp_timer_r[0]_i_1__1_n_0\,
      Q => rtp_timer_r,
      R => '0'
    );
\starve_limit_cntr_r[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r0,
      I2 => \^col_wait_r\,
      O => \starve_limit_cntr_r[0]_i_1__1_n_0\
    );
\starve_limit_cntr_r[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => starve_limit_cntr_r(1),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => \^col_wait_r\,
      O => \starve_limit_cntr_r[1]_i_1__1_n_0\
    );
\starve_limit_cntr_r[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => \^col_wait_r\,
      O => \starve_limit_cntr_r[2]_i_1__1_n_0\
    );
\starve_limit_cntr_r[2]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007F0000000000"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => \^req_bank_rdy_r\,
      I4 => ras_timer_zero_r_reg_2(1),
      I5 => \starve_limit_cntr_r_reg[0]_0\,
      O => starve_limit_cntr_r0
    );
\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[0]_i_1__1_n_0\,
      Q => starve_limit_cntr_r(0),
      R => '0'
    );
\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[1]_i_1__1_n_0\,
      Q => starve_limit_cntr_r(1),
      R => '0'
    );
\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[2]_i_1__1_n_0\,
      Q => starve_limit_cntr_r(2),
      R => '0'
    );
\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_wtp_timer0,
      Q => wr_this_rank_r(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_bank_state__parameterized2\ is
  port (
    bm_end_r1_4 : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    ras_timer_zero_r : out STD_LOGIC;
    pre_wait_r : out STD_LOGIC;
    demand_act_priority_r : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r_reg_0 : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_wait_r : out STD_LOGIC;
    col_wait_r_reg_0 : out STD_LOGIC;
    demand_priority_r_reg_1 : out STD_LOGIC;
    col_wait_ns : out STD_LOGIC;
    pre_bm_end_ns : out STD_LOGIC;
    pre_passing_open_bank_ns : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    act_wait_r_lcl_reg_1 : out STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : out STD_LOGIC;
    rd_wr_r_lcl_reg : out STD_LOGIC;
    demanded_prior_r_reg_1 : out STD_LOGIC;
    demanded_prior_r_reg_2 : out STD_LOGIC;
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    \grant_r_reg[3]_1\ : out STD_LOGIC;
    p_13_out : in STD_LOGIC;
    CLK : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    demand_priority_ns : in STD_LOGIC;
    ofs_rdy_r_reg_0 : in STD_LOGIC;
    ofs_rdy_r0 : in STD_LOGIC;
    start_wtp_timer0 : in STD_LOGIC;
    \rd_this_rank_r_reg[0]_0\ : in STD_LOGIC;
    col_wait_r_reg_1 : in STD_LOGIC;
    \grant_r_reg[0]\ : in STD_LOGIC;
    col_wait_r_reg_2 : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_1\ : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    demand_priority_r_reg_2 : in STD_LOGIC;
    act_wait_r_lcl_reg_3 : in STD_LOGIC;
    act_wait_r_lcl_reg_4 : in STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    \rtp_timer_r_reg[0]_0\ : in STD_LOGIC;
    \rtp_timer_r_reg[0]_1\ : in STD_LOGIC;
    tail_r : in STD_LOGIC;
    auto_pre_r_lcl_reg : in STD_LOGIC;
    auto_pre_r_lcl_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC;
    wait_for_maint_r : in STD_LOGIC;
    idle_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    head_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    demand_priority_r_0 : in STD_LOGIC;
    demanded_prior_r_1 : in STD_LOGIC;
    demanded_prior_r_reg_3 : in STD_LOGIC;
    demanded_prior_r_2 : in STD_LOGIC;
    demand_priority_r_3 : in STD_LOGIC;
    demanded_prior_r_4 : in STD_LOGIC;
    demand_priority_r_5 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    q_has_rd : in STD_LOGIC;
    req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_bank_state__parameterized2\ : entity is "mig_7series_v4_2_bank_state";
end \mig_7series_0_mig_7series_v4_2_bank_state__parameterized2\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_bank_state__parameterized2\ is
  signal act_wait_ns : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_1\ : STD_LOGIC;
  signal \^bm_end_r1_4\ : STD_LOGIC;
  signal \^col_wait_r\ : STD_LOGIC;
  signal col_wait_r_i_1_n_0 : STD_LOGIC;
  signal demand_act_priority_ns : STD_LOGIC;
  signal \^demand_act_priority_r\ : STD_LOGIC;
  signal \demand_priority_r_i_5__2_n_0\ : STD_LOGIC;
  signal \^demand_priority_r_reg_0\ : STD_LOGIC;
  signal demanded_prior_ns : STD_LOGIC;
  signal \^demanded_prior_r_reg_0\ : STD_LOGIC;
  signal \^pre_passing_open_bank_ns\ : STD_LOGIC;
  signal pre_wait_ns : STD_LOGIC;
  signal \^pre_wait_r\ : STD_LOGIC;
  signal \pre_wait_r_i_2__2_n_0\ : STD_LOGIC;
  signal ras_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ras_timer_zero_ns : STD_LOGIC;
  signal \^ras_timer_zero_r\ : STD_LOGIC;
  signal req_bank_rdy_r : STD_LOGIC;
  signal rtp_timer_r : STD_LOGIC;
  signal \rtp_timer_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal starve_limit_cntr_r0 : STD_LOGIC;
  signal \starve_limit_cntr_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[2]_i_1__2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of col_wait_r_i_1 : label is "soft_lutpair586";
  attribute SOFT_HLUTNM of \grant_r[3]_i_2\ : label is "soft_lutpair590";
  attribute SOFT_HLUTNM of \grant_r[3]_i_2__2\ : label is "soft_lutpair587";
  attribute SOFT_HLUTNM of \pre_4_1_1T_arb.granted_pre_r_i_2\ : label is "soft_lutpair588";
  attribute SOFT_HLUTNM of \pre_bm_end_r_i_1__2\ : label is "soft_lutpair587";
  attribute SOFT_HLUTNM of \pre_wait_r_i_2__2\ : label is "soft_lutpair588";
  attribute SOFT_HLUTNM of \ras_timer_zero_r_i_2__2\ : label is "soft_lutpair586";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[0]_i_1__2\ : label is "soft_lutpair590";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1__2\ : label is "soft_lutpair589";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1__2\ : label is "soft_lutpair589";
begin
  act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\;
  act_wait_r_lcl_reg_1 <= \^act_wait_r_lcl_reg_1\;
  bm_end_r1_4 <= \^bm_end_r1_4\;
  col_wait_r <= \^col_wait_r\;
  demand_act_priority_r <= \^demand_act_priority_r\;
  demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\;
  demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\;
  pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\;
  pre_wait_r <= \^pre_wait_r\;
  ras_timer_zero_r <= \^ras_timer_zero_r\;
\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^act_wait_r_lcl_reg_0\,
      Q => act_this_rank_r(0),
      R => '0'
    );
act_wait_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAEAEFFAEAEAEAE"
    )
        port map (
      I0 => \^bm_end_r1_4\,
      I1 => act_wait_r_lcl_reg_3,
      I2 => act_wait_r_lcl_reg_4,
      I3 => col_wait_r_reg_2,
      I4 => act_wait_r_lcl_reg_2(0),
      I5 => \^act_wait_r_lcl_reg_0\,
      O => act_wait_ns
    );
act_wait_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => act_wait_ns,
      Q => \^act_wait_r_lcl_reg_0\,
      R => '0'
    );
auto_pre_r_lcl_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000800080808000"
    )
        port map (
      I0 => tail_r,
      I1 => auto_pre_r_lcl_reg,
      I2 => auto_pre_r_lcl_reg_0(0),
      I3 => \^act_wait_r_lcl_reg_0\,
      I4 => \^col_wait_r\,
      I5 => Q(3),
      O => \compute_tail.tail_r_lcl_reg\
    );
bm_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_13_out,
      Q => \^bm_end_r1_4\,
      R => '0'
    );
col_wait_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAFFEAEA"
    )
        port map (
      I0 => col_wait_r_reg_2,
      I1 => act_wait_r_lcl_reg_2(0),
      I2 => \^act_wait_r_lcl_reg_0\,
      I3 => Q(3),
      I4 => \^col_wait_r\,
      O => col_wait_r_i_1_n_0
    );
col_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_wait_r_i_1_n_0,
      Q => \^col_wait_r\,
      R => col_wait_r_reg_1
    );
\demand_act_priority_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \^demand_act_priority_r\,
      I1 => wait_for_maint_r,
      I2 => \^ras_timer_zero_r\,
      I3 => \^act_wait_r_lcl_reg_0\,
      I4 => idle_r(0),
      I5 => head_r(0),
      O => demand_act_priority_ns
    );
demand_act_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demand_act_priority_ns,
      Q => \^demand_act_priority_r\,
      R => '0'
    );
demand_priority_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EAFFEAEA"
    )
        port map (
      I0 => col_wait_r_reg_2,
      I1 => act_wait_r_lcl_reg_2(0),
      I2 => \^act_wait_r_lcl_reg_0\,
      I3 => Q(3),
      I4 => \^col_wait_r\,
      I5 => demand_priority_r_reg_2,
      O => col_wait_ns
    );
\demand_priority_r_i_4__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1000"
    )
        port map (
      I0 => \demand_priority_r_i_5__2_n_0\,
      I1 => Q(3),
      I2 => demand_priority_r_reg_3,
      I3 => req_bank_rdy_r,
      I4 => \^demand_priority_r_reg_0\,
      O => \grant_r_reg[3]_1\
    );
\demand_priority_r_i_5__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4FFFFFFF"
    )
        port map (
      I0 => q_has_rd,
      I1 => req_wr_r(0),
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => starve_limit_cntr_r(2),
      O => \demand_priority_r_i_5__2_n_0\
    );
demand_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demand_priority_ns,
      Q => \^demand_priority_r_reg_0\,
      R => '0'
    );
\demanded_prior_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000D00DDDDDDDD"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r_reg_0\,
      I2 => Q(0),
      I3 => demand_priority_r_0,
      I4 => demanded_prior_r_1,
      I5 => demanded_prior_r_reg_3,
      O => demanded_prior_ns
    );
demanded_prior_r_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => Q(3),
      I1 => \^demand_priority_r_reg_0\,
      I2 => \^demanded_prior_r_reg_0\,
      O => \grant_r_reg[3]_0\
    );
demanded_prior_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demanded_prior_ns,
      Q => \^demanded_prior_r_reg_0\,
      R => '0'
    );
\grant_r[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"32"
    )
        port map (
      I0 => \^col_wait_r\,
      I1 => \grant_r_reg[0]\,
      I2 => col_wait_r_reg_2,
      O => col_wait_r_reg_0
    );
\grant_r[3]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFBFB00FBFBFBFB"
    )
        port map (
      I0 => \^demanded_prior_r_reg_0\,
      I1 => \^demand_priority_r_reg_0\,
      I2 => Q(3),
      I3 => Q(1),
      I4 => demanded_prior_r_2,
      I5 => demand_priority_r_3,
      O => demanded_prior_r_reg_1
    );
\grant_r[3]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \^ras_timer_zero_r\,
      I1 => \^pre_wait_r\,
      I2 => pre_bm_end_r_reg_0,
      I3 => pre_bm_end_r_reg(0),
      O => ras_timer_zero_r_reg_0
    );
\grant_r[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000E00"
    )
        port map (
      I0 => \rnk_config_strobe_r_reg[0]\,
      I1 => \^demand_priority_r_reg_0\,
      I2 => \rnk_config_strobe_r_reg[0]_0\,
      I3 => \^col_wait_r\,
      I4 => \rnk_config_strobe_r_reg[0]_1\,
      O => demand_priority_r_reg_1
    );
granted_col_r_i_12: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFBFB00FBFBFBFB"
    )
        port map (
      I0 => \^demanded_prior_r_reg_0\,
      I1 => \^demand_priority_r_reg_0\,
      I2 => Q(3),
      I3 => Q(2),
      I4 => demanded_prior_r_4,
      I5 => demand_priority_r_5,
      O => demanded_prior_r_reg_2
    );
ofs_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofs_rdy_r0,
      Q => ofs_rdy_r,
      R => ofs_rdy_r_reg_0
    );
\pre_4_1_1T_arb.granted_pre_r_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EFFF"
    )
        port map (
      I0 => pre_bm_end_r_reg(0),
      I1 => pre_bm_end_r_reg_0,
      I2 => \^pre_wait_r\,
      I3 => \^ras_timer_zero_r\,
      I4 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      O => \grant_r_reg[3]\
    );
\pre_bm_end_r_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEAAAAAA"
    )
        port map (
      I0 => \^pre_passing_open_bank_ns\,
      I1 => pre_bm_end_r_reg(0),
      I2 => pre_bm_end_r_reg_0,
      I3 => \^pre_wait_r\,
      I4 => \^ras_timer_zero_r\,
      O => pre_bm_end_ns
    );
\pre_passing_open_bank_r_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAA20"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => rtp_timer_r,
      I4 => Q(3),
      O => \^pre_passing_open_bank_ns\
    );
\pre_wait_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020F00000202"
    )
        port map (
      I0 => \^pre_wait_r\,
      I1 => \pre_wait_r_i_2__2_n_0\,
      I2 => pass_open_bank_ns,
      I3 => \rtp_timer_r_reg[0]_0\,
      I4 => \rtp_timer_r_reg[0]_1\,
      I5 => rtp_timer_r,
      O => pre_wait_ns
    );
\pre_wait_r_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => \^ras_timer_zero_r\,
      I1 => \^pre_wait_r\,
      I2 => pre_bm_end_r_reg_0,
      I3 => pre_bm_end_r_reg(0),
      O => \pre_wait_r_i_2__2_n_0\
    );
pre_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_wait_ns,
      Q => \^pre_wait_r\,
      R => '0'
    );
\ras_timer_r[0]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00020002000F0002"
    )
        port map (
      I0 => ras_timer_r(1),
      I1 => ras_timer_r(0),
      I2 => \ras_timer_r_reg[0]_0\,
      I3 => \^bm_end_r1_4\,
      I4 => Q(3),
      I5 => \rd_this_rank_r_reg[0]_0\,
      O => \ras_timer_r_reg[1]_0\
    );
\ras_timer_r[1]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0404040F04040F0"
    )
        port map (
      I0 => \rd_this_rank_r_reg[0]_0\,
      I1 => Q(3),
      I2 => ras_timer_zero_r_reg_1,
      I3 => ras_timer_r(1),
      I4 => ras_timer_r(0),
      I5 => \^act_wait_r_lcl_reg_1\,
      O => rd_wr_r_lcl_reg
    );
\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => ras_timer_r(0),
      R => '0'
    );
\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => ras_timer_r(1),
      R => '0'
    );
\ras_timer_zero_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0EFF0EFF00FF0EFF"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_1\,
      I1 => ras_timer_r(0),
      I2 => ras_timer_r(1),
      I3 => ras_timer_zero_r_reg_1,
      I4 => Q(3),
      I5 => \rd_this_rank_r_reg[0]_0\,
      O => ras_timer_zero_ns
    );
\ras_timer_zero_r_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => act_wait_r_lcl_reg_2(0),
      O => \^act_wait_r_lcl_reg_1\
    );
ras_timer_zero_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ras_timer_zero_ns,
      Q => \^ras_timer_zero_r\,
      R => '0'
    );
\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_this_rank_r_reg[0]_0\,
      Q => rd_this_rank_r(0),
      R => '0'
    );
req_bank_rdy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => req_bank_rdy_ns,
      Q => req_bank_rdy_r,
      R => '0'
    );
\rtp_timer_r[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => rtp_timer_r,
      I1 => Q(3),
      I2 => \rtp_timer_r_reg[0]_0\,
      I3 => \rtp_timer_r_reg[0]_1\,
      O => \rtp_timer_r[0]_i_1__2_n_0\
    );
\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtp_timer_r[0]_i_1__2_n_0\,
      Q => rtp_timer_r,
      R => '0'
    );
\starve_limit_cntr_r[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r0,
      I2 => \^col_wait_r\,
      O => \starve_limit_cntr_r[0]_i_1__2_n_0\
    );
\starve_limit_cntr_r[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => starve_limit_cntr_r(1),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => \^col_wait_r\,
      O => \starve_limit_cntr_r[1]_i_1__2_n_0\
    );
\starve_limit_cntr_r[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => \^col_wait_r\,
      O => \starve_limit_cntr_r[2]_i_1__2_n_0\
    );
\starve_limit_cntr_r[2]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007F000000"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => req_bank_rdy_r,
      I4 => demand_priority_r_reg_3,
      I5 => Q(3),
      O => starve_limit_cntr_r0
    );
\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[0]_i_1__2_n_0\,
      Q => starve_limit_cntr_r(0),
      R => '0'
    );
\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[1]_i_1__2_n_0\,
      Q => starve_limit_cntr_r(1),
      R => '0'
    );
\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[2]_i_1__2_n_0\,
      Q => starve_limit_cntr_r(2),
      R => '0'
    );
\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_wtp_timer0,
      Q => wr_this_rank_r(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_clk_ibuf is
  port (
    mmcm_clk : out STD_LOGIC;
    sys_clk_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_clk_ibuf : entity is "mig_7series_v4_2_clk_ibuf";
end mig_7series_0_mig_7series_v4_2_clk_ibuf;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_clk_ibuf is
  signal sys_clk_ibufg : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of sys_clk_ibufg : signal is "true";
  attribute syn_keep : string;
  attribute syn_keep of sys_clk_ibufg : signal is "true";
begin
  mmcm_clk <= sys_clk_ibufg;
  sys_clk_ibufg <= sys_clk_i;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_col_mach is
  port (
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_wrdata_en_ns : out STD_LOGIC;
    wr_data_en_ns : out STD_LOGIC;
    mc_ref_zq_wip_ns : out STD_LOGIC;
    mc_read_idle_ns : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.fifo_out_data_r_reg[7]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    CLK : in STD_LOGIC;
    DIC : in STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr : in STD_LOGIC;
    mc_cmd : in STD_LOGIC_VECTOR ( 0 to 0 );
    col_wr_data_buf_addr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    maint_ref_zq_wip : in STD_LOGIC;
    mc_read_idle_r_reg : in STD_LOGIC;
    \read_fifo.tail_r_reg[0]_0\ : in STD_LOGIC;
    \read_fifo.tail_r_reg[0]_1\ : in STD_LOGIC;
    \read_fifo.tail_r_reg[4]_0\ : in STD_LOGIC;
    \read_fifo.head_r_reg[0]_0\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_col_mach : entity is "mig_7series_v4_2_col_mach";
end mig_7series_0_mig_7series_v4_2_col_mach;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_col_mach is
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal col_rd_wr_r1 : STD_LOGIC;
  signal col_rd_wr_r2 : STD_LOGIC;
  signal mc_read_idle_r_i_2_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \read_fifo.fifo_out_data_ns\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \read_fifo.head_r\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \read_fifo.tail_ns\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \read_fifo.tail_r\ : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal sent_col_r2 : STD_LOGIC;
  signal \NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \read_fifo.fifo_ram[1].RAM32M0\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \read_fifo.head_r[1]_i_1\ : label is "soft_lutpair597";
  attribute SOFT_HLUTNM of \read_fifo.head_r[2]_i_1\ : label is "soft_lutpair597";
  attribute SOFT_HLUTNM of \read_fifo.head_r[3]_i_1\ : label is "soft_lutpair596";
  attribute SOFT_HLUTNM of \read_fifo.head_r[4]_i_1\ : label is "soft_lutpair596";
begin
  Q(0) <= \^q\(0);
\cmd_pipe_plus.mc_wrdata_en_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sent_col_r2,
      I1 => col_rd_wr_r2,
      O => mc_wrdata_en_ns
    );
\cmd_pipe_plus.wr_data_en_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mc_cmd(0),
      I1 => col_rd_wr_r1,
      O => wr_data_en_ns
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_wr_data_buf_addr(0),
      Q => D(0),
      R => '0'
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_wr_data_buf_addr(1),
      Q => D(1),
      R => '0'
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_wr_data_buf_addr(2),
      Q => D(2),
      R => '0'
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_wr_data_buf_addr(3),
      Q => D(3),
      R => '0'
    );
mc_read_idle_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000082000082"
    )
        port map (
      I0 => mc_read_idle_r_reg,
      I1 => \read_fifo.tail_r\(1),
      I2 => \read_fifo.head_r\(1),
      I3 => \read_fifo.tail_r\(2),
      I4 => \read_fifo.head_r\(2),
      I5 => mc_read_idle_r_i_2_n_0,
      O => mc_read_idle_ns
    );
mc_read_idle_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \read_fifo.head_r\(3),
      I1 => \read_fifo.tail_r\(3),
      I2 => \read_fifo.head_r\(4),
      I3 => \read_fifo.tail_r\(4),
      I4 => \^q\(0),
      I5 => \read_fifo.head_r\(0),
      O => mc_read_idle_r_i_2_n_0
    );
mc_ref_zq_wip_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000082000082"
    )
        port map (
      I0 => maint_ref_zq_wip,
      I1 => \read_fifo.tail_r\(1),
      I2 => \read_fifo.head_r\(1),
      I3 => \read_fifo.tail_r\(2),
      I4 => \read_fifo.head_r\(2),
      I5 => mc_read_idle_r_i_2_n_0,
      O => mc_ref_zq_wip_ns
    );
\offset_pipe_0.col_rd_wr_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_rd_wr,
      Q => col_rd_wr_r1,
      R => '0'
    );
\offset_pipe_1.col_rd_wr_r2_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_rd_wr_r1,
      Q => col_rd_wr_r2,
      R => '0'
    );
\read_fifo.fifo_out_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.fifo_out_data_ns\(6),
      Q => \read_fifo.fifo_out_data_r_reg[7]_0\(0),
      R => '0'
    );
\read_fifo.fifo_out_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.fifo_out_data_ns\(7),
      Q => \read_fifo.fifo_out_data_r_reg[7]_0\(1),
      R => '0'
    );
\read_fifo.fifo_ram[1].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \read_fifo.tail_ns\(4 downto 0),
      ADDRB(4 downto 0) => \read_fifo.tail_ns\(4 downto 0),
      ADDRC(4 downto 0) => \read_fifo.tail_ns\(4 downto 0),
      ADDRD(4 downto 0) => \read_fifo.head_r\(4 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => '1',
      DIC(0) => DIC(0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED\(1 downto 0),
      DOB(1 downto 0) => \NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED\(1 downto 0),
      DOC(1 downto 0) => \read_fifo.fifo_out_data_ns\(7 downto 6),
      DOD(1 downto 0) => \NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => '1'
    );
\read_fifo.fifo_ram[1].RAM32M0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => \read_fifo.tail_r\(3),
      I1 => \read_fifo.tail_r\(2),
      I2 => \read_fifo.tail_r_reg[4]_0\,
      I3 => \read_fifo.tail_r\(1),
      I4 => \read_fifo.tail_r\(4),
      I5 => \read_fifo.tail_r_reg[0]_1\,
      O => \read_fifo.tail_ns\(4)
    );
\read_fifo.fifo_ram[1].RAM32M0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => \read_fifo.tail_r\(1),
      I1 => \read_fifo.tail_r_reg[0]_0\,
      I2 => \^q\(0),
      I3 => \read_fifo.tail_r\(2),
      I4 => \read_fifo.tail_r\(3),
      I5 => \read_fifo.tail_r_reg[0]_1\,
      O => \read_fifo.tail_ns\(3)
    );
\read_fifo.fifo_ram[1].RAM32M0_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \^q\(0),
      I1 => \read_fifo.tail_r_reg[0]_0\,
      I2 => \read_fifo.tail_r\(1),
      I3 => \read_fifo.tail_r\(2),
      I4 => \read_fifo.tail_r_reg[0]_1\,
      O => \read_fifo.tail_ns\(2)
    );
\read_fifo.fifo_ram[1].RAM32M0_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => \read_fifo.tail_r_reg[0]_0\,
      I1 => \^q\(0),
      I2 => \read_fifo.tail_r\(1),
      I3 => \read_fifo.tail_r_reg[0]_1\,
      O => \read_fifo.tail_ns\(1)
    );
\read_fifo.fifo_ram[1].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \^q\(0),
      I1 => \read_fifo.tail_r_reg[0]_0\,
      I2 => \read_fifo.tail_r_reg[0]_1\,
      O => \read_fifo.tail_ns\(0)
    );
\read_fifo.head_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \read_fifo.head_r\(0),
      O => p_0_in(0)
    );
\read_fifo.head_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \read_fifo.head_r\(0),
      I1 => \read_fifo.head_r\(1),
      O => p_0_in(1)
    );
\read_fifo.head_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \read_fifo.head_r\(2),
      I1 => \read_fifo.head_r\(1),
      I2 => \read_fifo.head_r\(0),
      O => p_0_in(2)
    );
\read_fifo.head_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \read_fifo.head_r\(3),
      I1 => \read_fifo.head_r\(0),
      I2 => \read_fifo.head_r\(1),
      I3 => \read_fifo.head_r\(2),
      O => p_0_in(3)
    );
\read_fifo.head_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \read_fifo.head_r\(4),
      I1 => \read_fifo.head_r\(2),
      I2 => \read_fifo.head_r\(1),
      I3 => \read_fifo.head_r\(0),
      I4 => \read_fifo.head_r\(3),
      O => p_0_in(4)
    );
\read_fifo.head_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => p_0_in(0),
      Q => \read_fifo.head_r\(0),
      R => \read_fifo.head_r_reg[0]_0\
    );
\read_fifo.head_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => p_0_in(1),
      Q => \read_fifo.head_r\(1),
      R => \read_fifo.head_r_reg[0]_0\
    );
\read_fifo.head_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => p_0_in(2),
      Q => \read_fifo.head_r\(2),
      R => \read_fifo.head_r_reg[0]_0\
    );
\read_fifo.head_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => p_0_in(3),
      Q => \read_fifo.head_r\(3),
      R => \read_fifo.head_r_reg[0]_0\
    );
\read_fifo.head_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => p_0_in(4),
      Q => \read_fifo.head_r\(4),
      R => \read_fifo.head_r_reg[0]_0\
    );
\read_fifo.tail_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.tail_ns\(0),
      Q => \^q\(0),
      R => '0'
    );
\read_fifo.tail_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.tail_ns\(1),
      Q => \read_fifo.tail_r\(1),
      R => '0'
    );
\read_fifo.tail_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.tail_ns\(2),
      Q => \read_fifo.tail_r\(2),
      R => '0'
    );
\read_fifo.tail_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.tail_ns\(3),
      Q => \read_fifo.tail_r\(3),
      R => '0'
    );
\read_fifo.tail_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.tail_ns\(4),
      Q => \read_fifo.tail_r\(4),
      R => '0'
    );
sent_col_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cmd(0),
      Q => sent_col_r2,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_byte_group_io is
  port (
    mem_dqs_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    mem_dqs_ts : out STD_LOGIC_VECTOR ( 0 to 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    out_dq_2 : out STD_LOGIC;
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    out_dm_0 : out STD_LOGIC;
    out_dq_0 : out STD_LOGIC;
    out_dq_6 : out STD_LOGIC;
    out_dq_3 : out STD_LOGIC;
    out_dq_1 : out STD_LOGIC;
    out_dq_4 : out STD_LOGIC;
    out_dq_7 : out STD_LOGIC;
    out_dq_5 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_byte_group_io : entity is "mig_7series_v4_2_ddr_byte_group_io";
end mig_7series_0_mig_7series_v4_2_ddr_byte_group_io;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_byte_group_io is
  signal data_in_dly_1 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal data_in_dly_9 : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \input_[1].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[3].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[4].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[5].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[6].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[7].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[8].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[9].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => mem_dqs_out(0),
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => mem_dqs_ts(0),
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_1,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => \input_[9].iserdes_dq_.iserdesdq_1\
    );
\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_1,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D1(3),
      Q2 => D1(2),
      Q3 => D1(1),
      Q4 => D1(0),
      Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => \input_[9].iserdes_dq_.iserdesdq_1\
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => \input_[9].iserdes_dq_.iserdesdq_1\
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => \input_[9].iserdes_dq_.iserdesdq_1\
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => \input_[9].iserdes_dq_.iserdesdq_1\
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => \input_[9].iserdes_dq_.iserdesdq_1\
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => \input_[9].iserdes_dq_.iserdesdq_1\
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[9].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_9,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => \input_[9].iserdes_dq_.iserdesdq_1\
    );
\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_9,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D9(3),
      Q2 => D9(2),
      Q3 => D9(1),
      Q4 => D9(0),
      Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_2,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dm_0,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_0,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_6,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_3,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_1,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_4,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_7,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_5,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized0\ is
  port (
    mem_dq_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    oserdes_dq : in STD_LOGIC_VECTOR ( 47 downto 0 );
    po_oserdes_rst : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized0\ : entity is "mig_7series_v4_2_ddr_byte_group_io";
end \mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized0\ is
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \output_[0].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[10].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[11].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
begin
\output_[0].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(0),
      D2 => oserdes_dq(1),
      D3 => oserdes_dq(2),
      D4 => oserdes_dq(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[10].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(40),
      D2 => oserdes_dq(41),
      D3 => oserdes_dq(42),
      D4 => oserdes_dq(43),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(10),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[11].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(44),
      D2 => oserdes_dq(45),
      D3 => oserdes_dq(46),
      D4 => oserdes_dq(47),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(11),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[1].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(4),
      D2 => oserdes_dq(5),
      D3 => oserdes_dq(6),
      D4 => oserdes_dq(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[2].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(8),
      D2 => oserdes_dq(9),
      D3 => oserdes_dq(10),
      D4 => oserdes_dq(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[3].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(12),
      D2 => oserdes_dq(13),
      D3 => oserdes_dq(14),
      D4 => oserdes_dq(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[4].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(16),
      D2 => oserdes_dq(17),
      D3 => oserdes_dq(18),
      D4 => oserdes_dq(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[5].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(20),
      D2 => oserdes_dq(21),
      D3 => oserdes_dq(22),
      D4 => oserdes_dq(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[6].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(24),
      D2 => oserdes_dq(25),
      D3 => oserdes_dq(26),
      D4 => oserdes_dq(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[7].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(28),
      D2 => oserdes_dq(29),
      D3 => oserdes_dq(30),
      D4 => oserdes_dq(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[8].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(32),
      D2 => oserdes_dq(33),
      D3 => oserdes_dq(34),
      D4 => oserdes_dq(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[9].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(36),
      D2 => oserdes_dq(37),
      D3 => oserdes_dq(38),
      D4 => oserdes_dq(39),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(9),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized1\ is
  port (
    mem_dqs_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    mem_dqs_ts : out STD_LOGIC_VECTOR ( 0 to 0 );
    D0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    out_dq_13 : out STD_LOGIC;
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    out_dq_8 : out STD_LOGIC;
    out_dq_15 : out STD_LOGIC;
    out_dq_12 : out STD_LOGIC;
    out_dq_10 : out STD_LOGIC;
    out_dq_9 : out STD_LOGIC;
    out_dq_11 : out STD_LOGIC;
    out_dq_14 : out STD_LOGIC;
    out_dm_1 : out STD_LOGIC;
    idelay_ld_rst : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \input_[8].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_0 : in STD_LOGIC;
    idelay_ld_rst_reg_0 : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    CLKB0_5 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized1\ : entity is "mig_7series_v4_2_ddr_byte_group_io";
end \mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized1\ is
  signal data_in_dly_0 : STD_LOGIC;
  signal data_in_dly_1 : STD_LOGIC;
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal \^idelay_ld_rst\ : STD_LOGIC;
  signal idelay_ld_rst_i_1_n_0 : STD_LOGIC;
  signal rst_r3_reg_srl3_n_0 : STD_LOGIC;
  signal rst_r4 : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[0].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \input_[0].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[1].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[2].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[4].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[5].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[6].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[7].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED of \input_[8].iserdes_dq_.iserdesdq\ : label is "MLO";
  attribute BOX_TYPE of \output_[0].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of rst_r3_reg_srl3 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/rst_r3_reg_srl3 ";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst <= \^idelay_ld_rst\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => mem_dqs_out(0),
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => mem_dqs_ts(0),
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
idelay_ld_rst_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => rst_r4,
      I1 => \^idelay_ld_rst\,
      I2 => idelay_ld_rst_reg_0,
      O => idelay_ld_rst_i_1_n_0
    );
idelay_ld_rst_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_ld_rst_i_1_n_0,
      Q => \^idelay_ld_rst\,
      R => '0'
    );
\input_[0].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[8].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_0,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_0,
      LDPIPEEN => '0',
      REGRST => idelay_ld_rst_reg_0
    );
\input_[0].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_5,
      CLKDIV => \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_0,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D0(3),
      Q2 => D0(2),
      Q3 => D0(1),
      Q4 => D0(0),
      Q5 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[8].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_1,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_0,
      LDPIPEEN => '0',
      REGRST => idelay_ld_rst_reg_0
    );
\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_5,
      CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_1,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D1(3),
      Q2 => D1(2),
      Q3 => D1(1),
      Q4 => D1(0),
      Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[8].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_0,
      LDPIPEEN => '0',
      REGRST => idelay_ld_rst_reg_0
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_5,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[8].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_0,
      LDPIPEEN => '0',
      REGRST => idelay_ld_rst_reg_0
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_5,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[8].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_0,
      LDPIPEEN => '0',
      REGRST => idelay_ld_rst_reg_0
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_5,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[8].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_0,
      LDPIPEEN => '0',
      REGRST => idelay_ld_rst_reg_0
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_5,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[8].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_0,
      LDPIPEEN => '0',
      REGRST => idelay_ld_rst_reg_0
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_5,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \input_[8].iserdes_dq_.iserdesdq_0\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_0,
      LDPIPEEN => '0',
      REGRST => idelay_ld_rst_reg_0
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      CLKB => CLKB0_5,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[0].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_13,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_8,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_15,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_12,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_10,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_9,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_11,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dq_14,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => out_dm_1,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
rst_r3_reg_srl3: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => idelay_ld_rst_reg_0,
      Q => rst_r3_reg_srl3_n_0
    );
rst_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rst_r3_reg_srl3_n_0,
      Q => rst_r4,
      R => '0'
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized2\ is
  port (
    A_rst_primitives_reg : out STD_LOGIC_VECTOR ( 9 downto 0 );
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    oserdes_dq : in STD_LOGIC_VECTOR ( 39 downto 0 );
    po_oserdes_rst : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized2\ : entity is "mig_7series_v4_2_ddr_byte_group_io";
end \mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized2\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized2\ is
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \output_[10].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[11].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
begin
\output_[10].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(32),
      D2 => oserdes_dq(33),
      D3 => oserdes_dq(34),
      D4 => oserdes_dq(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => A_rst_primitives_reg(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[11].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(36),
      D2 => oserdes_dq(37),
      D3 => oserdes_dq(38),
      D4 => oserdes_dq(39),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => A_rst_primitives_reg(9),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[2].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(0),
      D2 => oserdes_dq(1),
      D3 => oserdes_dq(2),
      D4 => oserdes_dq(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => A_rst_primitives_reg(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[3].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(4),
      D2 => oserdes_dq(5),
      D3 => oserdes_dq(6),
      D4 => oserdes_dq(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => A_rst_primitives_reg(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[4].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(8),
      D2 => oserdes_dq(9),
      D3 => oserdes_dq(10),
      D4 => oserdes_dq(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => A_rst_primitives_reg(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[5].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(12),
      D2 => oserdes_dq(13),
      D3 => oserdes_dq(14),
      D4 => oserdes_dq(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => A_rst_primitives_reg(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[6].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(16),
      D2 => oserdes_dq(17),
      D3 => oserdes_dq(18),
      D4 => oserdes_dq(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => A_rst_primitives_reg(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[7].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(20),
      D2 => oserdes_dq(21),
      D3 => oserdes_dq(22),
      D4 => oserdes_dq(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => A_rst_primitives_reg(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[8].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(24),
      D2 => oserdes_dq(25),
      D3 => oserdes_dq(26),
      D4 => oserdes_dq(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => A_rst_primitives_reg(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[9].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(28),
      D2 => oserdes_dq(29),
      D3 => oserdes_dq(30),
      D4 => oserdes_dq(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => A_rst_primitives_reg(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_if_post_fifo is
  port (
    \rd_ptr_timing_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    init_complete_r1_timing_reg : out STD_LOGIC;
    \my_empty_reg[0]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ : out STD_LOGIC;
    phy_rddata_en : out STD_LOGIC;
    \wr_ptr_reg[1]_0\ : out STD_LOGIC;
    \wr_ptr_reg[0]_0\ : out STD_LOGIC;
    \my_empty_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    wr_en : out STD_LOGIC;
    \read_fifo.tail_r_reg[0]\ : in STD_LOGIC;
    \my_empty_reg[4]_rep__1_0\ : in STD_LOGIC;
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[4]_rep__1_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    app_rd_data : in STD_LOGIC_VECTOR ( 63 downto 0 );
    ififo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_if_post_fifo : entity is "mig_7series_v4_2_ddr_if_post_fifo";
end mig_7series_0_mig_7series_v4_2_ddr_if_post_fifo;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_if_post_fifo is
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal my_empty1 : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \my_empty[0]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_2_n_0\ : STD_LOGIC;
  signal \my_empty[2]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[0]_0\ : STD_LOGIC;
  signal \^my_empty_reg[3]_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep__0_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep__1_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1_n_0\ : STD_LOGIC;
  signal \my_full[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_3_n_0\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__0_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \wr_ptr[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_2_n_0\ : STD_LOGIC;
  signal \^wr_ptr_reg[0]_0\ : STD_LOGIC;
  signal \^wr_ptr_reg[1]_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \app_rd_data[104]_INST_0\ : label is "soft_lutpair467";
  attribute SOFT_HLUTNM of \app_rd_data[105]_INST_0\ : label is "soft_lutpair468";
  attribute SOFT_HLUTNM of \app_rd_data[106]_INST_0\ : label is "soft_lutpair468";
  attribute SOFT_HLUTNM of \app_rd_data[107]_INST_0\ : label is "soft_lutpair457";
  attribute SOFT_HLUTNM of \app_rd_data[108]_INST_0\ : label is "soft_lutpair472";
  attribute SOFT_HLUTNM of \app_rd_data[109]_INST_0\ : label is "soft_lutpair473";
  attribute SOFT_HLUTNM of \app_rd_data[10]_INST_0\ : label is "soft_lutpair469";
  attribute SOFT_HLUTNM of \app_rd_data[110]_INST_0\ : label is "soft_lutpair464";
  attribute SOFT_HLUTNM of \app_rd_data[111]_INST_0\ : label is "soft_lutpair462";
  attribute SOFT_HLUTNM of \app_rd_data[11]_INST_0\ : label is "soft_lutpair460";
  attribute SOFT_HLUTNM of \app_rd_data[120]_INST_0\ : label is "soft_lutpair467";
  attribute SOFT_HLUTNM of \app_rd_data[121]_INST_0\ : label is "soft_lutpair483";
  attribute SOFT_HLUTNM of \app_rd_data[122]_INST_0\ : label is "soft_lutpair481";
  attribute SOFT_HLUTNM of \app_rd_data[123]_INST_0\ : label is "soft_lutpair461";
  attribute SOFT_HLUTNM of \app_rd_data[124]_INST_0\ : label is "soft_lutpair456";
  attribute SOFT_HLUTNM of \app_rd_data[125]_INST_0\ : label is "soft_lutpair477";
  attribute SOFT_HLUTNM of \app_rd_data[126]_INST_0\ : label is "soft_lutpair485";
  attribute SOFT_HLUTNM of \app_rd_data[127]_INST_0\ : label is "soft_lutpair479";
  attribute SOFT_HLUTNM of \app_rd_data[12]_INST_0\ : label is "soft_lutpair471";
  attribute SOFT_HLUTNM of \app_rd_data[13]_INST_0\ : label is "soft_lutpair452";
  attribute SOFT_HLUTNM of \app_rd_data[14]_INST_0\ : label is "soft_lutpair465";
  attribute SOFT_HLUTNM of \app_rd_data[15]_INST_0\ : label is "soft_lutpair471";
  attribute SOFT_HLUTNM of \app_rd_data[24]_INST_0\ : label is "soft_lutpair462";
  attribute SOFT_HLUTNM of \app_rd_data[25]_INST_0\ : label is "soft_lutpair482";
  attribute SOFT_HLUTNM of \app_rd_data[27]_INST_0\ : label is "soft_lutpair458";
  attribute SOFT_HLUTNM of \app_rd_data[28]_INST_0\ : label is "soft_lutpair455";
  attribute SOFT_HLUTNM of \app_rd_data[29]_INST_0\ : label is "soft_lutpair476";
  attribute SOFT_HLUTNM of \app_rd_data[30]_INST_0\ : label is "soft_lutpair484";
  attribute SOFT_HLUTNM of \app_rd_data[31]_INST_0\ : label is "soft_lutpair478";
  attribute SOFT_HLUTNM of \app_rd_data[40]_INST_0\ : label is "soft_lutpair472";
  attribute SOFT_HLUTNM of \app_rd_data[41]_INST_0\ : label is "soft_lutpair459";
  attribute SOFT_HLUTNM of \app_rd_data[42]_INST_0\ : label is "soft_lutpair464";
  attribute SOFT_HLUTNM of \app_rd_data[43]_INST_0\ : label is "soft_lutpair470";
  attribute SOFT_HLUTNM of \app_rd_data[44]_INST_0\ : label is "soft_lutpair475";
  attribute SOFT_HLUTNM of \app_rd_data[45]_INST_0\ : label is "soft_lutpair463";
  attribute SOFT_HLUTNM of \app_rd_data[46]_INST_0\ : label is "soft_lutpair474";
  attribute SOFT_HLUTNM of \app_rd_data[47]_INST_0\ : label is "soft_lutpair475";
  attribute SOFT_HLUTNM of \app_rd_data[56]_INST_0\ : label is "soft_lutpair477";
  attribute SOFT_HLUTNM of \app_rd_data[57]_INST_0\ : label is "soft_lutpair459";
  attribute SOFT_HLUTNM of \app_rd_data[58]_INST_0\ : label is "soft_lutpair481";
  attribute SOFT_HLUTNM of \app_rd_data[59]_INST_0\ : label is "soft_lutpair483";
  attribute SOFT_HLUTNM of \app_rd_data[60]_INST_0\ : label is "soft_lutpair480";
  attribute SOFT_HLUTNM of \app_rd_data[61]_INST_0\ : label is "soft_lutpair463";
  attribute SOFT_HLUTNM of \app_rd_data[62]_INST_0\ : label is "soft_lutpair485";
  attribute SOFT_HLUTNM of \app_rd_data[63]_INST_0\ : label is "soft_lutpair479";
  attribute SOFT_HLUTNM of \app_rd_data[72]_INST_0\ : label is "soft_lutpair455";
  attribute SOFT_HLUTNM of \app_rd_data[73]_INST_0\ : label is "soft_lutpair474";
  attribute SOFT_HLUTNM of \app_rd_data[74]_INST_0\ : label is "soft_lutpair458";
  attribute SOFT_HLUTNM of \app_rd_data[75]_INST_0\ : label is "soft_lutpair470";
  attribute SOFT_HLUTNM of \app_rd_data[76]_INST_0\ : label is "soft_lutpair456";
  attribute SOFT_HLUTNM of \app_rd_data[77]_INST_0\ : label is "soft_lutpair473";
  attribute SOFT_HLUTNM of \app_rd_data[78]_INST_0\ : label is "soft_lutpair461";
  attribute SOFT_HLUTNM of \app_rd_data[79]_INST_0\ : label is "soft_lutpair469";
  attribute SOFT_HLUTNM of \app_rd_data[88]_INST_0\ : label is "soft_lutpair478";
  attribute SOFT_HLUTNM of \app_rd_data[89]_INST_0\ : label is "soft_lutpair482";
  attribute SOFT_HLUTNM of \app_rd_data[8]_INST_0\ : label is "soft_lutpair466";
  attribute SOFT_HLUTNM of \app_rd_data[90]_INST_0\ : label is "soft_lutpair457";
  attribute SOFT_HLUTNM of \app_rd_data[91]_INST_0\ : label is "soft_lutpair484";
  attribute SOFT_HLUTNM of \app_rd_data[92]_INST_0\ : label is "soft_lutpair480";
  attribute SOFT_HLUTNM of \app_rd_data[93]_INST_0\ : label is "soft_lutpair476";
  attribute SOFT_HLUTNM of \app_rd_data[94]_INST_0\ : label is "soft_lutpair460";
  attribute SOFT_HLUTNM of \app_rd_data[95]_INST_0\ : label is "soft_lutpair466";
  attribute SOFT_HLUTNM of \app_rd_data[9]_INST_0\ : label is "soft_lutpair465";
  attribute SOFT_HLUTNM of \gen_mux_rd[5].mux_rd_rise0_r[5]_i_1\ : label is "soft_lutpair452";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep__0\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__0\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep__1\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__1\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \my_full[0]_i_2__0\ : label is "soft_lutpair451";
  attribute SOFT_HLUTNM of rd_active_r_i_1 : label is "soft_lutpair453";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__0\ : label is "soft_lutpair454";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__0\ : label is "soft_lutpair454";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_2__0\ : label is "soft_lutpair451";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \read_fifo.fifo_ram[1].RAM32M0_i_7\ : label is "soft_lutpair453";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \my_empty_reg[0]_0\ <= \^my_empty_reg[0]_0\;
  \my_empty_reg[3]_0\ <= \^my_empty_reg[3]_0\;
  \rd_ptr_timing_reg[1]_0\(1 downto 0) <= rd_ptr_timing(1 downto 0);
  \wr_ptr_reg[0]_0\ <= \^wr_ptr_reg[0]_0\;
  \wr_ptr_reg[1]_0\ <= \^wr_ptr_reg[1]_0\;
\app_rd_data[104]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(14),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(14),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(48)
    );
\app_rd_data[105]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(46),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(46),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(49)
    );
\app_rd_data[106]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(38),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(38),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(50)
    );
\app_rd_data[107]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(54),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(54),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(51)
    );
\app_rd_data[108]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(30),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(30),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(52)
    );
\app_rd_data[109]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(6),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(6),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(53)
    );
\app_rd_data[10]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(32),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(32),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(2)
    );
\app_rd_data[110]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(62),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(62),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(54)
    );
\app_rd_data[111]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(22),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(22),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(55)
    );
\app_rd_data[11]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(48),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(48),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(3)
    );
\app_rd_data[120]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(15),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(15),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(56)
    );
\app_rd_data[121]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(47),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(47),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(57)
    );
\app_rd_data[122]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(39),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(39),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(58)
    );
\app_rd_data[123]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(55),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(55),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(59)
    );
\app_rd_data[124]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(31),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(31),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(60)
    );
\app_rd_data[125]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(7),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(7),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(61)
    );
\app_rd_data[126]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(63),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(62)
    );
\app_rd_data[127]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(23),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(23),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(63)
    );
\app_rd_data[12]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(24),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(24),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(4)
    );
\app_rd_data[13]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(0),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(0),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(5)
    );
\app_rd_data[14]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(56),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(56),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(6)
    );
\app_rd_data[15]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(16),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(16),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(7)
    );
\app_rd_data[24]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(9),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(9),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(8)
    );
\app_rd_data[25]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(41),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(41),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(9)
    );
\app_rd_data[26]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(33),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(33),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(10)
    );
\app_rd_data[27]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(49),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(49),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(11)
    );
\app_rd_data[28]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(25),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(25),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(12)
    );
\app_rd_data[29]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(1),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(1),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(13)
    );
\app_rd_data[30]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(57),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(57),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(14)
    );
\app_rd_data[31]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(17),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(17),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(15)
    );
\app_rd_data[40]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(10),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(10),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(16)
    );
\app_rd_data[41]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(42),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(42),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(17)
    );
\app_rd_data[42]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(34),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(34),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(18)
    );
\app_rd_data[43]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(50),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(50),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(19)
    );
\app_rd_data[44]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(26),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(26),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(20)
    );
\app_rd_data[45]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(2),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(2),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(21)
    );
\app_rd_data[46]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(58),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(58),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(22)
    );
\app_rd_data[47]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(18),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(18),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(23)
    );
\app_rd_data[56]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(11),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(11),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(24)
    );
\app_rd_data[57]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(43),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(43),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(25)
    );
\app_rd_data[58]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(35),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(35),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(26)
    );
\app_rd_data[59]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(51),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(51),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(27)
    );
\app_rd_data[60]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(27),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(27),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(28)
    );
\app_rd_data[61]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(3),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(3),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(29)
    );
\app_rd_data[62]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(59),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(59),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(30)
    );
\app_rd_data[63]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(19),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(19),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(31)
    );
\app_rd_data[72]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(12),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(12),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(32)
    );
\app_rd_data[73]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(44),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(44),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(33)
    );
\app_rd_data[74]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(36),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(36),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(34)
    );
\app_rd_data[75]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(52),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(52),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(35)
    );
\app_rd_data[76]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(28),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(28),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(36)
    );
\app_rd_data[77]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(4),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(4),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(37)
    );
\app_rd_data[78]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(60),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(60),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(38)
    );
\app_rd_data[79]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(20),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(20),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(39)
    );
\app_rd_data[88]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(13),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(13),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(40)
    );
\app_rd_data[89]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(45),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(45),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(41)
    );
\app_rd_data[8]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(8),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(8),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(0)
    );
\app_rd_data[90]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(37),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(37),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(42)
    );
\app_rd_data[91]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(53),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(53),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(43)
    );
\app_rd_data[92]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(29),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(29),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(44)
    );
\app_rd_data[93]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(5),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(5),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(45)
    );
\app_rd_data[94]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(61),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(61),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(46)
    );
\app_rd_data[95]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(21),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(21),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(47)
    );
\app_rd_data[9]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(40),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(40),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(1)
    );
\gen_mux_rd[0].mux_rd_fall0_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(9),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(9),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(8),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\
    );
\gen_mux_rd[0].mux_rd_fall1_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(11),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(11),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(24),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\
    );
\gen_mux_rd[0].mux_rd_fall2_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(13),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(13),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(40),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\
    );
\gen_mux_rd[0].mux_rd_fall3_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(15),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(15),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(56),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\
    );
\gen_mux_rd[0].mux_rd_rise0_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(8),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(8),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(0),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\
    );
\gen_mux_rd[0].mux_rd_rise1_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(10),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(10),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(16),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\
    );
\gen_mux_rd[0].mux_rd_rise2_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(12),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(12),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(32),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\
    );
\gen_mux_rd[0].mux_rd_rise3_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(14),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(14),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(48),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\
    );
\gen_mux_rd[1].mux_rd_fall0_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(41),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(41),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(9),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\
    );
\gen_mux_rd[1].mux_rd_fall1_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(43),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(43),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(25),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\
    );
\gen_mux_rd[1].mux_rd_fall2_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(45),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(45),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(41),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\
    );
\gen_mux_rd[1].mux_rd_fall3_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(47),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(47),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(57),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\
    );
\gen_mux_rd[1].mux_rd_rise0_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(40),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(40),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(1),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\
    );
\gen_mux_rd[1].mux_rd_rise1_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(42),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(42),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(17),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\
    );
\gen_mux_rd[1].mux_rd_rise2_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(44),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(44),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(33),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\
    );
\gen_mux_rd[1].mux_rd_rise3_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(46),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(46),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(49),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\
    );
\gen_mux_rd[2].mux_rd_fall0_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(33),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(33),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(10),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\
    );
\gen_mux_rd[2].mux_rd_fall1_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(35),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(35),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(26),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\
    );
\gen_mux_rd[2].mux_rd_fall2_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(37),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(37),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(42),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\
    );
\gen_mux_rd[2].mux_rd_fall3_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(39),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(39),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(58),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\
    );
\gen_mux_rd[2].mux_rd_rise0_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(32),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(32),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(2),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\
    );
\gen_mux_rd[2].mux_rd_rise1_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(34),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(34),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(18),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\
    );
\gen_mux_rd[2].mux_rd_rise2_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(36),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(36),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(34),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\
    );
\gen_mux_rd[2].mux_rd_rise3_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(38),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(38),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(50),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\
    );
\gen_mux_rd[3].mux_rd_fall0_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(49),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(49),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(11),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\
    );
\gen_mux_rd[3].mux_rd_fall1_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(51),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(51),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(27),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\
    );
\gen_mux_rd[3].mux_rd_fall2_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(53),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(53),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(43),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\
    );
\gen_mux_rd[3].mux_rd_fall3_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(55),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(55),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(59),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\
    );
\gen_mux_rd[3].mux_rd_rise0_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(48),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(48),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(3),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\
    );
\gen_mux_rd[3].mux_rd_rise1_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(50),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(50),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(19),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\
    );
\gen_mux_rd[3].mux_rd_rise2_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(52),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(52),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(35),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\
    );
\gen_mux_rd[3].mux_rd_rise3_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(54),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(54),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(51),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\
    );
\gen_mux_rd[4].mux_rd_fall0_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(25),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(25),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(12),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\
    );
\gen_mux_rd[4].mux_rd_fall1_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(27),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(27),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(28),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\
    );
\gen_mux_rd[4].mux_rd_fall2_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(29),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(29),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(44),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\
    );
\gen_mux_rd[4].mux_rd_fall3_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(31),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(31),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(60),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\
    );
\gen_mux_rd[4].mux_rd_rise0_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(24),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(24),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(4),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\
    );
\gen_mux_rd[4].mux_rd_rise1_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(26),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(26),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(20),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\
    );
\gen_mux_rd[4].mux_rd_rise2_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(28),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(28),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(36),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\
    );
\gen_mux_rd[4].mux_rd_rise3_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(30),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(30),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(52),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\
    );
\gen_mux_rd[5].mux_rd_fall0_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(1),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(1),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(13),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\
    );
\gen_mux_rd[5].mux_rd_fall1_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(3),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(3),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(29),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\
    );
\gen_mux_rd[5].mux_rd_fall2_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(5),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(5),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(45),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\
    );
\gen_mux_rd[5].mux_rd_fall3_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(7),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(7),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(61),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\
    );
\gen_mux_rd[5].mux_rd_rise0_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(0),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(0),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(5),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\
    );
\gen_mux_rd[5].mux_rd_rise1_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(2),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(2),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(21),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\
    );
\gen_mux_rd[5].mux_rd_rise2_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(4),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(4),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(37),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\
    );
\gen_mux_rd[5].mux_rd_rise3_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(6),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(6),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(53),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\
    );
\gen_mux_rd[6].mux_rd_fall0_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(57),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(57),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(14),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\
    );
\gen_mux_rd[6].mux_rd_fall1_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(59),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(59),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(30),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\
    );
\gen_mux_rd[6].mux_rd_fall2_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(61),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(61),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(46),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\
    );
\gen_mux_rd[6].mux_rd_fall3_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(63),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(62),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\
    );
\gen_mux_rd[6].mux_rd_rise0_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(56),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(56),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(6),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\
    );
\gen_mux_rd[6].mux_rd_rise1_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(58),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(58),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(22),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\
    );
\gen_mux_rd[6].mux_rd_rise2_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(60),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(60),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(38),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\
    );
\gen_mux_rd[6].mux_rd_rise3_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(62),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(62),
      I2 => my_empty(4),
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(54),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\
    );
\gen_mux_rd[7].mux_rd_fall0_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(17),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(17),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(15),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\
    );
\gen_mux_rd[7].mux_rd_fall1_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(19),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(19),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(31),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\
    );
\gen_mux_rd[7].mux_rd_fall2_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(21),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(21),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(47),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\
    );
\gen_mux_rd[7].mux_rd_fall3_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(23),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(23),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(63),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\
    );
\gen_mux_rd[7].mux_rd_rise0_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(16),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(16),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(7),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\
    );
\gen_mux_rd[7].mux_rd_rise1_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(18),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(18),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(23),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\
    );
\gen_mux_rd[7].mux_rd_rise2_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(20),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(20),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(39),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\
    );
\gen_mux_rd[7].mux_rd_rise3_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACFFAC00"
    )
        port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(22),
      I1 => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(22),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      I4 => app_rd_data(55),
      O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\
    );
mem_reg_0_3_0_5_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000078F"
    )
        port map (
      I0 => if_empty_r_0(0),
      I1 => \my_empty_reg[4]_rep__1_1\(1),
      I2 => my_empty(2),
      I3 => my_full(0),
      I4 => \my_empty_reg[4]_rep__1_0\,
      O => wr_en
    );
\my_empty[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBAAAAAA88AAA"
    )
        port map (
      I0 => \^my_empty_reg[0]_0\,
      I1 => my_full(1),
      I2 => \my_empty_reg[4]_rep__1_0\,
      I3 => \wr_ptr[1]_i_2_n_0\,
      I4 => my_empty(1),
      I5 => \my_empty[4]_i_2__0_n_0\,
      O => \my_empty[0]_i_1_n_0\
    );
\my_empty[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00411400"
    )
        port map (
      I0 => \my_empty[1]_i_2_n_0\,
      I1 => \^wr_ptr_reg[1]_0\,
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => \^wr_ptr_reg[0]_0\,
      I5 => my_empty(1),
      O => \my_empty[1]_i_1_n_0\
    );
\my_empty[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFFFBFFFFFEAFF"
    )
        port map (
      I0 => my_full(1),
      I1 => if_empty_r_0(0),
      I2 => \my_empty_reg[4]_rep__1_1\(1),
      I3 => \my_empty_reg[4]_rep__1_0\,
      I4 => \^my_empty_reg[3]_0\,
      I5 => my_empty(1),
      O => \my_empty[1]_i_2_n_0\
    );
\my_empty[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBAAAAAA88AAA"
    )
        port map (
      I0 => my_empty(2),
      I1 => my_full(1),
      I2 => \my_empty_reg[4]_rep__1_0\,
      I3 => \wr_ptr[1]_i_2_n_0\,
      I4 => my_empty(1),
      I5 => \my_empty[4]_i_2__0_n_0\,
      O => \my_empty[2]_i_1_n_0\
    );
\my_empty[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBAAAAAA88AAA"
    )
        port map (
      I0 => \^my_empty_reg[3]_0\,
      I1 => my_full(1),
      I2 => \my_empty_reg[4]_rep__1_0\,
      I3 => \wr_ptr[1]_i_2_n_0\,
      I4 => my_empty(1),
      I5 => \my_empty[4]_i_2__0_n_0\,
      O => \my_empty[3]_i_1_n_0\
    );
\my_empty[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBAAAAAA88AAA"
    )
        port map (
      I0 => my_empty(4),
      I1 => my_full(1),
      I2 => \my_empty_reg[4]_rep__1_0\,
      I3 => \wr_ptr[1]_i_2_n_0\,
      I4 => my_empty(1),
      I5 => \my_empty[4]_i_2__0_n_0\,
      O => \my_empty[4]_i_1_n_0\
    );
\my_empty[4]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000960"
    )
        port map (
      I0 => \^wr_ptr_reg[1]_0\,
      I1 => rd_ptr(1),
      I2 => rd_ptr(0),
      I3 => \^wr_ptr_reg[0]_0\,
      I4 => my_empty(1),
      O => \my_empty[4]_i_2__0_n_0\
    );
\my_empty_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[0]_i_1_n_0\,
      Q => \^my_empty_reg[0]_0\,
      S => ififo_rst
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[1]_i_1_n_0\,
      Q => my_empty(1),
      S => ififo_rst
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[2]_i_1_n_0\,
      Q => my_empty(2),
      S => ififo_rst
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[3]_i_1_n_0\,
      Q => \^my_empty_reg[3]_0\,
      S => ififo_rst
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[4]_i_1_n_0\,
      Q => my_empty(4),
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[4]_i_1_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep__0\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[4]_i_1_n_0\,
      Q => \my_empty_reg[4]_rep__0_n_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep__1\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[4]_i_1_n_0\,
      Q => \my_empty_reg[4]_rep__1_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAB8AAAAAA8"
    )
        port map (
      I0 => my_full(0),
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => \my_empty_reg[4]_rep__1_0\,
      I4 => \wr_ptr[1]_i_2_n_0\,
      I5 => \my_full[0]_i_2__0_n_0\,
      O => \my_full[0]_i_1_n_0\
    );
\my_full[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000960"
    )
        port map (
      I0 => rd_ptr(1),
      I1 => \^wr_ptr_reg[1]_0\,
      I2 => \^wr_ptr_reg[0]_0\,
      I3 => rd_ptr(0),
      I4 => my_full(1),
      O => \my_full[0]_i_2__0_n_0\
    );
\my_full[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAFFFF"
    )
        port map (
      I0 => my_full(1),
      I1 => if_empty_r_0(0),
      I2 => \my_empty_reg[4]_rep__1_1\(1),
      I3 => \my_empty_reg[4]_rep__1_0\,
      I4 => my_empty(1),
      O => \my_full[1]_i_1_n_0\
    );
\my_full[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00411400"
    )
        port map (
      I0 => \my_full[1]_i_3_n_0\,
      I1 => rd_ptr(1),
      I2 => \^wr_ptr_reg[1]_0\,
      I3 => \^wr_ptr_reg[0]_0\,
      I4 => rd_ptr(0),
      I5 => my_full(1),
      O => \my_full[1]_i_2_n_0\
    );
\my_full[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFFFEBFBFBF"
    )
        port map (
      I0 => my_empty(1),
      I1 => my_full(1),
      I2 => \my_empty_reg[4]_rep__1_0\,
      I3 => if_empty_r_0(0),
      I4 => \my_empty_reg[4]_rep__1_1\(1),
      I5 => \^my_empty_reg[3]_0\,
      O => \my_full[1]_i_3_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_full[0]_i_1_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_full[1]_i_2_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
rd_active_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__1_0\,
      I1 => \^my_empty_reg[0]_0\,
      I2 => if_empty_r_0(0),
      I3 => \my_empty_reg[4]_rep__1_1\(0),
      O => phy_rddata_en
    );
\rd_ptr[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => my_empty(1),
      I1 => \wr_ptr[1]_i_2_n_0\,
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__0_n_0\
    );
\rd_ptr[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \wr_ptr[1]_i_2_n_0\,
      I2 => my_empty(1),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1__0_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[0]_i_1__0_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[1]_i_1__0_n_0\,
      Q => rd_ptr(1),
      R => ififo_rst
    );
\rd_ptr_timing[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EF0F0000FFFF10F0"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__1_0\,
      I1 => my_full(1),
      I2 => \wr_ptr[1]_i_2_n_0\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(0),
      I5 => rd_ptr(0),
      O => \rd_ptr_timing[0]_i_1__0_n_0\
    );
\rd_ptr_timing[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF10F0EF0F0000"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__1_0\,
      I1 => my_full(1),
      I2 => \wr_ptr[1]_i_2_n_0\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(1),
      I5 => my_empty1(1),
      O => \rd_ptr_timing[1]_i_1__0_n_0\
    );
\rd_ptr_timing[1]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => my_empty1(1)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \rd_ptr_timing[0]_i_1__0_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \rd_ptr_timing[1]_i_1__0_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\read_fifo.fifo_ram[1].RAM32M0_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"002A2A2A"
    )
        port map (
      I0 => \read_fifo.tail_r_reg[0]\,
      I1 => \my_empty_reg[4]_rep__1_0\,
      I2 => \^my_empty_reg[0]_0\,
      I3 => if_empty_r_0(0),
      I4 => \my_empty_reg[4]_rep__1_1\(0),
      O => init_complete_r1_timing_reg
    );
\wr_ptr[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEC1013"
    )
        port map (
      I0 => my_empty(1),
      I1 => \my_empty_reg[4]_rep__1_0\,
      I2 => \wr_ptr[1]_i_2_n_0\,
      I3 => my_full(1),
      I4 => \^wr_ptr_reg[0]_0\,
      O => \wr_ptr[0]_i_1__1_n_0\
    );
\wr_ptr[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDFF5D000200A2"
    )
        port map (
      I0 => \^wr_ptr_reg[0]_0\,
      I1 => my_full(1),
      I2 => \wr_ptr[1]_i_2_n_0\,
      I3 => \my_empty_reg[4]_rep__1_0\,
      I4 => my_empty(1),
      I5 => \^wr_ptr_reg[1]_0\,
      O => \wr_ptr[1]_i_1__1_n_0\
    );
\wr_ptr[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \^my_empty_reg[3]_0\,
      I1 => \my_empty_reg[4]_rep__1_0\,
      I2 => \my_empty_reg[4]_rep__1_1\(1),
      I3 => if_empty_r_0(0),
      O => \wr_ptr[1]_i_2_n_0\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[0]_i_1__1_n_0\,
      Q => \^wr_ptr_reg[0]_0\,
      R => ififo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[1]_i_1__1_n_0\,
      Q => \^wr_ptr_reg[1]_0\,
      R => ififo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_if_post_fifo_9 is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    app_rd_data_valid : out STD_LOGIC;
    \my_empty_reg[0]_0\ : out STD_LOGIC;
    \my_empty_reg[0]_1\ : out STD_LOGIC;
    \wr_ptr_reg[1]_0\ : out STD_LOGIC;
    \wr_ptr_reg[0]_0\ : out STD_LOGIC;
    \my_empty_reg[3]_0\ : out STD_LOGIC;
    app_rd_data : out STD_LOGIC_VECTOR ( 63 downto 0 );
    p_1_in : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_61\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_62\ : out STD_LOGIC;
    \my_empty_reg[4]_rep__1_0\ : in STD_LOGIC;
    my_empty : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    app_rd_data_valid_0 : in STD_LOGIC;
    app_rd_data_valid_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.tail_r_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \app_rd_data[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \app_rd_data[117]_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    ififo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_if_post_fifo_9 : entity is "mig_7series_v4_2_ddr_if_post_fifo";
end mig_7series_0_mig_7series_v4_2_ddr_if_post_fifo_9;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_if_post_fifo_9 is
  signal my_empty1 : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \my_empty[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \my_empty[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2_n_0\ : STD_LOGIC;
  signal my_empty_0 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \^my_empty_reg[0]_0\ : STD_LOGIC;
  signal \^my_empty_reg[3]_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep__0_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep__1_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full[0]_i_2_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_3__0_n_0\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \wr_ptr[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \^wr_ptr_reg[0]_0\ : STD_LOGIC;
  signal \^wr_ptr_reg[1]_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \app_rd_data[0]_INST_0\ : label is "soft_lutpair392";
  attribute SOFT_HLUTNM of \app_rd_data[100]_INST_0\ : label is "soft_lutpair385";
  attribute SOFT_HLUTNM of \app_rd_data[101]_INST_0\ : label is "soft_lutpair400";
  attribute SOFT_HLUTNM of \app_rd_data[102]_INST_0\ : label is "soft_lutpair390";
  attribute SOFT_HLUTNM of \app_rd_data[103]_INST_0\ : label is "soft_lutpair404";
  attribute SOFT_HLUTNM of \app_rd_data[112]_INST_0\ : label is "soft_lutpair391";
  attribute SOFT_HLUTNM of \app_rd_data[113]_INST_0\ : label is "soft_lutpair399";
  attribute SOFT_HLUTNM of \app_rd_data[114]_INST_0\ : label is "soft_lutpair413";
  attribute SOFT_HLUTNM of \app_rd_data[115]_INST_0\ : label is "soft_lutpair396";
  attribute SOFT_HLUTNM of \app_rd_data[116]_INST_0\ : label is "soft_lutpair408";
  attribute SOFT_HLUTNM of \app_rd_data[117]_INST_0\ : label is "soft_lutpair407";
  attribute SOFT_HLUTNM of \app_rd_data[118]_INST_0\ : label is "soft_lutpair410";
  attribute SOFT_HLUTNM of \app_rd_data[119]_INST_0\ : label is "soft_lutpair404";
  attribute SOFT_HLUTNM of \app_rd_data[16]_INST_0\ : label is "soft_lutpair389";
  attribute SOFT_HLUTNM of \app_rd_data[17]_INST_0\ : label is "soft_lutpair397";
  attribute SOFT_HLUTNM of \app_rd_data[18]_INST_0\ : label is "soft_lutpair412";
  attribute SOFT_HLUTNM of \app_rd_data[19]_INST_0\ : label is "soft_lutpair394";
  attribute SOFT_HLUTNM of \app_rd_data[1]_INST_0\ : label is "soft_lutpair398";
  attribute SOFT_HLUTNM of \app_rd_data[20]_INST_0\ : label is "soft_lutpair407";
  attribute SOFT_HLUTNM of \app_rd_data[21]_INST_0\ : label is "soft_lutpair405";
  attribute SOFT_HLUTNM of \app_rd_data[22]_INST_0\ : label is "soft_lutpair411";
  attribute SOFT_HLUTNM of \app_rd_data[23]_INST_0\ : label is "soft_lutpair402";
  attribute SOFT_HLUTNM of \app_rd_data[2]_INST_0\ : label is "soft_lutpair383";
  attribute SOFT_HLUTNM of \app_rd_data[32]_INST_0\ : label is "soft_lutpair388";
  attribute SOFT_HLUTNM of \app_rd_data[33]_INST_0\ : label is "soft_lutpair382";
  attribute SOFT_HLUTNM of \app_rd_data[34]_INST_0\ : label is "soft_lutpair383";
  attribute SOFT_HLUTNM of \app_rd_data[35]_INST_0\ : label is "soft_lutpair395";
  attribute SOFT_HLUTNM of \app_rd_data[36]_INST_0\ : label is "soft_lutpair402";
  attribute SOFT_HLUTNM of \app_rd_data[37]_INST_0\ : label is "soft_lutpair397";
  attribute SOFT_HLUTNM of \app_rd_data[38]_INST_0\ : label is "soft_lutpair409";
  attribute SOFT_HLUTNM of \app_rd_data[39]_INST_0\ : label is "soft_lutpair382";
  attribute SOFT_HLUTNM of \app_rd_data[3]_INST_0\ : label is "soft_lutpair410";
  attribute SOFT_HLUTNM of \app_rd_data[48]_INST_0\ : label is "soft_lutpair412";
  attribute SOFT_HLUTNM of \app_rd_data[49]_INST_0\ : label is "soft_lutpair406";
  attribute SOFT_HLUTNM of \app_rd_data[4]_INST_0\ : label is "soft_lutpair384";
  attribute SOFT_HLUTNM of \app_rd_data[50]_INST_0\ : label is "soft_lutpair413";
  attribute SOFT_HLUTNM of \app_rd_data[51]_INST_0\ : label is "soft_lutpair395";
  attribute SOFT_HLUTNM of \app_rd_data[52]_INST_0\ : label is "soft_lutpair400";
  attribute SOFT_HLUTNM of \app_rd_data[53]_INST_0\ : label is "soft_lutpair386";
  attribute SOFT_HLUTNM of \app_rd_data[54]_INST_0\ : label is "soft_lutpair392";
  attribute SOFT_HLUTNM of \app_rd_data[55]_INST_0\ : label is "soft_lutpair403";
  attribute SOFT_HLUTNM of \app_rd_data[5]_INST_0\ : label is "soft_lutpair399";
  attribute SOFT_HLUTNM of \app_rd_data[64]_INST_0\ : label is "soft_lutpair396";
  attribute SOFT_HLUTNM of \app_rd_data[65]_INST_0\ : label is "soft_lutpair401";
  attribute SOFT_HLUTNM of \app_rd_data[66]_INST_0\ : label is "soft_lutpair387";
  attribute SOFT_HLUTNM of \app_rd_data[67]_INST_0\ : label is "soft_lutpair391";
  attribute SOFT_HLUTNM of \app_rd_data[68]_INST_0\ : label is "soft_lutpair384";
  attribute SOFT_HLUTNM of \app_rd_data[69]_INST_0\ : label is "soft_lutpair405";
  attribute SOFT_HLUTNM of \app_rd_data[6]_INST_0\ : label is "soft_lutpair389";
  attribute SOFT_HLUTNM of \app_rd_data[70]_INST_0\ : label is "soft_lutpair394";
  attribute SOFT_HLUTNM of \app_rd_data[71]_INST_0\ : label is "soft_lutpair386";
  attribute SOFT_HLUTNM of \app_rd_data[7]_INST_0\ : label is "soft_lutpair403";
  attribute SOFT_HLUTNM of \app_rd_data[80]_INST_0\ : label is "soft_lutpair390";
  attribute SOFT_HLUTNM of \app_rd_data[81]_INST_0\ : label is "soft_lutpair398";
  attribute SOFT_HLUTNM of \app_rd_data[82]_INST_0\ : label is "soft_lutpair388";
  attribute SOFT_HLUTNM of \app_rd_data[83]_INST_0\ : label is "soft_lutpair409";
  attribute SOFT_HLUTNM of \app_rd_data[84]_INST_0\ : label is "soft_lutpair401";
  attribute SOFT_HLUTNM of \app_rd_data[85]_INST_0\ : label is "soft_lutpair406";
  attribute SOFT_HLUTNM of \app_rd_data[86]_INST_0\ : label is "soft_lutpair393";
  attribute SOFT_HLUTNM of \app_rd_data[87]_INST_0\ : label is "soft_lutpair408";
  attribute SOFT_HLUTNM of \app_rd_data[96]_INST_0\ : label is "soft_lutpair393";
  attribute SOFT_HLUTNM of \app_rd_data[97]_INST_0\ : label is "soft_lutpair385";
  attribute SOFT_HLUTNM of \app_rd_data[98]_INST_0\ : label is "soft_lutpair387";
  attribute SOFT_HLUTNM of \app_rd_data[99]_INST_0\ : label is "soft_lutpair411";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep__0\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__0\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep__1\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__1\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \my_full[0]_i_2\ : label is "soft_lutpair380";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1\ : label is "soft_lutpair381";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1\ : label is "soft_lutpair381";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_2\ : label is "soft_lutpair380";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \my_empty_reg[0]_0\ <= \^my_empty_reg[0]_0\;
  \my_empty_reg[3]_0\ <= \^my_empty_reg[3]_0\;
  \out\(1 downto 0) <= rd_ptr_timing(1 downto 0);
  \wr_ptr_reg[0]_0\ <= \^wr_ptr_reg[0]_0\;
  \wr_ptr_reg[1]_0\ <= \^wr_ptr_reg[1]_0\;
\app_rd_data[0]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(8),
      I1 => \app_rd_data[117]_0\(8),
      I2 => my_empty_0(4),
      O => app_rd_data(0)
    );
\app_rd_data[100]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(46),
      I1 => \app_rd_data[117]_0\(46),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(52)
    );
\app_rd_data[101]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(62),
      I1 => \app_rd_data[117]_0\(62),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(53)
    );
\app_rd_data[102]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(22),
      I1 => \app_rd_data[117]_0\(22),
      I2 => my_empty_0(4),
      O => app_rd_data(54)
    );
\app_rd_data[103]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(54),
      I1 => \app_rd_data[117]_0\(54),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(55)
    );
\app_rd_data[112]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(15),
      I1 => \app_rd_data[117]_0\(15),
      I2 => my_empty_0(4),
      O => app_rd_data(56)
    );
\app_rd_data[113]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(39),
      I1 => \app_rd_data[117]_0\(39),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(57)
    );
\app_rd_data[114]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(7),
      I1 => \app_rd_data[117]_0\(7),
      I2 => my_empty_0(4),
      O => app_rd_data(58)
    );
\app_rd_data[115]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(31),
      I1 => \app_rd_data[117]_0\(31),
      I2 => my_empty_0(4),
      O => app_rd_data(59)
    );
\app_rd_data[116]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(47),
      I1 => \app_rd_data[117]_0\(47),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(60)
    );
\app_rd_data[117]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(63),
      I1 => \app_rd_data[117]_0\(63),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(61)
    );
\app_rd_data[118]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(23),
      I1 => \app_rd_data[117]_0\(23),
      I2 => my_empty_0(4),
      O => app_rd_data(62)
    );
\app_rd_data[119]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(55),
      I1 => \app_rd_data[117]_0\(55),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(63)
    );
\app_rd_data[16]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(9),
      I1 => \app_rd_data[117]_0\(9),
      I2 => my_empty_0(4),
      O => app_rd_data(8)
    );
\app_rd_data[17]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(33),
      I1 => \app_rd_data[117]_0\(33),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(9)
    );
\app_rd_data[18]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(1),
      I1 => \app_rd_data[117]_0\(1),
      I2 => my_empty_0(4),
      O => app_rd_data(10)
    );
\app_rd_data[19]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(25),
      I1 => \app_rd_data[117]_0\(25),
      I2 => my_empty_0(4),
      O => app_rd_data(11)
    );
\app_rd_data[1]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(32),
      I1 => \app_rd_data[117]_0\(32),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(1)
    );
\app_rd_data[20]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(41),
      I1 => \app_rd_data[117]_0\(41),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(12)
    );
\app_rd_data[21]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(57),
      I1 => \app_rd_data[117]_0\(57),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(13)
    );
\app_rd_data[22]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(17),
      I1 => \app_rd_data[117]_0\(17),
      I2 => my_empty_0(4),
      O => app_rd_data(14)
    );
\app_rd_data[23]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(49),
      I1 => \app_rd_data[117]_0\(49),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(15)
    );
\app_rd_data[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(0),
      I1 => \app_rd_data[117]_0\(0),
      I2 => my_empty_0(4),
      O => app_rd_data(2)
    );
\app_rd_data[32]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(10),
      I1 => \app_rd_data[117]_0\(10),
      I2 => my_empty_0(4),
      O => app_rd_data(16)
    );
\app_rd_data[33]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(34),
      I1 => \app_rd_data[117]_0\(34),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(17)
    );
\app_rd_data[34]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(2),
      I1 => \app_rd_data[117]_0\(2),
      I2 => my_empty_0(4),
      O => app_rd_data(18)
    );
\app_rd_data[35]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(26),
      I1 => \app_rd_data[117]_0\(26),
      I2 => my_empty_0(4),
      O => app_rd_data(19)
    );
\app_rd_data[36]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(42),
      I1 => \app_rd_data[117]_0\(42),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(20)
    );
\app_rd_data[37]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(58),
      I1 => \app_rd_data[117]_0\(58),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(21)
    );
\app_rd_data[38]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(18),
      I1 => \app_rd_data[117]_0\(18),
      I2 => my_empty_0(4),
      O => app_rd_data(22)
    );
\app_rd_data[39]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(50),
      I1 => \app_rd_data[117]_0\(50),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(23)
    );
\app_rd_data[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(24),
      I1 => \app_rd_data[117]_0\(24),
      I2 => my_empty_0(4),
      O => app_rd_data(3)
    );
\app_rd_data[48]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(11),
      I1 => \app_rd_data[117]_0\(11),
      I2 => my_empty_0(4),
      O => app_rd_data(24)
    );
\app_rd_data[49]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(35),
      I1 => \app_rd_data[117]_0\(35),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(25)
    );
\app_rd_data[4]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(40),
      I1 => \app_rd_data[117]_0\(40),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(4)
    );
\app_rd_data[50]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(3),
      I1 => \app_rd_data[117]_0\(3),
      I2 => my_empty_0(4),
      O => app_rd_data(26)
    );
\app_rd_data[51]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(27),
      I1 => \app_rd_data[117]_0\(27),
      I2 => my_empty_0(4),
      O => app_rd_data(27)
    );
\app_rd_data[52]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(43),
      I1 => \app_rd_data[117]_0\(43),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(28)
    );
\app_rd_data[53]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(59),
      I1 => \app_rd_data[117]_0\(59),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(29)
    );
\app_rd_data[54]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(19),
      I1 => \app_rd_data[117]_0\(19),
      I2 => my_empty_0(4),
      O => app_rd_data(30)
    );
\app_rd_data[55]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(51),
      I1 => \app_rd_data[117]_0\(51),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(31)
    );
\app_rd_data[5]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(56),
      I1 => \app_rd_data[117]_0\(56),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(5)
    );
\app_rd_data[64]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(12),
      I1 => \app_rd_data[117]_0\(12),
      I2 => my_empty_0(4),
      O => app_rd_data(32)
    );
\app_rd_data[65]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(36),
      I1 => \app_rd_data[117]_0\(36),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(33)
    );
\app_rd_data[66]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(4),
      I1 => \app_rd_data[117]_0\(4),
      I2 => my_empty_0(4),
      O => app_rd_data(34)
    );
\app_rd_data[67]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(28),
      I1 => \app_rd_data[117]_0\(28),
      I2 => my_empty_0(4),
      O => app_rd_data(35)
    );
\app_rd_data[68]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(44),
      I1 => \app_rd_data[117]_0\(44),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(36)
    );
\app_rd_data[69]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(60),
      I1 => \app_rd_data[117]_0\(60),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(37)
    );
\app_rd_data[6]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(16),
      I1 => \app_rd_data[117]_0\(16),
      I2 => my_empty_0(4),
      O => app_rd_data(6)
    );
\app_rd_data[70]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(20),
      I1 => \app_rd_data[117]_0\(20),
      I2 => my_empty_0(4),
      O => app_rd_data(38)
    );
\app_rd_data[71]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(52),
      I1 => \app_rd_data[117]_0\(52),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(39)
    );
\app_rd_data[7]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(48),
      I1 => \app_rd_data[117]_0\(48),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(7)
    );
\app_rd_data[80]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(13),
      I1 => \app_rd_data[117]_0\(13),
      I2 => my_empty_0(4),
      O => app_rd_data(40)
    );
\app_rd_data[81]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(37),
      I1 => \app_rd_data[117]_0\(37),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(41)
    );
\app_rd_data[82]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(5),
      I1 => \app_rd_data[117]_0\(5),
      I2 => my_empty_0(4),
      O => app_rd_data(42)
    );
\app_rd_data[83]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(29),
      I1 => \app_rd_data[117]_0\(29),
      I2 => my_empty_0(4),
      O => app_rd_data(43)
    );
\app_rd_data[84]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(45),
      I1 => \app_rd_data[117]_0\(45),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(44)
    );
\app_rd_data[85]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(61),
      I1 => \app_rd_data[117]_0\(61),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(45)
    );
\app_rd_data[86]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(21),
      I1 => \app_rd_data[117]_0\(21),
      I2 => my_empty_0(4),
      O => app_rd_data(46)
    );
\app_rd_data[87]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(53),
      I1 => \app_rd_data[117]_0\(53),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(47)
    );
\app_rd_data[96]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(14),
      I1 => \app_rd_data[117]_0\(14),
      I2 => my_empty_0(4),
      O => app_rd_data(48)
    );
\app_rd_data[97]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(38),
      I1 => \app_rd_data[117]_0\(38),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => app_rd_data(49)
    );
\app_rd_data[98]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(6),
      I1 => \app_rd_data[117]_0\(6),
      I2 => my_empty_0(4),
      O => app_rd_data(50)
    );
\app_rd_data[99]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \app_rd_data[117]\(30),
      I1 => \app_rd_data[117]_0\(30),
      I2 => my_empty_0(4),
      O => app_rd_data(51)
    );
app_rd_data_valid_INST_0: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000007770000"
    )
        port map (
      I0 => \^my_empty_reg[0]_0\,
      I1 => \my_empty_reg[4]_rep__1_0\,
      I2 => my_empty(0),
      I3 => if_empty_r_0(0),
      I4 => app_rd_data_valid_0,
      I5 => app_rd_data_valid_1(0),
      O => app_rd_data_valid
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(8),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(9),
      I4 => \app_rd_data[117]\(9),
      O => \po_stg2_wrcal_cnt_reg[0]_15\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(24),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(11),
      I4 => \app_rd_data[117]\(11),
      O => \po_stg2_wrcal_cnt_reg[0]_55\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(40),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(13),
      I4 => \app_rd_data[117]\(13),
      O => \po_stg2_wrcal_cnt_reg[0]_31\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(56),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(15),
      I4 => \app_rd_data[117]\(15),
      O => \po_stg2_wrcal_cnt_reg[0]_7\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(0),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(8),
      I4 => \app_rd_data[117]\(8),
      O => \po_stg2_wrcal_cnt_reg[0]_47\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(16),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep_n_0\,
      I3 => \app_rd_data[117]_0\(10),
      I4 => \app_rd_data[117]\(10),
      O => \po_stg2_wrcal_cnt_reg[0]\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(48),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(14),
      I4 => \app_rd_data[117]\(14),
      O => \po_stg2_wrcal_cnt_reg[0]_39\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(9),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(33),
      I4 => \app_rd_data[117]\(33),
      O => \po_stg2_wrcal_cnt_reg[0]_16\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(25),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(35),
      I4 => \app_rd_data[117]\(35),
      O => \po_stg2_wrcal_cnt_reg[0]_56\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(41),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(37),
      I4 => \app_rd_data[117]\(37),
      O => \po_stg2_wrcal_cnt_reg[0]_32\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(57),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(39),
      I4 => \app_rd_data[117]\(39),
      O => \po_stg2_wrcal_cnt_reg[0]_8\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(1),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(32),
      I4 => \app_rd_data[117]\(32),
      O => \po_stg2_wrcal_cnt_reg[0]_48\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(17),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(34),
      I4 => \app_rd_data[117]\(34),
      O => \po_stg2_wrcal_cnt_reg[0]_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(33),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(36),
      I4 => \app_rd_data[117]\(36),
      O => \po_stg2_wrcal_cnt_reg[0]_24\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(49),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(38),
      I4 => \app_rd_data[117]\(38),
      O => \po_stg2_wrcal_cnt_reg[0]_40\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(10),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(1),
      I4 => \app_rd_data[117]\(1),
      O => \po_stg2_wrcal_cnt_reg[0]_17\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(26),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(3),
      I4 => \app_rd_data[117]\(3),
      O => \po_stg2_wrcal_cnt_reg[0]_57\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(42),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(5),
      I4 => \app_rd_data[117]\(5),
      O => \po_stg2_wrcal_cnt_reg[0]_33\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(58),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(7),
      I4 => \app_rd_data[117]\(7),
      O => \po_stg2_wrcal_cnt_reg[0]_9\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(2),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(0),
      I4 => \app_rd_data[117]\(0),
      O => \po_stg2_wrcal_cnt_reg[0]_49\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(18),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(2),
      I4 => \app_rd_data[117]\(2),
      O => \po_stg2_wrcal_cnt_reg[0]_1\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(34),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(4),
      I4 => \app_rd_data[117]\(4),
      O => \po_stg2_wrcal_cnt_reg[0]_25\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(50),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(6),
      I4 => \app_rd_data[117]\(6),
      O => \po_stg2_wrcal_cnt_reg[0]_41\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(11),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(25),
      I4 => \app_rd_data[117]\(25),
      O => \po_stg2_wrcal_cnt_reg[0]_18\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(27),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(27),
      I4 => \app_rd_data[117]\(27),
      O => \po_stg2_wrcal_cnt_reg[0]_58\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(43),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(29),
      I4 => \app_rd_data[117]\(29),
      O => \po_stg2_wrcal_cnt_reg[0]_34\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(59),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(31),
      I4 => \app_rd_data[117]\(31),
      O => \po_stg2_wrcal_cnt_reg[0]_10\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(3),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(24),
      I4 => \app_rd_data[117]\(24),
      O => \po_stg2_wrcal_cnt_reg[0]_50\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(19),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(26),
      I4 => \app_rd_data[117]\(26),
      O => \po_stg2_wrcal_cnt_reg[0]_2\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(35),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(28),
      I4 => \app_rd_data[117]\(28),
      O => \po_stg2_wrcal_cnt_reg[0]_26\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(12),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(41),
      I4 => \app_rd_data[117]\(41),
      O => \po_stg2_wrcal_cnt_reg[0]_19\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(28),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(43),
      I4 => \app_rd_data[117]\(43),
      O => \po_stg2_wrcal_cnt_reg[0]_59\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(44),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(45),
      I4 => \app_rd_data[117]\(45),
      O => \po_stg2_wrcal_cnt_reg[0]_35\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(60),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(47),
      I4 => \app_rd_data[117]\(47),
      O => \po_stg2_wrcal_cnt_reg[0]_11\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(4),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(40),
      I4 => \app_rd_data[117]\(40),
      O => \po_stg2_wrcal_cnt_reg[0]_51\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(20),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(42),
      I4 => \app_rd_data[117]\(42),
      O => \po_stg2_wrcal_cnt_reg[0]_3\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(52),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(46),
      I4 => \app_rd_data[117]\(46),
      O => \po_stg2_wrcal_cnt_reg[0]_43\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(13),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(57),
      I4 => \app_rd_data[117]\(57),
      O => \po_stg2_wrcal_cnt_reg[0]_20\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(29),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(59),
      I4 => \app_rd_data[117]\(59),
      O => \po_stg2_wrcal_cnt_reg[0]_60\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(45),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(61),
      I4 => \app_rd_data[117]\(61),
      O => \po_stg2_wrcal_cnt_reg[0]_36\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(61),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(63),
      I4 => \app_rd_data[117]\(63),
      O => \po_stg2_wrcal_cnt_reg[0]_12\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(5),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(56),
      I4 => \app_rd_data[117]\(56),
      O => \po_stg2_wrcal_cnt_reg[0]_52\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(21),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(58),
      I4 => \app_rd_data[117]\(58),
      O => \po_stg2_wrcal_cnt_reg[0]_4\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(37),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(60),
      I4 => \app_rd_data[117]\(60),
      O => \po_stg2_wrcal_cnt_reg[0]_28\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(53),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(62),
      I4 => \app_rd_data[117]\(62),
      O => \po_stg2_wrcal_cnt_reg[0]_44\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(14),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(17),
      I4 => \app_rd_data[117]\(17),
      O => \po_stg2_wrcal_cnt_reg[0]_21\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(30),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(19),
      I4 => \app_rd_data[117]\(19),
      O => \po_stg2_wrcal_cnt_reg[0]_61\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(46),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(21),
      I4 => \app_rd_data[117]\(21),
      O => \po_stg2_wrcal_cnt_reg[0]_37\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(62),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(23),
      I4 => \app_rd_data[117]\(23),
      O => \po_stg2_wrcal_cnt_reg[0]_13\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(6),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(16),
      I4 => \app_rd_data[117]\(16),
      O => \po_stg2_wrcal_cnt_reg[0]_53\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(22),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(18),
      I4 => \app_rd_data[117]\(18),
      O => \po_stg2_wrcal_cnt_reg[0]_5\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(38),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(20),
      I4 => \app_rd_data[117]\(20),
      O => \po_stg2_wrcal_cnt_reg[0]_29\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(54),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(22),
      I4 => \app_rd_data[117]\(22),
      O => \po_stg2_wrcal_cnt_reg[0]_45\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(15),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(49),
      I4 => \app_rd_data[117]\(49),
      O => \po_stg2_wrcal_cnt_reg[0]_22\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(31),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(51),
      I4 => \app_rd_data[117]\(51),
      O => \po_stg2_wrcal_cnt_reg[0]_62\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(47),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(53),
      I4 => \app_rd_data[117]\(53),
      O => \po_stg2_wrcal_cnt_reg[0]_38\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(63),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(55),
      I4 => \app_rd_data[117]\(55),
      O => \po_stg2_wrcal_cnt_reg[0]_14\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(7),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(48),
      I4 => \app_rd_data[117]\(48),
      O => \po_stg2_wrcal_cnt_reg[0]_54\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(23),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(50),
      I4 => \app_rd_data[117]\(50),
      O => \po_stg2_wrcal_cnt_reg[0]_6\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(39),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(52),
      I4 => \app_rd_data[117]\(52),
      O => \po_stg2_wrcal_cnt_reg[0]_30\
    );
\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(32),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(12),
      I4 => \app_rd_data[117]\(12),
      O => \po_stg2_wrcal_cnt_reg[0]_23\
    );
\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(51),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(30),
      I4 => \app_rd_data[117]\(30),
      O => \po_stg2_wrcal_cnt_reg[0]_42\
    );
\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(36),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__0_n_0\,
      I3 => \app_rd_data[117]_0\(44),
      I4 => \app_rd_data[117]\(44),
      O => \po_stg2_wrcal_cnt_reg[0]_27\
    );
\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB88B88"
    )
        port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(55),
      I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      I2 => \my_empty_reg[4]_rep__1_n_0\,
      I3 => \app_rd_data[117]_0\(54),
      I4 => \app_rd_data[117]\(54),
      O => \po_stg2_wrcal_cnt_reg[0]_46\
    );
mem_reg_0_3_6_11_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000078F"
    )
        port map (
      I0 => if_empty_r_0(0),
      I1 => my_empty(1),
      I2 => my_empty_0(2),
      I3 => my_full(0),
      I4 => \my_empty_reg[4]_rep__1_0\,
      O => p_1_in
    );
\my_empty[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBAAAAAA88AAA"
    )
        port map (
      I0 => \^my_empty_reg[0]_0\,
      I1 => my_full(1),
      I2 => \my_empty_reg[4]_rep__1_0\,
      I3 => \wr_ptr[1]_i_2__0_n_0\,
      I4 => my_empty_0(1),
      I5 => \my_empty[4]_i_2_n_0\,
      O => \my_empty[0]_i_1__0_n_0\
    );
\my_empty[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00411400"
    )
        port map (
      I0 => \my_empty[1]_i_2__0_n_0\,
      I1 => \^wr_ptr_reg[1]_0\,
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => \^wr_ptr_reg[0]_0\,
      I5 => my_empty_0(1),
      O => \my_empty[1]_i_1__0_n_0\
    );
\my_empty[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFFFBFFFFFEAFF"
    )
        port map (
      I0 => my_full(1),
      I1 => if_empty_r_0(0),
      I2 => my_empty(1),
      I3 => \my_empty_reg[4]_rep__1_0\,
      I4 => \^my_empty_reg[3]_0\,
      I5 => my_empty_0(1),
      O => \my_empty[1]_i_2__0_n_0\
    );
\my_empty[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBAAAAAA88AAA"
    )
        port map (
      I0 => my_empty_0(2),
      I1 => my_full(1),
      I2 => \my_empty_reg[4]_rep__1_0\,
      I3 => \wr_ptr[1]_i_2__0_n_0\,
      I4 => my_empty_0(1),
      I5 => \my_empty[4]_i_2_n_0\,
      O => \my_empty[2]_i_1__0_n_0\
    );
\my_empty[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBAAAAAA88AAA"
    )
        port map (
      I0 => \^my_empty_reg[3]_0\,
      I1 => my_full(1),
      I2 => \my_empty_reg[4]_rep__1_0\,
      I3 => \wr_ptr[1]_i_2__0_n_0\,
      I4 => my_empty_0(1),
      I5 => \my_empty[4]_i_2_n_0\,
      O => \my_empty[3]_i_1__0_n_0\
    );
\my_empty[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBAAAAAA88AAA"
    )
        port map (
      I0 => my_empty_0(4),
      I1 => my_full(1),
      I2 => \my_empty_reg[4]_rep__1_0\,
      I3 => \wr_ptr[1]_i_2__0_n_0\,
      I4 => my_empty_0(1),
      I5 => \my_empty[4]_i_2_n_0\,
      O => \my_empty[4]_i_1__0_n_0\
    );
\my_empty[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000960"
    )
        port map (
      I0 => \^wr_ptr_reg[1]_0\,
      I1 => rd_ptr(1),
      I2 => rd_ptr(0),
      I3 => \^wr_ptr_reg[0]_0\,
      I4 => my_empty_0(1),
      O => \my_empty[4]_i_2_n_0\
    );
\my_empty_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__0_n_0\,
      D => \my_empty[0]_i_1__0_n_0\,
      Q => \^my_empty_reg[0]_0\,
      S => ififo_rst
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__0_n_0\,
      D => \my_empty[1]_i_1__0_n_0\,
      Q => my_empty_0(1),
      S => ififo_rst
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__0_n_0\,
      D => \my_empty[2]_i_1__0_n_0\,
      Q => my_empty_0(2),
      S => ififo_rst
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__0_n_0\,
      D => \my_empty[3]_i_1__0_n_0\,
      Q => \^my_empty_reg[3]_0\,
      S => ififo_rst
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__0_n_0\,
      D => \my_empty[4]_i_1__0_n_0\,
      Q => my_empty_0(4),
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__0_n_0\,
      D => \my_empty[4]_i_1__0_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep__0\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__0_n_0\,
      D => \my_empty[4]_i_1__0_n_0\,
      Q => \my_empty_reg[4]_rep__0_n_0\,
      S => ififo_rst
    );
\my_empty_reg[4]_rep__1\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__0_n_0\,
      D => \my_empty[4]_i_1__0_n_0\,
      Q => \my_empty_reg[4]_rep__1_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAB8AAAAAA8"
    )
        port map (
      I0 => my_full(0),
      I1 => my_empty_0(1),
      I2 => my_full(1),
      I3 => \my_empty_reg[4]_rep__1_0\,
      I4 => \wr_ptr[1]_i_2__0_n_0\,
      I5 => \my_full[0]_i_2_n_0\,
      O => \my_full[0]_i_1__0_n_0\
    );
\my_full[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000960"
    )
        port map (
      I0 => rd_ptr(1),
      I1 => \^wr_ptr_reg[1]_0\,
      I2 => \^wr_ptr_reg[0]_0\,
      I3 => rd_ptr(0),
      I4 => my_full(1),
      O => \my_full[0]_i_2_n_0\
    );
\my_full[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAFFFF"
    )
        port map (
      I0 => my_full(1),
      I1 => if_empty_r_0(0),
      I2 => my_empty(1),
      I3 => \my_empty_reg[4]_rep__1_0\,
      I4 => my_empty_0(1),
      O => \my_full[1]_i_1__0_n_0\
    );
\my_full[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00411400"
    )
        port map (
      I0 => \my_full[1]_i_3__0_n_0\,
      I1 => rd_ptr(1),
      I2 => \^wr_ptr_reg[1]_0\,
      I3 => \^wr_ptr_reg[0]_0\,
      I4 => rd_ptr(0),
      I5 => my_full(1),
      O => \my_full[1]_i_2__0_n_0\
    );
\my_full[1]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFFFEBFBFBF"
    )
        port map (
      I0 => my_empty_0(1),
      I1 => my_full(1),
      I2 => \my_empty_reg[4]_rep__1_0\,
      I3 => if_empty_r_0(0),
      I4 => my_empty(1),
      I5 => \^my_empty_reg[3]_0\,
      O => \my_full[1]_i_3__0_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__0_n_0\,
      D => \my_full[0]_i_1__0_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__0_n_0\,
      D => \my_full[1]_i_2__0_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
\rd_ptr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => my_empty_0(1),
      I1 => \wr_ptr[1]_i_2__0_n_0\,
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1_n_0\
    );
\rd_ptr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => \wr_ptr[1]_i_2__0_n_0\,
      I2 => my_empty_0(1),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[0]_i_1_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[1]_i_1_n_0\,
      Q => rd_ptr(1),
      R => ififo_rst
    );
\rd_ptr_timing[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EF0F0000FFFF10F0"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__1_0\,
      I1 => my_full(1),
      I2 => \wr_ptr[1]_i_2__0_n_0\,
      I3 => my_empty_0(1),
      I4 => rd_ptr_timing(0),
      I5 => rd_ptr(0),
      O => \rd_ptr_timing[0]_i_1__1_n_0\
    );
\rd_ptr_timing[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF10F0EF0F0000"
    )
        port map (
      I0 => \my_empty_reg[4]_rep__1_0\,
      I1 => my_full(1),
      I2 => \wr_ptr[1]_i_2__0_n_0\,
      I3 => my_empty_0(1),
      I4 => rd_ptr_timing(1),
      I5 => my_empty1(1),
      O => \rd_ptr_timing[1]_i_1__1_n_0\
    );
\rd_ptr_timing[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => my_empty1(1)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__0_n_0\,
      D => \rd_ptr_timing[0]_i_1__1_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__0_n_0\,
      D => \rd_ptr_timing[1]_i_1__1_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\read_fifo.fifo_ram[1].RAM32M0_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777000000000000"
    )
        port map (
      I0 => \^my_empty_reg[0]_0\,
      I1 => \my_empty_reg[4]_rep__1_0\,
      I2 => my_empty(0),
      I3 => if_empty_r_0(0),
      I4 => app_rd_data_valid_0,
      I5 => \read_fifo.tail_r_reg[4]\(0),
      O => \my_empty_reg[0]_1\
    );
\wr_ptr[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEC1013"
    )
        port map (
      I0 => my_empty_0(1),
      I1 => \my_empty_reg[4]_rep__1_0\,
      I2 => \wr_ptr[1]_i_2__0_n_0\,
      I3 => my_full(1),
      I4 => \^wr_ptr_reg[0]_0\,
      O => \wr_ptr[0]_i_1__0_n_0\
    );
\wr_ptr[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDFF5D000200A2"
    )
        port map (
      I0 => \^wr_ptr_reg[0]_0\,
      I1 => my_full(1),
      I2 => \wr_ptr[1]_i_2__0_n_0\,
      I3 => \my_empty_reg[4]_rep__1_0\,
      I4 => my_empty_0(1),
      I5 => \^wr_ptr_reg[1]_0\,
      O => \wr_ptr[1]_i_1__0_n_0\
    );
\wr_ptr[1]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \^my_empty_reg[3]_0\,
      I1 => \my_empty_reg[4]_rep__1_0\,
      I2 => my_empty(1),
      I3 => if_empty_r_0(0),
      O => \wr_ptr[1]_i_2__0_n_0\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[0]_i_1__0_n_0\,
      Q => \^wr_ptr_reg[0]_0\,
      R => ififo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[1]_i_1__0_n_0\,
      Q => \^wr_ptr_reg[1]_0\,
      R => ififo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo is
  port (
    \my_empty_reg[5]_0\ : out STD_LOGIC;
    \my_empty_reg[3]_0\ : out STD_LOGIC;
    UNCONN_IN : in STD_LOGIC;
    mux_cmd_wren : in STD_LOGIC;
    \my_full_reg[0]_0\ : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo is
  signal \my_empty0__0_n_0\ : STD_LOGIC;
  signal \my_empty0__1_n_0\ : STD_LOGIC;
  signal \my_empty0__2_n_0\ : STD_LOGIC;
  signal \my_empty0__3_n_0\ : STD_LOGIC;
  signal \my_empty0__4_n_0\ : STD_LOGIC;
  signal my_empty0_n_0 : STD_LOGIC;
  signal \my_empty[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[5]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[8]_i_1_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[3]_0\ : STD_LOGIC;
  signal \^my_empty_reg[5]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[4]\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[6]\ : STD_LOGIC;
  signal \my_full[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full[5]_i_1_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[0]\ : STD_LOGIC;
  signal \my_full_reg_n_0_[3]\ : STD_LOGIC;
  signal \my_full_reg_n_0_[5]\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_3_in : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rd_ptr0 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rd_ptr[2]_i_1_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rd_ptr_timing : signal is "50";
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rd_ptr_timing : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal wr_ptr0 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute syn_maxfan of \my_empty_reg[2]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[3]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[4]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[5]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[6]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[8]\ : label is "3";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_full[0]_i_1__1\ : label is "soft_lutpair371";
  attribute SOFT_HLUTNM of \my_full[3]_i_1__0\ : label is "soft_lutpair371";
  attribute syn_maxfan of \my_full_reg[0]\ : label is "3";
  attribute syn_maxfan of \my_full_reg[3]\ : label is "3";
  attribute syn_maxfan of \my_full_reg[5]\ : label is "3";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1\ : label is "soft_lutpair372";
  attribute SOFT_HLUTNM of \rd_ptr[2]_i_2\ : label is "soft_lutpair372";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[2]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1\ : label is "soft_lutpair373";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_2\ : label is "soft_lutpair373";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
begin
  \my_empty_reg[3]_0\ <= \^my_empty_reg[3]_0\;
  \my_empty_reg[5]_0\ <= \^my_empty_reg[5]_0\;
my_empty0: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => my_empty0_n_0
    );
\my_empty0__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__0_n_0\
    );
\my_empty0__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__1_n_0\
    );
\my_empty0__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__2_n_0\
    );
\my_empty0__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__3_n_0\
    );
\my_empty0__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__4_n_0\
    );
\my_empty[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F1F0"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => p_1_in,
      I3 => \my_empty0__0_n_0\,
      O => \my_empty[2]_i_1__1_n_0\
    );
\my_empty[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0100"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => p_1_in,
      I3 => \my_empty0__1_n_0\,
      I4 => \^my_empty_reg[3]_0\,
      O => \my_empty[3]_i_1__1_n_0\
    );
\my_empty[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0100"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => p_3_in,
      I2 => \my_full_reg_n_0_[5]\,
      I3 => \my_empty0__2_n_0\,
      I4 => \my_empty_reg_n_0_[4]\,
      O => \my_empty[4]_i_1__1_n_0\
    );
\my_empty[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0100"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => p_3_in,
      I2 => \my_full_reg_n_0_[5]\,
      I3 => \my_empty0__3_n_0\,
      I4 => \^my_empty_reg[5]_0\,
      O => \my_empty[5]_i_1_n_0\
    );
\my_empty[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0100"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => p_3_in,
      I2 => \my_full_reg_n_0_[5]\,
      I3 => \my_empty0__4_n_0\,
      I4 => \my_empty_reg_n_0_[6]\,
      O => \my_empty[6]_i_1_n_0\
    );
\my_empty[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDCC"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => p_3_in,
      I2 => \my_full_reg_n_0_[5]\,
      I3 => my_empty0_n_0,
      O => \my_empty[8]_i_1_n_0\
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[2]_i_1__1_n_0\,
      Q => p_1_in,
      S => \wr_ptr_timing_reg[0]_0\(0)
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[3]_i_1__1_n_0\,
      Q => \^my_empty_reg[3]_0\,
      S => \wr_ptr_timing_reg[0]_0\(0)
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[4]_i_1__1_n_0\,
      Q => \my_empty_reg_n_0_[4]\,
      S => \wr_ptr_timing_reg[0]_0\(0)
    );
\my_empty_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[5]_i_1_n_0\,
      Q => \^my_empty_reg[5]_0\,
      S => \wr_ptr_timing_reg[0]_0\(0)
    );
\my_empty_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[6]_i_1_n_0\,
      Q => \my_empty_reg_n_0_[6]\,
      S => \wr_ptr_timing_reg[0]_0\(0)
    );
\my_empty_reg[8]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[8]_i_1_n_0\,
      Q => p_3_in,
      S => \wr_ptr_timing_reg[0]_0\(0)
    );
\my_full[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[0]\,
      I2 => \my_empty_reg_n_0_[6]\,
      I3 => \my_full_reg[0]_0\,
      O => \my_full[0]_i_1__1_n_0\
    );
\my_full[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000C8CC"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => \my_empty_reg_n_0_[6]\,
      I3 => \my_full_reg_n_0_[0]\,
      I4 => \my_full_reg[0]_0\,
      O => \my_full[3]_i_1__0_n_0\
    );
\my_full[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000C8CC"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[5]\,
      I2 => \my_empty_reg_n_0_[6]\,
      I3 => \my_full_reg_n_0_[0]\,
      I4 => \my_full_reg[0]_0\,
      O => \my_full[5]_i_1_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[0]_i_1__1_n_0\,
      Q => \my_full_reg_n_0_[0]\,
      R => '0'
    );
\my_full_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[3]_i_1__0_n_0\,
      Q => \my_full_reg_n_0_[3]\,
      R => '0'
    );
\my_full_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[5]_i_1_n_0\,
      Q => \my_full_reg_n_0_[5]\,
      R => '0'
    );
\rd_ptr[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rd_ptr(0),
      O => rd_ptr0(0)
    );
\rd_ptr[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => rd_ptr0(1)
    );
\rd_ptr[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[4]\,
      O => \rd_ptr[2]_i_1_n_0\
    );
\rd_ptr[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      I2 => rd_ptr(2),
      O => rd_ptr0(2)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1_n_0\,
      D => rd_ptr0(0),
      Q => rd_ptr(0),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1_n_0\,
      D => rd_ptr0(1),
      Q => rd_ptr(1),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1_n_0\,
      D => rd_ptr0(2),
      Q => rd_ptr(2),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1_n_0\,
      D => rd_ptr0(0),
      Q => rd_ptr_timing(0),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1_n_0\,
      D => rd_ptr0(1),
      Q => rd_ptr_timing(1),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1_n_0\,
      D => rd_ptr0(2),
      Q => rd_ptr_timing(2),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wr_ptr(0),
      O => wr_ptr0(0)
    );
\wr_ptr[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => wr_ptr(1),
      O => wr_ptr0(1)
    );
\wr_ptr[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => wr_ptr(1),
      I2 => wr_ptr(2),
      O => wr_ptr0(2)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => wr_ptr0(0),
      Q => wr_ptr(0),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => wr_ptr0(1),
      Q => wr_ptr(1),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => wr_ptr0(2),
      Q => wr_ptr(2),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => wr_ptr0(0),
      Q => wr_ptr_timing(0),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => wr_ptr0(1),
      Q => wr_ptr_timing(1),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => wr_ptr0(2),
      Q => wr_ptr_timing(2),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\ is
  port (
    \my_empty_reg[5]_0\ : out STD_LOGIC;
    \my_empty_reg[3]_0\ : out STD_LOGIC;
    UNCONN_IN : in STD_LOGIC;
    mux_cmd_wren : in STD_LOGIC;
    \my_full_reg[0]_0\ : in STD_LOGIC;
    \rd_ptr_timing_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[8]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\ is
  signal \my_empty0__0_n_0\ : STD_LOGIC;
  signal \my_empty0__1_n_0\ : STD_LOGIC;
  signal \my_empty0__2_n_0\ : STD_LOGIC;
  signal \my_empty0__3_n_0\ : STD_LOGIC;
  signal \my_empty0__4_n_0\ : STD_LOGIC;
  signal my_empty0_n_0 : STD_LOGIC;
  signal \my_empty[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[3]_0\ : STD_LOGIC;
  signal \^my_empty_reg[5]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[4]\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[6]\ : STD_LOGIC;
  signal \my_full[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_full[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[0]\ : STD_LOGIC;
  signal \my_full_reg_n_0_[3]\ : STD_LOGIC;
  signal \my_full_reg_n_0_[5]\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_3_in : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rd_ptr0 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rd_ptr[2]_i_1__0_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rd_ptr_timing : signal is "50";
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rd_ptr_timing : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal wr_ptr0 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute syn_maxfan of \my_empty_reg[2]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[3]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[4]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[5]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[6]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[8]\ : label is "3";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_full[0]_i_1__2\ : label is "soft_lutpair374";
  attribute SOFT_HLUTNM of \my_full[3]_i_1__1\ : label is "soft_lutpair374";
  attribute syn_maxfan of \my_full_reg[0]\ : label is "3";
  attribute syn_maxfan of \my_full_reg[3]\ : label is "3";
  attribute syn_maxfan of \my_full_reg[5]\ : label is "3";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1\ : label is "soft_lutpair375";
  attribute SOFT_HLUTNM of \rd_ptr[2]_i_2\ : label is "soft_lutpair375";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[2]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1\ : label is "soft_lutpair376";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_2\ : label is "soft_lutpair376";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
begin
  \my_empty_reg[3]_0\ <= \^my_empty_reg[3]_0\;
  \my_empty_reg[5]_0\ <= \^my_empty_reg[5]_0\;
my_empty0: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => my_empty0_n_0
    );
\my_empty0__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__0_n_0\
    );
\my_empty0__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__1_n_0\
    );
\my_empty0__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__2_n_0\
    );
\my_empty0__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__3_n_0\
    );
\my_empty0__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__4_n_0\
    );
\my_empty[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F1F0"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => p_1_in,
      I3 => \my_empty0__0_n_0\,
      O => \my_empty[2]_i_1__2_n_0\
    );
\my_empty[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0100"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => p_1_in,
      I3 => \my_empty0__1_n_0\,
      I4 => \^my_empty_reg[3]_0\,
      O => \my_empty[3]_i_1__2_n_0\
    );
\my_empty[4]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0100"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => p_3_in,
      I2 => \my_full_reg_n_0_[5]\,
      I3 => \my_empty0__2_n_0\,
      I4 => \my_empty_reg_n_0_[4]\,
      O => \my_empty[4]_i_1__2_n_0\
    );
\my_empty[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0100"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => p_3_in,
      I2 => \my_full_reg_n_0_[5]\,
      I3 => \my_empty0__3_n_0\,
      I4 => \^my_empty_reg[5]_0\,
      O => \my_empty[5]_i_1__0_n_0\
    );
\my_empty[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0100"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => p_3_in,
      I2 => \my_full_reg_n_0_[5]\,
      I3 => \my_empty0__4_n_0\,
      I4 => \my_empty_reg_n_0_[6]\,
      O => \my_empty[6]_i_1__0_n_0\
    );
\my_empty[8]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDCC"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => p_3_in,
      I2 => \my_full_reg_n_0_[5]\,
      I3 => my_empty0_n_0,
      O => \my_empty[8]_i_1__0_n_0\
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[2]_i_1__2_n_0\,
      Q => p_1_in,
      S => \my_empty_reg[8]_0\
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[3]_i_1__2_n_0\,
      Q => \^my_empty_reg[3]_0\,
      S => \my_empty_reg[8]_0\
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[4]_i_1__2_n_0\,
      Q => \my_empty_reg_n_0_[4]\,
      S => \my_empty_reg[8]_0\
    );
\my_empty_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[5]_i_1__0_n_0\,
      Q => \^my_empty_reg[5]_0\,
      S => \my_empty_reg[8]_0\
    );
\my_empty_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[6]_i_1__0_n_0\,
      Q => \my_empty_reg_n_0_[6]\,
      S => \my_empty_reg[8]_0\
    );
\my_empty_reg[8]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[8]_i_1__0_n_0\,
      Q => p_3_in,
      S => \my_empty_reg[8]_0\
    );
\my_full[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[0]\,
      I2 => \my_empty_reg_n_0_[6]\,
      I3 => \my_full_reg[0]_0\,
      O => \my_full[0]_i_1__2_n_0\
    );
\my_full[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000C8CC"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => \my_empty_reg_n_0_[6]\,
      I3 => \my_full_reg_n_0_[0]\,
      I4 => \my_full_reg[0]_0\,
      O => \my_full[3]_i_1__1_n_0\
    );
\my_full[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000C8CC"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[5]\,
      I2 => \my_empty_reg_n_0_[6]\,
      I3 => \my_full_reg_n_0_[0]\,
      I4 => \my_full_reg[0]_0\,
      O => \my_full[5]_i_1__0_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[0]_i_1__2_n_0\,
      Q => \my_full_reg_n_0_[0]\,
      R => '0'
    );
\my_full_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[3]_i_1__1_n_0\,
      Q => \my_full_reg_n_0_[3]\,
      R => '0'
    );
\my_full_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[5]_i_1__0_n_0\,
      Q => \my_full_reg_n_0_[5]\,
      R => '0'
    );
\rd_ptr[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rd_ptr(0),
      O => rd_ptr0(0)
    );
\rd_ptr[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => rd_ptr0(1)
    );
\rd_ptr[2]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[4]\,
      O => \rd_ptr[2]_i_1__0_n_0\
    );
\rd_ptr[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      I2 => rd_ptr(2),
      O => rd_ptr0(2)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1__0_n_0\,
      D => rd_ptr0(0),
      Q => rd_ptr(0),
      R => \rd_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1__0_n_0\,
      D => rd_ptr0(1),
      Q => rd_ptr(1),
      R => \rd_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1__0_n_0\,
      D => rd_ptr0(2),
      Q => rd_ptr(2),
      R => \rd_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1__0_n_0\,
      D => rd_ptr0(0),
      Q => rd_ptr_timing(0),
      R => \rd_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1__0_n_0\,
      D => rd_ptr0(1),
      Q => rd_ptr_timing(1),
      R => \rd_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1__0_n_0\,
      D => rd_ptr0(2),
      Q => rd_ptr_timing(2),
      R => \rd_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wr_ptr(0),
      O => wr_ptr0(0)
    );
\wr_ptr[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => wr_ptr(1),
      O => wr_ptr0(1)
    );
\wr_ptr[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => wr_ptr(1),
      I2 => wr_ptr(2),
      O => wr_ptr0(2)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr_timing_reg[0]_0\(0),
      D => wr_ptr0(0),
      Q => wr_ptr(0),
      R => \rd_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr_timing_reg[0]_0\(0),
      D => wr_ptr0(1),
      Q => wr_ptr(1),
      R => \rd_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr_timing_reg[0]_0\(0),
      D => wr_ptr0(2),
      Q => wr_ptr(2),
      R => \rd_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr_timing_reg[0]_0\(0),
      D => wr_ptr0(0),
      Q => wr_ptr_timing(0),
      R => \my_empty_reg[8]_0\
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr_timing_reg[0]_0\(0),
      D => wr_ptr0(1),
      Q => wr_ptr_timing(1),
      R => \my_empty_reg[8]_0\
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr_timing_reg[0]_0\(0),
      D => wr_ptr0(2),
      Q => wr_ptr_timing(2),
      R => \my_empty_reg[8]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_6\ is
  port (
    \my_empty_reg[5]_0\ : out STD_LOGIC;
    \my_empty_reg[3]_0\ : out STD_LOGIC;
    UNCONN_IN : in STD_LOGIC;
    mux_cmd_wren : in STD_LOGIC;
    \my_full_reg[0]_0\ : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_timing_reg[2]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_6\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_6\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_6\ is
  signal \my_empty0__0_n_0\ : STD_LOGIC;
  signal \my_empty0__1_n_0\ : STD_LOGIC;
  signal \my_empty0__2_n_0\ : STD_LOGIC;
  signal \my_empty0__3_n_0\ : STD_LOGIC;
  signal \my_empty0__4_n_0\ : STD_LOGIC;
  signal my_empty0_n_0 : STD_LOGIC;
  signal \my_empty[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[3]_0\ : STD_LOGIC;
  signal \^my_empty_reg[5]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[4]\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[6]\ : STD_LOGIC;
  signal \my_full[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_full[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[0]\ : STD_LOGIC;
  signal \my_full_reg_n_0_[3]\ : STD_LOGIC;
  signal \my_full_reg_n_0_[5]\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_3_in : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rd_ptr0 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rd_ptr[2]_i_1__1_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rd_ptr_timing : signal is "50";
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rd_ptr_timing : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal wr_ptr0 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute syn_maxfan of \my_empty_reg[2]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[3]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[4]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[5]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[6]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[8]\ : label is "3";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_full[0]_i_1__3\ : label is "soft_lutpair377";
  attribute SOFT_HLUTNM of \my_full[3]_i_1__2\ : label is "soft_lutpair377";
  attribute syn_maxfan of \my_full_reg[0]\ : label is "3";
  attribute syn_maxfan of \my_full_reg[3]\ : label is "3";
  attribute syn_maxfan of \my_full_reg[5]\ : label is "3";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1\ : label is "soft_lutpair378";
  attribute SOFT_HLUTNM of \rd_ptr[2]_i_2\ : label is "soft_lutpair378";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[2]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1\ : label is "soft_lutpair379";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_2\ : label is "soft_lutpair379";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
begin
  \my_empty_reg[3]_0\ <= \^my_empty_reg[3]_0\;
  \my_empty_reg[5]_0\ <= \^my_empty_reg[5]_0\;
my_empty0: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => my_empty0_n_0
    );
\my_empty0__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__0_n_0\
    );
\my_empty0__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__1_n_0\
    );
\my_empty0__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__2_n_0\
    );
\my_empty0__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__3_n_0\
    );
\my_empty0__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041820014000082"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(2),
      I2 => rd_ptr(2),
      I3 => rd_ptr(1),
      I4 => rd_ptr(0),
      I5 => wr_ptr_timing(1),
      O => \my_empty0__4_n_0\
    );
\my_empty[2]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F1F0"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => p_1_in,
      I3 => \my_empty0__0_n_0\,
      O => \my_empty[2]_i_1__3_n_0\
    );
\my_empty[3]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0100"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => p_1_in,
      I3 => \my_empty0__1_n_0\,
      I4 => \^my_empty_reg[3]_0\,
      O => \my_empty[3]_i_1__3_n_0\
    );
\my_empty[4]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0100"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => p_3_in,
      I2 => \my_full_reg_n_0_[5]\,
      I3 => \my_empty0__2_n_0\,
      I4 => \my_empty_reg_n_0_[4]\,
      O => \my_empty[4]_i_1__3_n_0\
    );
\my_empty[5]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0100"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => p_3_in,
      I2 => \my_full_reg_n_0_[5]\,
      I3 => \my_empty0__3_n_0\,
      I4 => \^my_empty_reg[5]_0\,
      O => \my_empty[5]_i_1__1_n_0\
    );
\my_empty[6]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0100"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => p_3_in,
      I2 => \my_full_reg_n_0_[5]\,
      I3 => \my_empty0__4_n_0\,
      I4 => \my_empty_reg_n_0_[6]\,
      O => \my_empty[6]_i_1__1_n_0\
    );
\my_empty[8]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDCC"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => p_3_in,
      I2 => \my_full_reg_n_0_[5]\,
      I3 => my_empty0_n_0,
      O => \my_empty[8]_i_1__1_n_0\
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[2]_i_1__3_n_0\,
      Q => p_1_in,
      S => \wr_ptr_timing_reg[0]_0\(0)
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[3]_i_1__3_n_0\,
      Q => \^my_empty_reg[3]_0\,
      S => \wr_ptr_timing_reg[0]_0\(0)
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[4]_i_1__3_n_0\,
      Q => \my_empty_reg_n_0_[4]\,
      S => \wr_ptr_timing_reg[0]_0\(0)
    );
\my_empty_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[5]_i_1__1_n_0\,
      Q => \^my_empty_reg[5]_0\,
      S => \wr_ptr_timing_reg[0]_0\(0)
    );
\my_empty_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[6]_i_1__1_n_0\,
      Q => \my_empty_reg_n_0_[6]\,
      S => \wr_ptr_timing_reg[0]_0\(0)
    );
\my_empty_reg[8]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[8]_i_1__1_n_0\,
      Q => p_3_in,
      S => \wr_ptr_timing_reg[0]_0\(0)
    );
\my_full[0]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[0]\,
      I2 => \my_empty_reg_n_0_[6]\,
      I3 => \my_full_reg[0]_0\,
      O => \my_full[0]_i_1__3_n_0\
    );
\my_full[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000C8CC"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => \my_empty_reg_n_0_[6]\,
      I3 => \my_full_reg_n_0_[0]\,
      I4 => \my_full_reg[0]_0\,
      O => \my_full[3]_i_1__2_n_0\
    );
\my_full[5]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000C8CC"
    )
        port map (
      I0 => mux_cmd_wren,
      I1 => \my_full_reg_n_0_[5]\,
      I2 => \my_empty_reg_n_0_[6]\,
      I3 => \my_full_reg_n_0_[0]\,
      I4 => \my_full_reg[0]_0\,
      O => \my_full[5]_i_1__1_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[0]_i_1__3_n_0\,
      Q => \my_full_reg_n_0_[0]\,
      R => '0'
    );
\my_full_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[3]_i_1__2_n_0\,
      Q => \my_full_reg_n_0_[3]\,
      R => '0'
    );
\my_full_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[5]_i_1__1_n_0\,
      Q => \my_full_reg_n_0_[5]\,
      R => '0'
    );
\rd_ptr[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rd_ptr(0),
      O => rd_ptr0(0)
    );
\rd_ptr[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => rd_ptr0(1)
    );
\rd_ptr[2]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[4]\,
      O => \rd_ptr[2]_i_1__1_n_0\
    );
\rd_ptr[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      I2 => rd_ptr(2),
      O => rd_ptr0(2)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1__1_n_0\,
      D => rd_ptr0(0),
      Q => rd_ptr(0),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1__1_n_0\,
      D => rd_ptr0(1),
      Q => rd_ptr(1),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1__1_n_0\,
      D => rd_ptr0(2),
      Q => rd_ptr(2),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1__1_n_0\,
      D => rd_ptr0(0),
      Q => rd_ptr_timing(0),
      R => \rd_ptr_timing_reg[2]_0\
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1__1_n_0\,
      D => rd_ptr0(1),
      Q => rd_ptr_timing(1),
      R => \rd_ptr_timing_reg[2]_0\
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr[2]_i_1__1_n_0\,
      D => rd_ptr0(2),
      Q => rd_ptr_timing(2),
      R => \rd_ptr_timing_reg[2]_0\
    );
\wr_ptr[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wr_ptr(0),
      O => wr_ptr0(0)
    );
\wr_ptr[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => wr_ptr(1),
      O => wr_ptr0(1)
    );
\wr_ptr[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => wr_ptr(1),
      I2 => wr_ptr(2),
      O => wr_ptr0(2)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr_timing_reg[0]_1\(0),
      D => wr_ptr0(0),
      Q => wr_ptr(0),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr_timing_reg[0]_1\(0),
      D => wr_ptr0(1),
      Q => wr_ptr(1),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr_timing_reg[0]_1\(0),
      D => wr_ptr0(2),
      Q => wr_ptr(2),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr_timing_reg[0]_1\(0),
      D => wr_ptr0(0),
      Q => wr_ptr_timing(0),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr_timing_reg[0]_1\(0),
      D => wr_ptr0(1),
      Q => wr_ptr_timing(1),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr_timing_reg[0]_1\(0),
      D => wr_ptr0(2),
      Q => wr_ptr_timing(2),
      R => \wr_ptr_timing_reg[0]_0\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    D6 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 6 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_out : out STD_LOGIC_VECTOR ( 30 downto 0 );
    ofifo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    calib_cmd_wren : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC;
    \rd_ptr_reg[3]_0\ : in STD_LOGIC;
    out_fifo : in STD_LOGIC_VECTOR ( 1 downto 0 );
    out_fifo_0 : in STD_LOGIC;
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mux_cmd_wren : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\ is
  signal mem_out_0 : STD_LOGIC_VECTOR ( 77 downto 2 );
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_5_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_ptr0__0\ : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of mem_reg_0_15_12_17 : label is 720;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of mem_reg_0_15_12_17 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of mem_reg_0_15_12_17 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of mem_reg_0_15_12_17 : label is 8;
  attribute ram_offset : integer;
  attribute ram_offset of mem_reg_0_15_12_17 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of mem_reg_0_15_12_17 : label is 12;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of mem_reg_0_15_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_18_23 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_18_23 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_18_23 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_18_23 : label is 8;
  attribute ram_offset of mem_reg_0_15_18_23 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_18_23 : label is 18;
  attribute ram_slice_end of mem_reg_0_15_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_24_29 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_24_29 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_24_29 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_24_29 : label is 8;
  attribute ram_offset of mem_reg_0_15_24_29 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_24_29 : label is 24;
  attribute ram_slice_end of mem_reg_0_15_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8;
  attribute ram_offset of mem_reg_0_15_30_35 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30;
  attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8;
  attribute ram_offset of mem_reg_0_15_36_41 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36;
  attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8;
  attribute ram_offset of mem_reg_0_15_42_47 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42;
  attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8;
  attribute ram_offset of mem_reg_0_15_48_53 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48;
  attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8;
  attribute ram_offset of mem_reg_0_15_54_59 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54;
  attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_60_65 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_60_65 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_60_65 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_60_65 : label is 8;
  attribute ram_offset of mem_reg_0_15_60_65 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_60_65 : label is 60;
  attribute ram_slice_end of mem_reg_0_15_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_66_71 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_66_71 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_66_71 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_66_71 : label is 8;
  attribute ram_offset of mem_reg_0_15_66_71 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_66_71 : label is 66;
  attribute ram_slice_end of mem_reg_0_15_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8;
  attribute ram_offset of mem_reg_0_15_6_11 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6;
  attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute RTL_RAM_BITS of mem_reg_0_15_72_77 : label is 720;
  attribute RTL_RAM_NAME of mem_reg_0_15_72_77 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of mem_reg_0_15_72_77 : label is 0;
  attribute ram_addr_end of mem_reg_0_15_72_77 : label is 8;
  attribute ram_offset of mem_reg_0_15_72_77 : label is 0;
  attribute ram_slice_begin of mem_reg_0_15_72_77 : label is 72;
  attribute ram_slice_end of mem_reg_0_15_72_77 : label is 77;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[7]_i_4\ : label is "soft_lutpair497";
  attribute SOFT_HLUTNM of \my_empty[7]_i_5\ : label is "soft_lutpair497";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3\ : label is "soft_lutpair498";
  attribute SOFT_HLUTNM of \my_full[4]_i_4\ : label is "soft_lutpair498";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of out_fifo_i_1 : label is "soft_lutpair505";
  attribute SOFT_HLUTNM of \out_fifo_i_10__1\ : label is "soft_lutpair514";
  attribute SOFT_HLUTNM of \out_fifo_i_11__1\ : label is "soft_lutpair504";
  attribute SOFT_HLUTNM of \out_fifo_i_12__1\ : label is "soft_lutpair510";
  attribute SOFT_HLUTNM of \out_fifo_i_13__1\ : label is "soft_lutpair511";
  attribute SOFT_HLUTNM of \out_fifo_i_14__1\ : label is "soft_lutpair519";
  attribute SOFT_HLUTNM of \out_fifo_i_15__1\ : label is "soft_lutpair506";
  attribute SOFT_HLUTNM of \out_fifo_i_20__1\ : label is "soft_lutpair514";
  attribute SOFT_HLUTNM of \out_fifo_i_21__1\ : label is "soft_lutpair515";
  attribute SOFT_HLUTNM of \out_fifo_i_22__1\ : label is "soft_lutpair515";
  attribute SOFT_HLUTNM of \out_fifo_i_23__1\ : label is "soft_lutpair516";
  attribute SOFT_HLUTNM of \out_fifo_i_28__0\ : label is "soft_lutpair523";
  attribute SOFT_HLUTNM of \out_fifo_i_29__0\ : label is "soft_lutpair519";
  attribute SOFT_HLUTNM of \out_fifo_i_2__0\ : label is "soft_lutpair512";
  attribute SOFT_HLUTNM of \out_fifo_i_30__0\ : label is "soft_lutpair523";
  attribute SOFT_HLUTNM of \out_fifo_i_31__0\ : label is "soft_lutpair513";
  attribute SOFT_HLUTNM of \out_fifo_i_3__0\ : label is "soft_lutpair502";
  attribute SOFT_HLUTNM of \out_fifo_i_44__1\ : label is "soft_lutpair521";
  attribute SOFT_HLUTNM of out_fifo_i_45 : label is "soft_lutpair507";
  attribute SOFT_HLUTNM of out_fifo_i_46 : label is "soft_lutpair502";
  attribute SOFT_HLUTNM of \out_fifo_i_4__0\ : label is "soft_lutpair513";
  attribute SOFT_HLUTNM of \out_fifo_i_52__1\ : label is "soft_lutpair517";
  attribute SOFT_HLUTNM of \out_fifo_i_53__1\ : label is "soft_lutpair517";
  attribute SOFT_HLUTNM of \out_fifo_i_54__1\ : label is "soft_lutpair521";
  attribute SOFT_HLUTNM of \out_fifo_i_55__1\ : label is "soft_lutpair516";
  attribute SOFT_HLUTNM of \out_fifo_i_56__1\ : label is "soft_lutpair520";
  attribute SOFT_HLUTNM of out_fifo_i_57 : label is "soft_lutpair506";
  attribute SOFT_HLUTNM of out_fifo_i_58 : label is "soft_lutpair499";
  attribute SOFT_HLUTNM of \out_fifo_i_5__0\ : label is "soft_lutpair505";
  attribute SOFT_HLUTNM of \out_fifo_i_60__1\ : label is "soft_lutpair522";
  attribute SOFT_HLUTNM of \out_fifo_i_61__1\ : label is "soft_lutpair511";
  attribute SOFT_HLUTNM of \out_fifo_i_62__1\ : label is "soft_lutpair518";
  attribute SOFT_HLUTNM of \out_fifo_i_63__1\ : label is "soft_lutpair518";
  attribute SOFT_HLUTNM of \out_fifo_i_68__1\ : label is "soft_lutpair522";
  attribute SOFT_HLUTNM of \out_fifo_i_69__1\ : label is "soft_lutpair512";
  attribute SOFT_HLUTNM of \out_fifo_i_6__0\ : label is "soft_lutpair507";
  attribute SOFT_HLUTNM of \out_fifo_i_70__1\ : label is "soft_lutpair520";
  attribute SOFT_HLUTNM of out_fifo_i_71 : label is "soft_lutpair504";
  attribute SOFT_HLUTNM of out_fifo_i_72 : label is "soft_lutpair500";
  attribute SOFT_HLUTNM of \out_fifo_i_7__0\ : label is "soft_lutpair499";
  attribute SOFT_HLUTNM of \out_fifo_i_8__0\ : label is "soft_lutpair510";
  attribute SOFT_HLUTNM of \out_fifo_i_9__0\ : label is "soft_lutpair500";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1\ : label is "soft_lutpair508";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1\ : label is "soft_lutpair508";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1\ : label is "soft_lutpair503";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2\ : label is "soft_lutpair503";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1\ : label is "soft_lutpair509";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1\ : label is "soft_lutpair509";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1\ : label is "soft_lutpair501";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_1\ : label is "soft_lutpair501";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => phy_dout(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(13 downto 12),
      DOB(1 downto 0) => mem_out_0(15 downto 14),
      DOC(1 downto 0) => mem_out(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(3 downto 2),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(3 downto 2),
      DOB(1 downto 0) => mem_out_0(21 downto 20),
      DOC(1 downto 0) => mem_out_0(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(5 downto 4),
      DIB(1 downto 0) => phy_dout(7 downto 6),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(5 downto 4),
      DOB(1 downto 0) => mem_out(7 downto 6),
      DOC(1 downto 0) => mem_out_0(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => phy_dout(9 downto 8),
      DIC(1 downto 0) => phy_dout(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(31 downto 30),
      DOB(1 downto 0) => mem_out(9 downto 8),
      DOC(1 downto 0) => mem_out(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => phy_dout(12),
      DIC(0) => phy_dout(12),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(37 downto 36),
      DOB(1 downto 0) => mem_out_0(39 downto 38),
      DOC(1 downto 0) => mem_out(13 downto 12),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1) => phy_dout(12),
      DIA(0) => phy_dout(12),
      DIB(1 downto 0) => phy_dout(14 downto 13),
      DIC(1 downto 0) => phy_dout(16 downto 15),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(15 downto 14),
      DOB(1 downto 0) => mem_out(17 downto 16),
      DOC(1 downto 0) => mem_out(19 downto 18),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(18 downto 17),
      DIB(1 downto 0) => phy_dout(20 downto 19),
      DIC(1 downto 0) => phy_dout(22 downto 21),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(21 downto 20),
      DOB(1 downto 0) => mem_out(23 downto 22),
      DOC(1) => mem_out_0(53),
      DOC(0) => mem_out(24),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1) => '1',
      DIA(0) => phy_dout(23),
      DIB(1 downto 0) => phy_dout(25 downto 24),
      DIC(1) => '1',
      DIC(0) => phy_dout(26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(55 downto 54),
      DOB(1) => mem_out_0(57),
      DOB(0) => mem_out(25),
      DOC(1 downto 0) => mem_out_0(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => phy_dout(28 downto 27),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(61 downto 60),
      DOB(1 downto 0) => mem_out_0(63 downto 62),
      DOC(1 downto 0) => mem_out(27 downto 26),
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1) => phy_dout(28),
      DIA(0) => phy_dout(28),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(29 downto 28),
      DOB(1 downto 0) => mem_out_0(69 downto 68),
      DOC(1 downto 0) => mem_out_0(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(7 downto 6),
      DOB(1 downto 0) => mem_out_0(3 downto 2),
      DOC(1 downto 0) => mem_out_0(5 downto 4),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(30 downto 29),
      DIB(1) => '1',
      DIB(0) => phy_dout(31),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_out_0(73),
      DOA(0) => mem_out(30),
      DOB(1 downto 0) => mem_out_0(75 downto 74),
      DOC(1 downto 0) => mem_out_0(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \rd_ptr_reg[3]_0\,
      I1 => mux_cmd_wren,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_0\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1_n_0\
    );
\my_empty[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => \rd_ptr_reg[3]_0\,
      I1 => mux_cmd_wren,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1_n_0\
    );
\my_empty[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_4_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_5_n_0\,
      I4 => rd_ptr(2),
      O => my_empty0
    );
\my_empty[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      I3 => rd_ptr(3),
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_4_n_0\
    );
\my_empty[7]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      I4 => rd_ptr(3),
      O => \my_empty[7]_i_5_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1_n_0\,
      Q => \^my_empty_reg[1]_0\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[7]_i_1_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => mux_cmd_wren,
      I2 => \rd_ptr_reg[3]_0\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1_n_0\
    );
\my_full[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3_n_0\
    );
\my_full[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[4]_i_1_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
out_fifo_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FD"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => \wr_ptr_timing_reg[0]_0\,
      I2 => calib_cmd_wren,
      I3 => \rd_ptr_reg[3]_0\,
      O => \my_empty_reg[1]_1\
    );
\out_fifo_i_10__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(13),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(5)
    );
\out_fifo_i_11__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(12),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(4)
    );
\out_fifo_i_12__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(23),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(3)
    );
\out_fifo_i_13__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(22),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(2)
    );
\out_fifo_i_14__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(21),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
\out_fifo_i_15__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(20),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_20__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(31),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(3)
    );
\out_fifo_i_21__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(30),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(2)
    );
\out_fifo_i_22__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(29),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
\out_fifo_i_23__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(28),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_28__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(39),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(3)
    );
\out_fifo_i_29__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(38),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(2)
    );
\out_fifo_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(7),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(6)
    );
\out_fifo_i_30__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(37),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_31__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(36),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(6),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(5)
    );
\out_fifo_i_44__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => mem_out_0(55),
      I1 => \^my_empty_reg[1]_0\,
      O => D6(2)
    );
out_fifo_i_45: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => out_fifo(1),
      I1 => out_fifo_0,
      I2 => mem_out_0(54),
      I3 => \^my_empty_reg[1]_0\,
      O => D6(1)
    );
out_fifo_i_46: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => out_fifo(0),
      I1 => out_fifo_0,
      I2 => mem_out_0(53),
      I3 => \^my_empty_reg[1]_0\,
      O => D6(0)
    );
\out_fifo_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(5),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(3)
    );
\out_fifo_i_52__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(63),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(6)
    );
\out_fifo_i_53__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(62),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(5)
    );
\out_fifo_i_54__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(61),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(4)
    );
\out_fifo_i_55__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(60),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(3)
    );
\out_fifo_i_56__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => mem_out_0(59),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(2)
    );
out_fifo_i_57: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => out_fifo_0,
      I2 => mem_out_0(58),
      I3 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
out_fifo_i_58: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_cs_n(0),
      I1 => out_fifo_0,
      I2 => mem_out_0(57),
      I3 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(4),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
\out_fifo_i_60__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(71),
      I1 => \^my_empty_reg[1]_0\,
      O => D8(3)
    );
\out_fifo_i_61__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(70),
      I1 => \^my_empty_reg[1]_0\,
      O => D8(2)
    );
\out_fifo_i_62__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(69),
      I1 => \^my_empty_reg[1]_0\,
      O => D8(1)
    );
\out_fifo_i_63__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(68),
      I1 => \^my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_68__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(77),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(4)
    );
\out_fifo_i_69__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(76),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(3)
    );
\out_fifo_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(3),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_70__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => mem_out_0(75),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(2)
    );
out_fifo_i_71: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_cas_n(1),
      I1 => out_fifo_0,
      I2 => mem_out_0(74),
      I3 => \^my_empty_reg[1]_0\,
      O => D9(1)
    );
out_fifo_i_72: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => out_fifo_0,
      I2 => mem_out_0(73),
      I3 => \^my_empty_reg[1]_0\,
      O => D9(0)
    );
\out_fifo_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(2),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
\out_fifo_i_8__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(15),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(7)
    );
\out_fifo_i_9__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(14),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(6)
    );
p_17_out: unisim.vcomponents.LUT5
    generic map(
      INIT => X"27272700"
    )
        port map (
      I0 => \rd_ptr_reg[3]_0\,
      I1 => \my_full_reg_n_0_[4]\,
      I2 => \^my_empty_reg[1]_0\,
      I3 => calib_cmd_wren,
      I4 => \wr_ptr_timing_reg[0]_0\,
      O => wr_en
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr(0),
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr(1),
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr(2),
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr(3),
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(0),
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => rd_ptr(2),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      I3 => rd_ptr(3),
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rd_ptr_reg[3]_0\,
      I1 => \my_empty_reg_n_0_[7]\,
      O => \rd_ptr_timing[3]_i_1_n_0\
    );
\rd_ptr_timing[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(2),
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
wr_ptr0: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E00EEE"
    )
        port map (
      I0 => calib_cmd_wren,
      I1 => \wr_ptr_timing_reg[0]_0\,
      I2 => \rd_ptr_reg[3]_0\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \my_empty_reg_n_0_[7]\,
      O => \wr_ptr0__0\
    );
\wr_ptr[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_10\ is
  port (
    \rd_ptr_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    \rd_ptr_reg[2]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_mc_data_full : out STD_LOGIC;
    wr_en_3 : out STD_LOGIC;
    \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ofifo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    A_of_full : in STD_LOGIC;
    mux_wrdata_en : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC;
    calib_wrdata_en : in STD_LOGIC;
    out_fifo : in STD_LOGIC_VECTOR ( 7 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_10\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_10\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_10\ is
  signal \entry_cnt10_out__0\ : STD_LOGIC;
  signal \entry_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal entry_cnt_reg : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__0_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_5__0_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_1\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^rd_ptr_reg[0]_0\ : STD_LOGIC;
  signal \^rd_ptr_reg[1]_0\ : STD_LOGIC;
  signal \^rd_ptr_reg[2]_0\ : STD_LOGIC;
  signal \^rd_ptr_reg[3]_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__0_n_0\ : STD_LOGIC;
  signal wr_ptr0 : STD_LOGIC;
  signal \^wr_ptr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1\ : label is "soft_lutpair415";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1\ : label is "soft_lutpair415";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__0\ : label is "soft_lutpair414";
  attribute SOFT_HLUTNM of \my_empty[7]_i_5__0\ : label is "soft_lutpair414";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__0\ : label is "soft_lutpair416";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__0\ : label is "soft_lutpair416";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_2__1\ : label is "soft_lutpair421";
  attribute SOFT_HLUTNM of \out_fifo_i_3__1\ : label is "soft_lutpair422";
  attribute SOFT_HLUTNM of \out_fifo_i_4__1\ : label is "soft_lutpair424";
  attribute SOFT_HLUTNM of \out_fifo_i_5__1\ : label is "soft_lutpair423";
  attribute SOFT_HLUTNM of \out_fifo_i_6__1\ : label is "soft_lutpair423";
  attribute SOFT_HLUTNM of \out_fifo_i_7__1\ : label is "soft_lutpair421";
  attribute SOFT_HLUTNM of \out_fifo_i_8__1\ : label is "soft_lutpair424";
  attribute SOFT_HLUTNM of \out_fifo_i_9__1\ : label is "soft_lutpair422";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__2\ : label is "soft_lutpair419";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__2\ : label is "soft_lutpair419";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__0\ : label is "soft_lutpair418";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__0\ : label is "soft_lutpair418";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__2\ : label is "soft_lutpair420";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__2\ : label is "soft_lutpair420";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__0\ : label is "soft_lutpair417";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2\ : label is "soft_lutpair417";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\;
  \rd_ptr_reg[0]_0\ <= \^rd_ptr_reg[0]_0\;
  \rd_ptr_reg[1]_0\ <= \^rd_ptr_reg[1]_0\;
  \rd_ptr_reg[2]_0\ <= \^rd_ptr_reg[2]_0\;
  \rd_ptr_reg[3]_0\ <= \^rd_ptr_reg[3]_0\;
  \wr_ptr_reg[3]_0\(3 downto 0) <= \^wr_ptr_reg[3]_0\(3 downto 0);
\entry_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1_n_0\
    );
\entry_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => A_of_full,
      I2 => mux_wrdata_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1_n_0\
    );
\entry_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => A_of_full,
      I2 => mux_wrdata_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => entry_cnt_reg(2),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1_n_0\
    );
\entry_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt10_out__0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => entry_cnt_reg(3),
      I4 => entry_cnt_reg(2),
      O => \entry_cnt[3]_i_1_n_0\
    );
\entry_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5050500303035003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => A_of_full,
      I3 => calib_wrdata_en,
      I4 => \wr_ptr_timing_reg[0]_0\,
      I5 => mc_wrdata_en,
      O => \entry_cnt[4]_i_1_n_0\
    );
\entry_cnt[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt10_out__0\,
      I3 => entry_cnt_reg(2),
      I4 => entry_cnt_reg(4),
      I5 => entry_cnt_reg(3),
      O => \entry_cnt[4]_i_2_n_0\
    );
\entry_cnt[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008A80"
    )
        port map (
      I0 => A_of_full,
      I1 => mc_wrdata_en,
      I2 => \wr_ptr_timing_reg[0]_0\,
      I3 => calib_wrdata_en,
      I4 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt10_out__0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[0]_i_1_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[1]_i_1_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[2]_i_1_n_0\,
      Q => entry_cnt_reg(2),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[3]_i_1_n_0\,
      Q => entry_cnt_reg(3),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[4]_i_2_n_0\,
      Q => entry_cnt_reg(4),
      R => ofifo_rst
    );
\mem_reg_0_15_0_5_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2727270000002700"
    )
        port map (
      I0 => A_of_full,
      I1 => \my_full_reg_n_0_[4]\,
      I2 => \^my_empty_reg[1]_1\,
      I3 => calib_wrdata_en,
      I4 => \wr_ptr_timing_reg[0]_0\,
      I5 => mc_wrdata_en,
      O => wr_en_3
    );
\my_empty[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => A_of_full,
      I1 => mux_wrdata_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_1\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__0_n_0\
    );
\my_empty[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => A_of_full,
      I1 => mux_wrdata_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__0_n_0\
    );
\my_empty[7]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_4__0_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_5__0_n_0\,
      I4 => \^rd_ptr_reg[2]_0\,
      O => my_empty0
    );
\my_empty[7]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \^rd_ptr_reg[0]_0\,
      I2 => \^rd_ptr_reg[1]_0\,
      I3 => \^rd_ptr_reg[3]_0\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_4__0_n_0\
    );
\my_empty[7]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \^rd_ptr_reg[0]_0\,
      I3 => \^rd_ptr_reg[1]_0\,
      I4 => \^rd_ptr_reg[3]_0\,
      O => \my_empty[7]_i_5__0_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__0_n_0\,
      Q => \^my_empty_reg[1]_1\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[7]_i_1__0_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => mux_wrdata_en,
      I2 => A_of_full,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__0_n_0\
    );
\my_full[4]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__0_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__0_n_0\,
      I4 => \^wr_ptr_reg[3]_0\(2),
      O => my_full0
    );
\my_full[4]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => \^wr_ptr_reg[3]_0\(0),
      I2 => \^wr_ptr_reg[3]_0\(1),
      I3 => \^wr_ptr_reg[3]_0\(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__0_n_0\
    );
\my_full[4]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => \^wr_ptr_reg[3]_0\(0),
      I3 => \^wr_ptr_reg[3]_0\(1),
      I4 => \^wr_ptr_reg[3]_0\(3),
      O => \my_full[4]_i_4__0_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[4]_i_1__0_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
ofs_rdy_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => entry_cnt_reg(4),
      I1 => entry_cnt_reg(2),
      I2 => entry_cnt_reg(3),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => phy_mc_data_full
    );
\out_fifo_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000DFD5"
    )
        port map (
      I0 => \^my_empty_reg[1]_1\,
      I1 => mc_wrdata_en,
      I2 => \wr_ptr_timing_reg[0]_0\,
      I3 => calib_wrdata_en,
      I4 => A_of_full,
      O => \my_empty_reg[1]_0\
    );
\out_fifo_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(7),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(7)
    );
\out_fifo_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(6),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(6)
    );
\out_fifo_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(5),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(5)
    );
\out_fifo_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(4),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(4)
    );
\out_fifo_i_6__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(3),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(3)
    );
\out_fifo_i_7__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(2),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(2)
    );
\out_fifo_i_8__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(1),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(1)
    );
\out_fifo_i_9__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(0),
      I1 => \^my_empty_reg[1]_1\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(0),
      Q => \^rd_ptr_reg[0]_0\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(1),
      Q => \^rd_ptr_reg[1]_0\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(2),
      Q => \^rd_ptr_reg[2]_0\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(3),
      Q => \^rd_ptr_reg[3]_0\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^rd_ptr_reg[3]_0\,
      I1 => \^rd_ptr_reg[0]_0\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \^rd_ptr_reg[3]_0\,
      I1 => \^rd_ptr_reg[0]_0\,
      I2 => \^rd_ptr_reg[1]_0\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \^rd_ptr_reg[2]_0\,
      I1 => \^rd_ptr_reg[0]_0\,
      I2 => \^rd_ptr_reg[1]_0\,
      I3 => \^rd_ptr_reg[3]_0\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => A_of_full,
      I1 => \my_empty_reg_n_0_[7]\,
      O => \rd_ptr_timing[3]_i_1__0_n_0\
    );
\rd_ptr_timing[3]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^rd_ptr_reg[3]_0\,
      I1 => \^rd_ptr_reg[1]_0\,
      I2 => \^rd_ptr_reg[0]_0\,
      I3 => \^rd_ptr_reg[2]_0\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^wr_ptr_reg[3]_0\(3),
      I1 => \^wr_ptr_reg[3]_0\(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \^wr_ptr_reg[3]_0\(3),
      I1 => \^wr_ptr_reg[3]_0\(0),
      I2 => \^wr_ptr_reg[3]_0\(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \^wr_ptr_reg[3]_0\(2),
      I1 => \^wr_ptr_reg[3]_0\(0),
      I2 => \^wr_ptr_reg[3]_0\(1),
      I3 => \^wr_ptr_reg[3]_0\(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000E20000E2E2E2"
    )
        port map (
      I0 => calib_wrdata_en,
      I1 => \wr_ptr_timing_reg[0]_0\,
      I2 => mc_wrdata_en,
      I3 => A_of_full,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^wr_ptr_reg[3]_0\(3),
      I1 => \^wr_ptr_reg[3]_0\(1),
      I2 => \^wr_ptr_reg[3]_0\(0),
      I3 => \^wr_ptr_reg[3]_0\(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => \^wr_ptr_reg[3]_0\(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => \^wr_ptr_reg[3]_0\(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => \^wr_ptr_reg[3]_0\(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => \^wr_ptr_reg[3]_0\(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_7\ is
  port (
    \rd_ptr_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    \rd_ptr_reg[2]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    wr_en_2 : out STD_LOGIC;
    \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ofifo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    C_of_full : in STD_LOGIC;
    mux_wrdata_en : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    calib_wrdata_en : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_7\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_7\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_7\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt10_out__0\ : STD_LOGIC;
  signal \entry_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__1_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_1\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__1_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__1_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^rd_ptr_reg[0]_0\ : STD_LOGIC;
  signal \^rd_ptr_reg[1]_0\ : STD_LOGIC;
  signal \^rd_ptr_reg[2]_0\ : STD_LOGIC;
  signal \^rd_ptr_reg[3]_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__1_n_0\ : STD_LOGIC;
  signal wr_ptr0 : STD_LOGIC;
  signal \^wr_ptr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__0\ : label is "soft_lutpair488";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__0\ : label is "soft_lutpair488";
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__1\ : label is "soft_lutpair486";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__1\ : label is "soft_lutpair486";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__1\ : label is "soft_lutpair487";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__1\ : label is "soft_lutpair487";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_26__0\ : label is "soft_lutpair495";
  attribute SOFT_HLUTNM of \out_fifo_i_27__0\ : label is "soft_lutpair493";
  attribute SOFT_HLUTNM of \out_fifo_i_28__1\ : label is "soft_lutpair496";
  attribute SOFT_HLUTNM of \out_fifo_i_29__1\ : label is "soft_lutpair495";
  attribute SOFT_HLUTNM of \out_fifo_i_30__1\ : label is "soft_lutpair494";
  attribute SOFT_HLUTNM of \out_fifo_i_31__1\ : label is "soft_lutpair493";
  attribute SOFT_HLUTNM of \out_fifo_i_32__0\ : label is "soft_lutpair496";
  attribute SOFT_HLUTNM of \out_fifo_i_33__0\ : label is "soft_lutpair494";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__4\ : label is "soft_lutpair492";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__4\ : label is "soft_lutpair492";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__2\ : label is "soft_lutpair490";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__2\ : label is "soft_lutpair490";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__4\ : label is "soft_lutpair491";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__4\ : label is "soft_lutpair491";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__2\ : label is "soft_lutpair489";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__0\ : label is "soft_lutpair489";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\;
  \rd_ptr_reg[0]_0\ <= \^rd_ptr_reg[0]_0\;
  \rd_ptr_reg[1]_0\ <= \^rd_ptr_reg[1]_0\;
  \rd_ptr_reg[2]_0\ <= \^rd_ptr_reg[2]_0\;
  \rd_ptr_reg[3]_0\ <= \^rd_ptr_reg[3]_0\;
  \wr_ptr_reg[3]_0\(3 downto 0) <= \^wr_ptr_reg[3]_0\(3 downto 0);
\entry_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__0_n_0\
    );
\entry_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => C_of_full,
      I2 => mux_wrdata_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__0_n_0\
    );
\entry_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => C_of_full,
      I2 => mux_wrdata_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__0_n_0\
    );
\entry_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt10_out__0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \entry_cnt[3]_i_1__0_n_0\
    );
\entry_cnt[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5050500303035003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => C_of_full,
      I3 => calib_wrdata_en,
      I4 => \wr_ptr_timing_reg[0]_0\,
      I5 => mc_wrdata_en,
      O => \entry_cnt[4]_i_1__0_n_0\
    );
\entry_cnt[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt10_out__0\,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(1),
      O => \entry_cnt[4]_i_2__0_n_0\
    );
\entry_cnt[4]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008A80"
    )
        port map (
      I0 => C_of_full,
      I1 => mc_wrdata_en,
      I2 => \wr_ptr_timing_reg[0]_0\,
      I3 => calib_wrdata_en,
      I4 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt10_out__0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[0]_i_1__0_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[1]_i_1__0_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[2]_i_1__0_n_0\,
      Q => \^q\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[3]_i_1__0_n_0\,
      Q => \^q\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[4]_i_2__0_n_0\,
      Q => \^q\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2727270000002700"
    )
        port map (
      I0 => C_of_full,
      I1 => \my_full_reg_n_0_[4]\,
      I2 => \^my_empty_reg[1]_1\,
      I3 => calib_wrdata_en,
      I4 => \wr_ptr_timing_reg[0]_0\,
      I5 => mc_wrdata_en,
      O => wr_en_2
    );
\my_empty[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => C_of_full,
      I1 => mux_wrdata_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_1\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__2_n_0\
    );
\my_empty[7]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => C_of_full,
      I1 => mux_wrdata_en,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__1_n_0\
    );
\my_empty[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__1_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__1_n_0\,
      I4 => \^rd_ptr_reg[2]_0\,
      O => my_empty0
    );
\my_empty[7]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \^rd_ptr_reg[0]_0\,
      I2 => \^rd_ptr_reg[1]_0\,
      I3 => \^rd_ptr_reg[3]_0\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__1_n_0\
    );
\my_empty[7]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \^rd_ptr_reg[0]_0\,
      I3 => \^rd_ptr_reg[1]_0\,
      I4 => \^rd_ptr_reg[3]_0\,
      O => \my_empty[7]_i_4__1_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__2_n_0\,
      Q => \^my_empty_reg[1]_1\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[7]_i_1__1_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => mux_wrdata_en,
      I2 => C_of_full,
      I3 => \my_empty_reg_n_0_[7]\,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__1_n_0\
    );
\my_full[4]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__1_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__1_n_0\,
      I4 => \^wr_ptr_reg[3]_0\(2),
      O => my_full0
    );
\my_full[4]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => \^wr_ptr_reg[3]_0\(0),
      I2 => \^wr_ptr_reg[3]_0\(1),
      I3 => \^wr_ptr_reg[3]_0\(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__1_n_0\
    );
\my_full[4]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => \^wr_ptr_reg[3]_0\(0),
      I3 => \^wr_ptr_reg[3]_0\(1),
      I4 => \^wr_ptr_reg[3]_0\(3),
      O => \my_full[4]_i_4__1_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[4]_i_1__1_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000DFD5"
    )
        port map (
      I0 => \^my_empty_reg[1]_1\,
      I1 => mc_wrdata_en,
      I2 => out_fifo,
      I3 => calib_wrdata_en,
      I4 => C_of_full,
      O => \my_empty_reg[1]_0\
    );
\out_fifo_i_26__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo_0(7),
      I1 => \^my_empty_reg[1]_1\,
      O => D3(7)
    );
\out_fifo_i_27__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo_0(6),
      I1 => \^my_empty_reg[1]_1\,
      O => D3(6)
    );
\out_fifo_i_28__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo_0(5),
      I1 => \^my_empty_reg[1]_1\,
      O => D3(5)
    );
\out_fifo_i_29__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo_0(4),
      I1 => \^my_empty_reg[1]_1\,
      O => D3(4)
    );
\out_fifo_i_30__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo_0(3),
      I1 => \^my_empty_reg[1]_1\,
      O => D3(3)
    );
\out_fifo_i_31__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo_0(2),
      I1 => \^my_empty_reg[1]_1\,
      O => D3(2)
    );
\out_fifo_i_32__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo_0(1),
      I1 => \^my_empty_reg[1]_1\,
      O => D3(1)
    );
\out_fifo_i_33__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo_0(0),
      I1 => \^my_empty_reg[1]_1\,
      O => D3(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(0),
      Q => \^rd_ptr_reg[0]_0\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(1),
      Q => \^rd_ptr_reg[1]_0\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(2),
      Q => \^rd_ptr_reg[2]_0\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(3),
      Q => \^rd_ptr_reg[3]_0\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^rd_ptr_reg[3]_0\,
      I1 => \^rd_ptr_reg[0]_0\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \^rd_ptr_reg[3]_0\,
      I1 => \^rd_ptr_reg[0]_0\,
      I2 => \^rd_ptr_reg[1]_0\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \^rd_ptr_reg[2]_0\,
      I1 => \^rd_ptr_reg[0]_0\,
      I2 => \^rd_ptr_reg[1]_0\,
      I3 => \^rd_ptr_reg[3]_0\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => C_of_full,
      I1 => \my_empty_reg_n_0_[7]\,
      O => \rd_ptr_timing[3]_i_1__1_n_0\
    );
\rd_ptr_timing[3]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^rd_ptr_reg[3]_0\,
      I1 => \^rd_ptr_reg[1]_0\,
      I2 => \^rd_ptr_reg[0]_0\,
      I3 => \^rd_ptr_reg[2]_0\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^wr_ptr_reg[3]_0\(3),
      I1 => \^wr_ptr_reg[3]_0\(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \^wr_ptr_reg[3]_0\(3),
      I1 => \^wr_ptr_reg[3]_0\(0),
      I2 => \^wr_ptr_reg[3]_0\(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \^wr_ptr_reg[3]_0\(2),
      I1 => \^wr_ptr_reg[3]_0\(0),
      I2 => \^wr_ptr_reg[3]_0\(1),
      I3 => \^wr_ptr_reg[3]_0\(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000E20000E2E2E2"
    )
        port map (
      I0 => calib_wrdata_en,
      I1 => \wr_ptr_timing_reg[0]_0\,
      I2 => mc_wrdata_en,
      I3 => C_of_full,
      I4 => \my_full_reg_n_0_[4]\,
      I5 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^wr_ptr_reg[3]_0\(3),
      I1 => \^wr_ptr_reg[3]_0\(1),
      I2 => \^wr_ptr_reg[3]_0\(0),
      I3 => \^wr_ptr_reg[3]_0\(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => \^wr_ptr_reg[3]_0\(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => \^wr_ptr_reg[3]_0\(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => \^wr_ptr_reg[3]_0\(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => \^wr_ptr_reg[3]_0\(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_8\ is
  port (
    \rd_ptr_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    \rd_ptr_reg[2]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]_0\ : out STD_LOGIC;
    wr_en_4 : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    D4 : out STD_LOGIC_VECTOR ( 4 downto 0 );
    D0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    calib_cmd_wren : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC;
    B_of_full : in STD_LOGIC;
    out_fifo : in STD_LOGIC_VECTOR ( 32 downto 0 );
    mux_cmd_wren : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_8\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_8\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_8\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_3_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_4_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[6]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[3]_i_1_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_3_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_4_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[3]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^rd_ptr_reg[0]_0\ : STD_LOGIC;
  signal \^rd_ptr_reg[1]_0\ : STD_LOGIC;
  signal \^rd_ptr_reg[2]_0\ : STD_LOGIC;
  signal \^rd_ptr_reg[3]_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \wr_ptr0__0\ : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[6]_i_3\ : label is "soft_lutpair428";
  attribute SOFT_HLUTNM of \my_empty[6]_i_4\ : label is "soft_lutpair428";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[6]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[3]_i_3\ : label is "soft_lutpair429";
  attribute SOFT_HLUTNM of \my_full[3]_i_4\ : label is "soft_lutpair429";
  attribute syn_maxfan of \my_full_reg[3]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_10__2\ : label is "soft_lutpair439";
  attribute SOFT_HLUTNM of \out_fifo_i_11__2\ : label is "soft_lutpair432";
  attribute SOFT_HLUTNM of \out_fifo_i_12__2\ : label is "soft_lutpair443";
  attribute SOFT_HLUTNM of \out_fifo_i_13__2\ : label is "soft_lutpair436";
  attribute SOFT_HLUTNM of \out_fifo_i_18__1\ : label is "soft_lutpair436";
  attribute SOFT_HLUTNM of \out_fifo_i_19__1\ : label is "soft_lutpair440";
  attribute SOFT_HLUTNM of \out_fifo_i_1__2\ : label is "soft_lutpair432";
  attribute SOFT_HLUTNM of \out_fifo_i_20__2\ : label is "soft_lutpair435";
  attribute SOFT_HLUTNM of \out_fifo_i_21__2\ : label is "soft_lutpair438";
  attribute SOFT_HLUTNM of \out_fifo_i_26__1\ : label is "soft_lutpair446";
  attribute SOFT_HLUTNM of \out_fifo_i_27__1\ : label is "soft_lutpair443";
  attribute SOFT_HLUTNM of \out_fifo_i_28__2\ : label is "soft_lutpair442";
  attribute SOFT_HLUTNM of \out_fifo_i_29__2\ : label is "soft_lutpair444";
  attribute SOFT_HLUTNM of \out_fifo_i_2__2\ : label is "soft_lutpair441";
  attribute SOFT_HLUTNM of \out_fifo_i_34__1\ : label is "soft_lutpair447";
  attribute SOFT_HLUTNM of \out_fifo_i_35__1\ : label is "soft_lutpair441";
  attribute SOFT_HLUTNM of \out_fifo_i_36__1\ : label is "soft_lutpair449";
  attribute SOFT_HLUTNM of \out_fifo_i_37__1\ : label is "soft_lutpair440";
  attribute SOFT_HLUTNM of \out_fifo_i_38__1\ : label is "soft_lutpair448";
  attribute SOFT_HLUTNM of \out_fifo_i_3__2\ : label is "soft_lutpair435";
  attribute SOFT_HLUTNM of \out_fifo_i_4__2\ : label is "soft_lutpair442";
  attribute SOFT_HLUTNM of \out_fifo_i_58__1\ : label is "soft_lutpair447";
  attribute SOFT_HLUTNM of \out_fifo_i_59__1\ : label is "soft_lutpair445";
  attribute SOFT_HLUTNM of \out_fifo_i_5__2\ : label is "soft_lutpair437";
  attribute SOFT_HLUTNM of \out_fifo_i_60__2\ : label is "soft_lutpair445";
  attribute SOFT_HLUTNM of \out_fifo_i_61__2\ : label is "soft_lutpair437";
  attribute SOFT_HLUTNM of \out_fifo_i_66__1\ : label is "soft_lutpair449";
  attribute SOFT_HLUTNM of \out_fifo_i_67__1\ : label is "soft_lutpair438";
  attribute SOFT_HLUTNM of \out_fifo_i_68__2\ : label is "soft_lutpair448";
  attribute SOFT_HLUTNM of \out_fifo_i_69__2\ : label is "soft_lutpair444";
  attribute SOFT_HLUTNM of \out_fifo_i_74__1\ : label is "soft_lutpair450";
  attribute SOFT_HLUTNM of \out_fifo_i_75__1\ : label is "soft_lutpair439";
  attribute SOFT_HLUTNM of \out_fifo_i_76__1\ : label is "soft_lutpair450";
  attribute SOFT_HLUTNM of \out_fifo_i_77__1\ : label is "soft_lutpair446";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__3\ : label is "soft_lutpair433";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__3\ : label is "soft_lutpair433";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__1\ : label is "soft_lutpair431";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__1\ : label is "soft_lutpair431";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__3\ : label is "soft_lutpair434";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__3\ : label is "soft_lutpair434";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__1\ : label is "soft_lutpair430";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_1__2\ : label is "soft_lutpair430";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
  \rd_ptr_reg[0]_0\ <= \^rd_ptr_reg[0]_0\;
  \rd_ptr_reg[1]_0\ <= \^rd_ptr_reg[1]_0\;
  \rd_ptr_reg[2]_0\ <= \^rd_ptr_reg[2]_0\;
  \rd_ptr_reg[3]_0\ <= \^rd_ptr_reg[3]_0\;
\my_empty[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => B_of_full,
      I1 => mux_cmd_wren,
      I2 => \my_full_reg_n_0_[3]\,
      I3 => \^my_empty_reg[1]_0\,
      I4 => my_empty0,
      I5 => SR(0),
      O => \my_empty[1]_i_1__1_n_0\
    );
\my_empty[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF701F700"
    )
        port map (
      I0 => B_of_full,
      I1 => mux_cmd_wren,
      I2 => \my_full_reg_n_0_[3]\,
      I3 => \my_empty_reg_n_0_[6]\,
      I4 => my_empty0,
      I5 => SR(0),
      O => \my_empty[6]_i_1_n_0\
    );
\my_empty[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[6]_i_3_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[6]_i_4_n_0\,
      I4 => \^rd_ptr_reg[2]_0\,
      O => my_empty0
    );
\my_empty[6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \^rd_ptr_reg[0]_0\,
      I2 => \^rd_ptr_reg[1]_0\,
      I3 => \^rd_ptr_reg[3]_0\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[6]_i_3_n_0\
    );
\my_empty[6]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \^rd_ptr_reg[0]_0\,
      I3 => \^rd_ptr_reg[1]_0\,
      I4 => \^rd_ptr_reg[3]_0\,
      O => \my_empty[6]_i_4_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__1_n_0\,
      Q => \^my_empty_reg[1]_0\,
      R => '0'
    );
\my_empty_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[6]_i_1_n_0\,
      Q => \my_empty_reg_n_0_[6]\,
      R => '0'
    );
\my_full[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFC0080"
    )
        port map (
      I0 => my_full0,
      I1 => mux_cmd_wren,
      I2 => B_of_full,
      I3 => \my_empty_reg_n_0_[6]\,
      I4 => \my_full_reg_n_0_[3]\,
      I5 => SR(0),
      O => \my_full[3]_i_1_n_0\
    );
\my_full[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[3]_i_3_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[3]_i_4_n_0\,
      I4 => \^q\(2),
      O => my_full0
    );
\my_full[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[3]_i_3_n_0\
    );
\my_full[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => \my_full[3]_i_4_n_0\
    );
\my_full_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[3]_i_1_n_0\,
      Q => \my_full_reg_n_0_[3]\,
      R => '0'
    );
\out_fifo_i_10__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(7),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(3)
    );
\out_fifo_i_11__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(6),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
\out_fifo_i_12__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(5),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_13__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(4),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
\out_fifo_i_18__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(11),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(3)
    );
\out_fifo_i_19__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(10),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(2)
    );
\out_fifo_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FD"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => \wr_ptr_timing_reg[0]_0\,
      I2 => calib_cmd_wren,
      I3 => B_of_full,
      O => \my_empty_reg[1]_1\
    );
\out_fifo_i_20__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(9),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
\out_fifo_i_21__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(8),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_26__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(15),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(3)
    );
\out_fifo_i_27__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(14),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(2)
    );
\out_fifo_i_28__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(13),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
\out_fifo_i_29__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(12),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(3),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(3)
    );
\out_fifo_i_34__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(20),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(4)
    );
\out_fifo_i_35__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(19),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(3)
    );
\out_fifo_i_36__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(18),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(2)
    );
\out_fifo_i_37__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(17),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_38__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => out_fifo(16),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(2),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
\out_fifo_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(1),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
\out_fifo_i_58__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(24),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(3)
    );
\out_fifo_i_59__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(23),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(2)
    );
\out_fifo_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(0),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
\out_fifo_i_60__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(22),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
\out_fifo_i_61__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(21),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_66__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(28),
      I1 => \^my_empty_reg[1]_0\,
      O => D8(3)
    );
\out_fifo_i_67__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(27),
      I1 => \^my_empty_reg[1]_0\,
      O => D8(2)
    );
\out_fifo_i_68__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(26),
      I1 => \^my_empty_reg[1]_0\,
      O => D8(1)
    );
\out_fifo_i_69__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(25),
      I1 => \^my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_74__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(32),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(3)
    );
\out_fifo_i_75__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(31),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(2)
    );
\out_fifo_i_76__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(30),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(1)
    );
\out_fifo_i_77__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => out_fifo(29),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(0)
    );
p_17_out: unisim.vcomponents.LUT5
    generic map(
      INIT => X"27272700"
    )
        port map (
      I0 => B_of_full,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => \^my_empty_reg[1]_0\,
      I3 => calib_cmd_wren,
      I4 => \wr_ptr_timing_reg[0]_0\,
      O => wr_en_4
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(0),
      Q => \^rd_ptr_reg[0]_0\,
      R => SR(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(1),
      Q => \^rd_ptr_reg[1]_0\,
      R => SR(0)
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(2),
      Q => \^rd_ptr_reg[2]_0\,
      R => SR(0)
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(3),
      Q => \^rd_ptr_reg[3]_0\,
      R => SR(0)
    );
\rd_ptr_timing[0]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^rd_ptr_reg[3]_0\,
      I1 => \^rd_ptr_reg[0]_0\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \^rd_ptr_reg[3]_0\,
      I1 => \^rd_ptr_reg[0]_0\,
      I2 => \^rd_ptr_reg[1]_0\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \^rd_ptr_reg[2]_0\,
      I1 => \^rd_ptr_reg[0]_0\,
      I2 => \^rd_ptr_reg[1]_0\,
      I3 => \^rd_ptr_reg[3]_0\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => B_of_full,
      I1 => \my_empty_reg_n_0_[6]\,
      O => \rd_ptr_timing[3]_i_1__2_n_0\
    );
\rd_ptr_timing[3]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^rd_ptr_reg[3]_0\,
      I1 => \^rd_ptr_reg[1]_0\,
      I2 => \^rd_ptr_reg[0]_0\,
      I3 => \^rd_ptr_reg[2]_0\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => SR(0)
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => SR(0)
    );
wr_ptr0: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E00EEE"
    )
        port map (
      I0 => calib_cmd_wren,
      I1 => \wr_ptr_timing_reg[0]_0\,
      I2 => B_of_full,
      I3 => \my_full_reg_n_0_[3]\,
      I4 => \my_empty_reg_n_0_[6]\,
      O => \wr_ptr0__0\
    );
\wr_ptr[0]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => \^q\(0),
      R => SR(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => \^q\(1),
      R => SR(0)
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => \^q\(2),
      R => SR(0)
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => \^q\(3),
      R => SR(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => SR(0)
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => SR(0)
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr is
  port (
    init_dqsfound_done_r2 : out STD_LOGIC;
    init_dqsfound_done_r_reg_0 : out STD_LOGIC;
    pi_dqs_found_all_bank : out STD_LOGIC;
    pi_dqs_found_rank_done : out STD_LOGIC;
    pi_dqs_found_done : out STD_LOGIC;
    fine_adjust_done_r_reg_0 : out STD_LOGIC;
    dqs_found_prech_req : out STD_LOGIC;
    ck_po_stg2_f_en : out STD_LOGIC;
    ck_po_stg2_f_en_reg_0 : out STD_LOGIC;
    ck_po_stg2_f_indec_reg_0 : out STD_LOGIC;
    \calib_sel_reg[1]\ : out STD_LOGIC;
    \calib_sel_reg[1]_0\ : out STD_LOGIC;
    ck_po_stg2_f_indec_reg_1 : out STD_LOGIC;
    \pi_rst_stg1_cal_reg[0]_0\ : out STD_LOGIC;
    dqs_found_done_r_reg_0 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rd_byte_data_offset_reg[0][2]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pi_dqs_found_done_r1_reg_0 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_1 : out STD_LOGIC;
    pi_dqs_found_done_r1_reg_2 : out STD_LOGIC;
    dqs_found_done_r_reg_1 : out STD_LOGIC;
    ififo_rst_reg0 : out STD_LOGIC;
    ofifo_rst_reg0 : out STD_LOGIC;
    ififo_rst_reg0_1 : out STD_LOGIC;
    ofifo_rst_reg0_2 : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    CLK : in STD_LOGIC;
    pi_dqs_found_lanes : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dqs_found_start_r_reg_0 : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    first_fail_detect_reg_0 : in STD_LOGIC;
    init_dqsfound_done_r_reg_1 : in STD_LOGIC;
    po_en_s2_f : in STD_LOGIC;
    calib_zero_ctrl : in STD_LOGIC;
    ofifo_rst_reg : in STD_LOGIC;
    calib_zero_inputs : in STD_LOGIC;
    ofifo_rst_reg_0 : in STD_LOGIC;
    detect_pi_found_dqs : in STD_LOGIC;
    \stable_pass_cnt_reg[4]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    pi_dqs_found_done_r1 : in STD_LOGIC;
    \init_state_r[1]_i_14\ : in STD_LOGIC;
    phy_if_reset : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    \pi_rst_stg1_cal_r1_reg[0]_0\ : in STD_LOGIC;
    prech_done : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr : entity is "mig_7series_v4_2_ddr_phy_dqs_found_cal_hr";
end mig_7series_0_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr is
  signal \FSM_sequential_fine_adj_state_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \^ck_po_stg2_f_en\ : STD_LOGIC;
  signal ck_po_stg2_f_en_i_1_n_0 : STD_LOGIC;
  signal ck_po_stg2_f_indec_i_1_n_0 : STD_LOGIC;
  signal dec_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \dec_cnt[0]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[1]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[1]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_4_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_5_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_6_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_7_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_8_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_9_n_0\ : STD_LOGIC;
  signal \dec_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_10_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_4_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_5_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_6_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_7_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_8_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_9_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_10_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_11_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_4_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_5_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_6_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_7_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_8_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_9_n_0\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_3_n_1\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_3_n_2\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_3_n_3\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_3_n_4\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_3_n_5\ : STD_LOGIC;
  signal \dec_cnt_reg[2]_i_3_n_6\ : STD_LOGIC;
  signal \dec_cnt_reg[4]_i_3_n_3\ : STD_LOGIC;
  signal \dec_cnt_reg[4]_i_3_n_6\ : STD_LOGIC;
  signal \dec_cnt_reg[4]_i_3_n_7\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal detect_rd_cnt0 : STD_LOGIC;
  signal \detect_rd_cnt0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \detect_rd_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \detect_rd_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal detect_rd_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal dqs_found_done_r0 : STD_LOGIC;
  signal dqs_found_done_r_i_2_n_0 : STD_LOGIC;
  signal \^dqs_found_prech_req\ : STD_LOGIC;
  signal dqs_found_prech_req_i_1_n_0 : STD_LOGIC;
  signal dqs_found_prech_req_i_2_n_0 : STD_LOGIC;
  signal dqs_found_prech_req_i_3_n_0 : STD_LOGIC;
  signal dqs_found_prech_req_i_4_n_0 : STD_LOGIC;
  signal dqs_found_prech_req_i_5_n_0 : STD_LOGIC;
  signal dqs_found_prech_req_i_6_n_0 : STD_LOGIC;
  signal dqs_found_prech_req_i_7_n_0 : STD_LOGIC;
  signal dqs_found_start_r : STD_LOGIC;
  signal final_dec_done_i_1_n_0 : STD_LOGIC;
  signal final_dec_done_i_2_n_0 : STD_LOGIC;
  signal final_dec_done_reg_n_0 : STD_LOGIC;
  signal fine_adj_state_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal fine_adjust_done_r_i_1_n_0 : STD_LOGIC;
  signal \^fine_adjust_done_r_reg_0\ : STD_LOGIC;
  signal fine_adjust_i_1_n_0 : STD_LOGIC;
  signal fine_adjust_reg_n_0 : STD_LOGIC;
  signal first_fail_detect : STD_LOGIC;
  signal first_fail_detect_i_1_n_0 : STD_LOGIC;
  signal first_fail_detect_reg_n_0 : STD_LOGIC;
  signal \first_fail_taps[0]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[1]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[2]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[3]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[4]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_2_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_3_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_4_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_5_n_0\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[0]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[1]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[2]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[3]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[4]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[5]\ : STD_LOGIC;
  signal inc_cnt : STD_LOGIC;
  signal \inc_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \inc_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \inc_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal init_dec_cnt : STD_LOGIC;
  signal init_dec_cnt0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \init_dec_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal init_dec_cnt_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal init_dec_done_i_1_n_0 : STD_LOGIC;
  signal init_dec_done_i_2_n_0 : STD_LOGIC;
  signal init_dec_done_reg_n_0 : STD_LOGIC;
  signal init_dqsfound_done_r1_reg_n_0 : STD_LOGIC;
  signal \^init_dqsfound_done_r2\ : STD_LOGIC;
  signal init_dqsfound_done_r4_reg_srl2_n_0 : STD_LOGIC;
  signal init_dqsfound_done_r5 : STD_LOGIC;
  signal init_dqsfound_done_r_i_1_n_0 : STD_LOGIC;
  signal \^init_dqsfound_done_r_reg_0\ : STD_LOGIC;
  signal n_0_0 : STD_LOGIC;
  signal n_0_1 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal p_0_in22_out : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal p_1_out : STD_LOGIC_VECTOR ( 5 to 5 );
  signal \^pi_dqs_found_all_bank\ : STD_LOGIC;
  signal \pi_dqs_found_all_bank[0]_i_1_n_0\ : STD_LOGIC;
  signal pi_dqs_found_all_bank_r : STD_LOGIC;
  signal pi_dqs_found_any_bank : STD_LOGIC;
  signal \pi_dqs_found_any_bank[0]_i_1_n_0\ : STD_LOGIC;
  signal pi_dqs_found_any_bank_r : STD_LOGIC;
  signal \^pi_dqs_found_done\ : STD_LOGIC;
  signal pi_dqs_found_lanes_r1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute async_reg : string;
  attribute async_reg of pi_dqs_found_lanes_r1 : signal is "true";
  signal pi_dqs_found_lanes_r2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute async_reg of pi_dqs_found_lanes_r2 : signal is "true";
  signal pi_dqs_found_lanes_r3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute async_reg of pi_dqs_found_lanes_r3 : signal is "true";
  signal \^pi_dqs_found_rank_done\ : STD_LOGIC;
  signal \pi_rst_stg1_cal[0]_i_1_n_0\ : STD_LOGIC;
  signal pi_rst_stg1_cal_r : STD_LOGIC;
  signal \pi_rst_stg1_cal_r1[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r1_reg_n_0_[0]\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[0]_i_2_n_0\ : STD_LOGIC;
  signal po_stg2_fincdec : STD_LOGIC_VECTOR ( 2 to 2 );
  signal rank_done_r1 : STD_LOGIC;
  signal rank_done_r_i_1_n_0 : STD_LOGIC;
  signal rd_byte_data_offset : STD_LOGIC;
  signal \rd_byte_data_offset[0][5]_i_1_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][5]_i_4_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][5]_i_5_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][5]_i_6_n_0\ : STD_LOGIC;
  signal \^rd_byte_data_offset_reg[0][2]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_byte_data_offset_reg[0]_1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rd_data_offset_ranks_0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rnk_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rnk_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal rst_dqs_find : STD_LOGIC;
  signal \rst_dqs_find__0\ : STD_LOGIC;
  signal rst_dqs_find_i_1_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_3_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_4_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_5_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_6_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_7_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_8_n_0 : STD_LOGIC;
  signal rst_dqs_find_r1 : STD_LOGIC;
  signal rst_dqs_find_r2 : STD_LOGIC;
  signal rst_stg1_cal : STD_LOGIC;
  signal stable_pass_cnt : STD_LOGIC;
  signal \stable_pass_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \stable_pass_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \stable_pass_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \stable_pass_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal stable_pass_cnt_reg : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \stable_pass_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \NLW_dec_cnt_reg[2]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_dec_cnt_reg[4]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_dec_cnt_reg[4]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[0]_i_3\ : label is "soft_lutpair181";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[2]_i_3\ : label is "soft_lutpair199";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[2]_i_4\ : label is "soft_lutpair195";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[0]\ : label is "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[1]\ : label is "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[2]\ : label is "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[3]\ : label is "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110";
  attribute SOFT_HLUTNM of \calib_data_offset_0[0]_i_1\ : label is "soft_lutpair200";
  attribute SOFT_HLUTNM of ck_po_stg2_f_indec_i_1 : label is "soft_lutpair186";
  attribute SOFT_HLUTNM of \dec_cnt[2]_i_2\ : label is "soft_lutpair205";
  attribute SOFT_HLUTNM of \dec_cnt[2]_i_9\ : label is "soft_lutpair204";
  attribute SOFT_HLUTNM of \dec_cnt[3]_i_2\ : label is "soft_lutpair205";
  attribute SOFT_HLUTNM of \dec_cnt[3]_i_4\ : label is "soft_lutpair185";
  attribute SOFT_HLUTNM of \dec_cnt[4]_i_10\ : label is "soft_lutpair202";
  attribute SOFT_HLUTNM of \dec_cnt[4]_i_2\ : label is "soft_lutpair184";
  attribute SOFT_HLUTNM of \dec_cnt[4]_i_9\ : label is "soft_lutpair196";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_5\ : label is "soft_lutpair186";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_6\ : label is "soft_lutpair184";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_7\ : label is "soft_lutpair195";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_9\ : label is "soft_lutpair194";
  attribute SOFT_HLUTNM of \detect_rd_cnt[1]_i_1\ : label is "soft_lutpair209";
  attribute SOFT_HLUTNM of \detect_rd_cnt[2]_i_1\ : label is "soft_lutpair209";
  attribute SOFT_HLUTNM of \detect_rd_cnt[3]_i_3\ : label is "soft_lutpair182";
  attribute SOFT_HLUTNM of dqs_found_prech_req_i_2 : label is "soft_lutpair180";
  attribute SOFT_HLUTNM of dqs_found_prech_req_i_5 : label is "soft_lutpair210";
  attribute SOFT_HLUTNM of dqs_found_prech_req_i_7 : label is "soft_lutpair179";
  attribute SOFT_HLUTNM of \first_fail_taps[0]_i_1\ : label is "soft_lutpair203";
  attribute SOFT_HLUTNM of \first_fail_taps[1]_i_1\ : label is "soft_lutpair206";
  attribute SOFT_HLUTNM of \first_fail_taps[2]_i_1\ : label is "soft_lutpair203";
  attribute SOFT_HLUTNM of \first_fail_taps[3]_i_1\ : label is "soft_lutpair204";
  attribute SOFT_HLUTNM of \first_fail_taps[4]_i_1\ : label is "soft_lutpair206";
  attribute SOFT_HLUTNM of \first_fail_taps[5]_i_3\ : label is "soft_lutpair187";
  attribute SOFT_HLUTNM of \first_fail_taps[5]_i_4\ : label is "soft_lutpair199";
  attribute SOFT_HLUTNM of ififo_rst_i_1 : label is "soft_lutpair190";
  attribute SOFT_HLUTNM of \ififo_rst_i_1__0\ : label is "soft_lutpair190";
  attribute SOFT_HLUTNM of \inc_cnt[1]_i_1\ : label is "soft_lutpair210";
  attribute SOFT_HLUTNM of \inc_cnt[2]_i_1\ : label is "soft_lutpair202";
  attribute SOFT_HLUTNM of \inc_cnt[3]_i_1\ : label is "soft_lutpair196";
  attribute SOFT_HLUTNM of \inc_cnt[4]_i_1\ : label is "soft_lutpair185";
  attribute SOFT_HLUTNM of \init_dec_cnt[1]_i_1\ : label is "soft_lutpair208";
  attribute SOFT_HLUTNM of \init_dec_cnt[2]_i_1\ : label is "soft_lutpair208";
  attribute SOFT_HLUTNM of \init_dec_cnt[3]_i_1\ : label is "soft_lutpair189";
  attribute SOFT_HLUTNM of \init_dec_cnt[4]_i_1\ : label is "soft_lutpair189";
  attribute SOFT_HLUTNM of init_dec_done_i_2 : label is "soft_lutpair181";
  attribute srl_name : string;
  attribute srl_name of init_dqsfound_done_r4_reg_srl2 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r4_reg_srl2 ";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_17\ : label is "soft_lutpair207";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_19\ : label is "soft_lutpair207";
  attribute SOFT_HLUTNM of ofifo_rst_i_1 : label is "soft_lutpair191";
  attribute SOFT_HLUTNM of \ofifo_rst_i_1__0\ : label is "soft_lutpair191";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5\ : label is "soft_lutpair193";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__0\ : label is "soft_lutpair193";
  attribute SOFT_HLUTNM of \phaser_out_i_3__0\ : label is "soft_lutpair192";
  attribute SOFT_HLUTNM of \phaser_out_i_3__1\ : label is "soft_lutpair192";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \pi_rst_stg1_cal[0]_i_1\ : label is "soft_lutpair201";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][1]_i_1\ : label is "soft_lutpair200";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][3]_i_1\ : label is "soft_lutpair188";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][4]_i_1\ : label is "soft_lutpair188";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][5]_i_6\ : label is "soft_lutpair182";
  attribute SOFT_HLUTNM of \rnk_cnt_r[0]_i_1\ : label is "soft_lutpair198";
  attribute SOFT_HLUTNM of \rnk_cnt_r[1]_i_1\ : label is "soft_lutpair198";
  attribute SOFT_HLUTNM of rst_dqs_find_i_1 : label is "soft_lutpair201";
  attribute SOFT_HLUTNM of rst_dqs_find_i_5 : label is "soft_lutpair179";
  attribute SOFT_HLUTNM of rst_dqs_find_i_7 : label is "soft_lutpair180";
  attribute SOFT_HLUTNM of \stable_pass_cnt[0]_i_1\ : label is "soft_lutpair194";
  attribute SOFT_HLUTNM of \stable_pass_cnt[1]_i_1\ : label is "soft_lutpair197";
  attribute SOFT_HLUTNM of \stable_pass_cnt[2]_i_1\ : label is "soft_lutpair183";
  attribute SOFT_HLUTNM of \stable_pass_cnt[3]_i_1\ : label is "soft_lutpair183";
  attribute SOFT_HLUTNM of \stable_pass_cnt[5]_i_2\ : label is "soft_lutpair197";
  attribute SOFT_HLUTNM of \stable_pass_cnt[5]_i_3\ : label is "soft_lutpair187";
begin
  ck_po_stg2_f_en <= \^ck_po_stg2_f_en\;
  dqs_found_prech_req <= \^dqs_found_prech_req\;
  fine_adjust_done_r_reg_0 <= \^fine_adjust_done_r_reg_0\;
  init_dqsfound_done_r2 <= \^init_dqsfound_done_r2\;
  init_dqsfound_done_r_reg_0 <= \^init_dqsfound_done_r_reg_0\;
  pi_dqs_found_all_bank <= \^pi_dqs_found_all_bank\;
  pi_dqs_found_done <= \^pi_dqs_found_done\;
  pi_dqs_found_rank_done <= \^pi_dqs_found_rank_done\;
  \rd_byte_data_offset_reg[0][2]_0\(1 downto 0) <= \^rd_byte_data_offset_reg[0][2]_0\(1 downto 0);
\FSM_sequential_fine_adj_state_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFDFFFF"
    )
        port map (
      I0 => final_dec_done_reg_n_0,
      I1 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I2 => fine_adj_state_r(1),
      I3 => fine_adj_state_r(3),
      I4 => fine_adj_state_r(0),
      I5 => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\,
      O => \FSM_sequential_fine_adj_state_r[0]_i_1_n_0\
    );
\FSM_sequential_fine_adj_state_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABBABEABABBBBEA"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[0]_i_3_n_0\,
      I1 => fine_adj_state_r(2),
      I2 => fine_adj_state_r(0),
      I3 => fine_adj_state_r(3),
      I4 => fine_adj_state_r(1),
      I5 => \rd_byte_data_offset[0][5]_i_6_n_0\,
      O => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\
    );
\FSM_sequential_fine_adj_state_r[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \dec_cnt[5]_i_4_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I2 => fine_adj_state_r(0),
      I3 => fine_adj_state_r(1),
      I4 => fine_adj_state_r(3),
      O => \FSM_sequential_fine_adj_state_r[0]_i_3_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB00FB00FB00FBFB"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\,
      I1 => fine_adj_state_r(3),
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\,
      I3 => \FSM_sequential_fine_adj_state_r[1]_i_4_n_0\,
      I4 => fine_adj_state_r(1),
      I5 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_1_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFCFCFFFDFFFDF"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\,
      I1 => fine_adj_state_r(0),
      I2 => fine_adj_state_r(1),
      I3 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I4 => \^pi_dqs_found_all_bank\,
      I5 => detect_pi_found_dqs,
      O => \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D0D0D0D0F0F000F0"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[2]_i_5_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\,
      I2 => \stable_pass_cnt_reg[4]_0\,
      I3 => \FSM_sequential_fine_adj_state_r[2]_i_4_n_0\,
      I4 => \FSM_sequential_fine_adj_state_r[2]_i_6_n_0\,
      I5 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000550FFC0000"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I1 => \^pi_dqs_found_all_bank\,
      I2 => fine_adj_state_r(2),
      I3 => fine_adj_state_r(3),
      I4 => fine_adj_state_r(1),
      I5 => fine_adj_state_r(0),
      O => \FSM_sequential_fine_adj_state_r[1]_i_4_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EF00EFFF0F0F0F"
    )
        port map (
      I0 => \dec_cnt[5]_i_4_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I2 => fine_adj_state_r(3),
      I3 => fine_adj_state_r(0),
      I4 => \rd_byte_data_offset[0][5]_i_6_n_0\,
      I5 => fine_adj_state_r(2),
      O => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFEFEFFFFEFEFFF"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[1]\,
      I1 => \inc_cnt_reg_n_0_[0]\,
      I2 => \inc_cnt_reg_n_0_[3]\,
      I3 => \inc_cnt_reg_n_0_[2]\,
      I4 => \inc_cnt_reg_n_0_[4]\,
      I5 => \inc_cnt_reg_n_0_[5]\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[2]\,
      I1 => \inc_cnt_reg_n_0_[3]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[0]\,
      I4 => \inc_cnt_reg_n_0_[5]\,
      I5 => \inc_cnt_reg_n_0_[4]\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033F033FF02CFC2C"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(0),
      I3 => fine_adj_state_r(1),
      I4 => \FSM_sequential_fine_adj_state_r[2]_i_2_n_0\,
      I5 => fine_adj_state_r(2),
      O => \FSM_sequential_fine_adj_state_r[2]_i_1_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000F0B1F500F0"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[2]_i_4_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[2]_i_5_n_0\,
      I3 => \FSM_sequential_fine_adj_state_r[2]_i_6_n_0\,
      I4 => detect_pi_found_dqs,
      I5 => \^pi_dqs_found_all_bank\,
      O => \FSM_sequential_fine_adj_state_r[2]_i_2_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => \first_fail_taps[5]_i_5_n_0\,
      I1 => \first_fail_taps[5]_i_3_n_0\,
      I2 => first_fail_detect_reg_n_0,
      O => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \first_fail_taps[5]_i_5_n_0\,
      I1 => \first_fail_taps[5]_i_3_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      O => \FSM_sequential_fine_adj_state_r[2]_i_4_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF9FFFFFFFF"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[2]\,
      I1 => \inc_cnt_reg_n_0_[4]\,
      I2 => \inc_cnt_reg_n_0_[5]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[0]\,
      I5 => \inc_cnt_reg_n_0_[3]\,
      O => \FSM_sequential_fine_adj_state_r[2]_i_5_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008028"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \inc_cnt_reg_n_0_[4]\,
      I2 => \inc_cnt_reg_n_0_[2]\,
      I3 => \inc_cnt_reg_n_0_[3]\,
      I4 => \inc_cnt_reg_n_0_[0]\,
      I5 => \inc_cnt_reg_n_0_[1]\,
      O => \FSM_sequential_fine_adj_state_r[2]_i_6_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBEEBABBBBFFFF"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_3_n_0\,
      I1 => fine_adj_state_r(0),
      I2 => init_dqsfound_done_r5,
      I3 => fine_adj_state_r(1),
      I4 => fine_adj_state_r(2),
      I5 => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\,
      O => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A80A8080A80A800"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\,
      I1 => fine_adj_state_r(0),
      I2 => fine_adj_state_r(1),
      I3 => fine_adj_state_r(3),
      I4 => fine_adj_state_r(2),
      I5 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      O => \FSM_sequential_fine_adj_state_r[3]_i_2_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFFFF0CFA0FFF0"
    )
        port map (
      I0 => detect_pi_found_dqs,
      I1 => prech_done,
      I2 => fine_adj_state_r(3),
      I3 => fine_adj_state_r(2),
      I4 => fine_adj_state_r(1),
      I5 => \^pi_dqs_found_all_bank\,
      O => \FSM_sequential_fine_adj_state_r[3]_i_3_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => rst_dqs_find_r2,
      I1 => pi_dqs_found_any_bank,
      I2 => fine_adj_state_r(0),
      O => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0C04FFFF0C0C"
    )
        port map (
      I0 => dqs_found_prech_req_i_3_n_0,
      I1 => detect_pi_found_dqs,
      I2 => \^pi_dqs_found_all_bank\,
      I3 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\,
      I5 => \first_fail_taps[5]_i_4_n_0\,
      O => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => init_dec_cnt_reg(5),
      I1 => init_dec_cnt_reg(3),
      I2 => init_dec_cnt_reg(1),
      I3 => init_dec_cnt_reg(0),
      I4 => init_dec_cnt_reg(2),
      I5 => init_dec_cnt_reg(4),
      O => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => first_fail_detect_reg_n_0,
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I2 => \dec_cnt[4]_i_7_n_0\,
      O => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\
    );
\FSM_sequential_fine_adj_state_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\,
      D => \FSM_sequential_fine_adj_state_r[0]_i_1_n_0\,
      Q => fine_adj_state_r(0),
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\FSM_sequential_fine_adj_state_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\,
      D => \FSM_sequential_fine_adj_state_r[1]_i_1_n_0\,
      Q => fine_adj_state_r(1),
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\FSM_sequential_fine_adj_state_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\,
      D => \FSM_sequential_fine_adj_state_r[2]_i_1_n_0\,
      Q => fine_adj_state_r(2),
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\FSM_sequential_fine_adj_state_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\,
      D => \FSM_sequential_fine_adj_state_r[3]_i_2_n_0\,
      Q => fine_adj_state_r(3),
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\calib_data_offset_0[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(0),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg[0]_1\(0),
      O => pi_dqs_found_done_r1_reg_2
    );
\calib_data_offset_0[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(3),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg[0]_1\(3),
      O => pi_dqs_found_done_r1_reg_1
    );
\calib_data_offset_0[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(4),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg[0]_1\(4),
      O => pi_dqs_found_done_r1_reg_0
    );
\calib_data_offset_0[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(5),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg[0]_1\(5),
      O => pi_dqs_found_done_r1_reg
    );
ck_po_stg2_f_en_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7DF4200"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => fine_adj_state_r(0),
      I2 => fine_adj_state_r(3),
      I3 => fine_adj_state_r(1),
      I4 => \^ck_po_stg2_f_en\,
      O => ck_po_stg2_f_en_i_1_n_0
    );
ck_po_stg2_f_en_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ck_po_stg2_f_en_i_1_n_0,
      Q => \^ck_po_stg2_f_en\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
ck_po_stg2_f_indec_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B7DF0200"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => fine_adj_state_r(0),
      I2 => fine_adj_state_r(3),
      I3 => fine_adj_state_r(1),
      I4 => po_stg2_fincdec(2),
      O => ck_po_stg2_f_indec_i_1_n_0
    );
ck_po_stg2_f_indec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ck_po_stg2_f_indec_i_1_n_0,
      Q => po_stg2_fincdec(2),
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\dec_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47447777"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[0]\,
      I1 => fine_adj_state_r(0),
      I2 => \dec_cnt[5]_i_9_n_0\,
      I3 => \dec_cnt_reg[2]_i_3_n_6\,
      I4 => \dec_cnt[0]_i_2_n_0\,
      O => dec_cnt(0)
    );
\dec_cnt[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF8B8BFF00"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[1]\,
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I2 => \dec_cnt_reg[2]_i_3_n_6\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \dec_cnt[4]_i_7_n_0\,
      I5 => \dec_cnt[5]_i_7_n_0\,
      O => \dec_cnt[0]_i_2_n_0\
    );
\dec_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF400F400F4FFF4"
    )
        port map (
      I0 => \dec_cnt[5]_i_9_n_0\,
      I1 => \dec_cnt_reg[2]_i_3_n_5\,
      I2 => \dec_cnt[1]_i_2_n_0\,
      I3 => fine_adj_state_r(0),
      I4 => \dec_cnt_reg_n_0_[1]\,
      I5 => \dec_cnt_reg_n_0_[0]\,
      O => dec_cnt(1)
    );
\dec_cnt[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080808000C0C00"
    )
        port map (
      I0 => \dec_cnt[1]_i_3_n_0\,
      I1 => detect_pi_found_dqs,
      I2 => \^pi_dqs_found_all_bank\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[2]\,
      I5 => \dec_cnt[4]_i_7_n_0\,
      O => \dec_cnt[1]_i_2_n_0\
    );
\dec_cnt[1]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1F10"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[2]\,
      I1 => \first_fail_taps[5]_i_3_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I3 => \dec_cnt_reg[2]_i_3_n_5\,
      O => \dec_cnt[1]_i_3_n_0\
    );
\dec_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"909F90909F9F9F9F"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[2]\,
      I1 => \dec_cnt[2]_i_2_n_0\,
      I2 => fine_adj_state_r(0),
      I3 => \dec_cnt[5]_i_9_n_0\,
      I4 => \dec_cnt_reg[2]_i_3_n_4\,
      I5 => \dec_cnt[2]_i_4_n_0\,
      O => dec_cnt(2)
    );
\dec_cnt[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[1]\,
      I1 => \dec_cnt_reg_n_0_[0]\,
      O => \dec_cnt[2]_i_2_n_0\
    );
\dec_cnt[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEAEFEAEAEAEFE"
    )
        port map (
      I0 => \dec_cnt[5]_i_7_n_0\,
      I1 => \dec_cnt[2]_i_9_n_0\,
      I2 => \dec_cnt[4]_i_7_n_0\,
      I3 => \dec_cnt_reg[2]_i_3_n_4\,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I5 => \first_fail_taps_reg_n_0_[3]\,
      O => \dec_cnt[2]_i_4_n_0\
    );
\dec_cnt[2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \first_fail_taps_reg_n_0_[3]\,
      O => \dec_cnt[2]_i_5_n_0\
    );
\dec_cnt[2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[2]\,
      I1 => \first_fail_taps_reg_n_0_[2]\,
      O => \dec_cnt[2]_i_6_n_0\
    );
\dec_cnt[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[1]\,
      I1 => \first_fail_taps_reg_n_0_[1]\,
      O => \dec_cnt[2]_i_7_n_0\
    );
\dec_cnt[2]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \first_fail_taps_reg_n_0_[0]\,
      O => \dec_cnt[2]_i_8_n_0\
    );
\dec_cnt[2]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \inc_cnt_reg_n_0_[1]\,
      I2 => \inc_cnt_reg_n_0_[2]\,
      O => \dec_cnt[2]_i_9_n_0\
    );
\dec_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"909F90909F9F9F9F"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[3]\,
      I1 => \dec_cnt[3]_i_2_n_0\,
      I2 => fine_adj_state_r(0),
      I3 => \dec_cnt[5]_i_9_n_0\,
      I4 => \dec_cnt_reg[4]_i_3_n_7\,
      I5 => \dec_cnt[3]_i_3_n_0\,
      O => dec_cnt(3)
    );
\dec_cnt[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[2]\,
      I1 => \dec_cnt_reg_n_0_[0]\,
      I2 => \dec_cnt_reg_n_0_[1]\,
      O => \dec_cnt[3]_i_2_n_0\
    );
\dec_cnt[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEAEFEAEAEAEFE"
    )
        port map (
      I0 => \dec_cnt[5]_i_7_n_0\,
      I1 => \dec_cnt[3]_i_4_n_0\,
      I2 => \dec_cnt[4]_i_7_n_0\,
      I3 => \dec_cnt_reg[4]_i_3_n_7\,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I5 => \first_fail_taps_reg_n_0_[4]\,
      O => \dec_cnt[3]_i_3_n_0\
    );
\dec_cnt[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9555"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[4]\,
      I1 => \inc_cnt_reg_n_0_[3]\,
      I2 => \inc_cnt_reg_n_0_[2]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      O => \dec_cnt[3]_i_4_n_0\
    );
\dec_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"909F90909F9F9F9F"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[4]\,
      I1 => \dec_cnt[4]_i_2_n_0\,
      I2 => fine_adj_state_r(0),
      I3 => \dec_cnt[5]_i_9_n_0\,
      I4 => \dec_cnt_reg[4]_i_3_n_6\,
      I5 => \dec_cnt[4]_i_4_n_0\,
      O => dec_cnt(4)
    );
\dec_cnt[4]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[1]\,
      I1 => \inc_cnt_reg_n_0_[2]\,
      I2 => \inc_cnt_reg_n_0_[3]\,
      O => \dec_cnt[4]_i_10_n_0\
    );
\dec_cnt[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[3]\,
      I1 => \dec_cnt_reg_n_0_[1]\,
      I2 => \dec_cnt_reg_n_0_[0]\,
      I3 => \dec_cnt_reg_n_0_[2]\,
      O => \dec_cnt[4]_i_2_n_0\
    );
\dec_cnt[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFE0EF0000"
    )
        port map (
      I0 => \first_fail_taps[5]_i_3_n_0\,
      I1 => \first_fail_taps_reg_n_0_[5]\,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I3 => \dec_cnt_reg[4]_i_3_n_6\,
      I4 => \dec_cnt[4]_i_7_n_0\,
      I5 => \dec_cnt[4]_i_8_n_0\,
      O => \dec_cnt[4]_i_4_n_0\
    );
\dec_cnt[4]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \first_fail_taps_reg_n_0_[5]\,
      O => \dec_cnt[4]_i_5_n_0\
    );
\dec_cnt[4]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[4]\,
      I1 => \first_fail_taps_reg_n_0_[4]\,
      O => \dec_cnt[4]_i_6_n_0\
    );
\dec_cnt[4]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEFFEF"
    )
        port map (
      I0 => \first_fail_taps[5]_i_3_n_0\,
      I1 => first_fail_detect_reg_n_0,
      I2 => \inc_cnt_reg_n_0_[4]\,
      I3 => \dec_cnt[4]_i_9_n_0\,
      I4 => \inc_cnt_reg_n_0_[5]\,
      O => \dec_cnt[4]_i_7_n_0\
    );
\dec_cnt[4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00001000FFFFFFFF"
    )
        port map (
      I0 => first_fail_detect_reg_n_0,
      I1 => \first_fail_taps[5]_i_3_n_0\,
      I2 => \inc_cnt_reg_n_0_[5]\,
      I3 => \inc_cnt_reg_n_0_[4]\,
      I4 => \dec_cnt[4]_i_10_n_0\,
      I5 => \stable_pass_cnt_reg[4]_0\,
      O => \dec_cnt[4]_i_8_n_0\
    );
\dec_cnt[4]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \inc_cnt_reg_n_0_[1]\,
      I2 => \inc_cnt_reg_n_0_[3]\,
      I3 => \inc_cnt_reg_n_0_[2]\,
      O => \dec_cnt[4]_i_9_n_0\
    );
\dec_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002A22"
    )
        port map (
      I0 => \dec_cnt[5]_i_3_n_0\,
      I1 => fine_adj_state_r(0),
      I2 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I3 => \dec_cnt[5]_i_4_n_0\,
      I4 => fine_adj_state_r(2),
      I5 => \dec_cnt[5]_i_5_n_0\,
      O => \dec_cnt[5]_i_1_n_0\
    );
\dec_cnt[5]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABFFFFFFF"
    )
        port map (
      I0 => first_fail_detect_reg_n_0,
      I1 => stable_pass_cnt_reg(2),
      I2 => stable_pass_cnt_reg(3),
      I3 => stable_pass_cnt_reg(1),
      I4 => stable_pass_cnt_reg(4),
      I5 => stable_pass_cnt_reg(5),
      O => \dec_cnt[5]_i_10_n_0\
    );
\dec_cnt[5]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[5]\,
      I1 => \first_fail_taps_reg_n_0_[4]\,
      I2 => \first_fail_taps_reg_n_0_[3]\,
      I3 => \first_fail_taps_reg_n_0_[2]\,
      I4 => \first_fail_taps_reg_n_0_[1]\,
      O => \dec_cnt[5]_i_11_n_0\
    );
\dec_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9F9F9F9090909090"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[5]\,
      I1 => \dec_cnt[5]_i_6_n_0\,
      I2 => fine_adj_state_r(0),
      I3 => \dec_cnt[5]_i_7_n_0\,
      I4 => \dec_cnt[5]_i_8_n_0\,
      I5 => \dec_cnt[5]_i_9_n_0\,
      O => dec_cnt(5)
    );
\dec_cnt[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCCFCCFDCCCDCC"
    )
        port map (
      I0 => \first_fail_taps[5]_i_4_n_0\,
      I1 => fine_adj_state_r(0),
      I2 => \^pi_dqs_found_all_bank\,
      I3 => detect_pi_found_dqs,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I5 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\,
      O => \dec_cnt[5]_i_3_n_0\
    );
\dec_cnt[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[5]\,
      I1 => \dec_cnt_reg_n_0_[3]\,
      I2 => \dec_cnt_reg_n_0_[1]\,
      I3 => \dec_cnt_reg_n_0_[0]\,
      I4 => \dec_cnt_reg_n_0_[2]\,
      I5 => \dec_cnt_reg_n_0_[4]\,
      O => \dec_cnt[5]_i_4_n_0\
    );
\dec_cnt[5]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => fine_adj_state_r(3),
      I1 => fine_adj_state_r(1),
      O => \dec_cnt[5]_i_5_n_0\
    );
\dec_cnt[5]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[4]\,
      I1 => \dec_cnt_reg_n_0_[2]\,
      I2 => \dec_cnt_reg_n_0_[0]\,
      I3 => \dec_cnt_reg_n_0_[1]\,
      I4 => \dec_cnt_reg_n_0_[3]\,
      O => \dec_cnt[5]_i_6_n_0\
    );
\dec_cnt[5]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F8FF"
    )
        port map (
      I0 => \first_fail_taps[5]_i_3_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I2 => \^pi_dqs_found_all_bank\,
      I3 => detect_pi_found_dqs,
      O => \dec_cnt[5]_i_7_n_0\
    );
\dec_cnt[5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080000000"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \inc_cnt_reg_n_0_[2]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[4]\,
      I4 => \inc_cnt_reg_n_0_[5]\,
      I5 => \dec_cnt[5]_i_10_n_0\,
      O => \dec_cnt[5]_i_8_n_0\
    );
\dec_cnt[5]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBFB"
    )
        port map (
      I0 => \dec_cnt[5]_i_11_n_0\,
      I1 => first_fail_detect_reg_n_0,
      I2 => detect_pi_found_dqs,
      I3 => \^pi_dqs_found_all_bank\,
      O => \dec_cnt[5]_i_9_n_0\
    );
\dec_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(0),
      Q => \dec_cnt_reg_n_0_[0]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\dec_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(1),
      Q => \dec_cnt_reg_n_0_[1]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\dec_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(2),
      Q => \dec_cnt_reg_n_0_[2]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\dec_cnt_reg[2]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \dec_cnt_reg[2]_i_3_n_0\,
      CO(2) => \dec_cnt_reg[2]_i_3_n_1\,
      CO(1) => \dec_cnt_reg[2]_i_3_n_2\,
      CO(0) => \dec_cnt_reg[2]_i_3_n_3\,
      CYINIT => '1',
      DI(3) => \inc_cnt_reg_n_0_[3]\,
      DI(2) => \inc_cnt_reg_n_0_[2]\,
      DI(1) => \inc_cnt_reg_n_0_[1]\,
      DI(0) => \inc_cnt_reg_n_0_[0]\,
      O(3) => \dec_cnt_reg[2]_i_3_n_4\,
      O(2) => \dec_cnt_reg[2]_i_3_n_5\,
      O(1) => \dec_cnt_reg[2]_i_3_n_6\,
      O(0) => \NLW_dec_cnt_reg[2]_i_3_O_UNCONNECTED\(0),
      S(3) => \dec_cnt[2]_i_5_n_0\,
      S(2) => \dec_cnt[2]_i_6_n_0\,
      S(1) => \dec_cnt[2]_i_7_n_0\,
      S(0) => \dec_cnt[2]_i_8_n_0\
    );
\dec_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(3),
      Q => \dec_cnt_reg_n_0_[3]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\dec_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(4),
      Q => \dec_cnt_reg_n_0_[4]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\dec_cnt_reg[4]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \dec_cnt_reg[2]_i_3_n_0\,
      CO(3 downto 1) => \NLW_dec_cnt_reg[4]_i_3_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \dec_cnt_reg[4]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \inc_cnt_reg_n_0_[4]\,
      O(3 downto 2) => \NLW_dec_cnt_reg[4]_i_3_O_UNCONNECTED\(3 downto 2),
      O(1) => \dec_cnt_reg[4]_i_3_n_6\,
      O(0) => \dec_cnt_reg[4]_i_3_n_7\,
      S(3 downto 2) => B"00",
      S(1) => \dec_cnt[4]_i_5_n_0\,
      S(0) => \dec_cnt[4]_i_6_n_0\
    );
\dec_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(5),
      Q => \dec_cnt_reg_n_0_[5]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\detect_rd_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => detect_rd_cnt_reg(0),
      O => \detect_rd_cnt0__0\(0)
    );
\detect_rd_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => detect_rd_cnt_reg(1),
      I1 => detect_rd_cnt_reg(0),
      O => \detect_rd_cnt[1]_i_1_n_0\
    );
\detect_rd_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => detect_rd_cnt_reg(2),
      I1 => detect_rd_cnt_reg(0),
      I2 => detect_rd_cnt_reg(1),
      O => \detect_rd_cnt0__0\(2)
    );
\detect_rd_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAAB"
    )
        port map (
      I0 => \pi_rst_stg1_cal_r1_reg[0]_0\,
      I1 => detect_rd_cnt_reg(2),
      I2 => detect_rd_cnt_reg(3),
      I3 => detect_rd_cnt_reg(1),
      I4 => detect_rd_cnt_reg(0),
      O => \detect_rd_cnt[3]_i_1_n_0\
    );
\detect_rd_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => detect_pi_found_dqs,
      I1 => detect_rd_cnt_reg(2),
      I2 => detect_rd_cnt_reg(3),
      I3 => detect_rd_cnt_reg(1),
      I4 => detect_rd_cnt_reg(0),
      O => detect_rd_cnt0
    );
\detect_rd_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => detect_rd_cnt_reg(3),
      I1 => detect_rd_cnt_reg(2),
      I2 => detect_rd_cnt_reg(1),
      I3 => detect_rd_cnt_reg(0),
      O => \detect_rd_cnt0__0\(3)
    );
\detect_rd_cnt_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => detect_rd_cnt0,
      D => \detect_rd_cnt0__0\(0),
      Q => detect_rd_cnt_reg(0),
      S => \detect_rd_cnt[3]_i_1_n_0\
    );
\detect_rd_cnt_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => detect_rd_cnt0,
      D => \detect_rd_cnt[1]_i_1_n_0\,
      Q => detect_rd_cnt_reg(1),
      S => \detect_rd_cnt[3]_i_1_n_0\
    );
\detect_rd_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => detect_rd_cnt0,
      D => \detect_rd_cnt0__0\(2),
      Q => detect_rd_cnt_reg(2),
      S => \detect_rd_cnt[3]_i_1_n_0\
    );
\detect_rd_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => detect_rd_cnt0,
      D => \detect_rd_cnt0__0\(3),
      Q => detect_rd_cnt_reg(3),
      R => \detect_rd_cnt[3]_i_1_n_0\
    );
dqs_found_done_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => dqs_found_done_r_i_2_n_0,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => init_dqsfound_done_r1_reg_n_0,
      O => dqs_found_done_r0
    );
dqs_found_done_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => fine_adj_state_r(3),
      I1 => \^pi_dqs_found_all_bank\,
      I2 => fine_adj_state_r(1),
      I3 => fine_adj_state_r(2),
      I4 => fine_adj_state_r(0),
      O => dqs_found_done_r_i_2_n_0
    );
dqs_found_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => dqs_found_done_r0,
      Q => \^pi_dqs_found_done\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
dqs_found_prech_req_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF4500000045"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => dqs_found_prech_req_i_2_n_0,
      I2 => dqs_found_prech_req_i_3_n_0,
      I3 => \dec_cnt[5]_i_5_n_0\,
      I4 => dqs_found_prech_req_i_4_n_0,
      I5 => \^dqs_found_prech_req\,
      O => dqs_found_prech_req_i_1_n_0
    );
dqs_found_prech_req_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0B"
    )
        port map (
      I0 => \^pi_dqs_found_all_bank\,
      I1 => detect_pi_found_dqs,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\,
      O => dqs_found_prech_req_i_2_n_0
    );
dqs_found_prech_req_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEBFFFFFF7FD7"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \inc_cnt_reg_n_0_[4]\,
      I2 => \inc_cnt_reg_n_0_[2]\,
      I3 => \inc_cnt_reg_n_0_[3]\,
      I4 => dqs_found_prech_req_i_5_n_0,
      I5 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\,
      O => dqs_found_prech_req_i_3_n_0
    );
dqs_found_prech_req_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FFFFA8FFFFFFA8"
    )
        port map (
      I0 => dqs_found_prech_req_i_6_n_0,
      I1 => dqs_found_prech_req_i_7_n_0,
      I2 => \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\,
      I3 => fine_adj_state_r(0),
      I4 => fine_adj_state_r(2),
      I5 => prech_done,
      O => dqs_found_prech_req_i_4_n_0
    );
dqs_found_prech_req_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[1]\,
      I1 => \inc_cnt_reg_n_0_[0]\,
      O => dqs_found_prech_req_i_5_n_0
    );
dqs_found_prech_req_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF707FFFFFFFF"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[2]_i_6_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[2]_i_4_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\,
      I3 => \FSM_sequential_fine_adj_state_r[2]_i_5_n_0\,
      I4 => \^pi_dqs_found_all_bank\,
      I5 => detect_pi_found_dqs,
      O => dqs_found_prech_req_i_6_n_0
    );
dqs_found_prech_req_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^pi_dqs_found_all_bank\,
      I1 => detect_pi_found_dqs,
      O => dqs_found_prech_req_i_7_n_0
    );
dqs_found_prech_req_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => dqs_found_prech_req_i_1_n_0,
      Q => \^dqs_found_prech_req\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
dqs_found_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => dqs_found_start_r_reg_0,
      Q => dqs_found_start_r,
      R => '0'
    );
final_dec_done_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF54"
    )
        port map (
      I0 => final_dec_done_i_2_n_0,
      I1 => init_dec_done_reg_n_0,
      I2 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I3 => final_dec_done_reg_n_0,
      O => final_dec_done_i_1_n_0
    );
final_dec_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF7"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(1),
      I3 => fine_adj_state_r(0),
      I4 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I5 => \dec_cnt[5]_i_4_n_0\,
      O => final_dec_done_i_2_n_0
    );
final_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => final_dec_done_i_1_n_0,
      Q => final_dec_done_reg_n_0,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
fine_adjust_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000040"
    )
        port map (
      I0 => fine_adj_state_r(3),
      I1 => \^pi_dqs_found_all_bank\,
      I2 => fine_adj_state_r(1),
      I3 => fine_adj_state_r(2),
      I4 => fine_adj_state_r(0),
      I5 => \^fine_adjust_done_r_reg_0\,
      O => fine_adjust_done_r_i_1_n_0
    );
fine_adjust_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fine_adjust_done_r_i_1_n_0,
      Q => \^fine_adjust_done_r_reg_0\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
fine_adjust_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010000"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(0),
      I3 => fine_adj_state_r(1),
      I4 => init_dqsfound_done_r5,
      I5 => fine_adjust_reg_n_0,
      O => fine_adjust_i_1_n_0
    );
fine_adjust_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fine_adjust_i_1_n_0,
      Q => fine_adjust_reg_n_0,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
first_fail_detect_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007FFFFFFFFFFF"
    )
        port map (
      I0 => stable_pass_cnt_reg(2),
      I1 => stable_pass_cnt_reg(3),
      I2 => stable_pass_cnt_reg(1),
      I3 => stable_pass_cnt_reg(4),
      I4 => stable_pass_cnt_reg(5),
      I5 => first_fail_detect_reg_n_0,
      O => first_fail_detect_i_1_n_0
    );
first_fail_detect_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => first_fail_detect_i_1_n_0,
      Q => first_fail_detect_reg_n_0,
      R => first_fail_detect_reg_0
    );
\first_fail_taps[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \first_fail_taps[5]_i_4_n_0\,
      I2 => \first_fail_taps[5]_i_3_n_0\,
      O => \first_fail_taps[0]_i_1_n_0\
    );
\first_fail_taps[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[1]\,
      I1 => \first_fail_taps[5]_i_4_n_0\,
      I2 => \first_fail_taps[5]_i_3_n_0\,
      O => \first_fail_taps[1]_i_1_n_0\
    );
\first_fail_taps[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[2]\,
      I1 => \first_fail_taps[5]_i_4_n_0\,
      I2 => \first_fail_taps[5]_i_3_n_0\,
      O => \first_fail_taps[2]_i_1_n_0\
    );
\first_fail_taps[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \first_fail_taps[5]_i_4_n_0\,
      I2 => \first_fail_taps[5]_i_3_n_0\,
      O => \first_fail_taps[3]_i_1_n_0\
    );
\first_fail_taps[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[4]\,
      I1 => \first_fail_taps[5]_i_4_n_0\,
      I2 => \first_fail_taps[5]_i_3_n_0\,
      O => \first_fail_taps[4]_i_1_n_0\
    );
\first_fail_taps[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D0"
    )
        port map (
      I0 => first_fail_detect_reg_n_0,
      I1 => \first_fail_taps[5]_i_3_n_0\,
      I2 => stable_pass_cnt,
      I3 => \^pi_dqs_found_all_bank\,
      O => first_fail_detect
    );
\first_fail_taps[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \first_fail_taps[5]_i_4_n_0\,
      I2 => \first_fail_taps[5]_i_3_n_0\,
      O => \first_fail_taps[5]_i_2_n_0\
    );
\first_fail_taps[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15555555"
    )
        port map (
      I0 => stable_pass_cnt_reg(5),
      I1 => stable_pass_cnt_reg(4),
      I2 => stable_pass_cnt_reg(1),
      I3 => stable_pass_cnt_reg(3),
      I4 => stable_pass_cnt_reg(2),
      O => \first_fail_taps[5]_i_3_n_0\
    );
\first_fail_taps[5]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"75F5"
    )
        port map (
      I0 => first_fail_detect_reg_n_0,
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I2 => \first_fail_taps[5]_i_3_n_0\,
      I3 => \first_fail_taps[5]_i_5_n_0\,
      O => \first_fail_taps[5]_i_4_n_0\
    );
\first_fail_taps[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \inc_cnt_reg_n_0_[2]\,
      I2 => \inc_cnt_reg_n_0_[4]\,
      I3 => \inc_cnt_reg_n_0_[3]\,
      I4 => \inc_cnt_reg_n_0_[0]\,
      I5 => \inc_cnt_reg_n_0_[1]\,
      O => \first_fail_taps[5]_i_5_n_0\
    );
\first_fail_taps_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => \first_fail_taps[0]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[0]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\first_fail_taps_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => \first_fail_taps[1]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[1]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\first_fail_taps_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => \first_fail_taps[2]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[2]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\first_fail_taps_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => \first_fail_taps[3]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[3]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\first_fail_taps_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => \first_fail_taps[4]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[4]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\first_fail_taps_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => \first_fail_taps[5]_i_2_n_0\,
      Q => \first_fail_taps_reg_n_0_[5]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_0
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_1
    );
ififo_rst_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4050"
    )
        port map (
      I0 => calib_zero_inputs,
      I1 => ofifo_rst_reg,
      I2 => rst_stg1_cal,
      I3 => ofifo_rst_reg_0,
      I4 => phy_if_reset,
      O => ififo_rst_reg0
    );
\ififo_rst_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF5400"
    )
        port map (
      I0 => calib_zero_inputs,
      I1 => ofifo_rst_reg,
      I2 => ofifo_rst_reg_0,
      I3 => rst_stg1_cal,
      I4 => phy_if_reset,
      O => ififo_rst_reg0_1
    );
\inc_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      O => \p_0_in__0\(0)
    );
\inc_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[1]\,
      I1 => \inc_cnt_reg_n_0_[0]\,
      O => \p_0_in__0\(1)
    );
\inc_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[2]\,
      I1 => \inc_cnt_reg_n_0_[0]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      O => \inc_cnt[2]_i_1_n_0\
    );
\inc_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \inc_cnt_reg_n_0_[2]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[0]\,
      O => \inc_cnt[3]_i_1_n_0\
    );
\inc_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[4]\,
      I1 => \inc_cnt_reg_n_0_[2]\,
      I2 => \inc_cnt_reg_n_0_[3]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[0]\,
      O => \inc_cnt[4]_i_1_n_0\
    );
\inc_cnt[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => fine_adj_state_r(3),
      I1 => fine_adj_state_r(2),
      I2 => fine_adj_state_r(1),
      I3 => fine_adj_state_r(0),
      O => inc_cnt
    );
\inc_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \inc_cnt_reg_n_0_[0]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[3]\,
      I4 => \inc_cnt_reg_n_0_[2]\,
      I5 => \inc_cnt_reg_n_0_[4]\,
      O => \p_0_in__0\(5)
    );
\inc_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => inc_cnt,
      D => \p_0_in__0\(0),
      Q => \inc_cnt_reg_n_0_[0]\,
      R => SR(0)
    );
\inc_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => inc_cnt,
      D => \p_0_in__0\(1),
      Q => \inc_cnt_reg_n_0_[1]\,
      R => SR(0)
    );
\inc_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => inc_cnt,
      D => \inc_cnt[2]_i_1_n_0\,
      Q => \inc_cnt_reg_n_0_[2]\,
      R => SR(0)
    );
\inc_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => inc_cnt,
      D => \inc_cnt[3]_i_1_n_0\,
      Q => \inc_cnt_reg_n_0_[3]\,
      R => SR(0)
    );
\inc_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => inc_cnt,
      D => \inc_cnt[4]_i_1_n_0\,
      Q => \inc_cnt_reg_n_0_[4]\,
      R => SR(0)
    );
\inc_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => inc_cnt,
      D => \p_0_in__0\(5),
      Q => \inc_cnt_reg_n_0_[5]\,
      R => SR(0)
    );
\init_dec_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_dec_cnt_reg(0),
      O => init_dec_cnt0(0)
    );
\init_dec_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => init_dec_cnt_reg(1),
      I1 => init_dec_cnt_reg(0),
      O => \init_dec_cnt[1]_i_1_n_0\
    );
\init_dec_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => init_dec_cnt_reg(1),
      I1 => init_dec_cnt_reg(0),
      I2 => init_dec_cnt_reg(2),
      O => init_dec_cnt0(2)
    );
\init_dec_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => init_dec_cnt_reg(2),
      I1 => init_dec_cnt_reg(0),
      I2 => init_dec_cnt_reg(1),
      I3 => init_dec_cnt_reg(3),
      O => init_dec_cnt0(3)
    );
\init_dec_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => init_dec_cnt_reg(3),
      I1 => init_dec_cnt_reg(1),
      I2 => init_dec_cnt_reg(0),
      I3 => init_dec_cnt_reg(2),
      I4 => init_dec_cnt_reg(4),
      O => init_dec_cnt0(4)
    );
\init_dec_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000000"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I1 => fine_adj_state_r(0),
      I2 => fine_adj_state_r(2),
      I3 => fine_adj_state_r(1),
      I4 => fine_adj_state_r(3),
      O => init_dec_cnt
    );
\init_dec_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => init_dec_cnt_reg(4),
      I1 => init_dec_cnt_reg(2),
      I2 => init_dec_cnt_reg(0),
      I3 => init_dec_cnt_reg(1),
      I4 => init_dec_cnt_reg(3),
      I5 => init_dec_cnt_reg(5),
      O => init_dec_cnt0(5)
    );
\init_dec_cnt_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => init_dec_cnt,
      D => init_dec_cnt0(0),
      Q => init_dec_cnt_reg(0),
      S => SR(0)
    );
\init_dec_cnt_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => init_dec_cnt,
      D => \init_dec_cnt[1]_i_1_n_0\,
      Q => init_dec_cnt_reg(1),
      S => SR(0)
    );
\init_dec_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => init_dec_cnt,
      D => init_dec_cnt0(2),
      Q => init_dec_cnt_reg(2),
      S => SR(0)
    );
\init_dec_cnt_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => init_dec_cnt,
      D => init_dec_cnt0(3),
      Q => init_dec_cnt_reg(3),
      S => SR(0)
    );
\init_dec_cnt_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => init_dec_cnt,
      D => init_dec_cnt0(4),
      Q => init_dec_cnt_reg(4),
      S => SR(0)
    );
\init_dec_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => init_dec_cnt,
      D => init_dec_cnt0(5),
      Q => init_dec_cnt_reg(5),
      R => SR(0)
    );
init_dec_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABAAAAAAAAAAAAAA"
    )
        port map (
      I0 => init_dec_done_reg_n_0,
      I1 => \dec_cnt[5]_i_4_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I3 => init_dec_done_i_2_n_0,
      I4 => fine_adj_state_r(3),
      I5 => fine_adj_state_r(2),
      O => init_dec_done_i_1_n_0
    );
init_dec_done_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fine_adj_state_r(0),
      I1 => fine_adj_state_r(1),
      O => init_dec_done_i_2_n_0
    );
init_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_dec_done_i_1_n_0,
      Q => init_dec_done_reg_n_0,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
init_dqsfound_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^init_dqsfound_done_r_reg_0\,
      Q => init_dqsfound_done_r1_reg_n_0,
      R => '0'
    );
init_dqsfound_done_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_dqsfound_done_r1_reg_n_0,
      Q => \^init_dqsfound_done_r2\,
      R => '0'
    );
init_dqsfound_done_r4_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => \^init_dqsfound_done_r2\,
      Q => init_dqsfound_done_r4_reg_srl2_n_0
    );
init_dqsfound_done_r5_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_dqsfound_done_r4_reg_srl2_n_0,
      Q => init_dqsfound_done_r5,
      R => '0'
    );
init_dqsfound_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000222E"
    )
        port map (
      I0 => \^init_dqsfound_done_r_reg_0\,
      I1 => \^pi_dqs_found_all_bank\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \rnk_cnt_r_reg_n_0_[1]\,
      I4 => pi_rst_stg1_cal_r,
      O => init_dqsfound_done_r_i_1_n_0
    );
init_dqsfound_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_dqsfound_done_r_i_1_n_0,
      Q => \^init_dqsfound_done_r_reg_0\,
      R => init_dqsfound_done_r_reg_1
    );
\init_state_r[1]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^pi_dqs_found_done\,
      I1 => \^pi_dqs_found_rank_done\,
      I2 => \init_state_r[1]_i_14\,
      O => dqs_found_done_r_reg_1
    );
\init_state_r[2]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => \^pi_dqs_found_done\,
      I1 => D(0),
      I2 => Q(0),
      O => dqs_found_done_r_reg_0
    );
ofifo_rst_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4050"
    )
        port map (
      I0 => calib_zero_inputs,
      I1 => ofifo_rst_reg,
      I2 => rst_stg1_cal,
      I3 => ofifo_rst_reg_0,
      I4 => A_rst_primitives,
      O => ofifo_rst_reg0
    );
\ofifo_rst_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF5400"
    )
        port map (
      I0 => calib_zero_inputs,
      I1 => ofifo_rst_reg,
      I2 => ofifo_rst_reg_0,
      I3 => rst_stg1_cal,
      I4 => A_rst_primitives,
      O => ofifo_rst_reg0_2
    );
\phaser_in_gen.phaser_in_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C4"
    )
        port map (
      I0 => ofifo_rst_reg_0,
      I1 => rst_stg1_cal,
      I2 => ofifo_rst_reg,
      I3 => calib_zero_inputs,
      O => \calib_sel_reg[1]_0\
    );
\phaser_in_gen.phaser_in_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => rst_stg1_cal,
      I1 => ofifo_rst_reg_0,
      I2 => ofifo_rst_reg,
      I3 => calib_zero_inputs,
      O => \pi_rst_stg1_cal_reg[0]_0\
    );
phaser_out_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000E00"
    )
        port map (
      I0 => \^ck_po_stg2_f_en\,
      I1 => po_en_s2_f,
      I2 => calib_zero_ctrl,
      I3 => ofifo_rst_reg,
      I4 => calib_zero_inputs,
      O => ck_po_stg2_f_en_reg_0
    );
\phaser_out_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C4"
    )
        port map (
      I0 => ofifo_rst_reg_0,
      I1 => po_stg2_fincdec(2),
      I2 => ofifo_rst_reg,
      I3 => calib_zero_inputs,
      O => \calib_sel_reg[1]\
    );
\phaser_out_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => po_stg2_fincdec(2),
      I1 => ofifo_rst_reg_0,
      I2 => ofifo_rst_reg,
      I3 => calib_zero_inputs,
      O => ck_po_stg2_f_indec_reg_1
    );
phaser_out_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => po_stg2_fincdec(2),
      I1 => calib_zero_ctrl,
      I2 => ofifo_rst_reg,
      I3 => calib_zero_inputs,
      O => ck_po_stg2_f_indec_reg_0
    );
\pi_dqs_found_all_bank[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => pi_dqs_found_lanes_r3(2),
      I1 => pi_dqs_found_lanes_r3(0),
      I2 => dqs_found_start_r_reg_0,
      I3 => \^pi_dqs_found_all_bank\,
      O => \pi_dqs_found_all_bank[0]_i_1_n_0\
    );
\pi_dqs_found_all_bank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^pi_dqs_found_all_bank\,
      Q => pi_dqs_found_all_bank_r,
      R => '0'
    );
\pi_dqs_found_all_bank_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_dqs_found_all_bank[0]_i_1_n_0\,
      Q => \^pi_dqs_found_all_bank\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\pi_dqs_found_any_bank[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFE0"
    )
        port map (
      I0 => pi_dqs_found_lanes_r3(2),
      I1 => pi_dqs_found_lanes_r3(0),
      I2 => dqs_found_start_r_reg_0,
      I3 => pi_dqs_found_any_bank,
      O => \pi_dqs_found_any_bank[0]_i_1_n_0\
    );
\pi_dqs_found_any_bank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_any_bank,
      Q => pi_dqs_found_any_bank_r,
      R => '0'
    );
\pi_dqs_found_any_bank_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_dqs_found_any_bank[0]_i_1_n_0\,
      Q => pi_dqs_found_any_bank,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\pi_dqs_found_lanes_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes(0),
      Q => pi_dqs_found_lanes_r1(0),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => n_0_1,
      Q => pi_dqs_found_lanes_r1(1),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes(1),
      Q => pi_dqs_found_lanes_r1(2),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => n_0_0,
      Q => pi_dqs_found_lanes_r1(3),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(0),
      Q => pi_dqs_found_lanes_r2(0),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(1),
      Q => pi_dqs_found_lanes_r2(1),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(2),
      Q => pi_dqs_found_lanes_r2(2),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(3),
      Q => pi_dqs_found_lanes_r2(3),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(0),
      Q => pi_dqs_found_lanes_r3(0),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(1),
      Q => pi_dqs_found_lanes_r3(1),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(2),
      Q => pi_dqs_found_lanes_r3(2),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(3),
      Q => pi_dqs_found_lanes_r3(3),
      R => '0'
    );
\pi_rst_stg1_cal[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => pi_rst_stg1_cal_r,
      I1 => \rst_dqs_find__0\,
      O => \pi_rst_stg1_cal[0]_i_1_n_0\
    );
\pi_rst_stg1_cal_r1[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFA8"
    )
        port map (
      I0 => \pi_rst_stg1_cal_r1_reg_n_0_[0]\,
      I1 => pi_dqs_found_any_bank_r,
      I2 => \^pi_dqs_found_all_bank\,
      I3 => pi_rst_stg1_cal_r,
      I4 => fine_adjust_reg_n_0,
      I5 => \pi_rst_stg1_cal_r1_reg[0]_0\,
      O => \pi_rst_stg1_cal_r1[0]_i_1_n_0\
    );
\pi_rst_stg1_cal_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_rst_stg1_cal_r1[0]_i_1_n_0\,
      Q => \pi_rst_stg1_cal_r1_reg_n_0_[0]\,
      R => '0'
    );
\pi_rst_stg1_cal_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011110111"
    )
        port map (
      I0 => fine_adjust_reg_n_0,
      I1 => \pi_rst_stg1_cal_r1_reg[0]_0\,
      I2 => \pi_rst_stg1_cal_r[0]_i_2_n_0\,
      I3 => \rd_byte_data_offset[0][5]_i_4_n_0\,
      I4 => pi_rst_stg1_cal_r,
      I5 => \pi_rst_stg1_cal_r1_reg_n_0_[0]\,
      O => \pi_rst_stg1_cal_r[0]_i_1_n_0\
    );
\pi_rst_stg1_cal_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B0BB"
    )
        port map (
      I0 => \^pi_dqs_found_all_bank\,
      I1 => pi_dqs_found_any_bank_r,
      I2 => dqs_found_start_r,
      I3 => dqs_found_start_r_reg_0,
      O => \pi_rst_stg1_cal_r[0]_i_2_n_0\
    );
\pi_rst_stg1_cal_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_rst_stg1_cal_r[0]_i_1_n_0\,
      Q => pi_rst_stg1_cal_r,
      R => '0'
    );
\pi_rst_stg1_cal_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_rst_stg1_cal[0]_i_1_n_0\,
      Q => rst_stg1_cal,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
rank_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^pi_dqs_found_rank_done\,
      Q => rank_done_r1,
      R => '0'
    );
rank_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000EF0000"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[1]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \^init_dqsfound_done_r_reg_0\,
      I3 => \pi_rst_stg1_cal_r1_reg[0]_0\,
      I4 => \^pi_dqs_found_all_bank\,
      I5 => pi_dqs_found_all_bank_r,
      O => rank_done_r_i_1_n_0
    );
rank_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rank_done_r_i_1_n_0,
      Q => \^pi_dqs_found_rank_done\,
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset[0][5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^init_dqsfound_done_r_reg_0\,
      I1 => init_dqsfound_done_r1_reg_n_0,
      O => p_0_in22_out
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => init_dqsfound_done_r1_reg_n_0,
      I1 => \^init_dqsfound_done_r_reg_0\,
      I2 => \pi_rst_stg1_cal_r1_reg[0]_0\,
      O => p_1_out(5)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_1_out(5),
      D => \rd_byte_data_offset_reg[0]_1\(0),
      Q => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(0),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_1_out(5),
      D => \^rd_byte_data_offset_reg[0][2]_0\(0),
      Q => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(1),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_1_out(5),
      D => \^rd_byte_data_offset_reg[0][2]_0\(1),
      Q => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(2),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_1_out(5),
      D => \rd_byte_data_offset_reg[0]_1\(3),
      Q => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(3),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_1_out(5),
      D => \rd_byte_data_offset_reg[0]_1\(4),
      Q => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(4),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_1_out(5),
      D => \rd_byte_data_offset_reg[0]_1\(5),
      Q => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(5),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_0_in22_out,
      D => \rd_byte_data_offset_reg[0]_1\(0),
      Q => rd_data_offset_ranks_0(0),
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_0_in22_out,
      D => \^rd_byte_data_offset_reg[0][2]_0\(0),
      Q => \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2]_0\(0),
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_0_in22_out,
      D => \^rd_byte_data_offset_reg[0][2]_0\(1),
      Q => \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2]_0\(1),
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_0_in22_out,
      D => \rd_byte_data_offset_reg[0]_1\(3),
      Q => rd_data_offset_ranks_0(3),
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_0_in22_out,
      D => \rd_byte_data_offset_reg[0]_1\(4),
      Q => rd_data_offset_ranks_0(4),
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_0_in22_out,
      D => \rd_byte_data_offset_reg[0]_1\(5),
      Q => rd_data_offset_ranks_0(5),
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\rd_byte_data_offset[0][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rd_byte_data_offset_reg[0]_1\(0),
      O => p_0_in(0)
    );
\rd_byte_data_offset[0][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^rd_byte_data_offset_reg[0][2]_0\(0),
      I1 => \rd_byte_data_offset_reg[0]_1\(0),
      O => p_0_in(1)
    );
\rd_byte_data_offset[0][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \^rd_byte_data_offset_reg[0][2]_0\(1),
      I1 => \rd_byte_data_offset_reg[0]_1\(0),
      I2 => \^rd_byte_data_offset_reg[0][2]_0\(0),
      O => p_0_in(2)
    );
\rd_byte_data_offset[0][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \rd_byte_data_offset_reg[0]_1\(3),
      I1 => \^rd_byte_data_offset_reg[0][2]_0\(0),
      I2 => \rd_byte_data_offset_reg[0]_1\(0),
      I3 => \^rd_byte_data_offset_reg[0][2]_0\(1),
      O => p_0_in(3)
    );
\rd_byte_data_offset[0][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \rd_byte_data_offset_reg[0]_1\(4),
      I1 => \rd_byte_data_offset_reg[0]_1\(3),
      I2 => \^rd_byte_data_offset_reg[0][2]_0\(1),
      I3 => \rd_byte_data_offset_reg[0]_1\(0),
      I4 => \^rd_byte_data_offset_reg[0][2]_0\(0),
      O => p_0_in(4)
    );
\rd_byte_data_offset[0][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAABFBB"
    )
        port map (
      I0 => \pi_rst_stg1_cal_r1_reg[0]_0\,
      I1 => \rd_byte_data_offset[0][5]_i_4_n_0\,
      I2 => \^init_dqsfound_done_r_reg_0\,
      I3 => rank_done_r1,
      I4 => \rnk_cnt_r_reg_n_0_[1]\,
      I5 => \rnk_cnt_r_reg_n_0_[0]\,
      O => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset[0][5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000D0"
    )
        port map (
      I0 => rank_done_r1,
      I1 => \^init_dqsfound_done_r_reg_0\,
      I2 => \rd_byte_data_offset[0][5]_i_4_n_0\,
      I3 => \rd_byte_data_offset[0][5]_i_5_n_0\,
      I4 => \rd_byte_data_offset[0][5]_i_6_n_0\,
      O => rd_byte_data_offset
    );
\rd_byte_data_offset[0][5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \rd_byte_data_offset_reg[0]_1\(5),
      I1 => \^rd_byte_data_offset_reg[0][2]_0\(0),
      I2 => \rd_byte_data_offset_reg[0]_1\(0),
      I3 => \^rd_byte_data_offset_reg[0][2]_0\(1),
      I4 => \rd_byte_data_offset_reg[0]_1\(3),
      I5 => \rd_byte_data_offset_reg[0]_1\(4),
      O => p_0_in(5)
    );
\rd_byte_data_offset[0][5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00015555"
    )
        port map (
      I0 => \rd_byte_data_offset_reg[0]_1\(5),
      I1 => \rd_byte_data_offset_reg[0]_1\(3),
      I2 => \^rd_byte_data_offset_reg[0][2]_0\(0),
      I3 => \^rd_byte_data_offset_reg[0][2]_0\(1),
      I4 => \rd_byte_data_offset_reg[0]_1\(4),
      O => \rd_byte_data_offset[0][5]_i_4_n_0\
    );
\rd_byte_data_offset[0][5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[0]\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => \^pi_dqs_found_all_bank\,
      I3 => fine_adjust_reg_n_0,
      I4 => \^init_dqsfound_done_r_reg_0\,
      I5 => dqs_found_start_r,
      O => \rd_byte_data_offset[0][5]_i_5_n_0\
    );
\rd_byte_data_offset[0][5]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFDF"
    )
        port map (
      I0 => detect_rd_cnt_reg(0),
      I1 => detect_rd_cnt_reg(1),
      I2 => detect_pi_found_dqs,
      I3 => detect_rd_cnt_reg(2),
      I4 => detect_rd_cnt_reg(3),
      O => \rd_byte_data_offset[0][5]_i_6_n_0\
    );
\rd_byte_data_offset_reg[0][0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => rd_byte_data_offset,
      D => p_0_in(0),
      Q => \rd_byte_data_offset_reg[0]_1\(0),
      S => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => rd_byte_data_offset,
      D => p_0_in(1),
      Q => \^rd_byte_data_offset_reg[0][2]_0\(0),
      S => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_byte_data_offset,
      D => p_0_in(2),
      Q => \^rd_byte_data_offset_reg[0][2]_0\(1),
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_byte_data_offset,
      D => p_0_in(3),
      Q => \rd_byte_data_offset_reg[0]_1\(3),
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_byte_data_offset,
      D => p_0_in(4),
      Q => \rd_byte_data_offset_reg[0]_1\(4),
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_byte_data_offset,
      D => p_0_in(5),
      Q => \rd_byte_data_offset_reg[0]_1\(5),
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rnk_cnt_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \^init_dqsfound_done_r_reg_0\,
      I1 => \^pi_dqs_found_rank_done\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      O => \rnk_cnt_r[0]_i_1_n_0\
    );
\rnk_cnt_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[0]\,
      I1 => \^pi_dqs_found_rank_done\,
      I2 => \^init_dqsfound_done_r_reg_0\,
      I3 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \rnk_cnt_r[1]_i_1_n_0\
    );
\rnk_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rnk_cnt_r[0]_i_1_n_0\,
      Q => \rnk_cnt_r_reg_n_0_[0]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\rnk_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rnk_cnt_r[1]_i_1_n_0\,
      Q => \rnk_cnt_r_reg_n_0_[1]\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
rst_dqs_find_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => rst_dqs_find,
      I1 => rst_dqs_find_i_3_n_0,
      I2 => rst_dqs_find_i_4_n_0,
      I3 => \rst_dqs_find__0\,
      O => rst_dqs_find_i_1_n_0
    );
rst_dqs_find_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDD05555DDD05550"
    )
        port map (
      I0 => fine_adj_state_r(0),
      I1 => prech_done,
      I2 => rst_dqs_find_i_5_n_0,
      I3 => fine_adj_state_r(2),
      I4 => fine_adj_state_r(1),
      I5 => init_dqsfound_done_r5,
      O => rst_dqs_find
    );
rst_dqs_find_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E0E00000E0E0FF0F"
    )
        port map (
      I0 => rst_dqs_find_i_6_n_0,
      I1 => rst_dqs_find_i_7_n_0,
      I2 => fine_adj_state_r(1),
      I3 => \^pi_dqs_found_all_bank\,
      I4 => fine_adj_state_r(3),
      I5 => fine_adj_state_r(2),
      O => rst_dqs_find_i_3_n_0
    );
rst_dqs_find_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F0F0D0DF"
    )
        port map (
      I0 => rst_dqs_find_r2,
      I1 => pi_dqs_found_any_bank,
      I2 => fine_adj_state_r(0),
      I3 => init_dqsfound_done_r5,
      I4 => fine_adj_state_r(1),
      I5 => rst_dqs_find_i_8_n_0,
      O => rst_dqs_find_i_4_n_0
    );
rst_dqs_find_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4444C044"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I1 => fine_adj_state_r(3),
      I2 => \first_fail_taps[5]_i_4_n_0\,
      I3 => detect_pi_found_dqs,
      I4 => \^pi_dqs_found_all_bank\,
      O => rst_dqs_find_i_5_n_0
    );
rst_dqs_find_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800080800000000"
    )
        port map (
      I0 => \first_fail_taps[5]_i_4_n_0\,
      I1 => detect_pi_found_dqs,
      I2 => \^pi_dqs_found_all_bank\,
      I3 => first_fail_detect_reg_n_0,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I5 => \dec_cnt[4]_i_7_n_0\,
      O => rst_dqs_find_i_6_n_0
    );
rst_dqs_find_i_7: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BAAAAAAA"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\,
      I2 => detect_pi_found_dqs,
      I3 => \^pi_dqs_found_all_bank\,
      I4 => \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\,
      O => rst_dqs_find_i_7_n_0
    );
rst_dqs_find_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => prech_done,
      O => rst_dqs_find_i_8_n_0
    );
rst_dqs_find_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rst_dqs_find__0\,
      Q => rst_dqs_find_r1,
      R => '0'
    );
rst_dqs_find_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rst_dqs_find_r1,
      Q => rst_dqs_find_r2,
      R => '0'
    );
rst_dqs_find_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rst_dqs_find_i_1_n_0,
      Q => \rst_dqs_find__0\,
      R => ck_po_stg2_f_indec_reg_2(0)
    );
\stable_pass_cnt[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \stable_pass_cnt_reg_n_0_[0]\,
      I1 => \^pi_dqs_found_all_bank\,
      O => \stable_pass_cnt[0]_i_1_n_0\
    );
\stable_pass_cnt[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \stable_pass_cnt_reg_n_0_[0]\,
      I1 => stable_pass_cnt_reg(1),
      I2 => \^pi_dqs_found_all_bank\,
      O => \p_0_in__1\(1)
    );
\stable_pass_cnt[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \^pi_dqs_found_all_bank\,
      I1 => stable_pass_cnt_reg(1),
      I2 => \stable_pass_cnt_reg_n_0_[0]\,
      I3 => stable_pass_cnt_reg(2),
      O => \stable_pass_cnt[2]_i_1_n_0\
    );
\stable_pass_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F800000"
    )
        port map (
      I0 => \stable_pass_cnt_reg_n_0_[0]\,
      I1 => stable_pass_cnt_reg(1),
      I2 => stable_pass_cnt_reg(2),
      I3 => stable_pass_cnt_reg(3),
      I4 => \^pi_dqs_found_all_bank\,
      O => \p_0_in__1\(3)
    );
\stable_pass_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => stable_pass_cnt_reg(2),
      I1 => stable_pass_cnt_reg(3),
      I2 => \stable_pass_cnt_reg_n_0_[0]\,
      I3 => stable_pass_cnt_reg(1),
      I4 => stable_pass_cnt_reg(4),
      I5 => \stable_pass_cnt_reg[4]_0\,
      O => \p_0_in__1\(4)
    );
\stable_pass_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => detect_pi_found_dqs,
      I2 => fine_adj_state_r(3),
      I3 => fine_adj_state_r(1),
      I4 => fine_adj_state_r(0),
      O => stable_pass_cnt
    );
\stable_pass_cnt[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \^pi_dqs_found_all_bank\,
      I1 => \stable_pass_cnt[5]_i_3_n_0\,
      I2 => \stable_pass_cnt_reg_n_0_[0]\,
      I3 => stable_pass_cnt_reg(5),
      O => \stable_pass_cnt[5]_i_2_n_0\
    );
\stable_pass_cnt[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => stable_pass_cnt_reg(2),
      I1 => stable_pass_cnt_reg(3),
      I2 => stable_pass_cnt_reg(1),
      I3 => stable_pass_cnt_reg(4),
      O => \stable_pass_cnt[5]_i_3_n_0\
    );
\stable_pass_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_pass_cnt,
      D => \stable_pass_cnt[0]_i_1_n_0\,
      Q => \stable_pass_cnt_reg_n_0_[0]\,
      R => SR(0)
    );
\stable_pass_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_pass_cnt,
      D => \p_0_in__1\(1),
      Q => stable_pass_cnt_reg(1),
      R => SR(0)
    );
\stable_pass_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_pass_cnt,
      D => \stable_pass_cnt[2]_i_1_n_0\,
      Q => stable_pass_cnt_reg(2),
      R => SR(0)
    );
\stable_pass_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_pass_cnt,
      D => \p_0_in__1\(3),
      Q => stable_pass_cnt_reg(3),
      R => SR(0)
    );
\stable_pass_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_pass_cnt,
      D => \p_0_in__1\(4),
      Q => stable_pass_cnt_reg(4),
      R => SR(0)
    );
\stable_pass_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_pass_cnt,
      D => \stable_pass_cnt[5]_i_2_n_0\,
      Q => stable_pass_cnt_reg(5),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_phy_init is
  port (
    prech_done : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    prech_req_posedge_r_reg_0 : out STD_LOGIC;
    prbs_rdlvl_done_pulse_reg_0 : out STD_LOGIC;
    pi_calib_done : out STD_LOGIC;
    wrcal_rd_wait : out STD_LOGIC;
    detect_pi_found_dqs : out STD_LOGIC;
    init_calib_complete_reg_0 : out STD_LOGIC;
    calib_ctl_wren_reg_0 : out STD_LOGIC;
    cnt_pwron_cke_done_r_reg_0 : out STD_LOGIC;
    pi_dqs_found_done_r1 : out STD_LOGIC;
    calib_wrdata_en : out STD_LOGIC;
    \one_rank.stg1_wr_done_reg_0\ : out STD_LOGIC;
    wrlvl_final_if_rst : out STD_LOGIC;
    rdlvl_stg1_start_reg_0 : out STD_LOGIC;
    phy_read_calib : out STD_LOGIC;
    first_rdlvl_pat_r : out STD_LOGIC;
    first_wrcal_pat_r : out STD_LOGIC;
    rdlvl_stg1_done_r1 : out STD_LOGIC;
    calib_ctl_wren_reg_1 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    phy_dout : out STD_LOGIC_VECTOR ( 40 downto 0 );
    \cmd_pipe_plus.mc_cas_n_reg[0]\ : out STD_LOGIC_VECTOR ( 25 downto 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[3]\ : out STD_LOGIC;
    \my_empty_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[3]_0\ : out STD_LOGIC;
    \my_empty_reg[5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[3]_1\ : out STD_LOGIC;
    stg1_wr_done : out STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[117]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \write_buffer.wr_buf_out_data_reg[126]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    mux_wrdata_en : out STD_LOGIC;
    mux_cmd_wren : out STD_LOGIC;
    D1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 4 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 4 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 4 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    D0 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[104]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[127]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[108]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[122]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[121]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[123]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[126]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    detect_pi_found_dqs_reg_0 : out STD_LOGIC;
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_ras_n_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[0]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \cmd_pipe_plus.mc_cas_n_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_cke_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_cas_n_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    wrcal_start_reg_0 : out STD_LOGIC;
    pi_dqs_found_start_reg_0 : out STD_LOGIC;
    mpr_rdlvl_start_reg_0 : out STD_LOGIC;
    \calib_seq_reg[1]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    CLK : in STD_LOGIC;
    in0 : in STD_LOGIC;
    \complex_address_reg[9]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    prbs_rdlvl_done_pulse0 : in STD_LOGIC;
    rdlvl_stg1_start_reg_1 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rdlvl_last_byte_done : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    init_complete_r_timing_reg_0 : in STD_LOGIC;
    p_128_in : in STD_LOGIC;
    pi_dqs_found_done : in STD_LOGIC;
    phy_ctl_wr_i1_reg : in STD_LOGIC;
    \wrcal_reads_reg[0]_0\ : in STD_LOGIC;
    \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : in STD_LOGIC;
    \wr_ptr_timing_reg[0]\ : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC;
    \wr_en_inferred__0_i_1_0\ : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_1\ : in STD_LOGIC;
    \wr_en_inferred__0_i_1__0_0\ : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_2\ : in STD_LOGIC;
    \wr_en_inferred__0_i_1__1_0\ : in STD_LOGIC;
    \calib_data_offset_0_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    init_dqsfound_done_r2 : in STD_LOGIC;
    \calib_data_offset_0_reg[2]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \complex_num_writes_reg[4]_0\ : in STD_LOGIC;
    \init_state_r[6]_i_9_0\ : in STD_LOGIC;
    \init_state_r[2]_i_11_0\ : in STD_LOGIC;
    \back_to_back_reads_4_1.num_reads_reg[1]_0\ : in STD_LOGIC;
    burst_addr_r_reg_0 : in STD_LOGIC;
    rdlvl_pi_incdec : in STD_LOGIC;
    dqs_found_prech_req : in STD_LOGIC;
    \stg1_wr_rd_cnt_reg[3]_0\ : in STD_LOGIC;
    wrcal_prech_req : in STD_LOGIC;
    rdlvl_stg1_rank_done : in STD_LOGIC;
    \init_state_r[2]_i_2_0\ : in STD_LOGIC;
    \init_state_r_reg[3]_i_10_0\ : in STD_LOGIC;
    \init_state_r_reg[1]_i_7_0\ : in STD_LOGIC;
    wrlvl_byte_redo : in STD_LOGIC;
    rdlvl_prech_req : in STD_LOGIC;
    pi_dqs_found_rank_done : in STD_LOGIC;
    cnt_pwron_cke_done_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    out_fifo : in STD_LOGIC_VECTOR ( 87 downto 0 );
    \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : in STD_LOGIC;
    \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_odt : in STD_LOGIC_VECTOR ( 0 to 0 );
    mem_reg_0_15_48_53 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \phy_ctl_wd_i1_reg[22]\ : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC_VECTOR ( 43 downto 0 );
    out_fifo_2 : in STD_LOGIC;
    out_fifo_3 : in STD_LOGIC;
    out_fifo_4 : in STD_LOGIC;
    out_fifo_5 : in STD_LOGIC_VECTOR ( 43 downto 0 );
    out_fifo_6 : in STD_LOGIC;
    out_fifo_7 : in STD_LOGIC;
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    pi_dqs_found_all_bank : in STD_LOGIC;
    out_fifo_8 : in STD_LOGIC_VECTOR ( 40 downto 0 );
    out_fifo_9 : in STD_LOGIC;
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : in STD_LOGIC_VECTOR ( 36 downto 0 );
    out_fifo_10 : in STD_LOGIC;
    mem_out : in STD_LOGIC_VECTOR ( 30 downto 0 );
    out_fifo_11 : in STD_LOGIC;
    mem_reg_0_15_60_65 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_state_r1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_data_offset_0_reg[5]_0\ : in STD_LOGIC;
    \calib_data_offset_0_reg[4]_0\ : in STD_LOGIC;
    \calib_data_offset_0_reg[3]_0\ : in STD_LOGIC;
    \calib_data_offset_0_reg[0]_0\ : in STD_LOGIC;
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_pwron_r_reg[0]_0\ : in STD_LOGIC;
    mc_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \phy_ctl_wd_i1_reg[17]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \phy_ctl_wd_i1_reg[20]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[21]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[22]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_phy_init : entity is "mig_7series_v4_2_ddr_phy_init";
end mig_7series_0_mig_7series_v4_2_ddr_phy_init;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_phy_init is
  signal \DDR3_1rank.phy_int_cs_n[0]_i_10_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[0]_i_1_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[0]_i_2_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[0]_i_3_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[0]_i_4_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[0]_i_5_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[0]_i_6_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[0]_i_7_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[0]_i_8_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[0]_i_9_n_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal address_w : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \back_to_back_reads_4_1.num_reads[0]_i_1_n_0\ : STD_LOGIC;
  signal \back_to_back_reads_4_1.num_reads[1]_i_1_n_0\ : STD_LOGIC;
  signal bank_w : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal burst_addr_r_i_1_n_0 : STD_LOGIC;
  signal burst_addr_r_i_2_n_0 : STD_LOGIC;
  signal burst_addr_r_reg_n_0 : STD_LOGIC;
  signal calib_cke : STD_LOGIC_VECTOR ( 3 to 3 );
  signal calib_cmd : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \calib_cmd[0]_i_1_n_0\ : STD_LOGIC;
  signal \calib_cmd[1]_i_1_n_0\ : STD_LOGIC;
  signal \calib_cmd[1]_i_2_n_0\ : STD_LOGIC;
  signal \calib_cmd[1]_i_3_n_0\ : STD_LOGIC;
  signal \calib_cmd[1]_i_4_n_0\ : STD_LOGIC;
  signal \calib_cmd[1]_i_5_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_1_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_2_n_0\ : STD_LOGIC;
  signal \^calib_ctl_wren_reg_0\ : STD_LOGIC;
  signal calib_data_offset_0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \calib_data_offset_0[1]_i_1_n_0\ : STD_LOGIC;
  signal \calib_data_offset_0[1]_i_2_n_0\ : STD_LOGIC;
  signal \calib_data_offset_0[2]_i_1_n_0\ : STD_LOGIC;
  signal \calib_data_offset_0[2]_i_2_n_0\ : STD_LOGIC;
  signal \calib_data_offset_0[5]_i_1_n_0\ : STD_LOGIC;
  signal calib_odt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \calib_odt[0]_i_1_n_0\ : STD_LOGIC;
  signal \calib_odt[0]_i_2_n_0\ : STD_LOGIC;
  signal \calib_odt[0]_i_3_n_0\ : STD_LOGIC;
  signal \calib_odt[0]_i_4_n_0\ : STD_LOGIC;
  signal \calib_odt[0]_i_5_n_0\ : STD_LOGIC;
  signal \calib_seq[0]_i_1_n_0\ : STD_LOGIC;
  signal \calib_seq[1]_i_1_n_0\ : STD_LOGIC;
  signal \^calib_seq_reg[1]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \^calib_wrdata_en\ : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal cnt_cmd_done_m7_r : STD_LOGIC;
  signal cnt_cmd_done_m7_r_i_1_n_0 : STD_LOGIC;
  signal cnt_cmd_done_m7_r_i_2_n_0 : STD_LOGIC;
  signal cnt_cmd_done_r : STD_LOGIC;
  signal cnt_cmd_done_r_i_1_n_0 : STD_LOGIC;
  signal \cnt_cmd_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[6]\ : STD_LOGIC;
  signal cnt_dllk_zqinit_done_r : STD_LOGIC;
  signal cnt_dllk_zqinit_done_r_i_1_n_0 : STD_LOGIC;
  signal \cnt_dllk_zqinit_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_dllk_zqinit_r[7]_i_3_n_0\ : STD_LOGIC;
  signal cnt_dllk_zqinit_r_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal cnt_init_af_done_r : STD_LOGIC;
  signal cnt_init_af_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_init_af_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \cnt_init_af_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_init_af_r[1]_i_1_n_0\ : STD_LOGIC;
  signal cnt_init_mr_done_r : STD_LOGIC;
  signal cnt_init_mr_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_init_mr_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal cnt_init_mr_r1 : STD_LOGIC;
  signal \cnt_init_mr_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_init_mr_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_init_mr_r[1]_i_2_n_0\ : STD_LOGIC;
  signal cnt_init_pre_wait_done_r : STD_LOGIC;
  signal cnt_init_pre_wait_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_init_pre_wait_done_r_i_2_n_0 : STD_LOGIC;
  signal \cnt_init_pre_wait_r[7]_i_3_n_0\ : STD_LOGIC;
  signal cnt_init_pre_wait_r_reg : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \cnt_init_pre_wait_r_reg_n_0_[0]\ : STD_LOGIC;
  signal cnt_pwron_ce_r_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cnt_pwron_cke_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_pwron_cke_done_r_i_2_n_0 : STD_LOGIC;
  signal cnt_pwron_cke_done_r_i_3_n_0 : STD_LOGIC;
  signal \^cnt_pwron_cke_done_r_reg_0\ : STD_LOGIC;
  signal \cnt_pwron_r[8]_i_2_n_0\ : STD_LOGIC;
  signal cnt_pwron_r_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal complex_address0 : STD_LOGIC;
  signal \complex_address[9]_i_2_n_0\ : STD_LOGIC;
  signal \complex_address[9]_i_3_n_0\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[0]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[1]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[2]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[3]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[4]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[5]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[6]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[7]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[8]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[9]\ : STD_LOGIC;
  signal complex_byte_rd_done : STD_LOGIC;
  signal complex_byte_rd_done_i_1_n_0 : STD_LOGIC;
  signal complex_byte_rd_done_i_2_n_0 : STD_LOGIC;
  signal \complex_num_reads[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads[1]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_6_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_7_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_8_n_0\ : STD_LOGIC;
  signal complex_num_reads_dec : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \complex_num_reads_dec[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[2]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_6_n_0\ : STD_LOGIC;
  signal \complex_num_reads_reg_n_0_[0]\ : STD_LOGIC;
  signal \complex_num_reads_reg_n_0_[1]\ : STD_LOGIC;
  signal \complex_num_reads_reg_n_0_[2]\ : STD_LOGIC;
  signal \complex_num_reads_reg_n_0_[3]\ : STD_LOGIC;
  signal \complex_num_writes[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[0]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[0]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[1]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[1]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes[1]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_10_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_11_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_6_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_7_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_8_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_9_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_10_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_11_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_12_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_13_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_14_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_15_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_16_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_17_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_18_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_19_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_20_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_21_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_22_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_23_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_6_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_7_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_8_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_9_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[4]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[4]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[4]_i_5_n_0\ : STD_LOGIC;
  signal complex_num_writes_dec_reg : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \complex_num_writes_reg_n_0_[0]\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[1]\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[2]\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[3]\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[4]\ : STD_LOGIC;
  signal complex_ocal_odt_ext : STD_LOGIC;
  signal complex_ocal_odt_ext_i_1_n_0 : STD_LOGIC;
  signal complex_ocal_odt_ext_i_2_n_0 : STD_LOGIC;
  signal complex_ocal_odt_ext_i_3_n_0 : STD_LOGIC;
  signal complex_ocal_odt_ext_i_4_n_0 : STD_LOGIC;
  signal complex_ocal_odt_ext_i_5_n_0 : STD_LOGIC;
  signal complex_ocal_reset_rd_addr : STD_LOGIC;
  signal complex_ocal_reset_rd_addr0 : STD_LOGIC;
  signal complex_ocal_reset_rd_addr_i_2_n_0 : STD_LOGIC;
  signal complex_oclkdelay_calib_done_r1 : STD_LOGIC;
  signal complex_oclkdelay_calib_start_int : STD_LOGIC;
  signal complex_oclkdelay_calib_start_int_i_1_n_0 : STD_LOGIC;
  signal complex_oclkdelay_calib_start_r1 : STD_LOGIC;
  signal complex_odt_ext : STD_LOGIC;
  signal complex_odt_ext_i_1_n_0 : STD_LOGIC;
  signal complex_row0_rd_done : STD_LOGIC;
  signal complex_row0_rd_done1 : STD_LOGIC;
  signal complex_row0_rd_done_i_1_n_0 : STD_LOGIC;
  signal complex_row0_wr_done : STD_LOGIC;
  signal complex_row0_wr_done0 : STD_LOGIC;
  signal complex_row1_rd_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \complex_row1_rd_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_row1_rd_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_row1_rd_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal complex_row1_rd_done : STD_LOGIC;
  signal complex_row1_rd_done_i_1_n_0 : STD_LOGIC;
  signal complex_row1_rd_done_i_2_n_0 : STD_LOGIC;
  signal complex_row1_rd_done_r1 : STD_LOGIC;
  signal complex_row1_wr_done : STD_LOGIC;
  signal complex_row1_wr_done0 : STD_LOGIC;
  signal complex_row_cnt : STD_LOGIC;
  signal complex_row_cnt_ocal : STD_LOGIC;
  signal complex_row_cnt_ocal0 : STD_LOGIC;
  signal \complex_row_cnt_ocal[3]_i_4_n_0\ : STD_LOGIC;
  signal \complex_row_cnt_ocal[3]_i_5_n_0\ : STD_LOGIC;
  signal \complex_row_cnt_ocal[3]_i_6_n_0\ : STD_LOGIC;
  signal \complex_row_cnt_ocal[3]_i_7_n_0\ : STD_LOGIC;
  signal complex_row_cnt_ocal_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal complex_sample_cnt_inc0 : STD_LOGIC;
  signal complex_sample_cnt_inc_i_2_n_0 : STD_LOGIC;
  signal complex_sample_cnt_inc_r1 : STD_LOGIC;
  signal complex_sample_cnt_inc_r2 : STD_LOGIC;
  signal complex_sample_cnt_inc_reg_n_0 : STD_LOGIC;
  signal \complex_wait_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_wait_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \complex_wait_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal complex_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal ddr2_pre_flag_r_i_1_n_0 : STD_LOGIC;
  signal ddr2_pre_flag_r_i_2_n_0 : STD_LOGIC;
  signal ddr2_pre_flag_r_reg_n_0 : STD_LOGIC;
  signal ddr2_refresh_flag_r : STD_LOGIC;
  signal ddr2_refresh_flag_r_i_1_n_0 : STD_LOGIC;
  signal ddr2_refresh_flag_r_i_2_n_0 : STD_LOGIC;
  signal \^detect_pi_found_dqs\ : STD_LOGIC;
  signal detect_pi_found_dqs0 : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.wrlvl_odt_i_1_n_0\ : STD_LOGIC;
  signal enable_wrlvl_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \even_cwl.phy_cas_n[0]_i_1_n_0\ : STD_LOGIC;
  signal \even_cwl.phy_ras_n[0]_i_1_n_0\ : STD_LOGIC;
  signal \even_cwl.phy_we_n[0]_i_1_n_0\ : STD_LOGIC;
  signal \^first_rdlvl_pat_r\ : STD_LOGIC;
  signal first_rdlvl_pat_r_i_1_n_0 : STD_LOGIC;
  signal \^first_wrcal_pat_r\ : STD_LOGIC;
  signal first_wrcal_pat_r_i_1_n_0 : STD_LOGIC;
  signal first_wrcal_pat_r_i_2_n_0 : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_14_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_13_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_14_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_10_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_11_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_12_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_13_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_9_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4_n_0\ : STD_LOGIC;
  signal \gen_rnk[0].mr2_r_reg[0]_202\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal init_complete_r1 : STD_LOGIC;
  signal init_complete_r1_timing : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of init_complete_r1_timing : signal is "true";
  signal init_complete_r2 : STD_LOGIC;
  signal init_complete_r_i_1_n_0 : STD_LOGIC;
  signal init_complete_r_i_2_n_0 : STD_LOGIC;
  signal init_complete_r_reg_n_0 : STD_LOGIC;
  signal init_complete_r_timing : STD_LOGIC;
  attribute RTL_KEEP of init_complete_r_timing : signal is "true";
  signal init_complete_r_timing_i_1_n_0 : STD_LOGIC;
  signal init_next_state044_out : STD_LOGIC;
  signal init_state_r : STD_LOGIC_VECTOR ( 6 to 6 );
  signal init_state_r1 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \init_state_r[0]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_26_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_27_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_28_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_30_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_31_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_32_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_33_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_34_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_35_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_36_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r_reg[1]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r_reg[3]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[5]\ : STD_LOGIC;
  signal mem_init_done_r : STD_LOGIC;
  signal mem_init_done_r_i_1_n_0 : STD_LOGIC;
  signal mem_init_done_r_i_2_n_0 : STD_LOGIC;
  signal mpr_rdlvl_start_i_1_n_0 : STD_LOGIC;
  signal mpr_rdlvl_start_i_2_n_0 : STD_LOGIC;
  signal \^mpr_rdlvl_start_reg_0\ : STD_LOGIC;
  signal num_reads : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal num_refresh0 : STD_LOGIC;
  signal \num_refresh[3]_i_1_n_0\ : STD_LOGIC;
  signal \num_refresh[3]_i_4_n_0\ : STD_LOGIC;
  signal \num_refresh[3]_i_5_n_0\ : STD_LOGIC;
  signal \num_refresh[3]_i_6_n_0\ : STD_LOGIC;
  signal \num_refresh[3]_i_7_n_0\ : STD_LOGIC;
  signal \num_refresh[3]_i_8_n_0\ : STD_LOGIC;
  signal num_refresh_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \ocal_act_wait_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \ocal_act_wait_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \ocal_act_wait_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal ocal_act_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal oclk_wr_cnt0 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \oclk_wr_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[3]_i_5_n_0\ : STD_LOGIC;
  signal oclk_wr_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \one_rank.stg1_wr_done_i_1_n_0\ : STD_LOGIC;
  signal \^one_rank.stg1_wr_done_reg_0\ : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__6\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal phy_bank : STD_LOGIC_VECTOR ( 10 downto 9 );
  signal phy_cas_n : STD_LOGIC_VECTOR ( 0 to 0 );
  signal phy_cs_n : STD_LOGIC_VECTOR ( 0 to 0 );
  signal phy_ras_n : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^phy_read_calib\ : STD_LOGIC;
  signal phy_we_n : STD_LOGIC_VECTOR ( 0 to 0 );
  signal phy_wrdata : STD_LOGIC_VECTOR ( 127 downto 13 );
  signal phy_wrdata_en : STD_LOGIC;
  signal \^pi_calib_done\ : STD_LOGIC;
  signal pi_calib_done_r : STD_LOGIC;
  signal pi_calib_done_r_i_1_n_0 : STD_LOGIC;
  signal pi_calib_rank_done_r : STD_LOGIC;
  signal \^pi_dqs_found_done_r1\ : STD_LOGIC;
  signal pi_dqs_found_start_i_1_n_0 : STD_LOGIC;
  signal pi_dqs_found_start_i_2_n_0 : STD_LOGIC;
  signal \^pi_dqs_found_start_reg_0\ : STD_LOGIC;
  signal pi_phase_locked_all_r1 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of pi_phase_locked_all_r1 : signal is "true";
  signal pi_phase_locked_all_r2 : STD_LOGIC;
  attribute async_reg of pi_phase_locked_all_r2 : signal is "true";
  signal pi_phase_locked_all_r3 : STD_LOGIC;
  attribute async_reg of pi_phase_locked_all_r3 : signal is "true";
  signal pi_phase_locked_all_r4 : STD_LOGIC;
  attribute async_reg of pi_phase_locked_all_r4 : signal is "true";
  signal \^prbs_rdlvl_done_pulse_reg_0\ : STD_LOGIC;
  signal \prech_done_dly_r_reg[15]_srl16_n_0\ : STD_LOGIC;
  signal prech_done_pre : STD_LOGIC;
  signal prech_pending_r : STD_LOGIC;
  signal prech_pending_r_i_1_n_0 : STD_LOGIC;
  signal prech_pending_r_i_2_n_0 : STD_LOGIC;
  signal prech_pending_r_i_3_n_0 : STD_LOGIC;
  signal prech_pending_r_i_4_n_0 : STD_LOGIC;
  signal prech_pending_r_i_5_n_0 : STD_LOGIC;
  signal prech_pending_r_i_6_n_0 : STD_LOGIC;
  signal prech_pending_r_i_7_n_0 : STD_LOGIC;
  signal prech_req : STD_LOGIC;
  signal prech_req_posedge_r0 : STD_LOGIC;
  signal prech_req_posedge_r_i_2_n_0 : STD_LOGIC;
  signal \^prech_req_posedge_r_reg_0\ : STD_LOGIC;
  signal prech_req_r : STD_LOGIC;
  signal prech_req_r_i_2_n_0 : STD_LOGIC;
  signal pwron_ce_r : STD_LOGIC;
  signal pwron_ce_r_i_1_n_0 : STD_LOGIC;
  signal pwron_ce_r_i_2_n_0 : STD_LOGIC;
  signal rdlvl_last_byte_done_r : STD_LOGIC;
  signal rdlvl_start_dly0_r : STD_LOGIC_VECTOR ( 14 to 14 );
  signal \rdlvl_start_dly0_r_reg[13]_srl14_n_0\ : STD_LOGIC;
  signal rdlvl_start_pre : STD_LOGIC;
  signal rdlvl_start_pre_i_1_n_0 : STD_LOGIC;
  signal \^rdlvl_stg1_done_r1\ : STD_LOGIC;
  signal rdlvl_stg1_start_i_1_n_0 : STD_LOGIC;
  signal \^rdlvl_stg1_start_reg_0\ : STD_LOGIC;
  signal read_calib_i_1_n_0 : STD_LOGIC;
  signal read_calib_i_2_n_0 : STD_LOGIC;
  signal reg_ctrl_cnt_r : STD_LOGIC;
  signal \reg_ctrl_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \reg_ctrl_cnt_r[3]_i_4_n_0\ : STD_LOGIC;
  signal reg_ctrl_cnt_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal reset_rd_addr_r1 : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \^stg1_wr_done\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[6]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[7]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[7]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_3_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_4_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_5_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_6_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_7_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0\ : STD_LOGIC;
  signal \wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0\ : STD_LOGIC;
  signal \wr_done_victim_rotate.complex_row0_wr_done_i_4_n_0\ : STD_LOGIC;
  signal \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0\ : STD_LOGIC;
  signal wr_victim_inc : STD_LOGIC;
  signal wr_victim_inc0 : STD_LOGIC;
  signal wr_victim_inc_i_2_n_0 : STD_LOGIC;
  signal wrcal_rd_wait_i_1_n_0 : STD_LOGIC;
  signal wrcal_reads : STD_LOGIC;
  signal wrcal_reads05_out : STD_LOGIC;
  signal \wrcal_reads[0]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[1]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[2]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[3]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[4]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[5]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[6]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_2_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_3_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_4_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_5_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_6_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_8_n_0\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[0]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[1]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[2]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[3]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[4]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[5]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[6]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[7]\ : STD_LOGIC;
  signal wrcal_start_dly_r : STD_LOGIC_VECTOR ( 5 to 5 );
  signal \wrcal_start_dly_r_reg[4]_srl5_i_2_n_0\ : STD_LOGIC;
  signal \wrcal_start_dly_r_reg[4]_srl5_n_0\ : STD_LOGIC;
  signal wrcal_start_i_1_n_0 : STD_LOGIC;
  signal wrcal_start_pre : STD_LOGIC;
  signal \^wrcal_start_reg_0\ : STD_LOGIC;
  signal wrcal_wr_cnt0 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \wrcal_wr_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal wrcal_wr_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1_n_0\ : STD_LOGIC;
  signal \wrdq_div2_4to1_rdlvl_first.phy_wrdata[29]_i_1_n_0\ : STD_LOGIC;
  signal \wrdq_div2_4to1_rdlvl_first.phy_wrdata[46]_i_1_n_0\ : STD_LOGIC;
  signal \^wrlvl_final_if_rst\ : STD_LOGIC;
  signal wrlvl_final_if_rst_i_1_n_0 : STD_LOGIC;
  signal wrlvl_final_if_rst_i_2_n_0 : STD_LOGIC;
  signal wrlvl_odt : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \DDR3_1rank.phy_int_cs_n[0]_i_6\ : label is "soft_lutpair240";
  attribute SOFT_HLUTNM of \calib_cmd[0]_i_1\ : label is "soft_lutpair220";
  attribute SOFT_HLUTNM of \calib_cmd[1]_i_4\ : label is "soft_lutpair227";
  attribute SOFT_HLUTNM of \calib_cmd[2]_i_1\ : label is "soft_lutpair301";
  attribute SOFT_HLUTNM of \calib_data_offset_0[1]_i_1\ : label is "soft_lutpair347";
  attribute SOFT_HLUTNM of \calib_data_offset_0[2]_i_1\ : label is "soft_lutpair347";
  attribute SOFT_HLUTNM of \calib_odt[0]_i_1\ : label is "soft_lutpair301";
  attribute SOFT_HLUTNM of \calib_odt[0]_i_4\ : label is "soft_lutpair307";
  attribute SOFT_HLUTNM of \calib_odt[0]_i_5\ : label is "soft_lutpair241";
  attribute SOFT_HLUTNM of \calib_seq[0]_i_1\ : label is "soft_lutpair302";
  attribute SOFT_HLUTNM of \calib_seq[1]_i_1\ : label is "soft_lutpair302";
  attribute SOFT_HLUTNM of calib_wrdata_en_i_1 : label is "soft_lutpair223";
  attribute SOFT_HLUTNM of cnt_cmd_done_m7_r_i_1 : label is "soft_lutpair233";
  attribute SOFT_HLUTNM of cnt_cmd_done_m7_r_i_2 : label is "soft_lutpair237";
  attribute SOFT_HLUTNM of cnt_cmd_done_r_i_1 : label is "soft_lutpair237";
  attribute SOFT_HLUTNM of \cnt_cmd_r[1]_i_1\ : label is "soft_lutpair342";
  attribute SOFT_HLUTNM of \cnt_cmd_r[2]_i_1\ : label is "soft_lutpair342";
  attribute SOFT_HLUTNM of \cnt_cmd_r[3]_i_1\ : label is "soft_lutpair257";
  attribute SOFT_HLUTNM of \cnt_cmd_r[4]_i_1\ : label is "soft_lutpair257";
  attribute SOFT_HLUTNM of \cnt_cmd_r[6]_i_4\ : label is "soft_lutpair233";
  attribute SOFT_HLUTNM of cnt_dllk_zqinit_done_r_i_1 : label is "soft_lutpair309";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[1]_i_1\ : label is "soft_lutpair341";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[2]_i_1\ : label is "soft_lutpair341";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[3]_i_1\ : label is "soft_lutpair253";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[4]_i_1\ : label is "soft_lutpair253";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[7]_i_2\ : label is "soft_lutpair309";
  attribute SOFT_HLUTNM of cnt_init_af_done_r_i_1 : label is "soft_lutpair244";
  attribute SOFT_HLUTNM of \cnt_init_af_r[0]_i_1\ : label is "soft_lutpair274";
  attribute SOFT_HLUTNM of \cnt_init_af_r[1]_i_1\ : label is "soft_lutpair244";
  attribute SOFT_HLUTNM of \cnt_init_mr_r[0]_i_1\ : label is "soft_lutpair245";
  attribute SOFT_HLUTNM of \cnt_init_mr_r[1]_i_1\ : label is "soft_lutpair245";
  attribute SOFT_HLUTNM of cnt_init_pre_wait_done_r_i_2 : label is "soft_lutpair259";
  attribute SOFT_HLUTNM of \cnt_init_pre_wait_r[1]_i_1\ : label is "soft_lutpair336";
  attribute SOFT_HLUTNM of \cnt_init_pre_wait_r[2]_i_1\ : label is "soft_lutpair336";
  attribute SOFT_HLUTNM of \cnt_init_pre_wait_r[3]_i_1\ : label is "soft_lutpair314";
  attribute SOFT_HLUTNM of \cnt_init_pre_wait_r[4]_i_1\ : label is "soft_lutpair259";
  attribute SOFT_HLUTNM of \cnt_init_pre_wait_r[7]_i_3\ : label is "soft_lutpair314";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[1]_i_1\ : label is "soft_lutpair321";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[2]_i_1\ : label is "soft_lutpair321";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[3]_i_1\ : label is "soft_lutpair221";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[4]_i_1\ : label is "soft_lutpair221";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[6]_i_1\ : label is "soft_lutpair328";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[7]_i_1\ : label is "soft_lutpair328";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[8]_i_1\ : label is "soft_lutpair230";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[9]_i_1\ : label is "soft_lutpair230";
  attribute SOFT_HLUTNM of cnt_pwron_cke_done_r_i_2 : label is "soft_lutpair322";
  attribute SOFT_HLUTNM of \cnt_pwron_r[1]_i_1\ : label is "soft_lutpair340";
  attribute SOFT_HLUTNM of \cnt_pwron_r[2]_i_1\ : label is "soft_lutpair340";
  attribute SOFT_HLUTNM of \cnt_pwron_r[3]_i_1\ : label is "soft_lutpair258";
  attribute SOFT_HLUTNM of \cnt_pwron_r[4]_i_1\ : label is "soft_lutpair258";
  attribute SOFT_HLUTNM of \cnt_pwron_r[6]_i_1\ : label is "soft_lutpair322";
  attribute SOFT_HLUTNM of \cnt_pwron_r[7]_i_1\ : label is "soft_lutpair303";
  attribute SOFT_HLUTNM of \cnt_pwron_r[8]_i_1\ : label is "soft_lutpair303";
  attribute SOFT_HLUTNM of complex_byte_rd_done_i_1 : label is "soft_lutpair243";
  attribute SOFT_HLUTNM of \complex_num_reads[1]_i_2\ : label is "soft_lutpair250";
  attribute SOFT_HLUTNM of \complex_num_reads[2]_i_2\ : label is "soft_lutpair278";
  attribute SOFT_HLUTNM of \complex_num_reads[2]_i_4\ : label is "soft_lutpair293";
  attribute SOFT_HLUTNM of \complex_num_reads[3]_i_2\ : label is "soft_lutpair293";
  attribute SOFT_HLUTNM of \complex_num_reads[3]_i_3\ : label is "soft_lutpair250";
  attribute SOFT_HLUTNM of \complex_num_reads_dec[3]_i_6\ : label is "soft_lutpair275";
  attribute SOFT_HLUTNM of \complex_num_writes[1]_i_4\ : label is "soft_lutpair320";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_1\ : label is "soft_lutpair278";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_11\ : label is "soft_lutpair348";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_4\ : label is "soft_lutpair311";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_5\ : label is "soft_lutpair236";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_6\ : label is "soft_lutpair284";
  attribute SOFT_HLUTNM of \complex_num_writes[3]_i_2\ : label is "soft_lutpair284";
  attribute SOFT_HLUTNM of \complex_num_writes[3]_i_5\ : label is "soft_lutpair236";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_10\ : label is "soft_lutpair311";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_11\ : label is "soft_lutpair348";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_12\ : label is "soft_lutpair325";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_14\ : label is "soft_lutpair279";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_16\ : label is "soft_lutpair262";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_19\ : label is "soft_lutpair279";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_23\ : label is "soft_lutpair262";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_7\ : label is "soft_lutpair275";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_8\ : label is "soft_lutpair266";
  attribute SOFT_HLUTNM of \complex_num_writes_dec[0]_i_1\ : label is "soft_lutpair320";
  attribute SOFT_HLUTNM of \complex_num_writes_dec[4]_i_4\ : label is "soft_lutpair292";
  attribute SOFT_HLUTNM of complex_ocal_odt_ext_i_2 : label is "soft_lutpair231";
  attribute SOFT_HLUTNM of complex_ocal_odt_ext_i_5 : label is "soft_lutpair317";
  attribute SOFT_HLUTNM of complex_oclkdelay_calib_start_int_i_1 : label is "soft_lutpair268";
  attribute SOFT_HLUTNM of complex_row0_rd_done_i_3 : label is "soft_lutpair264";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[1]_i_1\ : label is "soft_lutpair318";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[2]_i_1\ : label is "soft_lutpair318";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[3]_i_3\ : label is "soft_lutpair280";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[3]_i_4\ : label is "soft_lutpair280";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[3]_i_7\ : label is "soft_lutpair255";
  attribute SOFT_HLUTNM of complex_sample_cnt_inc_i_1 : label is "soft_lutpair326";
  attribute SOFT_HLUTNM of complex_sample_cnt_inc_i_2 : label is "soft_lutpair239";
  attribute SOFT_HLUTNM of \complex_wait_cnt[0]_i_1\ : label is "soft_lutpair349";
  attribute SOFT_HLUTNM of \complex_wait_cnt[1]_i_1\ : label is "soft_lutpair349";
  attribute SOFT_HLUTNM of \complex_wait_cnt[2]_i_1\ : label is "soft_lutpair310";
  attribute SOFT_HLUTNM of \complex_wait_cnt[3]_i_2\ : label is "soft_lutpair310";
  attribute SOFT_HLUTNM of ddr2_pre_flag_r_i_2 : label is "soft_lutpair273";
  attribute SOFT_HLUTNM of ddr2_refresh_flag_r_i_1 : label is "soft_lutpair274";
  attribute SOFT_HLUTNM of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_22\ : label is "soft_lutpair291";
  attribute SOFT_HLUTNM of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_62\ : label is "soft_lutpair287";
  attribute SOFT_HLUTNM of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_70\ : label is "soft_lutpair286";
  attribute SOFT_HLUTNM of \en_cnt_div4.enable_wrlvl_cnt[2]_i_1\ : label is "soft_lutpair252";
  attribute SOFT_HLUTNM of \en_cnt_div4.enable_wrlvl_cnt[3]_i_1\ : label is "soft_lutpair252";
  attribute SOFT_HLUTNM of \even_cwl.phy_cas_n[0]_i_1\ : label is "soft_lutpair220";
  attribute SOFT_HLUTNM of \even_cwl.phy_we_n[0]_i_1\ : label is "soft_lutpair223";
  attribute SOFT_HLUTNM of first_wrcal_pat_r_i_1 : label is "soft_lutpair242";
  attribute SOFT_HLUTNM of first_wrcal_pat_r_i_2 : label is "soft_lutpair238";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1\ : label is "soft_lutpair260";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_3\ : label is "soft_lutpair297";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2\ : label is "soft_lutpair265";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4\ : label is "soft_lutpair295";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4\ : label is "soft_lutpair338";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5\ : label is "soft_lutpair323";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7\ : label is "soft_lutpair323";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3\ : label is "soft_lutpair338";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4\ : label is "soft_lutpair296";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5\ : label is "soft_lutpair288";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6\ : label is "soft_lutpair296";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12\ : label is "soft_lutpair304";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13\ : label is "soft_lutpair308";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3\ : label is "soft_lutpair235";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7\ : label is "soft_lutpair247";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9\ : label is "soft_lutpair238";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10\ : label is "soft_lutpair271";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12\ : label is "soft_lutpair299";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_13\ : label is "soft_lutpair254";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_14\ : label is "soft_lutpair255";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2\ : label is "soft_lutpair285";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5\ : label is "soft_lutpair276";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7\ : label is "soft_lutpair300";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9\ : label is "soft_lutpair308";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2\ : label is "soft_lutpair297";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6\ : label is "soft_lutpair276";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7\ : label is "soft_lutpair269";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8\ : label is "soft_lutpair271";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_13\ : label is "soft_lutpair325";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2\ : label is "soft_lutpair222";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_7\ : label is "soft_lutpair260";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_9\ : label is "soft_lutpair239";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11\ : label is "soft_lutpair269";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12\ : label is "soft_lutpair247";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3\ : label is "soft_lutpair295";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4\ : label is "soft_lutpair222";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6\ : label is "soft_lutpair285";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7\ : label is "soft_lutpair291";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3\ : label is "soft_lutpair248";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4\ : label is "soft_lutpair235";
  attribute KEEP : string;
  attribute KEEP of init_complete_r1_timing_reg : label is "yes";
  attribute SOFT_HLUTNM of init_complete_r_i_2 : label is "soft_lutpair272";
  attribute KEEP of init_complete_r_timing_reg : label is "yes";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_10\ : label is "soft_lutpair345";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_15\ : label is "soft_lutpair272";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_16\ : label is "soft_lutpair294";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_4\ : label is "soft_lutpair343";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_1\ : label is "soft_lutpair240";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_16\ : label is "soft_lutpair289";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_5\ : label is "soft_lutpair267";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_9\ : label is "soft_lutpair263";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_10\ : label is "soft_lutpair268";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_13\ : label is "soft_lutpair277";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_14\ : label is "soft_lutpair249";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_16\ : label is "soft_lutpair313";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_17\ : label is "soft_lutpair228";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_7\ : label is "soft_lutpair317";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_9\ : label is "soft_lutpair345";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_11\ : label is "soft_lutpair265";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_5\ : label is "soft_lutpair229";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_6\ : label is "soft_lutpair346";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_8\ : label is "soft_lutpair227";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_10\ : label is "soft_lutpair329";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_11\ : label is "soft_lutpair313";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_13\ : label is "soft_lutpair346";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_15\ : label is "soft_lutpair261";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_18\ : label is "soft_lutpair273";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_2\ : label is "soft_lutpair246";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_6\ : label is "soft_lutpair248";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_1\ : label is "soft_lutpair234";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_11\ : label is "soft_lutpair290";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_14\ : label is "soft_lutpair319";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_2\ : label is "soft_lutpair267";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_5\ : label is "soft_lutpair277";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_6\ : label is "soft_lutpair305";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_9\ : label is "soft_lutpair261";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_15\ : label is "soft_lutpair305";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_16\ : label is "soft_lutpair263";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_25\ : label is "soft_lutpair229";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_26\ : label is "soft_lutpair228";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_3\ : label is "soft_lutpair246";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_30\ : label is "soft_lutpair292";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_34\ : label is "soft_lutpair226";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_35\ : label is "soft_lutpair249";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_8\ : label is "soft_lutpair329";
  attribute SOFT_HLUTNM of mem_init_done_r_i_2 : label is "soft_lutpair266";
  attribute SOFT_HLUTNM of mpr_rdlvl_start_i_2 : label is "soft_lutpair307";
  attribute SOFT_HLUTNM of \my_empty[7]_i_2__1\ : label is "soft_lutpair286";
  attribute SOFT_HLUTNM of \num_refresh[0]_i_1\ : label is "soft_lutpair350";
  attribute SOFT_HLUTNM of \num_refresh[1]_i_1\ : label is "soft_lutpair350";
  attribute SOFT_HLUTNM of \num_refresh[2]_i_1\ : label is "soft_lutpair306";
  attribute SOFT_HLUTNM of \num_refresh[3]_i_3\ : label is "soft_lutpair306";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[1]_i_1\ : label is "soft_lutpair327";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[2]_i_1\ : label is "soft_lutpair327";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[3]_i_2\ : label is "soft_lutpair283";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[3]_i_3\ : label is "soft_lutpair283";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[3]_i_4\ : label is "soft_lutpair241";
  attribute SOFT_HLUTNM of \oclk_wr_cnt[0]_i_1\ : label is "soft_lutpair351";
  attribute SOFT_HLUTNM of \oclk_wr_cnt[1]_i_1\ : label is "soft_lutpair351";
  attribute SOFT_HLUTNM of \oclk_wr_cnt[3]_i_3\ : label is "soft_lutpair304";
  attribute SOFT_HLUTNM of \oclk_wr_cnt[3]_i_5\ : label is "soft_lutpair344";
  attribute SOFT_HLUTNM of \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_48\ : label is "soft_lutpair288";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[0]_i_1\ : label is "soft_lutpair332";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[17]_i_1\ : label is "soft_lutpair334";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[18]_i_1\ : label is "soft_lutpair337";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[19]_i_1\ : label is "soft_lutpair337";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[1]_i_1\ : label is "soft_lutpair332";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[20]_i_1\ : label is "soft_lutpair339";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[21]_i_1\ : label is "soft_lutpair339";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[2]_i_1\ : label is "soft_lutpair334";
  attribute SOFT_HLUTNM of phy_ctl_wr_i1_i_1 : label is "soft_lutpair287";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of pi_phase_locked_all_r1_reg : label is std.standard.true;
  attribute KEEP of pi_phase_locked_all_r1_reg : label is "yes";
  attribute ASYNC_REG_boolean of pi_phase_locked_all_r2_reg : label is std.standard.true;
  attribute KEEP of pi_phase_locked_all_r2_reg : label is "yes";
  attribute ASYNC_REG_boolean of pi_phase_locked_all_r3_reg : label is std.standard.true;
  attribute KEEP of pi_phase_locked_all_r3_reg : label is "yes";
  attribute ASYNC_REG_boolean of pi_phase_locked_all_r4_reg : label is std.standard.true;
  attribute KEEP of pi_phase_locked_all_r4_reg : label is "yes";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \prech_done_dly_r_reg[15]_srl16\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \prech_done_dly_r_reg[15]_srl16\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg[15]_srl16 ";
  attribute SOFT_HLUTNM of \prech_done_dly_r_reg[15]_srl16_i_1\ : label is "soft_lutpair324";
  attribute SOFT_HLUTNM of prech_pending_r_i_1 : label is "soft_lutpair324";
  attribute SOFT_HLUTNM of prech_req_r_i_2 : label is "soft_lutpair232";
  attribute srl_bus_name of \rdlvl_start_dly0_r_reg[13]_srl14\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg ";
  attribute srl_name of \rdlvl_start_dly0_r_reg[13]_srl14\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[13]_srl14 ";
  attribute SOFT_HLUTNM of read_calib_i_2 : label is "soft_lutpair232";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[1]_i_1\ : label is "soft_lutpair331";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[2]_i_1\ : label is "soft_lutpair331";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[3]_i_3\ : label is "soft_lutpair294";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[3]_i_4\ : label is "soft_lutpair344";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[0]_i_1\ : label is "soft_lutpair270";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[1]_i_1\ : label is "soft_lutpair270";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[3]_i_1\ : label is "soft_lutpair251";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[3]_i_2\ : label is "soft_lutpair319";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[4]_i_5\ : label is "soft_lutpair256";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[4]_i_7\ : label is "soft_lutpair256";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[5]_i_2\ : label is "soft_lutpair251";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[0]_i_1\ : label is "soft_lutpair335";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[2]_i_1\ : label is "soft_lutpair299";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[4]_i_3\ : label is "soft_lutpair326";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[5]_i_2\ : label is "soft_lutpair335";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[6]_i_1\ : label is "soft_lutpair298";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[6]_i_2\ : label is "soft_lutpair224";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[7]_i_1\ : label is "soft_lutpair298";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[8]_i_3\ : label is "soft_lutpair231";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[8]_i_5\ : label is "soft_lutpair224";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[8]_i_6\ : label is "soft_lutpair254";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[8]_i_7\ : label is "soft_lutpair290";
  attribute SOFT_HLUTNM of \wr_done_victim_rotate.complex_row0_wr_done_i_1\ : label is "soft_lutpair281";
  attribute SOFT_HLUTNM of \wr_done_victim_rotate.complex_row0_wr_done_i_2\ : label is "soft_lutpair264";
  attribute SOFT_HLUTNM of \wr_done_victim_rotate.complex_row0_wr_done_i_4\ : label is "soft_lutpair243";
  attribute SOFT_HLUTNM of \wr_done_victim_rotate.complex_row1_wr_done_i_1\ : label is "soft_lutpair281";
  attribute SOFT_HLUTNM of \wr_en_inferred__0_i_1\ : label is "soft_lutpair316";
  attribute SOFT_HLUTNM of \wr_en_inferred__0_i_1__0\ : label is "soft_lutpair333";
  attribute SOFT_HLUTNM of \wr_en_inferred__0_i_1__1\ : label is "soft_lutpair333";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__3\ : label is "soft_lutpair315";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__4\ : label is "soft_lutpair315";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__5\ : label is "soft_lutpair316";
  attribute SOFT_HLUTNM of \wrcal_reads[0]_i_1\ : label is "soft_lutpair330";
  attribute SOFT_HLUTNM of \wrcal_reads[1]_i_1\ : label is "soft_lutpair330";
  attribute SOFT_HLUTNM of \wrcal_reads[2]_i_1\ : label is "soft_lutpair282";
  attribute SOFT_HLUTNM of \wrcal_reads[3]_i_1\ : label is "soft_lutpair226";
  attribute SOFT_HLUTNM of \wrcal_reads[5]_i_1\ : label is "soft_lutpair225";
  attribute SOFT_HLUTNM of \wrcal_reads[6]_i_1\ : label is "soft_lutpair225";
  attribute SOFT_HLUTNM of \wrcal_reads[7]_i_4\ : label is "soft_lutpair343";
  attribute SOFT_HLUTNM of \wrcal_reads[7]_i_5\ : label is "soft_lutpair242";
  attribute SOFT_HLUTNM of \wrcal_reads[7]_i_6\ : label is "soft_lutpair282";
  attribute srl_bus_name of \wrcal_start_dly_r_reg[4]_srl5\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg ";
  attribute srl_name of \wrcal_start_dly_r_reg[4]_srl5\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[4]_srl5 ";
  attribute SOFT_HLUTNM of \wrcal_start_dly_r_reg[4]_srl5_i_2\ : label is "soft_lutpair234";
  attribute SOFT_HLUTNM of \wrcal_wr_cnt[1]_i_1\ : label is "soft_lutpair312";
  attribute SOFT_HLUTNM of \wrcal_wr_cnt[3]_i_3\ : label is "soft_lutpair312";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[29]_i_1\ : label is "soft_lutpair289";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[46]_i_1\ : label is "soft_lutpair300";
begin
  Q(0) <= \^q\(0);
  calib_ctl_wren_reg_0 <= \^calib_ctl_wren_reg_0\;
  \calib_seq_reg[1]_0\(10 downto 0) <= \^calib_seq_reg[1]_0\(10 downto 0);
  calib_wrdata_en <= \^calib_wrdata_en\;
  cnt_pwron_cke_done_r_reg_0 <= \^cnt_pwron_cke_done_r_reg_0\;
  detect_pi_found_dqs <= \^detect_pi_found_dqs\;
  first_rdlvl_pat_r <= \^first_rdlvl_pat_r\;
  first_wrcal_pat_r <= \^first_wrcal_pat_r\;
  mpr_rdlvl_start_reg_0 <= \^mpr_rdlvl_start_reg_0\;
  \one_rank.stg1_wr_done_reg_0\ <= \^one_rank.stg1_wr_done_reg_0\;
  \out\ <= init_complete_r1_timing;
  phy_read_calib <= \^phy_read_calib\;
  pi_calib_done <= \^pi_calib_done\;
  pi_dqs_found_done_r1 <= \^pi_dqs_found_done_r1\;
  pi_dqs_found_start_reg_0 <= \^pi_dqs_found_start_reg_0\;
  prbs_rdlvl_done_pulse_reg_0 <= \^prbs_rdlvl_done_pulse_reg_0\;
  prech_req_posedge_r_reg_0 <= \^prech_req_posedge_r_reg_0\;
  rdlvl_stg1_done_r1 <= \^rdlvl_stg1_done_r1\;
  rdlvl_stg1_start_reg_0 <= \^rdlvl_stg1_start_reg_0\;
  stg1_wr_done <= \^stg1_wr_done\;
  wrcal_start_reg_0 <= \^wrcal_start_reg_0\;
  wrlvl_final_if_rst <= \^wrlvl_final_if_rst\;
\DDR3_1rank.phy_int_cs_n[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000E00000000"
    )
        port map (
      I0 => \calib_cmd[2]_i_1_n_0\,
      I1 => \DDR3_1rank.phy_int_cs_n[0]_i_2_n_0\,
      I2 => \cnt_dllk_zqinit_r[7]_i_1_n_0\,
      I3 => \DDR3_1rank.phy_int_cs_n[0]_i_3_n_0\,
      I4 => \DDR3_1rank.phy_int_cs_n[0]_i_4_n_0\,
      I5 => \DDR3_1rank.phy_int_cs_n[0]_i_5_n_0\,
      O => \DDR3_1rank.phy_int_cs_n[0]_i_1_n_0\
    );
\DDR3_1rank.phy_int_cs_n[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000020000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \wrcal_start_dly_r_reg[4]_srl5_i_2_n_0\,
      O => \DDR3_1rank.phy_int_cs_n[0]_i_10_n_0\
    );
\DDR3_1rank.phy_int_cs_n[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \DDR3_1rank.phy_int_cs_n[0]_i_2_n_0\
    );
\DDR3_1rank.phy_int_cs_n[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200030000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \DDR3_1rank.phy_int_cs_n[0]_i_6_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \DDR3_1rank.phy_int_cs_n[0]_i_3_n_0\
    );
\DDR3_1rank.phy_int_cs_n[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0200"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => mpr_rdlvl_start_i_2_n_0,
      I3 => \^q\(0),
      I4 => \cnt_init_mr_r[1]_i_2_n_0\,
      I5 => \num_refresh[3]_i_6_n_0\,
      O => \DDR3_1rank.phy_int_cs_n[0]_i_4_n_0\
    );
\DDR3_1rank.phy_int_cs_n[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \num_refresh[3]_i_7_n_0\,
      I1 => \num_refresh[3]_i_5_n_0\,
      I2 => \DDR3_1rank.phy_int_cs_n[0]_i_7_n_0\,
      I3 => \DDR3_1rank.phy_int_cs_n[0]_i_8_n_0\,
      I4 => \num_refresh[3]_i_4_n_0\,
      I5 => \DDR3_1rank.phy_int_cs_n[0]_i_9_n_0\,
      O => \DDR3_1rank.phy_int_cs_n[0]_i_5_n_0\
    );
\DDR3_1rank.phy_int_cs_n[0]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      O => \DDR3_1rank.phy_int_cs_n[0]_i_6_n_0\
    );
\DDR3_1rank.phy_int_cs_n[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => init_complete_r_i_2_n_0,
      O => \DDR3_1rank.phy_int_cs_n[0]_i_7_n_0\
    );
\DDR3_1rank.phy_int_cs_n[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555545555555"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[0]_i_10_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4_n_0\,
      I3 => \init_state_r[3]_i_6_n_0\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => init_state_r(6),
      O => \DDR3_1rank.phy_int_cs_n[0]_i_8_n_0\
    );
\DDR3_1rank.phy_int_cs_n[0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000003000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \wrcal_reads[7]_i_4_n_0\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \DDR3_1rank.phy_int_cs_n[0]_i_9_n_0\
    );
\DDR3_1rank.phy_int_cs_n_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \DDR3_1rank.phy_int_cs_n[0]_i_1_n_0\,
      Q => phy_cs_n(0),
      S => init_complete_r_timing_reg_0
    );
\back_to_back_reads_4_1.num_reads[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000044444054"
    )
        port map (
      I0 => num_reads(0),
      I1 => num_reads(1),
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      I4 => prech_req_r_i_2_n_0,
      I5 => \wrcal_reads_reg[0]_0\,
      O => \back_to_back_reads_4_1.num_reads[0]_i_1_n_0\
    );
\back_to_back_reads_4_1.num_reads[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000088888098"
    )
        port map (
      I0 => num_reads(0),
      I1 => num_reads(1),
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      I4 => prech_req_r_i_2_n_0,
      I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      O => \back_to_back_reads_4_1.num_reads[1]_i_1_n_0\
    );
\back_to_back_reads_4_1.num_reads_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \back_to_back_reads_4_1.num_reads[0]_i_1_n_0\,
      Q => num_reads(0),
      R => '0'
    );
\back_to_back_reads_4_1.num_reads_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \back_to_back_reads_4_1.num_reads[1]_i_1_n_0\,
      Q => num_reads(1),
      R => '0'
    );
burst_addr_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000AB"
    )
        port map (
      I0 => burst_addr_r_i_2_n_0,
      I1 => burst_addr_r_reg_n_0,
      I2 => \calib_cmd[2]_i_1_n_0\,
      I3 => burst_addr_r_reg_0,
      I4 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      O => burst_addr_r_i_1_n_0
    );
burst_addr_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000C00030000020F"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => \wrcal_start_dly_r_reg[4]_srl5_i_2_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => burst_addr_r_i_2_n_0
    );
burst_addr_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => burst_addr_r_i_1_n_0,
      Q => burst_addr_r_reg_n_0,
      R => '0'
    );
\calib_cke_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^cnt_pwron_cke_done_r_reg_0\,
      Q => calib_cke(3),
      R => init_complete_r_timing_reg_0
    );
\calib_cmd[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \calib_cmd[2]_i_1_n_0\,
      O => \calib_cmd[0]_i_1_n_0\
    );
\calib_cmd[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF45FFFFFFFF"
    )
        port map (
      I0 => rdlvl_pi_incdec,
      I1 => \calib_cmd[1]_i_2_n_0\,
      I2 => \calib_cmd[1]_i_3_n_0\,
      I3 => wrcal_start_pre,
      I4 => \calib_cmd[1]_i_4_n_0\,
      I5 => \calib_cmd[1]_i_5_n_0\,
      O => \calib_cmd[1]_i_1_n_0\
    );
\calib_cmd[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \calib_cmd[1]_i_2_n_0\
    );
\calib_cmd[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFBFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      I5 => \^q\(0),
      O => \calib_cmd[1]_i_3_n_0\
    );
\calib_cmd[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00020000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      O => \calib_cmd[1]_i_4_n_0\
    );
\calib_cmd[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFBEFFF"
    )
        port map (
      I0 => \wrcal_start_dly_r_reg[4]_srl5_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \calib_cmd[1]_i_5_n_0\
    );
\calib_cmd[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      I1 => \calib_cmd[1]_i_1_n_0\,
      O => \calib_cmd[2]_i_1_n_0\
    );
\calib_cmd[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010101010101000"
    )
        port map (
      I0 => \oclk_wr_cnt[3]_i_2_n_0\,
      I1 => p_0_in1_in,
      I2 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \ocal_act_wait_cnt[3]_i_4_n_0\,
      O => \calib_cmd[2]_i_2_n_0\
    );
\calib_cmd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_cmd[0]_i_1_n_0\,
      Q => calib_cmd(0),
      R => '0'
    );
\calib_cmd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_cmd[1]_i_1_n_0\,
      Q => calib_cmd(1),
      R => '0'
    );
\calib_cmd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_cmd[2]_i_1_n_0\,
      Q => calib_cmd(2),
      R => '0'
    );
calib_ctl_wren_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_128_in,
      Q => \^calib_ctl_wren_reg_0\,
      R => \complex_address_reg[9]_0\(0)
    );
\calib_data_offset_0[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \calib_data_offset_0[1]_i_2_n_0\,
      I1 => \calib_cmd[2]_i_1_n_0\,
      O => \calib_data_offset_0[1]_i_1_n_0\
    );
\calib_data_offset_0[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A2A080FFFFFFFF"
    )
        port map (
      I0 => \^pi_calib_done\,
      I1 => \^pi_dqs_found_done_r1\,
      I2 => \calib_data_offset_0_reg[2]_0\(0),
      I3 => init_dqsfound_done_r2,
      I4 => \calib_data_offset_0_reg[2]_1\(0),
      I5 => \calib_cmd[2]_i_2_n_0\,
      O => \calib_data_offset_0[1]_i_2_n_0\
    );
\calib_data_offset_0[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \calib_data_offset_0[2]_i_2_n_0\,
      I1 => \calib_cmd[2]_i_1_n_0\,
      O => \calib_data_offset_0[2]_i_1_n_0\
    );
\calib_data_offset_0[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A2A080FFFFFFFF"
    )
        port map (
      I0 => \^pi_calib_done\,
      I1 => \^pi_dqs_found_done_r1\,
      I2 => \calib_data_offset_0_reg[2]_0\(1),
      I3 => init_dqsfound_done_r2,
      I4 => \calib_data_offset_0_reg[2]_1\(1),
      I5 => \calib_cmd[2]_i_2_n_0\,
      O => \calib_data_offset_0[2]_i_2_n_0\
    );
\calib_data_offset_0[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^pi_calib_done\,
      I1 => \calib_cmd[1]_i_1_n_0\,
      O => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_data_offset_0_reg[0]_0\,
      Q => calib_data_offset_0(0),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_data_offset_0[1]_i_1_n_0\,
      Q => calib_data_offset_0(1),
      R => '0'
    );
\calib_data_offset_0_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_data_offset_0[2]_i_1_n_0\,
      Q => calib_data_offset_0(2),
      R => '0'
    );
\calib_data_offset_0_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_data_offset_0_reg[3]_0\,
      Q => calib_data_offset_0(3),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_data_offset_0_reg[4]_0\,
      Q => calib_data_offset_0(4),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_data_offset_0_reg[5]_0\,
      Q => calib_data_offset_0(5),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_odt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D0"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      I1 => \calib_odt[0]_i_2_n_0\,
      I2 => \gen_rnk[0].mr2_r_reg[0]_202\(1),
      I3 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      O => \calib_odt[0]_i_1_n_0\
    );
\calib_odt[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => complex_ocal_odt_ext,
      I1 => complex_odt_ext,
      I2 => \wrcal_wr_cnt[3]_i_4_n_0\,
      I3 => \complex_address[9]_i_3_n_0\,
      I4 => \calib_odt[0]_i_3_n_0\,
      I5 => \^stg1_wr_done\,
      O => \calib_odt[0]_i_2_n_0\
    );
\calib_odt[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000004400000044"
    )
        port map (
      I0 => \calib_odt[0]_i_4_n_0\,
      I1 => \init_state_r[2]_i_18_n_0\,
      I2 => wrlvl_odt,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \calib_odt[0]_i_5_n_0\,
      O => \calib_odt[0]_i_3_n_0\
    );
\calib_odt[0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      O => \calib_odt[0]_i_4_n_0\
    );
\calib_odt[0]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      O => \calib_odt[0]_i_5_n_0\
    );
\calib_odt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_odt[0]_i_1_n_0\,
      Q => calib_odt(0),
      R => '0'
    );
\calib_seq[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^cnt_pwron_cke_done_r_reg_0\,
      I1 => cnt_pwron_cke_done_r_reg_1(0),
      I2 => \^calib_seq_reg[1]_0\(9),
      O => \calib_seq[0]_i_1_n_0\
    );
\calib_seq[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^calib_seq_reg[1]_0\(9),
      I1 => cnt_pwron_cke_done_r_reg_1(0),
      I2 => \^cnt_pwron_cke_done_r_reg_0\,
      I3 => \^calib_seq_reg[1]_0\(10),
      O => \calib_seq[1]_i_1_n_0\
    );
\calib_seq_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq[0]_i_1_n_0\,
      Q => \^calib_seq_reg[1]_0\(9),
      R => SR(0)
    );
\calib_seq_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq[1]_i_1_n_0\,
      Q => \^calib_seq_reg[1]_0\(10),
      R => SR(0)
    );
calib_wrdata_en_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      O => phy_wrdata_en
    );
calib_wrdata_en_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_wrdata_en,
      Q => \^calib_wrdata_en\,
      R => '0'
    );
cnt_cmd_done_m7_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => cnt_cmd_done_m7_r_i_2_n_0,
      I1 => \cnt_cmd_r_reg_n_0_[2]\,
      I2 => \cnt_cmd_r_reg_n_0_[6]\,
      I3 => \cnt_cmd_r_reg_n_0_[1]\,
      I4 => \cnt_cmd_r_reg_n_0_[0]\,
      O => cnt_cmd_done_m7_r_i_1_n_0
    );
cnt_cmd_done_m7_r_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[4]\,
      I1 => \cnt_cmd_r_reg_n_0_[3]\,
      I2 => \cnt_cmd_r_reg_n_0_[5]\,
      O => cnt_cmd_done_m7_r_i_2_n_0
    );
cnt_cmd_done_m7_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_cmd_done_m7_r_i_1_n_0,
      Q => cnt_cmd_done_m7_r,
      R => '0'
    );
cnt_cmd_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[6]\,
      I1 => \cnt_cmd_r[6]_i_4_n_0\,
      I2 => \cnt_cmd_r_reg_n_0_[4]\,
      I3 => \cnt_cmd_r_reg_n_0_[3]\,
      I4 => \cnt_cmd_r_reg_n_0_[5]\,
      O => cnt_cmd_done_r_i_1_n_0
    );
cnt_cmd_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_cmd_done_r_i_1_n_0,
      Q => cnt_cmd_done_r,
      R => '0'
    );
\cnt_cmd_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[0]\,
      O => \cnt_cmd_r[0]_i_1_n_0\
    );
\cnt_cmd_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[0]\,
      I1 => \cnt_cmd_r_reg_n_0_[1]\,
      O => \cnt_cmd_r[1]_i_1_n_0\
    );
\cnt_cmd_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[2]\,
      I1 => \cnt_cmd_r_reg_n_0_[0]\,
      I2 => \cnt_cmd_r_reg_n_0_[1]\,
      O => \cnt_cmd_r[2]_i_1_n_0\
    );
\cnt_cmd_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[3]\,
      I1 => \cnt_cmd_r_reg_n_0_[2]\,
      I2 => \cnt_cmd_r_reg_n_0_[1]\,
      I3 => \cnt_cmd_r_reg_n_0_[0]\,
      O => \cnt_cmd_r[3]_i_1_n_0\
    );
\cnt_cmd_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[4]\,
      I1 => \cnt_cmd_r_reg_n_0_[3]\,
      I2 => \cnt_cmd_r_reg_n_0_[0]\,
      I3 => \cnt_cmd_r_reg_n_0_[1]\,
      I4 => \cnt_cmd_r_reg_n_0_[2]\,
      O => \cnt_cmd_r[4]_i_1_n_0\
    );
\cnt_cmd_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[5]\,
      I1 => \cnt_cmd_r_reg_n_0_[3]\,
      I2 => \cnt_cmd_r_reg_n_0_[4]\,
      I3 => \cnt_cmd_r_reg_n_0_[0]\,
      I4 => \cnt_cmd_r_reg_n_0_[1]\,
      I5 => \cnt_cmd_r_reg_n_0_[2]\,
      O => \cnt_cmd_r[5]_i_1_n_0\
    );
\cnt_cmd_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \cnt_cmd_r[6]_i_3_n_0\,
      O => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[6]\,
      I1 => \cnt_cmd_r[6]_i_4_n_0\,
      I2 => \cnt_cmd_r_reg_n_0_[4]\,
      I3 => \cnt_cmd_r_reg_n_0_[3]\,
      I4 => \cnt_cmd_r_reg_n_0_[5]\,
      O => \cnt_cmd_r[6]_i_2_n_0\
    );
\cnt_cmd_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFD7F9C7B8C3EDC7"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \cnt_cmd_r[6]_i_3_n_0\
    );
\cnt_cmd_r[6]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[0]\,
      I1 => \cnt_cmd_r_reg_n_0_[1]\,
      I2 => \cnt_cmd_r_reg_n_0_[2]\,
      O => \cnt_cmd_r[6]_i_4_n_0\
    );
\cnt_cmd_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[0]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[0]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[1]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[1]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[2]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[2]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[3]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[3]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[4]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[4]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[5]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[5]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[6]_i_2_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[6]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
cnt_dllk_zqinit_done_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => cnt_dllk_zqinit_done_r,
      I1 => cnt_dllk_zqinit_r_reg(6),
      I2 => \cnt_dllk_zqinit_r[7]_i_3_n_0\,
      I3 => cnt_dllk_zqinit_r_reg(7),
      O => cnt_dllk_zqinit_done_r_i_1_n_0
    );
cnt_dllk_zqinit_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_dllk_zqinit_done_r_i_1_n_0,
      Q => cnt_dllk_zqinit_done_r,
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(0),
      O => \p_0_in__3\(0)
    );
\cnt_dllk_zqinit_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(0),
      I1 => cnt_dllk_zqinit_r_reg(1),
      O => \p_0_in__3\(1)
    );
\cnt_dllk_zqinit_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(2),
      I1 => cnt_dllk_zqinit_r_reg(1),
      I2 => cnt_dllk_zqinit_r_reg(0),
      O => \p_0_in__3\(2)
    );
\cnt_dllk_zqinit_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(3),
      I1 => cnt_dllk_zqinit_r_reg(0),
      I2 => cnt_dllk_zqinit_r_reg(1),
      I3 => cnt_dllk_zqinit_r_reg(2),
      O => \p_0_in__3\(3)
    );
\cnt_dllk_zqinit_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(4),
      I1 => cnt_dllk_zqinit_r_reg(2),
      I2 => cnt_dllk_zqinit_r_reg(1),
      I3 => cnt_dllk_zqinit_r_reg(0),
      I4 => cnt_dllk_zqinit_r_reg(3),
      O => \p_0_in__3\(4)
    );
\cnt_dllk_zqinit_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(5),
      I1 => cnt_dllk_zqinit_r_reg(3),
      I2 => cnt_dllk_zqinit_r_reg(0),
      I3 => cnt_dllk_zqinit_r_reg(1),
      I4 => cnt_dllk_zqinit_r_reg(2),
      I5 => cnt_dllk_zqinit_r_reg(4),
      O => \p_0_in__3\(5)
    );
\cnt_dllk_zqinit_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(6),
      I1 => \cnt_dllk_zqinit_r[7]_i_3_n_0\,
      O => \p_0_in__3\(6)
    );
\cnt_dllk_zqinit_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \wrcal_reads[7]_i_5_n_0\,
      O => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(7),
      I1 => \cnt_dllk_zqinit_r[7]_i_3_n_0\,
      I2 => cnt_dllk_zqinit_r_reg(6),
      O => \p_0_in__3\(7)
    );
\cnt_dllk_zqinit_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => cnt_dllk_zqinit_r_reg(5),
      I1 => cnt_dllk_zqinit_r_reg(3),
      I2 => cnt_dllk_zqinit_r_reg(0),
      I3 => cnt_dllk_zqinit_r_reg(1),
      I4 => cnt_dllk_zqinit_r_reg(2),
      I5 => cnt_dllk_zqinit_r_reg(4),
      O => \cnt_dllk_zqinit_r[7]_i_3_n_0\
    );
\cnt_dllk_zqinit_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__3\(0),
      Q => cnt_dllk_zqinit_r_reg(0),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__3\(1),
      Q => cnt_dllk_zqinit_r_reg(1),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__3\(2),
      Q => cnt_dllk_zqinit_r_reg(2),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__3\(3),
      Q => cnt_dllk_zqinit_r_reg(3),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__3\(4),
      Q => cnt_dllk_zqinit_r_reg(4),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__3\(5),
      Q => cnt_dllk_zqinit_r_reg(5),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__3\(6),
      Q => cnt_dllk_zqinit_r_reg(6),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
\cnt_dllk_zqinit_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__3\(7),
      Q => cnt_dllk_zqinit_r_reg(7),
      R => \cnt_dllk_zqinit_r[7]_i_1_n_0\
    );
cnt_init_af_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000E222"
    )
        port map (
      I0 => cnt_init_af_done_r,
      I1 => cnt_init_mr_r1,
      I2 => cnt_init_af_r(1),
      I3 => cnt_init_af_r(0),
      I4 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      O => cnt_init_af_done_r_i_1_n_0
    );
cnt_init_af_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_init_af_done_r_i_1_n_0,
      Q => cnt_init_af_done_r,
      R => '0'
    );
\cnt_init_af_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => cnt_init_af_r(0),
      I1 => cnt_init_mr_r1,
      I2 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      O => \cnt_init_af_r[0]_i_1_n_0\
    );
\cnt_init_af_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => cnt_init_af_r(1),
      I1 => cnt_init_mr_r1,
      I2 => cnt_init_af_r(0),
      I3 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      O => \cnt_init_af_r[1]_i_1_n_0\
    );
\cnt_init_af_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_init_af_r[0]_i_1_n_0\,
      Q => cnt_init_af_r(0),
      R => '0'
    );
\cnt_init_af_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_init_af_r[1]_i_1_n_0\,
      Q => cnt_init_af_r(1),
      R => '0'
    );
cnt_init_mr_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000E222"
    )
        port map (
      I0 => cnt_init_mr_done_r,
      I1 => \cnt_init_mr_r[1]_i_2_n_0\,
      I2 => cnt_init_mr_r(1),
      I3 => cnt_init_mr_r(0),
      I4 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      I5 => cnt_init_mr_r1,
      O => cnt_init_mr_done_r_i_1_n_0
    );
cnt_init_mr_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_init_mr_done_r_i_1_n_0,
      Q => cnt_init_mr_done_r,
      R => '0'
    );
\cnt_init_mr_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => cnt_init_mr_r(0),
      I1 => \cnt_init_mr_r[1]_i_2_n_0\,
      I2 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      I3 => cnt_init_mr_r1,
      O => \cnt_init_mr_r[0]_i_1_n_0\
    );
\cnt_init_mr_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000006A"
    )
        port map (
      I0 => cnt_init_mr_r(1),
      I1 => \cnt_init_mr_r[1]_i_2_n_0\,
      I2 => cnt_init_mr_r(0),
      I3 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      I4 => cnt_init_mr_r1,
      O => \cnt_init_mr_r[1]_i_1_n_0\
    );
\cnt_init_mr_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => init_complete_r_i_2_n_0,
      O => \cnt_init_mr_r[1]_i_2_n_0\
    );
\cnt_init_mr_r[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \num_refresh[3]_i_7_n_0\,
      I1 => mem_init_done_r,
      O => cnt_init_mr_r1
    );
\cnt_init_mr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_init_mr_r[0]_i_1_n_0\,
      Q => cnt_init_mr_r(0),
      R => '0'
    );
\cnt_init_mr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_init_mr_r[1]_i_1_n_0\,
      Q => cnt_init_mr_r(1),
      R => '0'
    );
cnt_init_pre_wait_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => cnt_init_pre_wait_done_r,
      I1 => cnt_init_pre_wait_r_reg(7),
      I2 => cnt_init_pre_wait_r_reg(6),
      I3 => cnt_init_pre_wait_r_reg(5),
      I4 => cnt_init_pre_wait_done_r_i_2_n_0,
      O => cnt_init_pre_wait_done_r_i_1_n_0
    );
cnt_init_pre_wait_done_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => cnt_init_pre_wait_r_reg(2),
      I1 => cnt_init_pre_wait_r_reg(1),
      I2 => cnt_init_pre_wait_r_reg(4),
      I3 => cnt_init_pre_wait_r_reg(3),
      O => cnt_init_pre_wait_done_r_i_2_n_0
    );
cnt_init_pre_wait_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_init_pre_wait_done_r_i_1_n_0,
      Q => cnt_init_pre_wait_done_r,
      R => clear
    );
\cnt_init_pre_wait_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \cnt_init_pre_wait_r_reg_n_0_[0]\,
      O => \p_0_in__1\(0)
    );
\cnt_init_pre_wait_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_init_pre_wait_r_reg_n_0_[0]\,
      I1 => cnt_init_pre_wait_r_reg(1),
      O => \p_0_in__1\(1)
    );
\cnt_init_pre_wait_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_init_pre_wait_r_reg(2),
      I1 => cnt_init_pre_wait_r_reg(1),
      I2 => \cnt_init_pre_wait_r_reg_n_0_[0]\,
      O => \p_0_in__1\(2)
    );
\cnt_init_pre_wait_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_init_pre_wait_r_reg(3),
      I1 => \cnt_init_pre_wait_r_reg_n_0_[0]\,
      I2 => cnt_init_pre_wait_r_reg(1),
      I3 => cnt_init_pre_wait_r_reg(2),
      O => \p_0_in__1\(3)
    );
\cnt_init_pre_wait_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cnt_init_pre_wait_r_reg(4),
      I1 => cnt_init_pre_wait_r_reg(2),
      I2 => cnt_init_pre_wait_r_reg(1),
      I3 => \cnt_init_pre_wait_r_reg_n_0_[0]\,
      I4 => cnt_init_pre_wait_r_reg(3),
      O => \p_0_in__1\(4)
    );
\cnt_init_pre_wait_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => cnt_init_pre_wait_r_reg(5),
      I1 => cnt_init_pre_wait_r_reg(3),
      I2 => cnt_init_pre_wait_r_reg(4),
      I3 => cnt_init_pre_wait_r_reg(2),
      I4 => cnt_init_pre_wait_r_reg(1),
      I5 => \cnt_init_pre_wait_r_reg_n_0_[0]\,
      O => \p_0_in__1\(5)
    );
\cnt_init_pre_wait_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cnt_init_pre_wait_r_reg(6),
      I1 => \cnt_init_pre_wait_r[7]_i_3_n_0\,
      I2 => cnt_init_pre_wait_r_reg(4),
      I3 => cnt_init_pre_wait_r_reg(3),
      I4 => cnt_init_pre_wait_r_reg(5),
      O => \p_0_in__1\(6)
    );
\cnt_init_pre_wait_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^cnt_pwron_cke_done_r_reg_0\,
      O => clear
    );
\cnt_init_pre_wait_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => cnt_init_pre_wait_r_reg(7),
      I1 => cnt_init_pre_wait_r_reg(5),
      I2 => cnt_init_pre_wait_r_reg(3),
      I3 => cnt_init_pre_wait_r_reg(4),
      I4 => \cnt_init_pre_wait_r[7]_i_3_n_0\,
      I5 => cnt_init_pre_wait_r_reg(6),
      O => \p_0_in__1\(7)
    );
\cnt_init_pre_wait_r[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => cnt_init_pre_wait_r_reg(2),
      I1 => cnt_init_pre_wait_r_reg(1),
      I2 => \cnt_init_pre_wait_r_reg_n_0_[0]\,
      O => \cnt_init_pre_wait_r[7]_i_3_n_0\
    );
\cnt_init_pre_wait_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(0),
      Q => \cnt_init_pre_wait_r_reg_n_0_[0]\,
      R => clear
    );
\cnt_init_pre_wait_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(1),
      Q => cnt_init_pre_wait_r_reg(1),
      R => clear
    );
\cnt_init_pre_wait_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(2),
      Q => cnt_init_pre_wait_r_reg(2),
      R => clear
    );
\cnt_init_pre_wait_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(3),
      Q => cnt_init_pre_wait_r_reg(3),
      R => clear
    );
\cnt_init_pre_wait_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(4),
      Q => cnt_init_pre_wait_r_reg(4),
      R => clear
    );
\cnt_init_pre_wait_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(5),
      Q => cnt_init_pre_wait_r_reg(5),
      R => clear
    );
\cnt_init_pre_wait_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(6),
      Q => cnt_init_pre_wait_r_reg(6),
      R => clear
    );
\cnt_init_pre_wait_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(7),
      Q => cnt_init_pre_wait_r_reg(7),
      R => clear
    );
\cnt_pwron_ce_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(0),
      O => \p_0_in__0\(0)
    );
\cnt_pwron_ce_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(0),
      I1 => cnt_pwron_ce_r_reg(1),
      O => \p_0_in__0\(1)
    );
\cnt_pwron_ce_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(2),
      I1 => cnt_pwron_ce_r_reg(1),
      I2 => cnt_pwron_ce_r_reg(0),
      O => \p_0_in__0\(2)
    );
\cnt_pwron_ce_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(3),
      I1 => cnt_pwron_ce_r_reg(0),
      I2 => cnt_pwron_ce_r_reg(1),
      I3 => cnt_pwron_ce_r_reg(2),
      O => \p_0_in__0\(3)
    );
\cnt_pwron_ce_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(4),
      I1 => cnt_pwron_ce_r_reg(2),
      I2 => cnt_pwron_ce_r_reg(1),
      I3 => cnt_pwron_ce_r_reg(0),
      I4 => cnt_pwron_ce_r_reg(3),
      O => \p_0_in__0\(4)
    );
\cnt_pwron_ce_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(5),
      I1 => cnt_pwron_ce_r_reg(3),
      I2 => cnt_pwron_ce_r_reg(0),
      I3 => cnt_pwron_ce_r_reg(1),
      I4 => cnt_pwron_ce_r_reg(2),
      I5 => cnt_pwron_ce_r_reg(4),
      O => \p_0_in__0\(5)
    );
\cnt_pwron_ce_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(6),
      I1 => pwron_ce_r_i_2_n_0,
      O => \p_0_in__0\(6)
    );
\cnt_pwron_ce_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(7),
      I1 => pwron_ce_r_i_2_n_0,
      I2 => cnt_pwron_ce_r_reg(6),
      O => \p_0_in__0\(7)
    );
\cnt_pwron_ce_r[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(8),
      I1 => cnt_pwron_ce_r_reg(6),
      I2 => pwron_ce_r_i_2_n_0,
      I3 => cnt_pwron_ce_r_reg(7),
      O => \p_0_in__0\(8)
    );
\cnt_pwron_ce_r[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(9),
      I1 => cnt_pwron_ce_r_reg(7),
      I2 => pwron_ce_r_i_2_n_0,
      I3 => cnt_pwron_ce_r_reg(6),
      I4 => cnt_pwron_ce_r_reg(8),
      O => \p_0_in__0\(9)
    );
\cnt_pwron_ce_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => cnt_pwron_ce_r_reg(0),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => cnt_pwron_ce_r_reg(1),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => cnt_pwron_ce_r_reg(2),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => cnt_pwron_ce_r_reg(3),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(4),
      Q => cnt_pwron_ce_r_reg(4),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(5),
      Q => cnt_pwron_ce_r_reg(5),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(6),
      Q => cnt_pwron_ce_r_reg(6),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(7),
      Q => cnt_pwron_ce_r_reg(7),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(8),
      Q => cnt_pwron_ce_r_reg(8),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_ce_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(9),
      Q => cnt_pwron_ce_r_reg(9),
      R => \cnt_pwron_r_reg[0]_0\
    );
cnt_pwron_cke_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F200"
    )
        port map (
      I0 => cnt_pwron_cke_done_r_i_2_n_0,
      I1 => cnt_pwron_cke_done_r_i_3_n_0,
      I2 => \^cnt_pwron_cke_done_r_reg_0\,
      I3 => cnt_pwron_cke_done_r_reg_1(0),
      I4 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      O => cnt_pwron_cke_done_r_i_1_n_0
    );
cnt_pwron_cke_done_r_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => cnt_pwron_r_reg(3),
      I1 => cnt_pwron_r_reg(4),
      I2 => cnt_pwron_r_reg(6),
      O => cnt_pwron_cke_done_r_i_2_n_0
    );
cnt_pwron_cke_done_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => cnt_pwron_r_reg(1),
      I1 => cnt_pwron_r_reg(0),
      I2 => cnt_pwron_r_reg(7),
      I3 => cnt_pwron_r_reg(8),
      I4 => cnt_pwron_r_reg(2),
      I5 => cnt_pwron_r_reg(5),
      O => cnt_pwron_cke_done_r_i_3_n_0
    );
cnt_pwron_cke_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_pwron_cke_done_r_i_1_n_0,
      Q => \^cnt_pwron_cke_done_r_reg_0\,
      R => '0'
    );
\cnt_pwron_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_pwron_r_reg(0),
      O => \p_0_in__0__0\(0)
    );
\cnt_pwron_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_pwron_r_reg(0),
      I1 => cnt_pwron_r_reg(1),
      O => \p_0_in__0__0\(1)
    );
\cnt_pwron_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_pwron_r_reg(2),
      I1 => cnt_pwron_r_reg(1),
      I2 => cnt_pwron_r_reg(0),
      O => \p_0_in__0__0\(2)
    );
\cnt_pwron_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_pwron_r_reg(3),
      I1 => cnt_pwron_r_reg(0),
      I2 => cnt_pwron_r_reg(1),
      I3 => cnt_pwron_r_reg(2),
      O => \p_0_in__0__0\(3)
    );
\cnt_pwron_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cnt_pwron_r_reg(4),
      I1 => cnt_pwron_r_reg(3),
      I2 => cnt_pwron_r_reg(2),
      I3 => cnt_pwron_r_reg(1),
      I4 => cnt_pwron_r_reg(0),
      O => \p_0_in__0__0\(4)
    );
\cnt_pwron_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => cnt_pwron_r_reg(5),
      I1 => cnt_pwron_r_reg(0),
      I2 => cnt_pwron_r_reg(1),
      I3 => cnt_pwron_r_reg(2),
      I4 => cnt_pwron_r_reg(3),
      I5 => cnt_pwron_r_reg(4),
      O => \p_0_in__0__0\(5)
    );
\cnt_pwron_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_pwron_r_reg(6),
      I1 => \cnt_pwron_r[8]_i_2_n_0\,
      O => \p_0_in__0__0\(6)
    );
\cnt_pwron_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_pwron_r_reg(7),
      I1 => \cnt_pwron_r[8]_i_2_n_0\,
      I2 => cnt_pwron_r_reg(6),
      O => \p_0_in__0__0\(7)
    );
\cnt_pwron_r[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_pwron_r_reg(8),
      I1 => cnt_pwron_r_reg(6),
      I2 => \cnt_pwron_r[8]_i_2_n_0\,
      I3 => cnt_pwron_r_reg(7),
      O => \p_0_in__0__0\(8)
    );
\cnt_pwron_r[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => cnt_pwron_r_reg(5),
      I1 => cnt_pwron_r_reg(0),
      I2 => cnt_pwron_r_reg(1),
      I3 => cnt_pwron_r_reg(2),
      I4 => cnt_pwron_r_reg(3),
      I5 => cnt_pwron_r_reg(4),
      O => \cnt_pwron_r[8]_i_2_n_0\
    );
\cnt_pwron_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__0__0\(0),
      Q => cnt_pwron_r_reg(0),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__0__0\(1),
      Q => cnt_pwron_r_reg(1),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__0__0\(2),
      Q => cnt_pwron_r_reg(2),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__0__0\(3),
      Q => cnt_pwron_r_reg(3),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__0__0\(4),
      Q => cnt_pwron_r_reg(4),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__0__0\(5),
      Q => cnt_pwron_r_reg(5),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__0__0\(6),
      Q => cnt_pwron_r_reg(6),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__0__0\(7),
      Q => cnt_pwron_r_reg(7),
      R => \cnt_pwron_r_reg[0]_0\
    );
\cnt_pwron_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__0__0\(8),
      Q => cnt_pwron_r_reg(8),
      R => \cnt_pwron_r_reg[0]_0\
    );
\complex_address[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF04FF04040400"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I3 => init_state_r1(2),
      I4 => \complex_address[9]_i_2_n_0\,
      I5 => \complex_address[9]_i_3_n_0\,
      O => complex_address0
    );
\complex_address[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFFFFFFFFFFFFF"
    )
        port map (
      I0 => init_state_r1(6),
      I1 => init_state_r1(5),
      I2 => init_state_r1(4),
      I3 => init_state_r1(1),
      I4 => init_state_r1(0),
      I5 => init_state_r1(3),
      O => \complex_address[9]_i_2_n_0\
    );
\complex_address[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080000000000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \complex_address[9]_i_3_n_0\
    );
\complex_address_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      Q => \complex_address_reg_n_0_[0]\,
      R => \complex_address_reg[9]_0\(1)
    );
\complex_address_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      Q => \complex_address_reg_n_0_[1]\,
      R => \complex_address_reg[9]_0\(1)
    );
\complex_address_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      Q => \complex_address_reg_n_0_[2]\,
      R => \complex_address_reg[9]_0\(1)
    );
\complex_address_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      Q => \complex_address_reg_n_0_[3]\,
      R => \complex_address_reg[9]_0\(1)
    );
\complex_address_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      Q => \complex_address_reg_n_0_[4]\,
      R => \complex_address_reg[9]_0\(1)
    );
\complex_address_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      Q => \complex_address_reg_n_0_[5]\,
      R => \complex_address_reg[9]_0\(1)
    );
\complex_address_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      Q => \complex_address_reg_n_0_[6]\,
      R => \complex_address_reg[9]_0\(1)
    );
\complex_address_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      Q => \complex_address_reg_n_0_[7]\,
      R => \complex_address_reg[9]_0\(1)
    );
\complex_address_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      Q => \complex_address_reg_n_0_[8]\,
      R => \complex_address_reg[9]_0\(1)
    );
\complex_address_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      Q => \complex_address_reg_n_0_[9]\,
      R => \complex_address_reg[9]_0\(1)
    );
complex_byte_rd_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02020200"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I1 => \wrcal_reads_reg[0]_0\,
      I2 => \^prbs_rdlvl_done_pulse_reg_0\,
      I3 => complex_byte_rd_done_i_2_n_0,
      I4 => complex_byte_rd_done,
      O => complex_byte_rd_done_i_1_n_0
    );
complex_byte_rd_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => complex_row1_rd_cnt(0),
      I1 => complex_row1_rd_cnt(1),
      I2 => complex_row1_rd_cnt(2),
      I3 => complex_row1_rd_done,
      I4 => complex_row1_rd_done_r1,
      I5 => D(2),
      O => complex_byte_rd_done_i_2_n_0
    );
complex_byte_rd_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_byte_rd_done_i_1_n_0,
      Q => complex_byte_rd_done,
      R => '0'
    );
\complex_num_reads[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF26EEFFEE"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[0]\,
      I1 => \complex_num_reads[3]_i_2_n_0\,
      I2 => \complex_num_writes[4]_i_4_n_0\,
      I3 => \complex_num_reads[3]_i_4_n_0\,
      I4 => \complex_num_writes[4]_i_3_n_0\,
      I5 => \complex_num_reads[3]_i_5_n_0\,
      O => \complex_num_reads[0]_i_1_n_0\
    );
\complex_num_reads[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000E2F222F2"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[1]\,
      I1 => \complex_num_reads[3]_i_2_n_0\,
      I2 => \complex_num_reads[3]_i_4_n_0\,
      I3 => \complex_num_writes[4]_i_3_n_0\,
      I4 => \complex_num_reads[1]_i_2_n_0\,
      I5 => \complex_num_reads[3]_i_5_n_0\,
      O => \complex_num_reads[1]_i_1_n_0\
    );
\complex_num_reads[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[1]\,
      I1 => \complex_num_reads_reg_n_0_[0]\,
      I2 => \complex_num_writes[4]_i_4_n_0\,
      O => \complex_num_reads[1]_i_2_n_0\
    );
\complex_num_reads[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040404440404000"
    )
        port map (
      I0 => \complex_num_reads[3]_i_5_n_0\,
      I1 => \complex_num_reads[2]_i_2_n_0\,
      I2 => \complex_num_reads[2]_i_3_n_0\,
      I3 => \complex_num_reads[2]_i_4_n_0\,
      I4 => \complex_num_reads[3]_i_2_n_0\,
      I5 => \complex_num_reads_reg_n_0_[2]\,
      O => \complex_num_reads[2]_i_1_n_0\
    );
\complex_num_reads[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \complex_num_writes[2]_i_2_n_0\,
      I1 => \complex_num_reads[3]_i_4_n_0\,
      O => \complex_num_reads[2]_i_2_n_0\
    );
\complex_num_reads[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2888AAAA"
    )
        port map (
      I0 => \complex_num_reads[3]_i_4_n_0\,
      I1 => \complex_num_reads_reg_n_0_[2]\,
      I2 => \complex_num_reads_reg_n_0_[1]\,
      I3 => \complex_num_reads_reg_n_0_[0]\,
      I4 => \complex_num_writes[2]_i_8_n_0\,
      O => \complex_num_reads[2]_i_3_n_0\
    );
\complex_num_reads[2]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \complex_num_writes[4]_i_9_n_0\,
      I1 => \complex_num_reads[3]_i_4_n_0\,
      O => \complex_num_reads[2]_i_4_n_0\
    );
\complex_num_reads[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000002E220022"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[3]\,
      I1 => \complex_num_reads[3]_i_2_n_0\,
      I2 => \complex_num_reads[3]_i_3_n_0\,
      I3 => \complex_num_reads[3]_i_4_n_0\,
      I4 => \complex_num_writes[4]_i_3_n_0\,
      I5 => \complex_num_reads[3]_i_5_n_0\,
      O => \complex_num_reads[3]_i_1_n_0\
    );
\complex_num_reads[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AABA"
    )
        port map (
      I0 => \complex_num_reads_dec[3]_i_5_n_0\,
      I1 => \complex_num_reads[3]_i_6_n_0\,
      I2 => \complex_num_reads[3]_i_4_n_0\,
      I3 => \complex_num_reads[3]_i_7_n_0\,
      O => \complex_num_reads[3]_i_2_n_0\
    );
\complex_num_reads[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000807F"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[2]\,
      I1 => \complex_num_reads_reg_n_0_[1]\,
      I2 => \complex_num_reads_reg_n_0_[0]\,
      I3 => \complex_num_reads_reg_n_0_[3]\,
      I4 => \complex_num_writes[4]_i_4_n_0\,
      O => \complex_num_reads[3]_i_3_n_0\
    );
\complex_num_reads[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => \complex_num_reads[3]_i_8_n_0\,
      I1 => complex_wait_cnt_reg(3),
      I2 => complex_wait_cnt_reg(2),
      I3 => complex_wait_cnt_reg(1),
      I4 => complex_wait_cnt_reg(0),
      I5 => complex_row0_rd_done,
      O => \complex_num_reads[3]_i_4_n_0\
    );
\complex_num_reads[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAEAEAEAEAAAAAAA"
    )
        port map (
      I0 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      I1 => \complex_num_reads[3]_i_4_n_0\,
      I2 => \complex_num_writes[4]_i_15_n_0\,
      I3 => \complex_num_reads_reg_n_0_[1]\,
      I4 => \complex_num_reads_reg_n_0_[2]\,
      I5 => \complex_num_reads_reg_n_0_[3]\,
      O => \complex_num_reads[3]_i_5_n_0\
    );
\complex_num_reads[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000044400000"
    )
        port map (
      I0 => \complex_num_writes[4]_i_4_n_0\,
      I1 => \complex_num_writes[4]_i_22_n_0\,
      I2 => \complex_num_reads_reg_n_0_[1]\,
      I3 => \complex_num_reads_reg_n_0_[2]\,
      I4 => \complex_num_reads_reg_n_0_[3]\,
      I5 => \complex_num_writes[4]_i_13_n_0\,
      O => \complex_num_reads[3]_i_6_n_0\
    );
\complex_num_reads[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFA8"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[2]\,
      I1 => \complex_num_reads_reg_n_0_[1]\,
      I2 => \complex_num_reads_reg_n_0_[0]\,
      I3 => \complex_num_reads_reg_n_0_[3]\,
      I4 => \complex_num_writes[4]_i_15_n_0\,
      I5 => \complex_num_writes[4]_i_22_n_0\,
      O => \complex_num_reads[3]_i_7_n_0\
    );
\complex_num_reads[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \complex_num_reads[3]_i_8_n_0\
    );
\complex_num_reads_dec[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => complex_num_reads_dec(0),
      I1 => \complex_num_reads_dec[3]_i_3_n_0\,
      I2 => \complex_num_reads_reg_n_0_[0]\,
      O => \complex_num_reads_dec[0]_i_1_n_0\
    );
\complex_num_reads_dec[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9F90"
    )
        port map (
      I0 => complex_num_reads_dec(0),
      I1 => complex_num_reads_dec(1),
      I2 => \complex_num_reads_dec[3]_i_3_n_0\,
      I3 => \complex_num_reads_reg_n_0_[1]\,
      O => \complex_num_reads_dec[1]_i_1_n_0\
    );
\complex_num_reads_dec[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A9FFA900"
    )
        port map (
      I0 => complex_num_reads_dec(2),
      I1 => complex_num_reads_dec(1),
      I2 => complex_num_reads_dec(0),
      I3 => \complex_num_reads_dec[3]_i_3_n_0\,
      I4 => \complex_num_reads_reg_n_0_[2]\,
      O => \complex_num_reads_dec[2]_i_1_n_0\
    );
\complex_num_reads_dec[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555555FFFFFFFD"
    )
        port map (
      I0 => \complex_num_reads_dec[3]_i_3_n_0\,
      I1 => complex_num_reads_dec(3),
      I2 => complex_num_reads_dec(2),
      I3 => complex_num_reads_dec(0),
      I4 => complex_num_reads_dec(1),
      I5 => \complex_num_reads_dec[3]_i_4_n_0\,
      O => \complex_num_reads_dec[3]_i_1_n_0\
    );
\complex_num_reads_dec[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA9FFFFAAA90000"
    )
        port map (
      I0 => complex_num_reads_dec(3),
      I1 => complex_num_reads_dec(2),
      I2 => complex_num_reads_dec(0),
      I3 => complex_num_reads_dec(1),
      I4 => \complex_num_reads_dec[3]_i_3_n_0\,
      I5 => \complex_num_reads_reg_n_0_[3]\,
      O => \complex_num_reads_dec[3]_i_2_n_0\
    );
\complex_num_reads_dec[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555545555"
    )
        port map (
      I0 => \complex_num_reads_dec[3]_i_5_n_0\,
      I1 => complex_row0_rd_done,
      I2 => \complex_num_reads_dec[3]_i_6_n_0\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      O => \complex_num_reads_dec[3]_i_3_n_0\
    );
\complex_num_reads_dec[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFFFFFFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \wrcal_reads[7]_i_5_n_0\,
      O => \complex_num_reads_dec[3]_i_4_n_0\
    );
\complex_num_reads_dec[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400100000000000"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4_n_0\,
      O => \complex_num_reads_dec[3]_i_5_n_0\
    );
\complex_num_reads_dec[3]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => complex_wait_cnt_reg(1),
      I1 => complex_wait_cnt_reg(0),
      I2 => complex_wait_cnt_reg(3),
      I3 => complex_wait_cnt_reg(2),
      O => \complex_num_reads_dec[3]_i_6_n_0\
    );
\complex_num_reads_dec_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \complex_num_reads_dec[3]_i_1_n_0\,
      D => \complex_num_reads_dec[0]_i_1_n_0\,
      Q => complex_num_reads_dec(0),
      S => \complex_address_reg[9]_0\(0)
    );
\complex_num_reads_dec_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_reads_dec[3]_i_1_n_0\,
      D => \complex_num_reads_dec[1]_i_1_n_0\,
      Q => complex_num_reads_dec(1),
      R => \complex_address_reg[9]_0\(0)
    );
\complex_num_reads_dec_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_reads_dec[3]_i_1_n_0\,
      D => \complex_num_reads_dec[2]_i_1_n_0\,
      Q => complex_num_reads_dec(2),
      R => \complex_address_reg[9]_0\(0)
    );
\complex_num_reads_dec_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_reads_dec[3]_i_1_n_0\,
      D => \complex_num_reads_dec[3]_i_2_n_0\,
      Q => complex_num_reads_dec(3),
      R => \complex_address_reg[9]_0\(0)
    );
\complex_num_reads_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_reads[0]_i_1_n_0\,
      Q => \complex_num_reads_reg_n_0_[0]\,
      R => '0'
    );
\complex_num_reads_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_reads[1]_i_1_n_0\,
      Q => \complex_num_reads_reg_n_0_[1]\,
      R => '0'
    );
\complex_num_reads_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_reads[2]_i_1_n_0\,
      Q => \complex_num_reads_reg_n_0_[2]\,
      R => '0'
    );
\complex_num_reads_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_reads[3]_i_1_n_0\,
      Q => \complex_num_reads_reg_n_0_[3]\,
      R => '0'
    );
\complex_num_writes[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF2226EE26"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[0]\,
      I1 => \complex_num_writes[3]_i_2_n_0\,
      I2 => \complex_num_writes[4]_i_4_n_0\,
      I3 => \complex_num_writes[4]_i_2_n_0\,
      I4 => \complex_num_writes[0]_i_2_n_0\,
      I5 => \complex_num_writes[0]_i_3_n_0\,
      O => \complex_num_writes[0]_i_1_n_0\
    );
\complex_num_writes[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800000000000000"
    )
        port map (
      I0 => complex_row0_wr_done,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \wrcal_reads[7]_i_4_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4_n_0\,
      O => \complex_num_writes[0]_i_2_n_0\
    );
\complex_num_writes[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5F5D5F5F5F5D5F5D"
    )
        port map (
      I0 => \complex_num_writes_reg[4]_0\,
      I1 => \complex_num_writes[4]_i_5_n_0\,
      I2 => \complex_num_writes[4]_i_2_n_0\,
      I3 => \complex_num_writes[4]_i_9_n_0\,
      I4 => \complex_num_writes[1]_i_3_n_0\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      O => \complex_num_writes[0]_i_3_n_0\
    );
\complex_num_writes[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEF2220"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[1]\,
      I1 => \complex_num_writes[3]_i_2_n_0\,
      I2 => \complex_num_writes[4]_i_3_n_0\,
      I3 => \complex_num_writes[4]_i_2_n_0\,
      I4 => \complex_num_writes[1]_i_2_n_0\,
      I5 => \complex_num_writes[3]_i_4_n_0\,
      O => \complex_num_writes[1]_i_1_n_0\
    );
\complex_num_writes[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000FFFFFFBA"
    )
        port map (
      I0 => \complex_num_writes[4]_i_9_n_0\,
      I1 => \complex_num_writes[1]_i_3_n_0\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \complex_num_writes[1]_i_4_n_0\,
      I4 => \complex_num_writes[0]_i_2_n_0\,
      I5 => \complex_num_writes[4]_i_2_n_0\,
      O => \complex_num_writes[1]_i_2_n_0\
    );
\complex_num_writes[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I2 => \complex_num_writes[2]_i_4_n_0\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I5 => \complex_num_writes[4]_i_11_n_0\,
      O => \complex_num_writes[1]_i_3_n_0\
    );
\complex_num_writes[1]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[1]\,
      I1 => \complex_num_writes_reg_n_0_[0]\,
      I2 => \complex_num_writes[4]_i_4_n_0\,
      O => \complex_num_writes[1]_i_4_n_0\
    );
\complex_num_writes[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4500"
    )
        port map (
      I0 => \complex_num_writes[3]_i_4_n_0\,
      I1 => \complex_num_writes[4]_i_2_n_0\,
      I2 => \complex_num_writes[2]_i_2_n_0\,
      I3 => \complex_num_writes[2]_i_3_n_0\,
      O => \complex_num_writes[2]_i_1_n_0\
    );
\complex_num_writes[2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800000000000000"
    )
        port map (
      I0 => \complex_num_writes[4]_i_20_n_0\,
      I1 => \complex_num_writes[2]_i_11_n_0\,
      I2 => \complex_num_writes[4]_i_13_n_0\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      O => \complex_num_writes[2]_i_10_n_0\
    );
\complex_num_writes[2]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      O => \complex_num_writes[2]_i_11_n_0\
    );
\complex_num_writes[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => \complex_num_writes[4]_i_14_n_0\,
      I1 => \complex_num_writes[2]_i_4_n_0\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      O => \complex_num_writes[2]_i_2_n_0\
    );
\complex_num_writes[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2FFF3F3F20003030"
    )
        port map (
      I0 => \complex_num_writes[2]_i_5_n_0\,
      I1 => \complex_num_writes[2]_i_6_n_0\,
      I2 => \complex_num_writes[2]_i_7_n_0\,
      I3 => \complex_num_writes[4]_i_18_n_0\,
      I4 => \complex_num_writes[2]_i_8_n_0\,
      I5 => \complex_num_writes_reg_n_0_[2]\,
      O => \complex_num_writes[2]_i_3_n_0\
    );
\complex_num_writes[2]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \complex_num_writes[2]_i_4_n_0\
    );
\complex_num_writes[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8FFFF888"
    )
        port map (
      I0 => \complex_num_writes[4]_i_17_n_0\,
      I1 => complex_row0_wr_done,
      I2 => \complex_num_writes_reg_n_0_[0]\,
      I3 => \complex_num_writes_reg_n_0_[1]\,
      I4 => \complex_num_writes_reg_n_0_[2]\,
      O => \complex_num_writes[2]_i_5_n_0\
    );
\complex_num_writes[2]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \complex_num_writes[4]_i_2_n_0\,
      I1 => \complex_num_writes[4]_i_17_n_0\,
      I2 => complex_row0_wr_done,
      O => \complex_num_writes[2]_i_6_n_0\
    );
\complex_num_writes[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20000000FFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \wrcal_reads[7]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4_n_0\,
      I5 => \complex_num_writes[4]_i_2_n_0\,
      O => \complex_num_writes[2]_i_7_n_0\
    );
\complex_num_writes[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFB00FFFFFBFB"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \complex_num_writes[2]_i_9_n_0\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I5 => \complex_num_writes[2]_i_10_n_0\,
      O => \complex_num_writes[2]_i_8_n_0\
    );
\complex_num_writes[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFDFFF"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      O => \complex_num_writes[2]_i_9_n_0\
    );
\complex_num_writes[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000E2E2E200"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[3]\,
      I1 => \complex_num_writes[3]_i_2_n_0\,
      I2 => \complex_num_writes[3]_i_3_n_0\,
      I3 => \complex_num_writes[4]_i_3_n_0\,
      I4 => \complex_num_writes[4]_i_2_n_0\,
      I5 => \complex_num_writes[3]_i_4_n_0\,
      O => \complex_num_writes[3]_i_1_n_0\
    );
\complex_num_writes[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DDD0"
    )
        port map (
      I0 => \complex_num_writes[4]_i_2_n_0\,
      I1 => \complex_num_writes[4]_i_17_n_0\,
      I2 => \complex_num_writes[4]_i_18_n_0\,
      I3 => \complex_num_writes[4]_i_4_n_0\,
      O => \complex_num_writes[3]_i_2_n_0\
    );
\complex_num_writes[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000FFFFFFD2"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[0]\,
      I1 => \complex_num_writes[3]_i_5_n_0\,
      I2 => \complex_num_writes_reg_n_0_[3]\,
      I3 => \complex_num_writes[4]_i_4_n_0\,
      I4 => \complex_num_writes[0]_i_2_n_0\,
      I5 => \complex_num_writes[4]_i_2_n_0\,
      O => \complex_num_writes[3]_i_3_n_0\
    );
\complex_num_writes[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF4"
    )
        port map (
      I0 => \complex_num_writes[4]_i_2_n_0\,
      I1 => \complex_num_writes[4]_i_5_n_0\,
      I2 => \^prbs_rdlvl_done_pulse_reg_0\,
      I3 => \wrcal_reads_reg[0]_0\,
      O => \complex_num_writes[3]_i_4_n_0\
    );
\complex_num_writes[3]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[1]\,
      I1 => \complex_num_writes_reg_n_0_[2]\,
      O => \complex_num_writes[3]_i_5_n_0\
    );
\complex_num_writes[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAE000000000000"
    )
        port map (
      I0 => \complex_num_writes[4]_i_2_n_0\,
      I1 => \complex_num_writes[4]_i_3_n_0\,
      I2 => \complex_num_writes[4]_i_4_n_0\,
      I3 => \complex_num_writes[4]_i_5_n_0\,
      I4 => \complex_num_writes_reg[4]_0\,
      I5 => \complex_num_writes[4]_i_6_n_0\,
      O => \complex_num_writes[4]_i_1_n_0\
    );
\complex_num_writes[4]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      O => \complex_num_writes[4]_i_10_n_0\
    );
\complex_num_writes[4]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      O => \complex_num_writes[4]_i_11_n_0\
    );
\complex_num_writes[4]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \complex_num_writes[4]_i_12_n_0\
    );
\complex_num_writes[4]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000100010101"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      O => \complex_num_writes[4]_i_13_n_0\
    );
\complex_num_writes[4]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      O => \complex_num_writes[4]_i_14_n_0\
    );
\complex_num_writes[4]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFBAAAAFAFAAAAA"
    )
        port map (
      I0 => \complex_num_writes[4]_i_11_n_0\,
      I1 => \complex_num_writes[4]_i_12_n_0\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      O => \complex_num_writes[4]_i_15_n_0\
    );
\complex_num_writes[4]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"95555555"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[4]\,
      I1 => \complex_num_writes_reg_n_0_[0]\,
      I2 => \complex_num_writes_reg_n_0_[2]\,
      I3 => \complex_num_writes_reg_n_0_[1]\,
      I4 => \complex_num_writes_reg_n_0_[3]\,
      O => \complex_num_writes[4]_i_16_n_0\
    );
\complex_num_writes[4]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \complex_num_writes[4]_i_17_n_0\
    );
\complex_num_writes[4]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF4FFF4F0"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[4]\,
      I1 => \complex_num_writes[4]_i_21_n_0\,
      I2 => \complex_num_writes[4]_i_15_n_0\,
      I3 => \complex_num_writes[4]_i_22_n_0\,
      I4 => \complex_num_writes[4]_i_23_n_0\,
      I5 => \complex_num_writes[4]_i_2_n_0\,
      O => \complex_num_writes[4]_i_18_n_0\
    );
\complex_num_writes[4]_i_19\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \complex_num_writes[4]_i_13_n_0\,
      O => \complex_num_writes[4]_i_19_n_0\
    );
\complex_num_writes[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFFFFFFFFFF"
    )
        port map (
      I0 => complex_row0_wr_done,
      I1 => \complex_num_writes[4]_i_7_n_0\,
      I2 => \complex_num_writes[4]_i_8_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \complex_num_writes[4]_i_2_n_0\
    );
\complex_num_writes[4]_i_20\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      O => \complex_num_writes[4]_i_20_n_0\
    );
\complex_num_writes[4]_i_21\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F57"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[3]\,
      I1 => \complex_num_writes_reg_n_0_[1]\,
      I2 => \complex_num_writes_reg_n_0_[2]\,
      I3 => \complex_num_writes[4]_i_13_n_0\,
      O => \complex_num_writes[4]_i_21_n_0\
    );
\complex_num_writes[4]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000003B3B3BBB"
    )
        port map (
      I0 => \complex_num_writes[4]_i_20_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I5 => \complex_num_writes[4]_i_11_n_0\,
      O => \complex_num_writes[4]_i_22_n_0\
    );
\complex_num_writes[4]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00011111"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[4]\,
      I1 => \complex_num_writes_reg_n_0_[3]\,
      I2 => \complex_num_writes_reg_n_0_[0]\,
      I3 => \complex_num_writes_reg_n_0_[1]\,
      I4 => \complex_num_writes_reg_n_0_[2]\,
      O => \complex_num_writes[4]_i_23_n_0\
    );
\complex_num_writes[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555455555555"
    )
        port map (
      I0 => \complex_num_writes[4]_i_9_n_0\,
      I1 => \complex_num_writes[4]_i_10_n_0\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I4 => \complex_num_writes[4]_i_11_n_0\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      O => \complex_num_writes[4]_i_3_n_0\
    );
\complex_num_writes[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => \complex_num_writes[4]_i_12_n_0\,
      I2 => \complex_num_writes[4]_i_13_n_0\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I4 => \stg1_wr_rd_cnt[8]_i_7_n_0\,
      I5 => \complex_num_writes[4]_i_14_n_0\,
      O => \complex_num_writes[4]_i_4_n_0\
    );
\complex_num_writes[4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA8A8A8"
    )
        port map (
      I0 => \complex_num_writes[4]_i_15_n_0\,
      I1 => \complex_num_writes_reg_n_0_[3]\,
      I2 => \complex_num_writes_reg_n_0_[4]\,
      I3 => \complex_num_writes_reg_n_0_[1]\,
      I4 => \complex_num_writes_reg_n_0_[2]\,
      O => \complex_num_writes[4]_i_5_n_0\
    );
\complex_num_writes[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABF3FFFFAB030000"
    )
        port map (
      I0 => complex_row0_wr_done,
      I1 => \complex_num_writes[4]_i_16_n_0\,
      I2 => \complex_num_writes[4]_i_2_n_0\,
      I3 => \complex_num_writes[4]_i_17_n_0\,
      I4 => \complex_num_writes[4]_i_18_n_0\,
      I5 => \complex_num_writes_reg_n_0_[4]\,
      O => \complex_num_writes[4]_i_6_n_0\
    );
\complex_num_writes[4]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => complex_wait_cnt_reg(3),
      I1 => complex_wait_cnt_reg(2),
      I2 => complex_wait_cnt_reg(1),
      I3 => complex_wait_cnt_reg(0),
      O => \complex_num_writes[4]_i_7_n_0\
    );
\complex_num_writes[4]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      O => \complex_num_writes[4]_i_8_n_0\
    );
\complex_num_writes[4]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \complex_num_writes[4]_i_19_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I3 => \complex_num_writes[4]_i_20_n_0\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \complex_num_writes[4]_i_9_n_0\
    );
\complex_num_writes_dec[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => complex_num_writes_dec_reg(0),
      I1 => \complex_num_writes_dec[4]_i_5_n_0\,
      I2 => \complex_num_writes_reg_n_0_[0]\,
      O => \p_0_in__5\(0)
    );
\complex_num_writes_dec[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9F90"
    )
        port map (
      I0 => complex_num_writes_dec_reg(0),
      I1 => complex_num_writes_dec_reg(1),
      I2 => \complex_num_writes_dec[4]_i_5_n_0\,
      I3 => \complex_num_writes_reg_n_0_[1]\,
      O => \p_0_in__5\(1)
    );
\complex_num_writes_dec[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A9FFA900"
    )
        port map (
      I0 => complex_num_writes_dec_reg(2),
      I1 => complex_num_writes_dec_reg(1),
      I2 => complex_num_writes_dec_reg(0),
      I3 => \complex_num_writes_dec[4]_i_5_n_0\,
      I4 => \complex_num_writes_reg_n_0_[2]\,
      O => \p_0_in__5\(2)
    );
\complex_num_writes_dec[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA9FFFFAAA90000"
    )
        port map (
      I0 => complex_num_writes_dec_reg(3),
      I1 => complex_num_writes_dec_reg(2),
      I2 => complex_num_writes_dec_reg(0),
      I3 => complex_num_writes_dec_reg(1),
      I4 => \complex_num_writes_dec[4]_i_5_n_0\,
      I5 => \complex_num_writes_reg_n_0_[3]\,
      O => \p_0_in__5\(3)
    );
\complex_num_writes_dec[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^prbs_rdlvl_done_pulse_reg_0\,
      I1 => \wrcal_reads_reg[0]_0\,
      O => complex_row0_rd_done1
    );
\complex_num_writes_dec[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0DFF"
    )
        port map (
      I0 => \complex_num_writes_dec[4]_i_4_n_0\,
      I1 => complex_num_writes_dec_reg(4),
      I2 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I3 => \complex_num_writes_dec[4]_i_5_n_0\,
      O => \complex_num_writes_dec[4]_i_2_n_0\
    );
\complex_num_writes_dec[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6F60"
    )
        port map (
      I0 => complex_num_writes_dec_reg(4),
      I1 => \complex_num_writes_dec[4]_i_4_n_0\,
      I2 => \complex_num_writes_dec[4]_i_5_n_0\,
      I3 => \complex_num_writes_reg_n_0_[4]\,
      O => \p_0_in__5\(4)
    );
\complex_num_writes_dec[4]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => complex_num_writes_dec_reg(2),
      I1 => complex_num_writes_dec_reg(0),
      I2 => complex_num_writes_dec_reg(1),
      I3 => complex_num_writes_dec_reg(3),
      O => \complex_num_writes_dec[4]_i_4_n_0\
    );
\complex_num_writes_dec[4]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EF"
    )
        port map (
      I0 => complex_row0_rd_done,
      I1 => \complex_num_reads_dec[3]_i_6_n_0\,
      I2 => \complex_address[9]_i_3_n_0\,
      I3 => \complex_num_reads_dec[3]_i_5_n_0\,
      O => \complex_num_writes_dec[4]_i_5_n_0\
    );
\complex_num_writes_dec_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \p_0_in__5\(0),
      Q => complex_num_writes_dec_reg(0),
      S => complex_row0_rd_done1
    );
\complex_num_writes_dec_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \p_0_in__5\(1),
      Q => complex_num_writes_dec_reg(1),
      R => complex_row0_rd_done1
    );
\complex_num_writes_dec_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \p_0_in__5\(2),
      Q => complex_num_writes_dec_reg(2),
      R => complex_row0_rd_done1
    );
\complex_num_writes_dec_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \p_0_in__5\(3),
      Q => complex_num_writes_dec_reg(3),
      R => complex_row0_rd_done1
    );
\complex_num_writes_dec_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \p_0_in__5\(4),
      Q => complex_num_writes_dec_reg(4),
      R => complex_row0_rd_done1
    );
\complex_num_writes_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_writes[0]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[0]\,
      R => '0'
    );
\complex_num_writes_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_writes[1]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[1]\,
      R => '0'
    );
\complex_num_writes_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_writes[2]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[2]\,
      R => '0'
    );
\complex_num_writes_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_writes[3]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[3]\,
      R => '0'
    );
\complex_num_writes_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_writes[4]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[4]\,
      R => '0'
    );
complex_ocal_odt_ext_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000D0D0D00"
    )
        port map (
      I0 => init_complete_r_i_2_n_0,
      I1 => complex_ocal_odt_ext_i_2_n_0,
      I2 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      I3 => complex_ocal_odt_ext,
      I4 => complex_ocal_odt_ext_i_3_n_0,
      I5 => complex_ocal_odt_ext_i_4_n_0,
      O => complex_ocal_odt_ext_i_1_n_0
    );
complex_ocal_odt_ext_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFDF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      O => complex_ocal_odt_ext_i_2_n_0
    );
complex_ocal_odt_ext_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => complex_ocal_odt_ext_i_3_n_0
    );
complex_ocal_odt_ext_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800000000000000"
    )
        port map (
      I0 => complex_ocal_odt_ext_i_5_n_0,
      I1 => cnt_cmd_done_m7_r,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => complex_ocal_odt_ext_i_4_n_0
    );
complex_ocal_odt_ext_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[5]\,
      O => complex_ocal_odt_ext_i_5_n_0
    );
complex_ocal_odt_ext_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_ocal_odt_ext_i_1_n_0,
      Q => complex_ocal_odt_ext,
      R => '0'
    );
complex_ocal_reset_rd_addr_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAEAAAAAAAAAA"
    )
        port map (
      I0 => prbs_rdlvl_done_pulse0,
      I1 => complex_wait_cnt_reg(0),
      I2 => complex_wait_cnt_reg(1),
      I3 => complex_wait_cnt_reg(3),
      I4 => complex_wait_cnt_reg(2),
      I5 => complex_ocal_reset_rd_addr_i_2_n_0,
      O => complex_ocal_reset_rd_addr0
    );
complex_ocal_reset_rd_addr_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080000000000000"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => complex_ocal_reset_rd_addr_i_2_n_0
    );
complex_ocal_reset_rd_addr_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_ocal_reset_rd_addr0,
      Q => complex_ocal_reset_rd_addr,
      R => '0'
    );
complex_oclkdelay_calib_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(2),
      Q => complex_oclkdelay_calib_done_r1,
      R => rdlvl_stg1_start_reg_1
    );
complex_oclkdelay_calib_start_int_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1000"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \^q\(0),
      I3 => \^rdlvl_stg1_done_r1\,
      I4 => complex_oclkdelay_calib_start_int,
      O => complex_oclkdelay_calib_start_int_i_1_n_0
    );
complex_oclkdelay_calib_start_int_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_oclkdelay_calib_start_int_i_1_n_0,
      Q => complex_oclkdelay_calib_start_int,
      R => \complex_address_reg[9]_0\(0)
    );
complex_oclkdelay_calib_start_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_oclkdelay_calib_start_int,
      Q => complex_oclkdelay_calib_start_r1,
      R => '0'
    );
complex_odt_ext_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055550010"
    )
        port map (
      I0 => \wrcal_reads_reg[0]_0\,
      I1 => complex_sample_cnt_inc_i_2_n_0,
      I2 => \^rdlvl_stg1_done_r1\,
      I3 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I4 => complex_odt_ext,
      I5 => complex_row1_rd_done_i_2_n_0,
      O => complex_odt_ext_i_1_n_0
    );
complex_odt_ext_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_odt_ext_i_1_n_0,
      Q => complex_odt_ext,
      R => '0'
    );
complex_row0_rd_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAA8000"
    )
        port map (
      I0 => \complex_num_writes_reg[4]_0\,
      I1 => complex_row1_wr_done,
      I2 => complex_oclkdelay_calib_start_int,
      I3 => complex_row1_wr_done0,
      I4 => complex_row0_rd_done,
      I5 => complex_sample_cnt_inc_reg_n_0,
      O => complex_row0_rd_done_i_1_n_0
    );
complex_row0_rd_done_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00020000"
    )
        port map (
      I0 => complex_row0_wr_done,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I2 => wr_victim_inc_i_2_n_0,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      O => complex_row1_wr_done0
    );
complex_row0_rd_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_row0_rd_done_i_1_n_0,
      Q => complex_row0_rd_done,
      R => '0'
    );
\complex_row1_rd_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000A6"
    )
        port map (
      I0 => complex_row1_rd_cnt(0),
      I1 => complex_row1_rd_done,
      I2 => complex_row1_rd_done_r1,
      I3 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      I4 => \^prbs_rdlvl_done_pulse_reg_0\,
      O => \complex_row1_rd_cnt[0]_i_1_n_0\
    );
\complex_row1_rd_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000009AAA"
    )
        port map (
      I0 => complex_row1_rd_cnt(1),
      I1 => complex_row1_rd_done_r1,
      I2 => complex_row1_rd_done,
      I3 => complex_row1_rd_cnt(0),
      I4 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      I5 => \^prbs_rdlvl_done_pulse_reg_0\,
      O => \complex_row1_rd_cnt[1]_i_1_n_0\
    );
\complex_row1_rd_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000009AAAAAAA"
    )
        port map (
      I0 => complex_row1_rd_cnt(2),
      I1 => complex_row1_rd_done_r1,
      I2 => complex_row1_rd_done,
      I3 => complex_row1_rd_cnt(0),
      I4 => complex_row1_rd_cnt(1),
      I5 => complex_row0_rd_done1,
      O => \complex_row1_rd_cnt[2]_i_1_n_0\
    );
\complex_row1_rd_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_row1_rd_cnt[0]_i_1_n_0\,
      Q => complex_row1_rd_cnt(0),
      R => '0'
    );
\complex_row1_rd_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_row1_rd_cnt[1]_i_1_n_0\,
      Q => complex_row1_rd_cnt(1),
      R => '0'
    );
\complex_row1_rd_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_row1_rd_cnt[2]_i_1_n_0\,
      Q => complex_row1_rd_cnt(2),
      R => '0'
    );
complex_row1_rd_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011110100"
    )
        port map (
      I0 => \wrcal_reads_reg[0]_0\,
      I1 => \^prbs_rdlvl_done_pulse_reg_0\,
      I2 => \wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0\,
      I3 => complex_row0_rd_done,
      I4 => complex_row1_rd_done,
      I5 => complex_row1_rd_done_i_2_n_0,
      O => complex_row1_rd_done_i_1_n_0
    );
complex_row1_rd_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => init_state_r(6),
      O => complex_row1_rd_done_i_2_n_0
    );
complex_row1_rd_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_row1_rd_done,
      Q => complex_row1_rd_done_r1,
      R => '0'
    );
complex_row1_rd_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_row1_rd_done_i_1_n_0,
      Q => complex_row1_rd_done,
      R => '0'
    );
\complex_row_cnt_ocal[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => complex_row_cnt_ocal_reg(0),
      O => \p_0_in__2\(0)
    );
\complex_row_cnt_ocal[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => complex_row_cnt_ocal_reg(0),
      I1 => complex_row_cnt_ocal_reg(1),
      O => \p_0_in__2\(1)
    );
\complex_row_cnt_ocal[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => complex_row_cnt_ocal_reg(2),
      I1 => complex_row_cnt_ocal_reg(1),
      I2 => complex_row_cnt_ocal_reg(0),
      O => \p_0_in__2\(2)
    );
\complex_row_cnt_ocal[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFF8F"
    )
        port map (
      I0 => wr_victim_inc,
      I1 => \complex_row_cnt_ocal[3]_i_4_n_0\,
      I2 => \^rdlvl_stg1_done_r1\,
      I3 => \wrcal_reads_reg[0]_0\,
      I4 => complex_byte_rd_done,
      I5 => \^prbs_rdlvl_done_pulse_reg_0\,
      O => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFF80000"
    )
        port map (
      I0 => \complex_row_cnt_ocal[3]_i_5_n_0\,
      I1 => \complex_row_cnt_ocal[3]_i_6_n_0\,
      I2 => wr_victim_inc,
      I3 => complex_sample_cnt_inc_r2,
      I4 => D(2),
      I5 => \complex_row_cnt_ocal[3]_i_4_n_0\,
      O => complex_row_cnt_ocal
    );
\complex_row_cnt_ocal[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => complex_row_cnt_ocal_reg(3),
      I1 => complex_row_cnt_ocal_reg(0),
      I2 => complex_row_cnt_ocal_reg(1),
      I3 => complex_row_cnt_ocal_reg(2),
      O => \p_0_in__2\(3)
    );
\complex_row_cnt_ocal[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => complex_row_cnt_ocal_reg(3),
      I1 => complex_row_cnt_ocal_reg(0),
      I2 => complex_row_cnt_ocal_reg(1),
      I3 => complex_row_cnt_ocal_reg(2),
      O => \complex_row_cnt_ocal[3]_i_4_n_0\
    );
\complex_row_cnt_ocal[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \wrcal_reads[7]_i_5_n_0\,
      O => \complex_row_cnt_ocal[3]_i_5_n_0\
    );
\complex_row_cnt_ocal[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008000000"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I5 => \complex_row_cnt_ocal[3]_i_7_n_0\,
      O => \complex_row_cnt_ocal[3]_i_6_n_0\
    );
\complex_row_cnt_ocal[3]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      O => \complex_row_cnt_ocal[3]_i_7_n_0\
    );
\complex_row_cnt_ocal_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__2\(0),
      Q => complex_row_cnt_ocal_reg(0),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__2\(1),
      Q => complex_row_cnt_ocal_reg(1),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__2\(2),
      Q => complex_row_cnt_ocal_reg(2),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__2\(3),
      Q => complex_row_cnt_ocal_reg(3),
      R => complex_row_cnt_ocal0
    );
complex_sample_cnt_inc_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => complex_row1_rd_done,
      I1 => complex_sample_cnt_inc_i_2_n_0,
      O => complex_sample_cnt_inc0
    );
complex_sample_cnt_inc_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => wr_victim_inc_i_2_n_0,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      O => complex_sample_cnt_inc_i_2_n_0
    );
complex_sample_cnt_inc_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_sample_cnt_inc_reg_n_0,
      Q => complex_sample_cnt_inc_r1,
      R => '0'
    );
complex_sample_cnt_inc_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_sample_cnt_inc_r1,
      Q => complex_sample_cnt_inc_r2,
      R => '0'
    );
complex_sample_cnt_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_sample_cnt_inc0,
      Q => complex_sample_cnt_inc_reg_n_0,
      R => \complex_address_reg[9]_0\(0)
    );
\complex_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => complex_wait_cnt_reg(0),
      O => \p_0_in__4\(0)
    );
\complex_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => complex_wait_cnt_reg(0),
      I1 => complex_wait_cnt_reg(1),
      O => \p_0_in__4\(1)
    );
\complex_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => complex_wait_cnt_reg(2),
      I1 => complex_wait_cnt_reg(0),
      I2 => complex_wait_cnt_reg(1),
      O => \p_0_in__4\(2)
    );
\complex_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEAAAAAAA"
    )
        port map (
      I0 => \complex_wait_cnt[3]_i_3_n_0\,
      I1 => complex_wait_cnt_reg(1),
      I2 => complex_wait_cnt_reg(0),
      I3 => complex_wait_cnt_reg(3),
      I4 => complex_wait_cnt_reg(2),
      I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      O => \complex_wait_cnt[3]_i_1_n_0\
    );
\complex_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6CCC"
    )
        port map (
      I0 => complex_wait_cnt_reg(2),
      I1 => complex_wait_cnt_reg(3),
      I2 => complex_wait_cnt_reg(0),
      I3 => complex_wait_cnt_reg(1),
      O => \complex_wait_cnt[3]_i_2_n_0\
    );
\complex_wait_cnt[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFA93FFFFF"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \wrcal_start_dly_r_reg[4]_srl5_i_2_n_0\,
      O => \complex_wait_cnt[3]_i_3_n_0\
    );
\complex_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__4\(0),
      Q => complex_wait_cnt_reg(0),
      R => \complex_wait_cnt[3]_i_1_n_0\
    );
\complex_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__4\(1),
      Q => complex_wait_cnt_reg(1),
      R => \complex_wait_cnt[3]_i_1_n_0\
    );
\complex_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__4\(2),
      Q => complex_wait_cnt_reg(2),
      R => \complex_wait_cnt[3]_i_1_n_0\
    );
\complex_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_wait_cnt[3]_i_2_n_0\,
      Q => complex_wait_cnt_reg(3),
      R => \complex_wait_cnt[3]_i_1_n_0\
    );
ddr2_pre_flag_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A2AFF00AAAAAAAA"
    )
        port map (
      I0 => ddr2_pre_flag_r_reg_n_0,
      I1 => ddr2_pre_flag_r_i_2_n_0,
      I2 => cnt_cmd_done_r,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => mem_init_done_r_i_2_n_0,
      O => ddr2_pre_flag_r_i_1_n_0
    );
ddr2_pre_flag_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => cnt_init_mr_done_r,
      I3 => ddr2_refresh_flag_r,
      O => ddr2_pre_flag_r_i_2_n_0
    );
ddr2_pre_flag_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ddr2_pre_flag_r_i_1_n_0,
      Q => ddr2_pre_flag_r_reg_n_0,
      R => '0'
    );
ddr2_refresh_flag_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F2"
    )
        port map (
      I0 => ddr2_refresh_flag_r,
      I1 => ddr2_refresh_flag_r_i_2_n_0,
      I2 => cnt_init_mr_r1,
      I3 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      O => ddr2_refresh_flag_r_i_1_n_0
    );
ddr2_refresh_flag_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => cnt_init_mr_done_r,
      I3 => ddr2_refresh_flag_r,
      I4 => mem_init_done_r_i_2_n_0,
      I5 => cnt_cmd_done_r,
      O => ddr2_refresh_flag_r_i_2_n_0
    );
ddr2_refresh_flag_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ddr2_refresh_flag_r_i_1_n_0,
      Q => ddr2_refresh_flag_r,
      R => '0'
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I1 => out_fifo_7,
      I2 => out_fifo_8(7),
      I3 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(3)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(26),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => out_fifo_7,
      I3 => out_fifo_8(6),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(2)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(13),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => out_fifo_7,
      I3 => out_fifo_8(5),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(1)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(2),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => out_fifo_7,
      I3 => out_fifo_8(4),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(0)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_22\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => out_fifo_8(11),
      I3 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0\(3)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(27),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(10),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0\(2)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_24\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(14),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => out_fifo_7,
      I3 => out_fifo_8(9),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0\(1)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(3),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => out_fifo_7,
      I3 => out_fifo_8(8),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0\(0)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_41\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => phy_ras_n(0),
      I3 => out_fifo_8(12),
      I4 => out_fifo_9,
      O => \cmd_pipe_plus.mc_ras_n_reg[0]\(0)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_42\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => out_fifo_8(20),
      I3 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(7)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_43\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(34),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(19),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(6)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_44\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(21),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(18),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(5)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_45\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(10),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(17),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(4)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_46\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => out_fifo_8(16),
      I3 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(3)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_47\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(24),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(15),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(2)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_48\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(11),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(14),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(1)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_49\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(0),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(13),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(0)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_50\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => phy_bank(9),
      I1 => phy_ctl_wr_i1_reg,
      I2 => out_fifo_8(28),
      I3 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(7)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_51\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(4),
      I1 => phy_bank(9),
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(27),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(6)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_52\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(2),
      I1 => phy_bank(9),
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(26),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(5)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_53\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(0),
      I1 => phy_bank(9),
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(25),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(4)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_54\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => phy_bank(10),
      I1 => phy_ctl_wr_i1_reg,
      I2 => out_fifo_8(24),
      I3 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(3)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_55\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(5),
      I1 => phy_bank(10),
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(23),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(2)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_56\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(3),
      I1 => phy_bank(10),
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(22),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(1)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_57\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(1),
      I1 => phy_bank(10),
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(21),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(0)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I1 => out_fifo_7,
      I2 => out_fifo_8(3),
      I3 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0\(3)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_62\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => out_fifo_8(32),
      I3 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0\(3)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_63\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(25),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(31),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0\(2)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_64\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(12),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(30),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0\(1)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_65\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(1),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(29),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0\(0)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(36),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => out_fifo_7,
      I3 => out_fifo_8(2),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0\(2)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_70\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => out_fifo_8(36),
      I3 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0\(3)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_71\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(29),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(35),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0\(2)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_72\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(16),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(34),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0\(1)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_73\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(5),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(33),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0\(0)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_78\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I1 => phy_ctl_wr_i1_reg,
      I2 => out_fifo_8(40),
      I3 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(3)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_79\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(33),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(39),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(2)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(23),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => out_fifo_7,
      I3 => out_fifo_8(1),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0\(1)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_80\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(20),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(38),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(1)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_81\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(9),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => phy_ctl_wr_i1_reg,
      I3 => out_fifo_8(37),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(0)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => out_fifo_7,
      I3 => out_fifo_8(0),
      I4 => out_fifo_9,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0\(0)
    );
detect_pi_found_dqs_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080000000"
    )
        port map (
      I0 => prech_req_posedge_r_i_2_n_0,
      I1 => \cnt_cmd_r_reg_n_0_[5]\,
      I2 => \cnt_cmd_r_reg_n_0_[3]\,
      I3 => \cnt_cmd_r_reg_n_0_[4]\,
      I4 => \cnt_cmd_r[6]_i_4_n_0\,
      I5 => \cnt_cmd_r_reg_n_0_[6]\,
      O => detect_pi_found_dqs0
    );
detect_pi_found_dqs_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => detect_pi_found_dqs0,
      Q => \^detect_pi_found_dqs\,
      R => \complex_address_reg[9]_0\(0)
    );
\en_cnt_div4.enable_wrlvl_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000005554"
    )
        port map (
      I0 => enable_wrlvl_cnt(0),
      I1 => enable_wrlvl_cnt(3),
      I2 => enable_wrlvl_cnt(1),
      I3 => enable_wrlvl_cnt(2),
      I4 => \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0\,
      I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000C3C2"
    )
        port map (
      I0 => enable_wrlvl_cnt(2),
      I1 => enable_wrlvl_cnt(1),
      I2 => enable_wrlvl_cnt(0),
      I3 => enable_wrlvl_cnt(3),
      I4 => \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0\,
      I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFA9A8"
    )
        port map (
      I0 => enable_wrlvl_cnt(2),
      I1 => enable_wrlvl_cnt(1),
      I2 => enable_wrlvl_cnt(0),
      I3 => enable_wrlvl_cnt(3),
      I4 => \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFE00"
    )
        port map (
      I0 => enable_wrlvl_cnt(2),
      I1 => enable_wrlvl_cnt(1),
      I2 => enable_wrlvl_cnt(0),
      I3 => enable_wrlvl_cnt(3),
      I4 => \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAAA"
    )
        port map (
      I0 => \en_cnt_div4.enable_wrlvl_cnt[3]_i_3_n_0\,
      I1 => enable_wrlvl_cnt(3),
      I2 => enable_wrlvl_cnt(0),
      I3 => enable_wrlvl_cnt(1),
      I4 => enable_wrlvl_cnt(2),
      I5 => wrlvl_odt,
      O => \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => init_complete_r_i_2_n_0,
      O => \en_cnt_div4.enable_wrlvl_cnt[3]_i_3_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0\,
      Q => enable_wrlvl_cnt(0),
      R => '0'
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0\,
      Q => enable_wrlvl_cnt(1),
      R => '0'
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0\,
      Q => enable_wrlvl_cnt(2),
      R => \complex_address_reg[9]_0\(0)
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0\,
      Q => enable_wrlvl_cnt(3),
      R => \complex_address_reg[9]_0\(0)
    );
\en_cnt_div4.wrlvl_odt_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0010"
    )
        port map (
      I0 => enable_wrlvl_cnt(2),
      I1 => enable_wrlvl_cnt(3),
      I2 => enable_wrlvl_cnt(0),
      I3 => enable_wrlvl_cnt(1),
      I4 => wrlvl_odt,
      O => \en_cnt_div4.wrlvl_odt_i_1_n_0\
    );
\en_cnt_div4.wrlvl_odt_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \en_cnt_div4.wrlvl_odt_i_1_n_0\,
      Q => wrlvl_odt,
      R => \complex_address_reg[9]_0\(0)
    );
\even_cwl.phy_cas_n[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[0]_i_4_n_0\,
      I1 => reg_ctrl_cnt_r,
      I2 => \DDR3_1rank.phy_int_cs_n[0]_i_3_n_0\,
      I3 => \calib_cmd[2]_i_1_n_0\,
      I4 => \num_refresh[3]_i_7_n_0\,
      O => \even_cwl.phy_cas_n[0]_i_1_n_0\
    );
\even_cwl.phy_cas_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \even_cwl.phy_cas_n[0]_i_1_n_0\,
      Q => phy_cas_n(0),
      R => '0'
    );
\even_cwl.phy_ras_n[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[0]_i_4_n_0\,
      I1 => reg_ctrl_cnt_r,
      I2 => \DDR3_1rank.phy_int_cs_n[0]_i_3_n_0\,
      I3 => \DDR3_1rank.phy_int_cs_n[0]_i_5_n_0\,
      O => \even_cwl.phy_ras_n[0]_i_1_n_0\
    );
\even_cwl.phy_ras_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \even_cwl.phy_ras_n[0]_i_1_n_0\,
      Q => phy_ras_n(0),
      R => '0'
    );
\even_cwl.phy_we_n[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[0]_i_4_n_0\,
      I1 => reg_ctrl_cnt_r,
      I2 => \DDR3_1rank.phy_int_cs_n[0]_i_3_n_0\,
      I3 => \calib_cmd[2]_i_2_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\,
      O => \even_cwl.phy_we_n[0]_i_1_n_0\
    );
\even_cwl.phy_we_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \even_cwl.phy_we_n[0]_i_1_n_0\,
      Q => phy_we_n(0),
      R => '0'
    );
first_rdlvl_pat_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => \^first_rdlvl_pat_r\,
      I1 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I2 => rdlvl_stg1_rank_done,
      I3 => \wrcal_reads_reg[0]_0\,
      O => first_rdlvl_pat_r_i_1_n_0
    );
first_rdlvl_pat_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => first_rdlvl_pat_r_i_1_n_0,
      Q => \^first_rdlvl_pat_r\,
      R => '0'
    );
first_wrcal_pat_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFAA8B"
    )
        port map (
      I0 => \^first_wrcal_pat_r\,
      I1 => first_wrcal_pat_r_i_2_n_0,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      I4 => \wrcal_reads_reg[0]_0\,
      O => first_wrcal_pat_r_i_1_n_0
    );
first_wrcal_pat_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      O => first_wrcal_pat_r_i_2_n_0
    );
first_wrcal_pat_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => first_wrcal_pat_r_i_1_n_0,
      Q => \^first_wrcal_pat_r\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAAAAA"
    )
        port map (
      I0 => address_w(11),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      O => address_w(0)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44F444CCFFFFFFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => \complex_address_reg_n_0_[0]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABABABAAAAAAABAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\,
      I2 => address_w(12),
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I4 => D(2),
      I5 => complex_row_cnt_ocal_reg(0),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B080"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\,
      I3 => \complex_address_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAABAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_4_n_0\,
      I3 => init_state_r(6),
      I4 => \gen_rnk[0].mr2_r_reg[0]_202\(1),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0\,
      O => address_w(10)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0019000100000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \wrcal_reads[7]_i_4_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFAFFFBFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1001200000002000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \^q\(0),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00202200"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_3_n_0\,
      I2 => cnt_init_mr_r(0),
      I3 => ddr2_refresh_flag_r,
      I4 => cnt_init_mr_r(1),
      O => address_w(11)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0202000100000100"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_4_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\,
      I2 => init_state_r(6),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001002000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      O => address_w(12)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^q\(0),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAAAAA"
    )
        port map (
      I0 => address_w(11),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      O => address_w(1)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44F444CCFFFFFFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => \complex_address_reg_n_0_[1]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABABABAAAAAAABAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\,
      I2 => address_w(12),
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I4 => D(2),
      I5 => complex_row_cnt_ocal_reg(1),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B080"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\,
      I3 => \complex_address_reg_n_0_[1]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000075777575"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0\,
      O => address_w(2)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00005F3F5F3F5F3F"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I1 => \complex_address_reg_n_0_[2]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABABABBBBBBBABB"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      I2 => address_w(12),
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I4 => D(2),
      I5 => complex_row_cnt_ocal_reg(2),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D5"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\,
      I2 => \complex_address_reg_n_0_[2]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AB"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\,
      I2 => init_state_r(6),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0705050507050705"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_4_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0\,
      I3 => cnt_init_mr_r(1),
      I4 => ddr2_refresh_flag_r,
      I5 => cnt_init_mr_r(0),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000888AAAAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0\,
      O => address_w(3)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"5D"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\,
      I2 => \complex_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2FF"
    )
        port map (
      I0 => \complex_address_reg_n_0_[3]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47444777"
    )
        port map (
      I0 => burst_addr_r_reg_n_0,
      I1 => address_w(12),
      I2 => complex_row_cnt_ocal_reg(3),
      I3 => D(2),
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => address_w(11),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      O => address_w(4)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F90909F9FFFFFFFF"
    )
        port map (
      I0 => \complex_address_reg_n_0_[3]\,
      I1 => \complex_address_reg_n_0_[4]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE0EEAA00000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAABAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      I1 => address_w(12),
      I2 => D(2),
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \complex_address_reg_n_0_[4]\,
      I1 => \complex_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF2EEE"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0\,
      O => address_w(5)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFCFFFFFF00AAAA"
    )
        port map (
      I0 => \ocal_act_wait_cnt[3]_i_4_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \complex_num_writes[4]_i_8_n_0\,
      I3 => complex_ocal_odt_ext_i_2_n_0,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \^q\(0),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888888A88"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_14_n_0\,
      I2 => wrcal_wr_cnt_reg(3),
      I3 => wrcal_wr_cnt_reg(2),
      I4 => wrcal_wr_cnt_reg(1),
      I5 => wrcal_wr_cnt_reg(0),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => oclk_wr_cnt_reg(1),
      I1 => oclk_wr_cnt_reg(0),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \complex_address_reg_n_0_[5]\,
      I1 => \complex_address_reg_n_0_[4]\,
      I2 => \complex_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFDFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_14_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0151515151010101"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I3 => \complex_address_reg_n_0_[3]\,
      I4 => \complex_address_reg_n_0_[4]\,
      I5 => \complex_address_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FAFCFFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0\,
      I1 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      I4 => D(2),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFFFFFFFDFFFDFF"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      I1 => D(2),
      I2 => address_w(12),
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0\,
      I4 => first_wrcal_pat_r_i_2_n_0,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEEEFEE"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0\,
      I3 => oclk_wr_cnt_reg(2),
      I4 => oclk_wr_cnt_reg(3),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FD5D0000FFFFFFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_10_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_11_n_0\,
      I2 => \complex_row_cnt_ocal[3]_i_6_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEFFF"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFAAEFAAEFAAEAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0\,
      O => address_w(6)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF7FFFFFFFF"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I4 => \complex_row_cnt_ocal[3]_i_7_n_0\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_14_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_13_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF7F"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_14_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_3_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0\,
      I2 => ddr2_refresh_flag_r,
      I3 => cnt_init_mr_r(1),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08A8A808A808A808"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4555555545554555"
    )
        port map (
      I0 => D(2),
      I1 => \calib_cmd[1]_i_2_n_0\,
      I2 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I3 => \complex_num_reads_dec[3]_i_4_n_0\,
      I4 => read_calib_i_2_n_0,
      I5 => init_complete_r_i_2_n_0,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5504"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I3 => init_state_r(6),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55F700C0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      I1 => D(2),
      I2 => address_w(12),
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEEEEE0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_11_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0\,
      I2 => D(2),
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0\,
      I4 => wr_victim_inc_i_2_n_0,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_13_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \complex_address_reg_n_0_[6]\,
      I1 => \complex_address_reg_n_0_[5]\,
      I2 => \complex_address_reg_n_0_[3]\,
      I3 => \complex_address_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444455545555"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\,
      O => address_w(7)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000408800001012"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2303AF8F2000AC8C"
    )
        port map (
      I0 => first_wrcal_pat_r_i_2_n_0,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => complex_ocal_odt_ext_i_2_n_0,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0\,
      I5 => \ocal_act_wait_cnt[3]_i_4_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"001C"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_4_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\,
      I3 => init_state_r(6),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"02A2"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      I2 => D(2),
      I3 => address_w(12),
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEE0AA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"95555555"
    )
        port map (
      I0 => \complex_address_reg_n_0_[7]\,
      I1 => \complex_address_reg_n_0_[4]\,
      I2 => \complex_address_reg_n_0_[3]\,
      I3 => \complex_address_reg_n_0_[5]\,
      I4 => \complex_address_reg_n_0_[6]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"95555555"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55570000FFFFFFFF"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I3 => \^q\(0),
      I4 => D(2),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAEEEAE"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_6_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_7_n_0\,
      O => address_w(8)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_13_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I5 => \complex_num_writes[4]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_10_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555500000004"
    )
        port map (
      I0 => complex_row0_rd_done,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      I2 => init_state_r1(5),
      I3 => init_state_r1(6),
      I4 => init_state_r1(4),
      I5 => \^one_rank.stg1_wr_done_reg_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_11_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => init_state_r1(1),
      I1 => init_state_r1(4),
      I2 => init_state_r1(5),
      I3 => init_state_r1(6),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_12_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_13_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"040415FF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_6_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000100000001"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_8_n_0\,
      I1 => D(2),
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_9_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_10_n_0\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => \complex_address_reg_n_0_[8]\,
      I1 => \complex_address_reg_n_0_[7]\,
      I2 => \complex_address_reg_n_0_[6]\,
      I3 => \complex_address_reg_n_0_[5]\,
      I4 => \complex_address_reg_n_0_[3]\,
      I5 => \complex_address_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABAAAAA"
    )
        port map (
      I0 => \complex_num_reads_dec[3]_i_4_n_0\,
      I1 => init_state_r1(2),
      I2 => init_state_r1(3),
      I3 => init_state_r1(0),
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_12_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002800"
    )
        port map (
      I0 => cnt_init_mr_r(1),
      I1 => cnt_init_mr_r(0),
      I2 => ddr2_refresh_flag_r,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFA0FFCCFFA0FF00"
    )
        port map (
      I0 => read_calib_i_2_n_0,
      I1 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => prech_req_r_i_2_n_0,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => wr_victim_inc_i_2_n_0,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => D(2),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_9_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF2AFF2AFF2AFFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_3_n_0\,
      O => address_w(9)
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222222022222222"
    )
        port map (
      I0 => init_complete_r_i_2_n_0,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0\,
      I2 => init_state_r1(4),
      I3 => init_state_r1(6),
      I4 => init_state_r1(5),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \complex_address_reg_n_0_[4]\,
      I1 => \complex_address_reg_n_0_[3]\,
      I2 => \complex_address_reg_n_0_[5]\,
      I3 => \complex_address_reg_n_0_[6]\,
      I4 => \complex_address_reg_n_0_[7]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002022"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_10_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_11_n_0\,
      I3 => \complex_row_cnt_ocal[3]_i_6_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFEF0000"
    )
        port map (
      I0 => wrcal_wr_cnt_reg(0),
      I1 => wrcal_wr_cnt_reg(1),
      I2 => wrcal_wr_cnt_reg(2),
      I3 => wrcal_wr_cnt_reg(3),
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => first_wrcal_pat_r_i_2_n_0,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => init_state_r1(2),
      I1 => init_state_r1(1),
      I2 => init_state_r1(3),
      I3 => init_state_r1(0),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7800787878007800"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\,
      I1 => \complex_address_reg_n_0_[8]\,
      I2 => \complex_address_reg_n_0_[9]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0\,
      I1 => ddr2_refresh_flag_r,
      I2 => cnt_init_mr_r(1),
      I3 => cnt_init_mr_r(0),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555500005555000C"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I1 => oclk_wr_cnt_reg(2),
      I2 => oclk_wr_cnt_reg(1),
      I3 => oclk_wr_cnt_reg(0),
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0\,
      I5 => oclk_wr_cnt_reg(3),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFD5D5FFD5"
    )
        port map (
      I0 => D(2),
      I1 => \complex_num_reads_dec[3]_i_4_n_0\,
      I2 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I3 => \complex_row_cnt_ocal[3]_i_6_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_11_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_10_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(0),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(10),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(11),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(12),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(1),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(2),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(3),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(4),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(5),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(6),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(7),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(8),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => address_w(9),
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0002AAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0\,
      O => bank_w(0)
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAAAA0451FFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => cnt_init_mr_r(0),
      I2 => ddr2_refresh_flag_r,
      I3 => cnt_init_mr_r(1),
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"9FFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \^q\(0),
      O => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA8888888888888"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_3_n_0\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4_n_0\,
      O => bank_w(1)
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0303030303030301"
    )
        port map (
      I0 => \wrcal_reads[7]_i_4_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \^q\(0),
      O => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404040400000004"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_complete_r_i_2_n_0,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => ddr2_refresh_flag_r,
      I4 => cnt_init_mr_r(1),
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => bank_w(0),
      Q => phy_bank(9),
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => bank_w(1),
      Q => phy_bank(10),
      R => '0'
    );
\gen_rnk[0].mr2_r_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '1',
      Q => \gen_rnk[0].mr2_r_reg[0]_202\(1),
      R => \complex_address_reg[9]_0\(0)
    );
init_calib_complete_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_complete_r2,
      Q => init_calib_complete_reg_0,
      R => \complex_address_reg[9]_0\(0)
    );
init_complete_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_complete_r_reg_n_0,
      Q => init_complete_r1,
      R => \complex_address_reg[9]_0\(0)
    );
init_complete_r1_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_complete_r_timing,
      Q => init_complete_r1_timing,
      R => \complex_address_reg[9]_0\(0)
    );
init_complete_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_complete_r1,
      Q => init_complete_r2,
      R => SR(0)
    );
init_complete_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00400000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \wrcal_reads[7]_i_4_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => init_complete_r_i_2_n_0,
      I5 => init_complete_r_reg_n_0,
      O => init_complete_r_i_1_n_0
    );
init_complete_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[0]\,
      O => init_complete_r_i_2_n_0
    );
init_complete_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_complete_r_i_1_n_0,
      Q => init_complete_r_reg_n_0,
      R => SR(0)
    );
init_complete_r_timing_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00400000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \wrcal_reads[7]_i_4_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => init_complete_r_i_2_n_0,
      I5 => init_complete_r_timing,
      O => init_complete_r_timing_i_1_n_0
    );
init_complete_r_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_complete_r_timing_i_1_n_0,
      Q => init_complete_r_timing,
      R => init_complete_r_timing_reg_0
    );
\init_state_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r_reg_n_0_[0]\,
      Q => init_state_r1(0),
      R => \init_state_r1_reg[0]_0\(0)
    );
\init_state_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^q\(0),
      Q => init_state_r1(1),
      R => \init_state_r1_reg[0]_0\(0)
    );
\init_state_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r_reg_n_0_[2]\,
      Q => init_state_r1(2),
      R => \init_state_r1_reg[0]_0\(0)
    );
\init_state_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r_reg_n_0_[3]\,
      Q => init_state_r1(3),
      R => \init_state_r1_reg[0]_0\(0)
    );
\init_state_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r_reg_n_0_[4]\,
      Q => init_state_r1(4),
      R => \init_state_r1_reg[0]_0\(0)
    );
\init_state_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r_reg_n_0_[5]\,
      Q => init_state_r1(5),
      R => \init_state_r1_reg[0]_0\(0)
    );
\init_state_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_state_r(6),
      Q => init_state_r1(6),
      R => \init_state_r1_reg[0]_0\(0)
    );
\init_state_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0047FF47FF47FF47"
    )
        port map (
      I0 => \init_state_r[0]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r[0]_i_3_n_0\,
      I3 => init_state_r(6),
      I4 => \init_state_r[0]_i_4_n_0\,
      I5 => \init_state_r[0]_i_5_n_0\,
      O => \init_state_r[0]_i_1_n_0\
    );
\init_state_r[0]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[0]_i_10_n_0\
    );
\init_state_r[0]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A202A202A2A2A202"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => ddr2_pre_flag_r_reg_n_0,
      I2 => \^q\(0),
      I3 => \init_state_r[4]_i_17_n_0\,
      I4 => cnt_init_af_done_r,
      I5 => mem_init_done_r,
      O => \init_state_r[0]_i_11_n_0\
    );
\init_state_r[0]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000C08C000CC08C"
    )
        port map (
      I0 => \init_state_r[0]_i_16_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r[2]_i_11_0\,
      O => \init_state_r[0]_i_12_n_0\
    );
\init_state_r[0]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFE0A040A0"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r[6]_i_20_n_0\,
      I2 => \^q\(0),
      I3 => \^rdlvl_stg1_done_r1\,
      I4 => reset_rd_addr_r1,
      I5 => \init_state_r[0]_i_17_n_0\,
      O => \init_state_r[0]_i_13_n_0\
    );
\init_state_r[0]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FFF0FF4FFF"
    )
        port map (
      I0 => \init_state_r[2]_i_11_0\,
      I1 => \init_state_r[4]_i_18_n_0\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[0]_i_14_n_0\
    );
\init_state_r[0]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FFF7F7"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \^prech_req_posedge_r_reg_0\,
      I3 => \^one_rank.stg1_wr_done_reg_0\,
      I4 => complex_row1_wr_done,
      O => \init_state_r[0]_i_15_n_0\
    );
\init_state_r[0]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => reg_ctrl_cnt_r_reg(1),
      I1 => reg_ctrl_cnt_r_reg(0),
      I2 => reg_ctrl_cnt_r_reg(3),
      I3 => reg_ctrl_cnt_r_reg(2),
      O => \init_state_r[0]_i_16_n_0\
    );
\init_state_r[0]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0400FF00"
    )
        port map (
      I0 => rdlvl_last_byte_done,
      I1 => pi_dqs_found_done,
      I2 => D(2),
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I4 => \^pi_calib_done\,
      I5 => \oclk_wr_cnt[3]_i_5_n_0\,
      O => \init_state_r[0]_i_17_n_0\
    );
\init_state_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02AA0200AAAAAAAA"
    )
        port map (
      I0 => \init_state_r[0]_i_6_n_0\,
      I1 => \init_state_r[0]_i_7_n_0\,
      I2 => \init_state_r[0]_i_8_n_0\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r[0]_i_9_n_0\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[0]_i_2_n_0\
    );
\init_state_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D000D000DFF0D00"
    )
        port map (
      I0 => \init_state_r[0]_i_10_n_0\,
      I1 => \init_state_r[0]_i_11_n_0\,
      I2 => \init_state_r[0]_i_12_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r[0]_i_13_n_0\,
      I5 => \init_state_r[0]_i_14_n_0\,
      O => \init_state_r[0]_i_3_n_0\
    );
\init_state_r[0]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[0]_i_4_n_0\
    );
\init_state_r[0]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^prech_req_posedge_r_reg_0\,
      O => \init_state_r[0]_i_5_n_0\
    );
\init_state_r[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEEEFEE"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => cnt_cmd_done_r,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[0]_i_6_n_0\
    );
\init_state_r[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000FFF0C0D"
    )
        port map (
      I0 => \init_state_r[1]_i_11_n_0\,
      I1 => \^prech_req_posedge_r_reg_0\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => prbs_rdlvl_done_pulse0,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[0]_i_7_n_0\
    );
\init_state_r[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222222288880080"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => D(2),
      I3 => complex_oclkdelay_calib_done_r1,
      I4 => \^prech_req_posedge_r_reg_0\,
      I5 => \^q\(0),
      O => \init_state_r[0]_i_8_n_0\
    );
\init_state_r[0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010F0F0FFFFF0F0"
    )
        port map (
      I0 => \^rdlvl_stg1_done_r1\,
      I1 => D(2),
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r[0]_i_15_n_0\,
      O => \init_state_r[0]_i_9_n_0\
    );
\init_state_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"74777444"
    )
        port map (
      I0 => \init_state_r[4]_i_2_n_0\,
      I1 => init_state_r(6),
      I2 => \init_state_r[1]_i_2_n_0\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r[1]_i_3_n_0\,
      O => \init_state_r[1]_i_1_n_0\
    );
\init_state_r[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000003CCFFCC77CC"
    )
        port map (
      I0 => \init_state_r[1]_i_16_n_0\,
      I1 => \^q\(0),
      I2 => mem_init_done_r,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[1]_i_10_n_0\
    );
\init_state_r[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => complex_row0_rd_done,
      I1 => D(2),
      I2 => complex_num_reads_dec(3),
      I3 => complex_num_reads_dec(2),
      I4 => complex_num_reads_dec(1),
      I5 => complex_num_reads_dec(0),
      O => \init_state_r[1]_i_11_n_0\
    );
\init_state_r[1]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444444440"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => wrlvl_byte_redo,
      I3 => \^q\(0),
      I4 => \^prech_req_posedge_r_reg_0\,
      I5 => burst_addr_r_reg_0,
      O => \init_state_r[1]_i_12_n_0\
    );
\init_state_r[1]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => wrcal_prech_req,
      O => \init_state_r[1]_i_13_n_0\
    );
\init_state_r[1]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"008F008FFF0FF00F"
    )
        port map (
      I0 => D(2),
      I1 => pi_dqs_found_done,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg[1]_i_7_0\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[1]_i_14_n_0\
    );
\init_state_r[1]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FFBAAA00FFBAFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => mem_init_done_r,
      I2 => cnt_init_af_done_r,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => ddr2_pre_flag_r_reg_n_0,
      O => \init_state_r[1]_i_15_n_0\
    );
\init_state_r[1]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => cnt_init_mr_done_r,
      I1 => ddr2_refresh_flag_r,
      I2 => pi_dqs_found_done,
      I3 => D(2),
      O => \init_state_r[1]_i_16_n_0\
    );
\init_state_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFE0FFFFEFE00000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r[1]_i_4_n_0\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r[1]_i_5_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r[1]_i_6_n_0\,
      O => \init_state_r[1]_i_2_n_0\
    );
\init_state_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB8888BB8B"
    )
        port map (
      I0 => \init_state_r_reg[1]_i_7_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r[1]_i_8_n_0\,
      I3 => \init_state_r[1]_i_9_n_0\,
      I4 => \oclk_wr_cnt[3]_i_5_n_0\,
      I5 => \init_state_r[1]_i_10_n_0\,
      O => \init_state_r[1]_i_3_n_0\
    );
\init_state_r[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0ECF0ECE0FCF0FCE"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => prbs_rdlvl_done_pulse0,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r[1]_i_11_n_0\,
      I5 => complex_sample_cnt_inc_i_2_n_0,
      O => \init_state_r[1]_i_4_n_0\
    );
\init_state_r[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7AA55AA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^one_rank.stg1_wr_done_reg_0\,
      I2 => \^prech_req_posedge_r_reg_0\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[1]_i_5_n_0\
    );
\init_state_r[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4EEE4EEE4FF44FF5"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r[1]_i_12_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      I4 => \init_state_r[1]_i_13_n_0\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[1]_i_6_n_0\
    );
\init_state_r[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"70707050FFFFFFFF"
    )
        port map (
      I0 => pi_dqs_found_done,
      I1 => D(2),
      I2 => \^pi_calib_done\,
      I3 => \^one_rank.stg1_wr_done_reg_0\,
      I4 => rdlvl_last_byte_done,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      O => \init_state_r[1]_i_8_n_0\
    );
\init_state_r[1]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E0E0F000"
    )
        port map (
      I0 => reset_rd_addr_r1,
      I1 => \^rdlvl_stg1_done_r1\,
      I2 => \^q\(0),
      I3 => \init_state_r[6]_i_20_n_0\,
      I4 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[1]_i_9_n_0\
    );
\init_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEFEFEFFFE"
    )
        port map (
      I0 => \init_state_r[2]_i_2_n_0\,
      I1 => \init_state_r[2]_i_3_n_0\,
      I2 => \init_state_r[2]_i_4_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r[2]_i_5_n_0\,
      I5 => \init_state_r[2]_i_6_n_0\,
      O => \init_state_r[2]_i_1_n_0\
    );
\init_state_r[2]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \^rdlvl_stg1_done_r1\,
      O => \init_state_r[2]_i_10_n_0\
    );
\init_state_r[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080880000"
    )
        port map (
      I0 => \init_state_r[4]_i_17_n_0\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => mem_init_done_r,
      I3 => cnt_init_af_done_r,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[2]_i_11_n_0\
    );
\init_state_r[2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3D393939C0C0C0C0"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \^q\(0),
      I3 => D(2),
      I4 => pi_dqs_found_done,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[2]_i_12_n_0\
    );
\init_state_r[2]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A2"
    )
        port map (
      I0 => complex_sample_cnt_inc_i_2_n_0,
      I1 => D(2),
      I2 => complex_oclkdelay_calib_done_r1,
      I3 => \^prech_req_posedge_r_reg_0\,
      O => \init_state_r[2]_i_13_n_0\
    );
\init_state_r[2]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0A0A0A0B"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => wrlvl_byte_redo,
      I2 => \^q\(0),
      I3 => \^prech_req_posedge_r_reg_0\,
      I4 => burst_addr_r_reg_0,
      O => \init_state_r[2]_i_14_n_0\
    );
\init_state_r[2]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F3B3F3B3F3B333B3"
    )
        port map (
      I0 => prbs_rdlvl_done_pulse0,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      I4 => \^prech_req_posedge_r_reg_0\,
      I5 => \^one_rank.stg1_wr_done_reg_0\,
      O => \init_state_r[2]_i_15_n_0\
    );
\init_state_r[2]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0111"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      O => \init_state_r[2]_i_16_n_0\
    );
\init_state_r[2]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0444"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      O => \init_state_r[2]_i_17_n_0\
    );
\init_state_r[2]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[2]_i_18_n_0\
    );
\init_state_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"888888888888A8AA"
    )
        port map (
      I0 => \init_state_r[2]_i_7_n_0\,
      I1 => \init_state_r[2]_i_8_n_0\,
      I2 => \init_state_r[2]_i_9_n_0\,
      I3 => \init_state_r[2]_i_10_n_0\,
      I4 => \init_state_r[4]_i_16_n_0\,
      I5 => \oclk_wr_cnt[3]_i_5_n_0\,
      O => \init_state_r[2]_i_2_n_0\
    );
\init_state_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFE0EFE0EFE0E0E0"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4_n_0\,
      I2 => init_state_r(6),
      I3 => \init_state_r[4]_i_10_n_0\,
      I4 => \init_state_r[2]_i_11_n_0\,
      I5 => \init_state_r[2]_i_12_n_0\,
      O => \init_state_r[2]_i_3_n_0\
    );
\init_state_r[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"14401040FFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => cnt_cmd_done_r,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[2]_i_4_n_0\
    );
\init_state_r[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCFCC77773333"
    )
        port map (
      I0 => \init_state_r[2]_i_13_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \^rdlvl_stg1_done_r1\,
      I3 => D(2),
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \^q\(0),
      O => \init_state_r[2]_i_5_n_0\
    );
\init_state_r[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFD000"
    )
        port map (
      I0 => \init_state_r[2]_i_14_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \wrcal_reads[7]_i_4_n_0\,
      I3 => \init_state_r[2]_i_15_n_0\,
      I4 => \init_state_r[2]_i_16_n_0\,
      I5 => \wrcal_start_dly_r_reg[4]_srl5_i_2_n_0\,
      O => \init_state_r[2]_i_6_n_0\
    );
\init_state_r[2]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[2]_i_7_n_0\
    );
\init_state_r[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FC8CFC8CFC8C8C8C"
    )
        port map (
      I0 => mem_init_done_r,
      I1 => \init_state_r[2]_i_17_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r[2]_i_18_n_0\,
      I4 => cnt_init_mr_done_r,
      I5 => \init_state_r[2]_i_2_0\,
      O => \init_state_r[2]_i_8_n_0\
    );
\init_state_r[2]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r[6]_i_20_n_0\,
      O => \init_state_r[2]_i_9_n_0\
    );
\init_state_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFD00000FFD0"
    )
        port map (
      I0 => \init_state_r[3]_i_2_n_0\,
      I1 => \init_state_r[3]_i_3_n_0\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r[3]_i_4_n_0\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[3]_i_1_n_0\
    );
\init_state_r[3]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000220F"
    )
        port map (
      I0 => cnt_init_af_done_r,
      I1 => mem_init_done_r,
      I2 => ddr2_pre_flag_r_reg_n_0,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[3]_i_11_n_0\
    );
\init_state_r[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00DD0FDDFFDDFFDD"
    )
        port map (
      I0 => ddr2_pre_flag_r_i_2_n_0,
      I1 => \init_state_r[2]_i_11_0\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => mem_init_done_r,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[3]_i_12_n_0\
    );
\init_state_r[3]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FFF770000000000"
    )
        port map (
      I0 => \^pi_calib_done\,
      I1 => \init_state_r_reg[3]_i_10_0\,
      I2 => reset_rd_addr_r1,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[3]_i_13_n_0\
    );
\init_state_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F05CFA5CFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r[5]_i_5_n_0\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r[3]_i_5_n_0\,
      I5 => \init_state_r[3]_i_6_n_0\,
      O => \init_state_r[3]_i_2_n_0\
    );
\init_state_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBAAFAAAAAAAAAAA"
    )
        port map (
      I0 => \init_state_r[3]_i_7_n_0\,
      I1 => \^prech_req_posedge_r_reg_0\,
      I2 => \^rdlvl_stg1_done_r1\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \init_state_r[3]_i_8_n_0\,
      O => \init_state_r[3]_i_3_n_0\
    );
\init_state_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F1F1000000FF"
    )
        port map (
      I0 => \init_state_r[4]_i_12_n_0\,
      I1 => \oclk_wr_cnt[3]_i_5_n_0\,
      I2 => \init_state_r[3]_i_9_n_0\,
      I3 => \init_state_r_reg[3]_i_10_n_0\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[3]_i_4_n_0\
    );
\init_state_r[3]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => complex_oclkdelay_calib_done_r1,
      I2 => D(2),
      O => \init_state_r[3]_i_5_n_0\
    );
\init_state_r[3]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[3]_i_6_n_0\
    );
\init_state_r[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0545550550000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[3]_i_7_n_0\
    );
\init_state_r[3]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[3]_i_8_n_0\
    );
\init_state_r[3]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF8A8A0000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => \init_state_r[2]_i_11_0\,
      I3 => \init_state_r[3]_i_11_n_0\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[3]_i_9_n_0\
    );
\init_state_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7777777777774744"
    )
        port map (
      I0 => \init_state_r[4]_i_2_n_0\,
      I1 => init_state_r(6),
      I2 => \init_state_r[4]_i_3_n_0\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r[4]_i_4_n_0\,
      I5 => \init_state_r[4]_i_5_n_0\,
      O => \init_state_r[4]_i_1_n_0\
    );
\init_state_r[4]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[4]_i_10_n_0\
    );
\init_state_r[4]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[4]_i_11_n_0\
    );
\init_state_r[4]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAABAA"
    )
        port map (
      I0 => \^q\(0),
      I1 => reg_ctrl_cnt_r_reg(1),
      I2 => reg_ctrl_cnt_r_reg(0),
      I3 => reg_ctrl_cnt_r_reg(3),
      I4 => reg_ctrl_cnt_r_reg(2),
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[4]_i_12_n_0\
    );
\init_state_r[4]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[4]_i_13_n_0\
    );
\init_state_r[4]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222020222200202"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r[4]_i_18_n_0\,
      I4 => \^q\(0),
      I5 => \init_state_r[2]_i_11_0\,
      O => \init_state_r[4]_i_14_n_0\
    );
\init_state_r[4]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A828"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^rdlvl_stg1_done_r1\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => reset_rd_addr_r1,
      O => \init_state_r[4]_i_15_n_0\
    );
\init_state_r[4]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBFB000000000000"
    )
        port map (
      I0 => D(2),
      I1 => pi_dqs_found_done,
      I2 => \^one_rank.stg1_wr_done_reg_0\,
      I3 => rdlvl_last_byte_done,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \^pi_calib_done\,
      O => \init_state_r[4]_i_16_n_0\
    );
\init_state_r[4]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888888B8888"
    )
        port map (
      I0 => mem_init_done_r,
      I1 => \init_state_r[2]_i_11_0\,
      I2 => num_refresh_reg(1),
      I3 => num_refresh_reg(0),
      I4 => num_refresh_reg(3),
      I5 => num_refresh_reg(2),
      O => \init_state_r[4]_i_17_n_0\
    );
\init_state_r[4]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => cnt_init_mr_done_r,
      I1 => ddr2_refresh_flag_r,
      I2 => mem_init_done_r,
      O => \init_state_r[4]_i_18_n_0\
    );
\init_state_r[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1115"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \^prech_req_posedge_r_reg_0\,
      I3 => \^q\(0),
      O => \init_state_r[4]_i_2_n_0\
    );
\init_state_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FFFFFF10FF0000"
    )
        port map (
      I0 => \^one_rank.stg1_wr_done_reg_0\,
      I1 => \^prech_req_posedge_r_reg_0\,
      I2 => \init_state_r[4]_i_6_n_0\,
      I3 => \init_state_r[4]_i_7_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r[4]_i_8_n_0\,
      O => \init_state_r[4]_i_3_n_0\
    );
\init_state_r[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FE00FE00FE00"
    )
        port map (
      I0 => \init_state_r[4]_i_9_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      I3 => \init_state_r[4]_i_10_n_0\,
      I4 => \init_state_r[4]_i_11_n_0\,
      I5 => \init_state_r[4]_i_12_n_0\,
      O => \init_state_r[4]_i_4_n_0\
    );
\init_state_r[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A888A8A8A888A88"
    )
        port map (
      I0 => \init_state_r[4]_i_13_n_0\,
      I1 => \init_state_r[4]_i_14_n_0\,
      I2 => \oclk_wr_cnt[3]_i_5_n_0\,
      I3 => \init_state_r[4]_i_15_n_0\,
      I4 => \^q\(0),
      I5 => \init_state_r[4]_i_16_n_0\,
      O => \init_state_r[4]_i_5_n_0\
    );
\init_state_r[4]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      O => \init_state_r[4]_i_6_n_0\
    );
\init_state_r[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F777FF77FF77FF7"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      I4 => complex_sample_cnt_inc_i_2_n_0,
      I5 => \init_state_r[3]_i_5_n_0\,
      O => \init_state_r[4]_i_7_n_0\
    );
\init_state_r[4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A8AAA0AAAAAAAAA"
    )
        port map (
      I0 => \init_state_r[5]_i_13_n_0\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[4]_i_8_n_0\
    );
\init_state_r[4]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0BFF0B00"
    )
        port map (
      I0 => mem_init_done_r,
      I1 => cnt_init_af_done_r,
      I2 => \init_state_r[4]_i_17_n_0\,
      I3 => \^q\(0),
      I4 => ddr2_pre_flag_r_reg_n_0,
      O => \init_state_r[4]_i_9_n_0\
    );
\init_state_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \init_state_r[5]_i_2_n_0\,
      I1 => init_state_r(6),
      I2 => \init_state_r[5]_i_3_n_0\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r[5]_i_4_n_0\,
      O => \init_state_r[5]_i_1_n_0\
    );
\init_state_r[5]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00DF003300570033"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => prbs_rdlvl_done_pulse0,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r[5]_i_14_n_0\,
      O => \init_state_r[5]_i_10_n_0\
    );
\init_state_r[5]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      O => \init_state_r[5]_i_11_n_0\
    );
\init_state_r[5]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[5]_i_12_n_0\
    );
\init_state_r[5]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAABABABBBBBBBB"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r[1]_i_12_n_0\,
      I2 => cnt_cmd_done_r,
      I3 => \^q\(0),
      I4 => wrcal_prech_req,
      I5 => \init_state_r[0]_i_10_n_0\,
      O => \init_state_r[5]_i_13_n_0\
    );
\init_state_r[5]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^one_rank.stg1_wr_done_reg_0\,
      I1 => \^prech_req_posedge_r_reg_0\,
      O => \init_state_r[5]_i_14_n_0\
    );
\init_state_r[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[5]_i_2_n_0\
    );
\init_state_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0DFFFFFF0D0000"
    )
        port map (
      I0 => \init_state_r[5]_i_5_n_0\,
      I1 => \init_state_r[5]_i_6_n_0\,
      I2 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      I3 => \init_state_r[5]_i_7_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r[5]_i_8_n_0\,
      O => \init_state_r[5]_i_3_n_0\
    );
\init_state_r[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C800080008000800"
    )
        port map (
      I0 => \init_state_r[5]_i_9_n_0\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[5]_i_4_n_0\
    );
\init_state_r[5]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => \^rdlvl_stg1_done_r1\,
      I2 => D(2),
      O => \init_state_r[5]_i_5_n_0\
    );
\init_state_r[5]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA8A"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => D(2),
      I3 => \^rdlvl_stg1_done_r1\,
      O => \init_state_r[5]_i_6_n_0\
    );
\init_state_r[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAAA"
    )
        port map (
      I0 => \init_state_r[5]_i_10_n_0\,
      I1 => \init_state_r[5]_i_11_n_0\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I4 => \init_state_r[5]_i_12_n_0\,
      I5 => \init_state_r[3]_i_5_n_0\,
      O => \init_state_r[5]_i_7_n_0\
    );
\init_state_r[5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A0AAAAAAAAAAAA"
    )
        port map (
      I0 => \init_state_r[5]_i_13_n_0\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => cnt_cmd_done_r,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[5]_i_8_n_0\
    );
\init_state_r[5]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F344C044"
    )
        port map (
      I0 => \^pi_calib_done\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => reset_rd_addr_r1,
      I3 => \^q\(0),
      I4 => \^rdlvl_stg1_done_r1\,
      O => \init_state_r[5]_i_9_n_0\
    );
\init_state_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBB8BB8888B888"
    )
        port map (
      I0 => \init_state_r[6]_i_3_n_0\,
      I1 => init_state_r(6),
      I2 => \init_state_r[6]_i_4_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \init_state_r[6]_i_5_n_0\,
      O => \init_state_r[6]_i_1_n_0\
    );
\init_state_r[6]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF7FFFFF"
    )
        port map (
      I0 => \init_state_r[6]_i_20_n_0\,
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => complex_sample_cnt_inc_i_2_n_0,
      I5 => \init_state_r[6]_i_21_n_0\,
      O => \init_state_r[6]_i_10_n_0\
    );
\init_state_r[6]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000E200FFFFFF"
    )
        port map (
      I0 => \init_state_r[6]_i_22_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r[6]_i_23_n_0\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[6]_i_11_n_0\
    );
\init_state_r[6]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001555555555555"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r[6]_i_24_n_0\,
      O => \init_state_r[6]_i_12_n_0\
    );
\init_state_r[6]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF2FFF0000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => complex_sample_cnt_inc_i_2_n_0,
      I2 => \init_state_r[6]_i_25_n_0\,
      I3 => \complex_num_reads_dec[3]_i_6_n_0\,
      I4 => \init_state_r[6]_i_26_n_0\,
      I5 => \init_state_r[6]_i_27_n_0\,
      O => \init_state_r[6]_i_13_n_0\
    );
\init_state_r[6]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDDDFDFDFDDDFDD"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r[6]_i_28_n_0\,
      I3 => \^q\(0),
      I4 => \init_state_r[5]_i_5_n_0\,
      I5 => complex_sample_cnt_inc_i_2_n_0,
      O => \init_state_r[6]_i_14_n_0\
    );
\init_state_r[6]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[6]_i_15_n_0\
    );
\init_state_r[6]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => reset_rd_addr_r1,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \^rdlvl_stg1_done_r1\,
      O => \init_state_r[6]_i_16_n_0\
    );
\init_state_r[6]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCC44444440"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => pi_dqs_found_done,
      I3 => pi_dqs_found_rank_done,
      I4 => \^prech_req_posedge_r_reg_0\,
      I5 => cnt_cmd_done_r,
      O => \init_state_r[6]_i_17_n_0\
    );
\init_state_r[6]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111110111010"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => \^prech_req_posedge_r_reg_0\,
      I3 => \^rdlvl_stg1_done_r1\,
      I4 => D(2),
      I5 => rdlvl_stg1_rank_done,
      O => \init_state_r[6]_i_18_n_0\
    );
\init_state_r[6]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000553FFF00553F"
    )
        port map (
      I0 => cnt_init_pre_wait_done_r,
      I1 => p_128_in,
      I2 => \init_state_r[6]_i_9_0\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => cnt_cmd_done_r,
      O => \init_state_r[6]_i_19_n_0\
    );
\init_state_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1115FFFF11150000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \^prech_req_posedge_r_reg_0\,
      I3 => \^q\(0),
      I4 => init_state_r(6),
      I5 => \init_state_r[6]_i_6_n_0\,
      O => \init_state_r[6]_i_2_n_0\
    );
\init_state_r[6]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \init_state_r[6]_i_30_n_0\,
      I1 => complex_num_writes_dec_reg(1),
      I2 => complex_row0_wr_done,
      I3 => D(2),
      I4 => \^rdlvl_stg1_done_r1\,
      I5 => complex_num_writes_dec_reg(0),
      O => \init_state_r[6]_i_20_n_0\
    );
\init_state_r[6]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007F00FFFFFFFF"
    )
        port map (
      I0 => reset_rd_addr_r1,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => cnt_cmd_done_r,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[6]_i_21_n_0\
    );
\init_state_r[6]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFAAAEEAA"
    )
        port map (
      I0 => \init_state_r[6]_i_31_n_0\,
      I1 => cnt_cmd_done_r,
      I2 => burst_addr_r_reg_n_0,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r[6]_i_32_n_0\,
      O => \init_state_r[6]_i_22_n_0\
    );
\init_state_r[6]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55554444555F5555"
    )
        port map (
      I0 => \init_state_r[2]_i_14_n_0\,
      I1 => init_next_state044_out,
      I2 => \init_state_r[6]_i_33_n_0\,
      I3 => \init_state_r[6]_i_34_n_0\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \^q\(0),
      O => \init_state_r[6]_i_23_n_0\
    );
\init_state_r[6]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDDDDDDDDDFDD"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r[6]_i_15_n_0\,
      I2 => oclk_wr_cnt_reg(1),
      I3 => oclk_wr_cnt_reg(0),
      I4 => oclk_wr_cnt_reg(2),
      I5 => oclk_wr_cnt_reg(3),
      O => \init_state_r[6]_i_24_n_0\
    );
\init_state_r[6]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10115555"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^prech_req_posedge_r_reg_0\,
      I2 => complex_oclkdelay_calib_done_r1,
      I3 => D(2),
      I4 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[6]_i_25_n_0\
    );
\init_state_r[6]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => D(2),
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[6]_i_26_n_0\
    );
\init_state_r[6]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB030B0B0"
    )
        port map (
      I0 => \init_state_r[6]_i_35_n_0\,
      I1 => \complex_num_reads_dec[3]_i_6_n_0\,
      I2 => \wrcal_reads[7]_i_4_n_0\,
      I3 => prbs_rdlvl_done_pulse0,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I5 => \init_state_r[6]_i_36_n_0\,
      O => \init_state_r[6]_i_27_n_0\
    );
\init_state_r[6]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF4F0F00FF4F0FFF"
    )
        port map (
      I0 => \^rdlvl_stg1_done_r1\,
      I1 => D(2),
      I2 => \complex_num_reads_dec[3]_i_6_n_0\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \^q\(0),
      I5 => \init_state_r[1]_i_11_n_0\,
      O => \init_state_r[6]_i_28_n_0\
    );
\init_state_r[6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04550405"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \ocal_act_wait_cnt[3]_i_3_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      I4 => \^prech_req_posedge_r_reg_0\,
      O => \init_state_r[6]_i_3_n_0\
    );
\init_state_r[6]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => complex_num_writes_dec_reg(2),
      I1 => complex_num_writes_dec_reg(4),
      I2 => complex_num_writes_dec_reg(3),
      O => \init_state_r[6]_i_30_n_0\
    );
\init_state_r[6]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111110010"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => cnt_cmd_done_r,
      I3 => wrcal_prech_req,
      I4 => \^prech_req_posedge_r_reg_0\,
      I5 => burst_addr_r_reg_0,
      O => \init_state_r[6]_i_31_n_0\
    );
\init_state_r[6]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => wrcal_wr_cnt_reg(1),
      I3 => wrcal_wr_cnt_reg(0),
      I4 => wrcal_wr_cnt_reg(2),
      I5 => wrcal_wr_cnt_reg(3),
      O => \init_state_r[6]_i_32_n_0\
    );
\init_state_r[6]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[4]\,
      I1 => \wrcal_reads_reg_n_0_[5]\,
      I2 => \wrcal_reads_reg_n_0_[6]\,
      I3 => \wrcal_reads_reg_n_0_[7]\,
      O => \init_state_r[6]_i_33_n_0\
    );
\init_state_r[6]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[0]\,
      I1 => \wrcal_reads_reg_n_0_[1]\,
      I2 => \wrcal_reads_reg_n_0_[2]\,
      I3 => \wrcal_reads_reg_n_0_[3]\,
      O => \init_state_r[6]_i_34_n_0\
    );
\init_state_r[6]_i_35\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \^q\(0),
      O => \init_state_r[6]_i_35_n_0\
    );
\init_state_r[6]_i_36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555500005555DFFD"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[6]_i_36_n_0\
    );
\init_state_r[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFC0AAAAA2AA"
    )
        port map (
      I0 => \init_state_r[6]_i_7_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => cnt_cmd_done_r,
      I5 => \init_state_r[6]_i_8_n_0\,
      O => \init_state_r[6]_i_4_n_0\
    );
\init_state_r[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E0EEE0E0E0EEE0EE"
    )
        port map (
      I0 => \init_state_r[6]_i_9_n_0\,
      I1 => \init_state_r[6]_i_10_n_0\,
      I2 => \init_state_r[6]_i_11_n_0\,
      I3 => \init_state_r[6]_i_12_n_0\,
      I4 => \init_state_r[6]_i_13_n_0\,
      I5 => \init_state_r[6]_i_14_n_0\,
      O => \init_state_r[6]_i_5_n_0\
    );
\init_state_r[6]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2003000020000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r[6]_i_15_n_0\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r[6]_i_16_n_0\,
      O => \init_state_r[6]_i_6_n_0\
    );
\init_state_r[6]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEFEEEEEE"
    )
        port map (
      I0 => \init_state_r[6]_i_17_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => num_reads(1),
      I3 => num_reads(0),
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I5 => \init_state_r[6]_i_18_n_0\,
      O => \init_state_r[6]_i_7_n_0\
    );
\init_state_r[6]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[6]_i_8_n_0\
    );
\init_state_r[6]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF31013131"
    )
        port map (
      I0 => \init_state_r[6]_i_19_n_0\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => cnt_dllk_zqinit_done_r,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I5 => \init_state_r[6]_i_8_n_0\,
      O => \init_state_r[6]_i_9_n_0\
    );
\init_state_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \init_state_r[6]_i_1_n_0\,
      D => \init_state_r[0]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[0]\,
      R => \complex_address_reg[9]_0\(0)
    );
\init_state_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \init_state_r[6]_i_1_n_0\,
      D => \init_state_r[1]_i_1_n_0\,
      Q => \^q\(0),
      R => \complex_address_reg[9]_0\(0)
    );
\init_state_r_reg[1]_i_7\: unisim.vcomponents.MUXF7
     port map (
      I0 => \init_state_r[1]_i_14_n_0\,
      I1 => \init_state_r[1]_i_15_n_0\,
      O => \init_state_r_reg[1]_i_7_n_0\,
      S => \init_state_r_reg_n_0_[3]\
    );
\init_state_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \init_state_r[6]_i_1_n_0\,
      D => \init_state_r[2]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[2]\,
      R => \complex_address_reg[9]_0\(0)
    );
\init_state_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \init_state_r[6]_i_1_n_0\,
      D => \init_state_r[3]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[3]\,
      R => \complex_address_reg[9]_0\(0)
    );
\init_state_r_reg[3]_i_10\: unisim.vcomponents.MUXF7
     port map (
      I0 => \init_state_r[3]_i_12_n_0\,
      I1 => \init_state_r[3]_i_13_n_0\,
      O => \init_state_r_reg[3]_i_10_n_0\,
      S => \init_state_r_reg_n_0_[3]\
    );
\init_state_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \init_state_r[6]_i_1_n_0\,
      D => \init_state_r[4]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[4]\,
      R => \complex_address_reg[9]_0\(0)
    );
\init_state_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \init_state_r[6]_i_1_n_0\,
      D => \init_state_r[5]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[5]\,
      R => \complex_address_reg[9]_0\(0)
    );
\init_state_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \init_state_r[6]_i_1_n_0\,
      D => \init_state_r[6]_i_2_n_0\,
      Q => init_state_r(6),
      R => \complex_address_reg[9]_0\(0)
    );
mem_init_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => cnt_init_mr_done_r,
      I3 => ddr2_refresh_flag_r,
      I4 => mem_init_done_r_i_2_n_0,
      I5 => mem_init_done_r,
      O => mem_init_done_r_i_1_n_0
    );
mem_init_done_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      O => mem_init_done_r_i_2_n_0
    );
mem_init_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mem_init_done_r_i_1_n_0,
      Q => mem_init_done_r,
      R => rdlvl_stg1_start_reg_1
    );
\mem_reg_0_15_0_5_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(23),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(1)
    );
mem_reg_0_15_0_5_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(0)
    );
\mem_reg_0_15_0_5_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(15),
      I1 => phy_wrdata(29),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(1)
    );
mem_reg_0_15_0_5_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(6),
      I1 => phy_wrdata(13),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(0)
    );
\mem_reg_0_15_0_5_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(3)
    );
mem_reg_0_15_0_5_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(36),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(2)
    );
\mem_reg_0_15_0_5_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(38),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(2)
    );
mem_reg_0_15_0_5_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(58),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(3)
    );
mem_reg_0_15_12_17_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(14),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(9)
    );
\mem_reg_0_15_12_17_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(19),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(1)
    );
\mem_reg_0_15_12_17_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(50),
      I1 => phy_wrdata(127),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(2)
    );
\mem_reg_0_15_12_17_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(54),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(10)
    );
mem_reg_0_15_12_17_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(3),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(8)
    );
\mem_reg_0_15_12_17_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(8),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(0)
    );
\mem_reg_0_15_12_17_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(44),
      I1 => phy_wrdata(125),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(9)
    );
mem_reg_0_15_12_17_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(77),
      I1 => phy_wrdata(126),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(4)
    );
mem_reg_0_15_12_17_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(62),
      I1 => phy_wrdata(127),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(3)
    );
\mem_reg_0_15_12_17_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(68),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(11)
    );
mem_reg_0_15_18_23_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(39),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(13)
    );
\mem_reg_0_15_18_23_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(11)
    );
\mem_reg_0_15_18_23_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(3)
    );
mem_reg_0_15_18_23_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(27),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(10)
    );
\mem_reg_0_15_18_23_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(32),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(2)
    );
\mem_reg_0_15_18_23_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(27),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(12)
    );
mem_reg_0_15_18_23_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(47),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(14)
    );
mem_reg_0_15_18_23_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(87),
      I1 => phy_wrdata(127),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(16)
    );
mem_reg_0_15_18_23_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(75),
      I1 => phy_wrdata(111),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(15)
    );
mem_reg_0_15_24_29_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(22),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(5)
    );
\mem_reg_0_15_24_29_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(8),
      I1 => phy_wrdata(46),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(5)
    );
mem_reg_0_15_24_29_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(4)
    );
\mem_reg_0_15_24_29_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(28),
      I1 => phy_wrdata(125),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(7)
    );
\mem_reg_0_15_24_29_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(7)
    );
mem_reg_0_15_24_29_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(35),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11]\,
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(6)
    );
\mem_reg_0_15_24_29_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(16),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(6)
    );
mem_reg_0_15_24_29_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(48),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(9)
    );
mem_reg_0_15_24_29_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(40),
      I1 => phy_wrdata(125),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(8)
    );
mem_reg_0_15_30_35_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(17),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(9)
    );
\mem_reg_0_15_30_35_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(14),
      I1 => phy_wrdata(46),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(17)
    );
mem_reg_0_15_30_35_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(6),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(8)
    );
\mem_reg_0_15_30_35_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(60),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(10)
    );
\mem_reg_0_15_30_35_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => phy_ras_n(0),
      O => phy_dout(12)
    );
\mem_reg_0_15_30_35_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(37),
      I1 => phy_wrdata(125),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(19)
    );
\mem_reg_0_15_30_35_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(11)
    );
mem_reg_0_15_30_35_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(30),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(10)
    );
\mem_reg_0_15_30_35_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(3),
      I1 => phy_wrdata(125),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(11)
    );
\mem_reg_0_15_30_35_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(25),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(18)
    );
mem_reg_0_15_30_35_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(20),
      I1 => phy_wrdata(46),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(12)
    );
mem_reg_0_15_36_41_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(11),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(14)
    );
\mem_reg_0_15_36_41_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(53),
      I1 => phy_wrdata(127),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(13)
    );
\mem_reg_0_15_36_41_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(57),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(21)
    );
\mem_reg_0_15_36_41_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_odt(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_odt(0),
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(12)
    );
mem_reg_0_15_36_41_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(0),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(13)
    );
\mem_reg_0_15_36_41_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(46),
      I1 => phy_wrdata(125),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(20)
    );
mem_reg_0_15_36_41_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(80),
      I1 => phy_wrdata(126),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(15)
    );
mem_reg_0_15_36_41_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(66),
      I1 => phy_wrdata(127),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(14)
    );
\mem_reg_0_15_36_41_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(72),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(22)
    );
\mem_reg_0_15_36_41_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(5),
      I1 => phy_wrdata(125),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(23)
    );
mem_reg_0_15_42_47_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(18),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(14)
    );
\mem_reg_0_15_42_47_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(30),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(17)
    );
\mem_reg_0_15_42_47_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(16)
    );
mem_reg_0_15_42_47_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(7),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(13)
    );
\mem_reg_0_15_42_47_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(24),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(15)
    );
\mem_reg_0_15_42_47_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(18),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(16)
    );
\mem_reg_0_15_42_47_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(23),
      I1 => phy_wrdata(46),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(24)
    );
mem_reg_0_15_42_47_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(21),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(18)
    );
\mem_reg_0_15_42_47_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(56),
      I1 => phy_wrdata(127),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(25)
    );
\mem_reg_0_15_42_47_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(16)
    );
mem_reg_0_15_42_47_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(10),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(17)
    );
\mem_reg_0_15_42_47_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(31),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(15)
    );
\mem_reg_0_15_42_47_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(41),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(18)
    );
mem_reg_0_15_42_47_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(78),
      I1 => phy_wrdata(127),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(20)
    );
\mem_reg_0_15_42_47_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(83),
      I1 => phy_wrdata(126),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(27)
    );
\mem_reg_0_15_42_47_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(20)
    );
mem_reg_0_15_42_47_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(34),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(19)
    );
\mem_reg_0_15_42_47_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(63),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(19)
    );
\mem_reg_0_15_42_47_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(70),
      I1 => phy_wrdata(127),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(26)
    );
mem_reg_0_15_48_53_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(15),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(18)
    );
\mem_reg_0_15_48_53_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(3),
      I1 => phy_bank(10),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(22)
    );
\mem_reg_0_15_48_53_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(9),
      I1 => phy_wrdata(29),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(22)
    );
\mem_reg_0_15_48_53_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(13),
      I1 => phy_wrdata(29),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(29)
    );
mem_reg_0_15_48_53_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(4),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(17)
    );
\mem_reg_0_15_48_53_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(1),
      I1 => phy_bank(10),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(21)
    );
\mem_reg_0_15_48_53_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(0),
      I1 => phy_wrdata(13),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(21)
    );
\mem_reg_0_15_48_53_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(4),
      I1 => phy_wrdata(13),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(28)
    );
mem_reg_0_15_48_53_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(29),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(23)
    );
\mem_reg_0_15_48_53_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(35),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(30)
    );
\mem_reg_0_15_48_53_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(20)
    );
\mem_reg_0_15_48_53_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => phy_bank(10),
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(24)
    );
mem_reg_0_15_48_53_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(28),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(19)
    );
\mem_reg_0_15_48_53_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(5),
      I1 => phy_bank(10),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(23)
    );
mem_reg_0_15_48_53_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(2),
      I1 => phy_bank(9),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(26)
    );
\mem_reg_0_15_48_53_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(49),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(24)
    );
\mem_reg_0_15_48_53_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(55),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(31)
    );
mem_reg_0_15_48_53_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(0),
      I1 => phy_bank(9),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(25)
    );
\mem_reg_0_15_48_53_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mem_reg_0_15_48_53(0),
      I1 => \phy_ctl_wd_i1_reg[22]\,
      I2 => phy_we_n(0),
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(21)
    );
mem_reg_0_15_54_59_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(76),
      I1 => phy_wrdata(125),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(26)
    );
\mem_reg_0_15_54_59_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(82),
      I1 => phy_wrdata(125),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(33)
    );
\mem_reg_0_15_54_59_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => phy_bank(9),
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(28)
    );
mem_reg_0_15_54_59_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(4),
      I1 => phy_bank(9),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(27)
    );
\mem_reg_0_15_54_59_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(61),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(25)
    );
\mem_reg_0_15_54_59_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(69),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(32)
    );
mem_reg_0_15_54_59_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(12),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(30)
    );
\mem_reg_0_15_54_59_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(10),
      I1 => phy_wrdata(46),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(27)
    );
\mem_reg_0_15_54_59_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => phy_cs_n(0),
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(22)
    );
mem_reg_0_15_54_59_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(1),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(29)
    );
mem_reg_0_15_54_59_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(31),
      I1 => phy_wrdata(125),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(29)
    );
\mem_reg_0_15_54_59_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(36),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(35)
    );
\mem_reg_0_15_54_59_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(32)
    );
mem_reg_0_15_54_59_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(25),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(31)
    );
\mem_reg_0_15_54_59_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(19),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(28)
    );
\mem_reg_0_15_54_59_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(24),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(34)
    );
mem_reg_0_15_60_65_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mem_reg_0_15_60_65(1),
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_cke(3),
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(24)
    );
\mem_reg_0_15_60_65_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(16),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(34)
    );
\mem_reg_0_15_60_65_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(51),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(31)
    );
mem_reg_0_15_60_65_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mem_reg_0_15_60_65(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => calib_cke(3),
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(23)
    );
\mem_reg_0_15_60_65_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(5),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(33)
    );
\mem_reg_0_15_60_65_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(42),
      I1 => phy_wrdata(125),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(30)
    );
\mem_reg_0_15_60_65_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(45),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(36)
    );
\mem_reg_0_15_60_65_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(84),
      I1 => phy_wrdata(127),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(38)
    );
mem_reg_0_15_60_65_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(64),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(32)
    );
\mem_reg_0_15_60_65_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(71),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(37)
    );
\mem_reg_0_15_60_65_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(7),
      I1 => phy_wrdata(125),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(39)
    );
mem_reg_0_15_66_71_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(33),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(34)
    );
\mem_reg_0_15_66_71_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(36)
    );
mem_reg_0_15_66_71_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(29),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(35)
    );
\mem_reg_0_15_66_71_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(21),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(33)
    );
\mem_reg_0_15_66_71_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(26),
      I1 => phy_wrdata(46),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(40)
    );
\mem_reg_0_15_66_71_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(59),
      I1 => phy_wrdata(127),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(41)
    );
mem_reg_0_15_66_71_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(43),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(35)
    );
mem_reg_0_15_66_71_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(81),
      I1 => phy_wrdata(127),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(37)
    );
\mem_reg_0_15_66_71_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(86),
      I1 => phy_wrdata(126),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(43)
    );
mem_reg_0_15_66_71_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(67),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(36)
    );
\mem_reg_0_15_66_71_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(74),
      I1 => phy_wrdata(127),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(42)
    );
mem_reg_0_15_6_11_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(13),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(5)
    );
\mem_reg_0_15_6_11_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(85),
      I1 => phy_wrdata(125),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(5)
    );
mem_reg_0_15_6_11_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(2),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(4)
    );
\mem_reg_0_15_6_11_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(1),
      I1 => phy_wrdata(125),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(0)
    );
\mem_reg_0_15_6_11_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(73),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(4)
    );
mem_reg_0_15_6_11_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(12),
      I1 => phy_wrdata(46),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(6)
    );
\mem_reg_0_15_6_11_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(7)
    );
mem_reg_0_15_6_11_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(26),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(6)
    );
\mem_reg_0_15_6_11_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(17),
      I1 => phy_wrdata(46),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(1)
    );
mem_reg_0_15_6_11_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(34),
      I1 => phy_wrdata(125),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(8)
    );
mem_reg_0_15_6_11_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(22),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[126]\(7)
    );
mem_reg_0_15_72_77_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(20),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(38)
    );
\mem_reg_0_15_72_77_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(11),
      I1 => phy_wrdata(29),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(39)
    );
mem_reg_0_15_72_77_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(9),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(37)
    );
\mem_reg_0_15_72_77_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(2),
      I1 => phy_wrdata(13),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(38)
    );
\mem_reg_0_15_72_77_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => phy_ctl_wr_i1_reg,
      I2 => phy_cas_n(0),
      O => \cmd_pipe_plus.mc_cas_n_reg[0]\(25)
    );
mem_reg_0_15_72_77_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(32),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(40)
    );
\mem_reg_0_15_72_77_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I1 => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\,
      O => phy_dout(40)
    );
mem_reg_0_15_72_77_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(33),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => phy_dout(39)
    );
mem_reg_0_15_72_77_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(52),
      I1 => phy_wrdata(111),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(41)
    );
mem_reg_0_15_78_79_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(79),
      I1 => phy_wrdata(125),
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(43)
    );
mem_reg_0_15_78_79_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => out_fifo(65),
      I1 => phy_wrdata(109),
      I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[117]\(42)
    );
mpr_rdlvl_start_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00100000"
    )
        port map (
      I0 => mpr_rdlvl_start_i_2_n_0,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \^q\(0),
      I4 => pi_dqs_found_done,
      I5 => \^mpr_rdlvl_start_reg_0\,
      O => mpr_rdlvl_start_i_1_n_0
    );
mpr_rdlvl_start_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      O => mpr_rdlvl_start_i_2_n_0
    );
mpr_rdlvl_start_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mpr_rdlvl_start_i_1_n_0,
      Q => \^mpr_rdlvl_start_reg_0\,
      R => SR(0)
    );
\my_empty[7]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_wrdata_en,
      I1 => phy_ctl_wr_i1_reg,
      I2 => \^calib_wrdata_en\,
      O => mux_wrdata_en
    );
\my_empty[7]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => phy_ctl_wr_i1_reg,
      I1 => \^calib_ctl_wren_reg_0\,
      O => mux_cmd_wren
    );
\num_refresh[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => num_refresh_reg(0),
      O => \p_0_in__8\(0)
    );
\num_refresh[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => num_refresh_reg(0),
      I1 => num_refresh_reg(1),
      O => \p_0_in__8\(1)
    );
\num_refresh[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => num_refresh_reg(2),
      I1 => num_refresh_reg(1),
      I2 => num_refresh_reg(0),
      O => \p_0_in__8\(2)
    );
\num_refresh[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBA"
    )
        port map (
      I0 => \num_refresh[3]_i_4_n_0\,
      I1 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I2 => \^q\(0),
      I3 => \num_refresh[3]_i_5_n_0\,
      I4 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      I5 => \num_refresh[3]_i_6_n_0\,
      O => \num_refresh[3]_i_1_n_0\
    );
\num_refresh[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \num_refresh[3]_i_7_n_0\,
      I1 => pi_dqs_found_done,
      I2 => D(2),
      O => num_refresh0
    );
\num_refresh[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => num_refresh_reg(3),
      I1 => num_refresh_reg(0),
      I2 => num_refresh_reg(1),
      I3 => num_refresh_reg(2),
      O => \p_0_in__8\(3)
    );
\num_refresh[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAABAAAA"
    )
        port map (
      I0 => \num_refresh[3]_i_8_n_0\,
      I1 => \^q\(0),
      I2 => \oclk_wr_cnt[3]_i_5_n_0\,
      I3 => \wrcal_start_dly_r_reg[4]_srl5_i_2_n_0\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \num_refresh[3]_i_4_n_0\
    );
\num_refresh[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => init_state_r(6),
      O => \num_refresh[3]_i_5_n_0\
    );
\num_refresh[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \num_refresh[3]_i_6_n_0\
    );
\num_refresh[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => init_state_r(6),
      O => \num_refresh[3]_i_7_n_0\
    );
\num_refresh[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000020000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r[6]_i_15_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => init_state_r(6),
      O => \num_refresh[3]_i_8_n_0\
    );
\num_refresh_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => num_refresh0,
      D => \p_0_in__8\(0),
      Q => num_refresh_reg(0),
      R => \num_refresh[3]_i_1_n_0\
    );
\num_refresh_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => num_refresh0,
      D => \p_0_in__8\(1),
      Q => num_refresh_reg(1),
      R => \num_refresh[3]_i_1_n_0\
    );
\num_refresh_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => num_refresh0,
      D => \p_0_in__8\(2),
      Q => num_refresh_reg(2),
      R => \num_refresh[3]_i_1_n_0\
    );
\num_refresh_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => num_refresh0,
      D => \p_0_in__8\(3),
      Q => num_refresh_reg(3),
      R => \num_refresh[3]_i_1_n_0\
    );
\ocal_act_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ocal_act_wait_cnt_reg(0),
      O => \p_0_in__6\(0)
    );
\ocal_act_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ocal_act_wait_cnt_reg(0),
      I1 => ocal_act_wait_cnt_reg(1),
      O => \p_0_in__6\(1)
    );
\ocal_act_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => ocal_act_wait_cnt_reg(2),
      I1 => ocal_act_wait_cnt_reg(1),
      I2 => ocal_act_wait_cnt_reg(0),
      O => \p_0_in__6\(2)
    );
\ocal_act_wait_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => \ocal_act_wait_cnt[3]_i_3_n_0\,
      I1 => \wrcal_reads_reg[0]_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^q\(0),
      I4 => \ocal_act_wait_cnt[3]_i_4_n_0\,
      O => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\ocal_act_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => ocal_act_wait_cnt_reg(3),
      I1 => ocal_act_wait_cnt_reg(0),
      I2 => ocal_act_wait_cnt_reg(1),
      I3 => ocal_act_wait_cnt_reg(2),
      O => \p_0_in__6\(3)
    );
\ocal_act_wait_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => ocal_act_wait_cnt_reg(3),
      I1 => ocal_act_wait_cnt_reg(0),
      I2 => ocal_act_wait_cnt_reg(1),
      I3 => ocal_act_wait_cnt_reg(2),
      O => \ocal_act_wait_cnt[3]_i_3_n_0\
    );
\ocal_act_wait_cnt[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      O => \ocal_act_wait_cnt[3]_i_4_n_0\
    );
\ocal_act_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__6\(0),
      Q => ocal_act_wait_cnt_reg(0),
      R => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\ocal_act_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__6\(1),
      Q => ocal_act_wait_cnt_reg(1),
      R => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\ocal_act_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__6\(2),
      Q => ocal_act_wait_cnt_reg(2),
      R => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\ocal_act_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__6\(3),
      Q => ocal_act_wait_cnt_reg(3),
      R => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oclk_wr_cnt_reg(0),
      O => \oclk_wr_cnt[0]_i_1_n_0\
    );
\oclk_wr_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => oclk_wr_cnt_reg(1),
      I1 => oclk_wr_cnt_reg(0),
      O => \oclk_wr_cnt[1]_i_1_n_0\
    );
\oclk_wr_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => oclk_wr_cnt_reg(2),
      I1 => oclk_wr_cnt_reg(0),
      I2 => oclk_wr_cnt_reg(1),
      O => \oclk_wr_cnt[2]_i_1_n_0\
    );
\oclk_wr_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAAAB"
    )
        port map (
      I0 => \oclk_wr_cnt[3]_i_4_n_0\,
      I1 => oclk_wr_cnt_reg(3),
      I2 => oclk_wr_cnt_reg(2),
      I3 => oclk_wr_cnt_reg(0),
      I4 => oclk_wr_cnt_reg(1),
      I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      O => \oclk_wr_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000004000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \oclk_wr_cnt[3]_i_5_n_0\,
      I5 => \^q\(0),
      O => \oclk_wr_cnt[3]_i_2_n_0\
    );
\oclk_wr_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => oclk_wr_cnt_reg(3),
      I1 => oclk_wr_cnt_reg(1),
      I2 => oclk_wr_cnt_reg(0),
      I3 => oclk_wr_cnt_reg(2),
      O => oclk_wr_cnt0(3)
    );
\oclk_wr_cnt[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \oclk_wr_cnt[3]_i_4_n_0\
    );
\oclk_wr_cnt[3]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      O => \oclk_wr_cnt[3]_i_5_n_0\
    );
\oclk_wr_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \oclk_wr_cnt[3]_i_2_n_0\,
      D => \oclk_wr_cnt[0]_i_1_n_0\,
      Q => oclk_wr_cnt_reg(0),
      R => \oclk_wr_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \oclk_wr_cnt[3]_i_2_n_0\,
      D => \oclk_wr_cnt[1]_i_1_n_0\,
      Q => oclk_wr_cnt_reg(1),
      R => \oclk_wr_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \oclk_wr_cnt[3]_i_2_n_0\,
      D => \oclk_wr_cnt[2]_i_1_n_0\,
      Q => oclk_wr_cnt_reg(2),
      S => \oclk_wr_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \oclk_wr_cnt[3]_i_2_n_0\,
      D => oclk_wr_cnt0(3),
      Q => oclk_wr_cnt_reg(3),
      R => \oclk_wr_cnt[3]_i_1_n_0\
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I1 => out_fifo_10,
      I2 => mem_out(3),
      I3 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(3)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(32),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => out_fifo_10,
      I3 => mem_out(2),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(2)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(19),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => out_fifo_10,
      I3 => mem_out(1),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(1)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(8),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => out_fifo_10,
      I3 => mem_out(0),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(0)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11]\,
      I1 => out_fifo_10,
      I2 => mem_out(7),
      I3 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[11]_0\(3)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(35),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11]\,
      I2 => out_fifo_10,
      I3 => mem_out(6),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[11]_0\(2)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(22),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11]\,
      I2 => out_fifo_10,
      I3 => mem_out(5),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[11]_0\(1)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_27\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11]\,
      I2 => out_fifo_10,
      I3 => mem_out(4),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[11]_0\(0)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I1 => out_fifo_10,
      I2 => mem_out(11),
      I3 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0\(3)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(30),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => out_fifo_10,
      I3 => mem_out(10),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0\(2)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_34\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(17),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => out_fifo_10,
      I3 => mem_out(9),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0\(1)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_35\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(6),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => out_fifo_10,
      I3 => mem_out(8),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0\(0)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I1 => out_fifo_10,
      I2 => mem_out(19),
      I3 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(7)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_37\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(31),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => out_fifo_10,
      I3 => mem_out(18),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(6)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_38\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(18),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => out_fifo_10,
      I3 => mem_out(17),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(5)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_39\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(7),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => out_fifo_10,
      I3 => mem_out(16),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(4)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_40\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_odt(0),
      I1 => out_fifo_10,
      I2 => calib_odt(0),
      I3 => mem_out(15),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(3)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_41\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_odt(0),
      I1 => out_fifo_10,
      I2 => calib_odt(0),
      I3 => mem_out(14),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(2)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_42\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_odt(0),
      I1 => out_fifo_10,
      I2 => calib_odt(0),
      I3 => mem_out(13),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(1)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_43\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_odt(0),
      I1 => out_fifo_10,
      I2 => calib_odt(0),
      I3 => mem_out(12),
      I4 => out_fifo_11,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(0)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_47\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mem_reg_0_15_48_53(0),
      I1 => out_fifo_0,
      I2 => phy_we_n(0),
      I3 => mem_out(24),
      I4 => out_fifo_11,
      O => \cmd_pipe_plus.mc_we_n_reg[0]\(4)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_48\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I1 => out_fifo_0,
      I2 => mem_out(23),
      I3 => out_fifo_11,
      O => \cmd_pipe_plus.mc_we_n_reg[0]\(3)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_49\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(28),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => out_fifo_0,
      I3 => mem_out(22),
      I4 => out_fifo_11,
      O => \cmd_pipe_plus.mc_we_n_reg[0]\(2)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_50\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(15),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => out_fifo_0,
      I3 => mem_out(21),
      I4 => out_fifo_11,
      O => \cmd_pipe_plus.mc_we_n_reg[0]\(1)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_51\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(4),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => out_fifo_0,
      I3 => mem_out(20),
      I4 => out_fifo_11,
      O => \cmd_pipe_plus.mc_we_n_reg[0]\(0)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_59\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => out_fifo_0,
      I2 => phy_cs_n(0),
      I3 => mem_out(25),
      I4 => out_fifo_11,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]_0\(0)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_64\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mem_reg_0_15_60_65(1),
      I1 => out_fifo_0,
      I2 => calib_cke(3),
      I3 => mem_out(29),
      I4 => out_fifo_11,
      O => \cmd_pipe_plus.mc_cke_reg[3]\(3)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_65\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mem_reg_0_15_60_65(1),
      I1 => out_fifo_0,
      I2 => calib_cke(3),
      I3 => mem_out(28),
      I4 => out_fifo_11,
      O => \cmd_pipe_plus.mc_cke_reg[3]\(2)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_66\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mem_reg_0_15_60_65(1),
      I1 => out_fifo_0,
      I2 => calib_cke(3),
      I3 => mem_out(27),
      I4 => out_fifo_11,
      O => \cmd_pipe_plus.mc_cke_reg[3]\(1)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_67\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mem_reg_0_15_60_65(0),
      I1 => out_fifo_0,
      I2 => calib_cke(3),
      I3 => mem_out(26),
      I4 => out_fifo_11,
      O => \cmd_pipe_plus.mc_cke_reg[3]\(0)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_73\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => out_fifo_0,
      I2 => phy_cas_n(0),
      I3 => mem_out(30),
      I4 => out_fifo_11,
      O => \cmd_pipe_plus.mc_cas_n_reg[0]_1\(0)
    );
\one_rank.stg1_wr_done_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000100010000"
    )
        port map (
      I0 => \reg_ctrl_cnt_r[3]_i_1_n_0\,
      I1 => rdlvl_last_byte_done,
      I2 => \^prbs_rdlvl_done_pulse_reg_0\,
      I3 => complex_byte_rd_done,
      I4 => \^stg1_wr_done\,
      I5 => \^one_rank.stg1_wr_done_reg_0\,
      O => \one_rank.stg1_wr_done_i_1_n_0\
    );
\one_rank.stg1_wr_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \one_rank.stg1_wr_done_i_1_n_0\,
      Q => \^one_rank.stg1_wr_done_reg_0\,
      R => '0'
    );
out_fifo_i_10: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(77),
      I1 => phy_wrdata(126),
      I2 => out_fifo_0,
      I3 => out_fifo_1(4),
      I4 => out_fifo_2,
      O => D1(4)
    );
out_fifo_i_11: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(62),
      I1 => phy_wrdata(127),
      I2 => out_fifo_0,
      I3 => out_fifo_1(3),
      I4 => out_fifo_2,
      O => D1(3)
    );
\out_fifo_i_11__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(68),
      I1 => phy_wrdata(111),
      I2 => out_fifo_4,
      I3 => out_fifo_5(11),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[104]\(5)
    );
out_fifo_i_12: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(50),
      I1 => phy_wrdata(127),
      I2 => out_fifo_0,
      I3 => out_fifo_1(2),
      I4 => out_fifo_2,
      O => D1(2)
    );
\out_fifo_i_12__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(54),
      I1 => phy_wrdata(109),
      I2 => out_fifo_4,
      I3 => out_fifo_5(10),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[104]\(4)
    );
\out_fifo_i_13__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(44),
      I1 => phy_wrdata(125),
      I2 => out_fifo_4,
      I3 => out_fifo_5(9),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[104]\(3)
    );
\out_fifo_i_14__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(34),
      I1 => phy_wrdata(125),
      I2 => out_fifo_4,
      I3 => out_fifo_5(8),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[104]\(2)
    );
out_fifo_i_15: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(17),
      I1 => phy_wrdata(46),
      I2 => out_fifo_0,
      I3 => out_fifo_1(1),
      I4 => out_fifo_2,
      O => D1(1)
    );
\out_fifo_i_15__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(22),
      I1 => phy_wrdata(109),
      I2 => out_fifo_4,
      I3 => out_fifo_5(7),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[104]\(1)
    );
\out_fifo_i_16__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(12),
      I1 => phy_wrdata(46),
      I2 => out_fifo_4,
      I3 => out_fifo_5(6),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[104]\(0)
    );
out_fifo_i_17: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(1),
      I1 => phy_wrdata(125),
      I2 => out_fifo_0,
      I3 => out_fifo_1(0),
      I4 => out_fifo_2,
      O => D1(0)
    );
\out_fifo_i_18__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(87),
      I1 => phy_wrdata(127),
      I2 => out_fifo_4,
      I3 => out_fifo_5(16),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[127]\(4)
    );
\out_fifo_i_19__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(75),
      I1 => phy_wrdata(111),
      I2 => out_fifo_4,
      I3 => out_fifo_5(15),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[127]\(3)
    );
out_fifo_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(85),
      I1 => phy_wrdata(125),
      I2 => out_fifo_4,
      I3 => out_fifo_5(5),
      I4 => out_fifo_6,
      O => D0(5)
    );
\out_fifo_i_21__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(47),
      I1 => phy_wrdata(109),
      I2 => out_fifo_4,
      I3 => out_fifo_5(14),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[127]\(2)
    );
\out_fifo_i_22__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(39),
      I1 => phy_wrdata(109),
      I2 => out_fifo_4,
      I3 => out_fifo_5(13),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[127]\(1)
    );
\out_fifo_i_23__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(27),
      I1 => phy_wrdata(111),
      I2 => out_fifo_4,
      I3 => out_fifo_5(12),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[127]\(0)
    );
out_fifo_i_27: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(60),
      I1 => phy_wrdata(111),
      I2 => out_fifo_3,
      I3 => out_fifo_1(10),
      I4 => out_fifo_2,
      O => D3(5)
    );
out_fifo_i_28: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(48),
      I1 => phy_wrdata(109),
      I2 => out_fifo_3,
      I3 => out_fifo_1(9),
      I4 => out_fifo_2,
      O => D3(4)
    );
out_fifo_i_29: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(40),
      I1 => phy_wrdata(125),
      I2 => out_fifo_3,
      I3 => out_fifo_1(8),
      I4 => out_fifo_2,
      O => D3(3)
    );
out_fifo_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(73),
      I1 => phy_wrdata(109),
      I2 => out_fifo_4,
      I3 => out_fifo_5(4),
      I4 => out_fifo_6,
      O => D0(4)
    );
out_fifo_i_30: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(28),
      I1 => phy_wrdata(125),
      I2 => out_fifo_0,
      I3 => out_fifo_1(7),
      I4 => out_fifo_2,
      O => D3(2)
    );
out_fifo_i_31: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(16),
      I1 => phy_wrdata(109),
      I2 => out_fifo_0,
      I3 => out_fifo_1(6),
      I4 => out_fifo_2,
      O => D3(1)
    );
out_fifo_i_32: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(8),
      I1 => phy_wrdata(46),
      I2 => out_fifo_0,
      I3 => out_fifo_1(5),
      I4 => out_fifo_2,
      O => D3(0)
    );
out_fifo_i_34: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(80),
      I1 => phy_wrdata(126),
      I2 => out_fifo_3,
      I3 => out_fifo_1(15),
      I4 => out_fifo_2,
      O => D4(4)
    );
out_fifo_i_35: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(66),
      I1 => phy_wrdata(127),
      I2 => out_fifo_3,
      I3 => out_fifo_1(14),
      I4 => out_fifo_2,
      O => D4(3)
    );
\out_fifo_i_35__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(72),
      I1 => phy_wrdata(111),
      I2 => out_fifo_4,
      I3 => out_fifo_5(22),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[108]\(5)
    );
out_fifo_i_36: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(53),
      I1 => phy_wrdata(127),
      I2 => out_fifo_3,
      I3 => out_fifo_1(13),
      I4 => out_fifo_2,
      O => D4(2)
    );
\out_fifo_i_36__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(57),
      I1 => phy_wrdata(109),
      I2 => out_fifo_4,
      I3 => out_fifo_5(21),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[108]\(4)
    );
\out_fifo_i_37__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(46),
      I1 => phy_wrdata(125),
      I2 => out_fifo_4,
      I3 => out_fifo_5(20),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[108]\(3)
    );
\out_fifo_i_38__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(37),
      I1 => phy_wrdata(125),
      I2 => out_fifo_4,
      I3 => out_fifo_5(19),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[108]\(2)
    );
out_fifo_i_39: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(20),
      I1 => phy_wrdata(46),
      I2 => out_fifo_3,
      I3 => out_fifo_1(12),
      I4 => out_fifo_2,
      O => D4(1)
    );
\out_fifo_i_39__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(25),
      I1 => phy_wrdata(109),
      I2 => out_fifo_4,
      I3 => out_fifo_5(18),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[108]\(1)
    );
out_fifo_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(58),
      I1 => phy_wrdata(111),
      I2 => out_fifo_4,
      I3 => out_fifo_5(3),
      I4 => out_fifo_6,
      O => D0(3)
    );
\out_fifo_i_40__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(14),
      I1 => phy_wrdata(46),
      I2 => out_fifo_4,
      I3 => out_fifo_5(17),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[108]\(0)
    );
out_fifo_i_41: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(3),
      I1 => phy_wrdata(125),
      I2 => out_fifo_3,
      I3 => out_fifo_1(11),
      I4 => out_fifo_2,
      O => D4(0)
    );
out_fifo_i_42: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(78),
      I1 => phy_wrdata(127),
      I2 => out_fifo_3,
      I3 => out_fifo_1(20),
      I4 => out_fifo_2,
      O => D5(4)
    );
\out_fifo_i_42__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(83),
      I1 => phy_wrdata(126),
      I2 => out_fifo_7,
      I3 => out_fifo_5(27),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[122]\(4)
    );
out_fifo_i_43: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(63),
      I1 => phy_wrdata(111),
      I2 => out_fifo_3,
      I3 => out_fifo_1(19),
      I4 => out_fifo_2,
      O => D5(3)
    );
\out_fifo_i_43__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(70),
      I1 => phy_wrdata(127),
      I2 => out_fifo_4,
      I3 => out_fifo_5(26),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[122]\(3)
    );
\out_fifo_i_44__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(56),
      I1 => phy_wrdata(127),
      I2 => out_fifo_4,
      I3 => out_fifo_5(25),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[122]\(2)
    );
out_fifo_i_45: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(41),
      I1 => phy_wrdata(109),
      I2 => out_fifo_3,
      I3 => out_fifo_1(18),
      I4 => out_fifo_2,
      O => D5(2)
    );
out_fifo_i_46: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(30),
      I1 => phy_wrdata(109),
      I2 => out_fifo_3,
      I3 => out_fifo_1(17),
      I4 => out_fifo_2,
      O => D5(1)
    );
out_fifo_i_47: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(18),
      I1 => phy_wrdata(111),
      I2 => out_fifo_3,
      I3 => out_fifo_1(16),
      I4 => out_fifo_2,
      O => D5(0)
    );
\out_fifo_i_47__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(23),
      I1 => phy_wrdata(46),
      I2 => out_fifo_4,
      I3 => out_fifo_5(24),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[122]\(1)
    );
\out_fifo_i_49__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(5),
      I1 => phy_wrdata(125),
      I2 => out_fifo_4,
      I3 => out_fifo_5(23),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[122]\(0)
    );
out_fifo_i_50: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(76),
      I1 => phy_wrdata(125),
      I2 => out_fifo_3,
      I3 => out_fifo_1(26),
      I4 => out_fifo_2,
      O => D6(5)
    );
\out_fifo_i_50__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(82),
      I1 => phy_wrdata(125),
      I2 => out_fifo_7,
      I3 => out_fifo_5(33),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[121]\(5)
    );
out_fifo_i_51: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(61),
      I1 => phy_wrdata(109),
      I2 => out_fifo_3,
      I3 => out_fifo_1(25),
      I4 => out_fifo_2,
      O => D6(4)
    );
\out_fifo_i_51__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(69),
      I1 => phy_wrdata(109),
      I2 => out_fifo_7,
      I3 => out_fifo_5(32),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[121]\(4)
    );
out_fifo_i_52: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(49),
      I1 => phy_wrdata(111),
      I2 => out_fifo_3,
      I3 => out_fifo_1(24),
      I4 => out_fifo_2,
      O => D6(3)
    );
\out_fifo_i_52__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(55),
      I1 => phy_wrdata(111),
      I2 => out_fifo_7,
      I3 => out_fifo_5(31),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[121]\(3)
    );
out_fifo_i_54: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(29),
      I1 => phy_wrdata(109),
      I2 => out_fifo_3,
      I3 => out_fifo_1(23),
      I4 => out_fifo_2,
      O => D6(2)
    );
\out_fifo_i_54__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(35),
      I1 => phy_wrdata(109),
      I2 => out_fifo_7,
      I3 => out_fifo_5(30),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[121]\(2)
    );
out_fifo_i_56: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(9),
      I1 => phy_wrdata(29),
      I2 => out_fifo_3,
      I3 => out_fifo_1(22),
      I4 => out_fifo_2,
      O => D6(1)
    );
\out_fifo_i_56__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(13),
      I1 => phy_wrdata(29),
      I2 => out_fifo_7,
      I3 => out_fifo_5(29),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[121]\(1)
    );
out_fifo_i_57: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(0),
      I1 => phy_wrdata(13),
      I2 => out_fifo_3,
      I3 => out_fifo_1(21),
      I4 => out_fifo_2,
      O => D6(0)
    );
\out_fifo_i_57__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(4),
      I1 => phy_wrdata(13),
      I2 => out_fifo_7,
      I3 => out_fifo_5(28),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[121]\(0)
    );
\out_fifo_i_58__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(84),
      I1 => phy_wrdata(127),
      I2 => out_fifo_7,
      I3 => out_fifo_5(38),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[123]\(4)
    );
out_fifo_i_59: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(64),
      I1 => phy_wrdata(111),
      I2 => out_fifo_3,
      I3 => out_fifo_1(32),
      I4 => out_fifo_2,
      O => D7(5)
    );
\out_fifo_i_59__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(71),
      I1 => phy_wrdata(111),
      I2 => out_fifo_7,
      I3 => out_fifo_5(37),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[123]\(3)
    );
out_fifo_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(38),
      I1 => phy_wrdata(109),
      I2 => out_fifo_4,
      I3 => out_fifo_5(2),
      I4 => out_fifo_6,
      O => D0(2)
    );
out_fifo_i_60: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(51),
      I1 => phy_wrdata(109),
      I2 => out_fifo_3,
      I3 => out_fifo_1(31),
      I4 => out_fifo_2,
      O => D7(4)
    );
out_fifo_i_61: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(42),
      I1 => phy_wrdata(125),
      I2 => out_fifo_3,
      I3 => out_fifo_1(30),
      I4 => out_fifo_2,
      O => D7(3)
    );
\out_fifo_i_61__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(45),
      I1 => phy_wrdata(109),
      I2 => out_fifo_7,
      I3 => out_fifo_5(36),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[123]\(2)
    );
out_fifo_i_62: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(31),
      I1 => phy_wrdata(125),
      I2 => out_fifo_3,
      I3 => out_fifo_1(29),
      I4 => out_fifo_2,
      O => D7(2)
    );
\out_fifo_i_62__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(36),
      I1 => phy_wrdata(109),
      I2 => out_fifo_7,
      I3 => out_fifo_5(35),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[123]\(1)
    );
out_fifo_i_63: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(19),
      I1 => phy_wrdata(109),
      I2 => out_fifo_3,
      I3 => out_fifo_1(28),
      I4 => out_fifo_2,
      O => D7(1)
    );
\out_fifo_i_63__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(24),
      I1 => phy_wrdata(111),
      I2 => out_fifo_7,
      I3 => out_fifo_5(34),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[123]\(0)
    );
out_fifo_i_64: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(10),
      I1 => phy_wrdata(46),
      I2 => out_fifo_3,
      I3 => out_fifo_1(27),
      I4 => out_fifo_2,
      O => D7(0)
    );
out_fifo_i_66: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(81),
      I1 => phy_wrdata(127),
      I2 => out_fifo_3,
      I3 => out_fifo_1(37),
      I4 => out_fifo_2,
      O => D8(4)
    );
\out_fifo_i_66__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(86),
      I1 => phy_wrdata(126),
      I2 => out_fifo_7,
      I3 => out_fifo_5(43),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[126]_0\(4)
    );
out_fifo_i_67: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(67),
      I1 => phy_wrdata(111),
      I2 => out_fifo_3,
      I3 => out_fifo_1(36),
      I4 => out_fifo_2,
      O => D8(3)
    );
\out_fifo_i_67__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(74),
      I1 => phy_wrdata(127),
      I2 => out_fifo_7,
      I3 => out_fifo_5(42),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[126]_0\(3)
    );
\out_fifo_i_68__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(59),
      I1 => phy_wrdata(127),
      I2 => out_fifo_7,
      I3 => out_fifo_5(41),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[126]_0\(2)
    );
out_fifo_i_69: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(43),
      I1 => phy_wrdata(109),
      I2 => out_fifo_3,
      I3 => out_fifo_1(35),
      I4 => out_fifo_2,
      O => D8(2)
    );
out_fifo_i_70: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(33),
      I1 => phy_wrdata(109),
      I2 => out_fifo_3,
      I3 => out_fifo_1(34),
      I4 => out_fifo_2,
      O => D8(1)
    );
out_fifo_i_71: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(21),
      I1 => phy_wrdata(111),
      I2 => out_fifo_3,
      I3 => out_fifo_1(33),
      I4 => out_fifo_2,
      O => D8(0)
    );
\out_fifo_i_71__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(26),
      I1 => phy_wrdata(46),
      I2 => out_fifo_7,
      I3 => out_fifo_5(40),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[126]_0\(1)
    );
\out_fifo_i_73__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(7),
      I1 => phy_wrdata(125),
      I2 => out_fifo_7,
      I3 => out_fifo_5(39),
      I4 => out_fifo_6,
      O => \write_buffer.wr_buf_out_data_reg[126]_0\(0)
    );
out_fifo_i_74: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(79),
      I1 => phy_wrdata(125),
      I2 => out_fifo_4,
      I3 => out_fifo_1(43),
      I4 => out_fifo_2,
      O => D9(5)
    );
out_fifo_i_75: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(65),
      I1 => phy_wrdata(109),
      I2 => out_fifo_4,
      I3 => out_fifo_1(42),
      I4 => out_fifo_2,
      O => D9(4)
    );
out_fifo_i_76: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(52),
      I1 => phy_wrdata(111),
      I2 => out_fifo_4,
      I3 => out_fifo_1(41),
      I4 => out_fifo_2,
      O => D9(3)
    );
out_fifo_i_78: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(32),
      I1 => phy_wrdata(109),
      I2 => out_fifo_4,
      I3 => out_fifo_1(40),
      I4 => out_fifo_2,
      O => D9(2)
    );
out_fifo_i_8: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(15),
      I1 => phy_wrdata(29),
      I2 => out_fifo_4,
      I3 => out_fifo_5(1),
      I4 => out_fifo_6,
      O => D0(1)
    );
out_fifo_i_80: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(11),
      I1 => phy_wrdata(29),
      I2 => out_fifo_3,
      I3 => out_fifo_1(39),
      I4 => out_fifo_2,
      O => D9(1)
    );
out_fifo_i_81: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(2),
      I1 => phy_wrdata(13),
      I2 => out_fifo_3,
      I3 => out_fifo_1(38),
      I4 => out_fifo_2,
      O => D9(0)
    );
out_fifo_i_9: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ACACFF00"
    )
        port map (
      I0 => out_fifo(6),
      I1 => phy_wrdata(13),
      I2 => out_fifo_4,
      I3 => out_fifo_5(0),
      I4 => out_fifo_6,
      O => D0(0)
    );
\phy_ctl_wd_i1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_cmd(0),
      I1 => calib_cmd(0),
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \^calib_seq_reg[1]_0\(0)
    );
\phy_ctl_wd_i1[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \phy_ctl_wd_i1_reg[17]\,
      I1 => calib_data_offset_0(0),
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \^calib_seq_reg[1]_0\(3)
    );
\phy_ctl_wd_i1[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \phy_ctl_wd_i1_reg[19]\(0),
      I1 => calib_data_offset_0(1),
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \^calib_seq_reg[1]_0\(4)
    );
\phy_ctl_wd_i1[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \phy_ctl_wd_i1_reg[19]\(1),
      I1 => calib_data_offset_0(2),
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \^calib_seq_reg[1]_0\(5)
    );
\phy_ctl_wd_i1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_cmd(1),
      I1 => calib_cmd(1),
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \^calib_seq_reg[1]_0\(1)
    );
\phy_ctl_wd_i1[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \phy_ctl_wd_i1_reg[20]\,
      I1 => calib_data_offset_0(3),
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \^calib_seq_reg[1]_0\(6)
    );
\phy_ctl_wd_i1[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \phy_ctl_wd_i1_reg[21]\,
      I1 => calib_data_offset_0(4),
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \^calib_seq_reg[1]_0\(7)
    );
\phy_ctl_wd_i1[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \phy_ctl_wd_i1_reg[22]_0\,
      I1 => calib_data_offset_0(5),
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \^calib_seq_reg[1]_0\(8)
    );
\phy_ctl_wd_i1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => calib_cmd(2),
      I2 => \phy_ctl_wd_i1_reg[22]\,
      O => \^calib_seq_reg[1]_0\(2)
    );
phy_ctl_wr_i1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^calib_ctl_wren_reg_0\,
      I1 => phy_ctl_wr_i1_reg,
      O => calib_ctl_wren_reg_1
    );
pi_calib_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_calib_done_r,
      Q => \^pi_calib_done\,
      R => '0'
    );
pi_calib_done_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => pi_calib_rank_done_r,
      I1 => pi_calib_done_r,
      O => pi_calib_done_r_i_1_n_0
    );
pi_calib_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_calib_done_r_i_1_n_0,
      Q => pi_calib_done_r,
      R => \complex_address_reg[9]_0\(0)
    );
pi_calib_rank_done_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => pi_phase_locked_all_r3,
      I1 => pi_phase_locked_all_r4,
      O => init_next_state044_out
    );
pi_calib_rank_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_next_state044_out,
      Q => pi_calib_rank_done_r,
      R => rdlvl_stg1_start_reg_1
    );
pi_dqs_found_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done,
      Q => \^pi_dqs_found_done_r1\,
      R => \complex_address_reg[9]_0\(0)
    );
pi_dqs_found_start_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000AE"
    )
        port map (
      I0 => \^pi_dqs_found_start_reg_0\,
      I1 => pi_dqs_found_start_i_2_n_0,
      I2 => pi_dqs_found_done,
      I3 => wrlvl_byte_redo,
      I4 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      O => pi_dqs_found_start_i_1_n_0
    );
pi_dqs_found_start_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => pi_dqs_found_start_i_2_n_0
    );
pi_dqs_found_start_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_start_i_1_n_0,
      Q => \^pi_dqs_found_start_reg_0\,
      R => '0'
    );
pi_phase_locked_all_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => in0,
      Q => pi_phase_locked_all_r1,
      R => '0'
    );
pi_phase_locked_all_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_phase_locked_all_r1,
      Q => pi_phase_locked_all_r2,
      R => '0'
    );
pi_phase_locked_all_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_phase_locked_all_r2,
      Q => pi_phase_locked_all_r3,
      R => '0'
    );
pi_phase_locked_all_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_phase_locked_all_r3,
      Q => pi_phase_locked_all_r4,
      R => '0'
    );
prbs_rdlvl_done_pulse_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => prbs_rdlvl_done_pulse0,
      Q => \^prbs_rdlvl_done_pulse_reg_0\,
      R => '0'
    );
\prech_done_dly_r_reg[15]_srl16\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => '1',
      CLK => CLK,
      D => prech_done_pre,
      Q => \prech_done_dly_r_reg[15]_srl16_n_0\
    );
\prech_done_dly_r_reg[15]_srl16_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => prech_pending_r_i_2_n_0,
      I1 => prech_pending_r,
      I2 => \^prech_req_posedge_r_reg_0\,
      O => prech_done_pre
    );
prech_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \prech_done_dly_r_reg[15]_srl16_n_0\,
      Q => prech_done,
      R => '0'
    );
prech_pending_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AE"
    )
        port map (
      I0 => \^prech_req_posedge_r_reg_0\,
      I1 => prech_pending_r,
      I2 => prech_pending_r_i_2_n_0,
      O => prech_pending_r_i_1_n_0
    );
prech_pending_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFAFFFEFAFA"
    )
        port map (
      I0 => prech_pending_r_i_3_n_0,
      I1 => rdlvl_last_byte_done_r,
      I2 => prech_pending_r_i_4_n_0,
      I3 => \^rdlvl_stg1_done_r1\,
      I4 => prech_pending_r_i_5_n_0,
      I5 => \complex_row_cnt_ocal[3]_i_5_n_0\,
      O => prech_pending_r_i_2_n_0
    );
prech_pending_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000FFFF10001000"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \^q\(0),
      I3 => complex_oclkdelay_calib_start_r1,
      I4 => prech_pending_r_i_6_n_0,
      I5 => cnt_cmd_done_r,
      O => prech_pending_r_i_3_n_0
    );
prech_pending_r_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFEFFFFFFFE"
    )
        port map (
      I0 => \^stg1_wr_done\,
      I1 => \num_refresh[3]_i_6_n_0\,
      I2 => \calib_cmd[1]_i_2_n_0\,
      I3 => \num_refresh[3]_i_8_n_0\,
      I4 => dqs_found_prech_req,
      I5 => prech_pending_r_i_7_n_0,
      O => prech_pending_r_i_4_n_0
    );
prech_pending_r_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \oclk_wr_cnt[3]_i_5_n_0\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => prech_pending_r_i_5_n_0
    );
prech_pending_r_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFBFFFFE"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \wrcal_start_dly_r_reg[4]_srl5_i_2_n_0\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[0]\,
      O => prech_pending_r_i_6_n_0
    );
prech_pending_r_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFBFFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      O => prech_pending_r_i_7_n_0
    );
prech_pending_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => prech_pending_r_i_1_n_0,
      Q => prech_pending_r,
      R => \complex_address_reg[9]_0\(0)
    );
prech_req_posedge_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55545454"
    )
        port map (
      I0 => prech_req_r,
      I1 => wrcal_prech_req,
      I2 => rdlvl_prech_req,
      I3 => dqs_found_prech_req,
      I4 => prech_req_posedge_r_i_2_n_0,
      O => prech_req_posedge_r0
    );
prech_req_posedge_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => init_complete_r_i_2_n_0,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => prech_req_posedge_r_i_2_n_0
    );
prech_req_posedge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => prech_req_posedge_r0,
      Q => \^prech_req_posedge_r_reg_0\,
      R => \complex_address_reg[9]_0\(0)
    );
prech_req_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEFEEEEE"
    )
        port map (
      I0 => wrcal_prech_req,
      I1 => rdlvl_prech_req,
      I2 => dqs_found_prech_req,
      I3 => prech_req_r_i_2_n_0,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[0]\,
      O => prech_req
    );
prech_req_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[4]\,
      O => prech_req_r_i_2_n_0
    );
prech_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => prech_req,
      Q => prech_req_r,
      R => \complex_address_reg[9]_0\(0)
    );
pwron_ce_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(9),
      I1 => cnt_pwron_ce_r_reg(7),
      I2 => pwron_ce_r_i_2_n_0,
      I3 => cnt_pwron_ce_r_reg(6),
      I4 => cnt_pwron_ce_r_reg(8),
      O => pwron_ce_r_i_1_n_0
    );
pwron_ce_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => cnt_pwron_ce_r_reg(5),
      I1 => cnt_pwron_ce_r_reg(3),
      I2 => cnt_pwron_ce_r_reg(0),
      I3 => cnt_pwron_ce_r_reg(1),
      I4 => cnt_pwron_ce_r_reg(2),
      I5 => cnt_pwron_ce_r_reg(4),
      O => pwron_ce_r_i_2_n_0
    );
pwron_ce_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pwron_ce_r_i_1_n_0,
      Q => pwron_ce_r,
      R => \complex_address_reg[9]_0\(0)
    );
rdlvl_last_byte_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_last_byte_done,
      Q => rdlvl_last_byte_done_r,
      R => '0'
    );
\rdlvl_start_dly0_r_reg[13]_srl14\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '1',
      A3 => '1',
      CE => '1',
      CLK => CLK,
      D => rdlvl_start_pre,
      Q => \rdlvl_start_dly0_r_reg[13]_srl14_n_0\
    );
\rdlvl_start_dly0_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rdlvl_start_dly0_r_reg[13]_srl14_n_0\,
      Q => rdlvl_start_dly0_r(14),
      R => '0'
    );
rdlvl_start_pre_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => pi_dqs_found_done,
      I1 => \calib_cmd[1]_i_2_n_0\,
      I2 => rdlvl_start_pre,
      O => rdlvl_start_pre_i_1_n_0
    );
rdlvl_start_pre_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_start_pre_i_1_n_0,
      Q => rdlvl_start_pre,
      R => \complex_address_reg[9]_0\(0)
    );
rdlvl_stg1_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(2),
      Q => \^rdlvl_stg1_done_r1\,
      R => '0'
    );
rdlvl_stg1_start_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BF80"
    )
        port map (
      I0 => rdlvl_start_dly0_r(14),
      I1 => \calib_cmd[1]_i_2_n_0\,
      I2 => pi_dqs_found_done,
      I3 => \^rdlvl_stg1_start_reg_0\,
      O => rdlvl_stg1_start_i_1_n_0
    );
rdlvl_stg1_start_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_stg1_start_i_1_n_0,
      Q => \^rdlvl_stg1_start_reg_0\,
      R => rdlvl_stg1_start_reg_1
    );
read_calib_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055550010"
    )
        port map (
      I0 => \wrcal_reads_reg[0]_0\,
      I1 => read_calib_i_2_n_0,
      I2 => \^q\(0),
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \^phy_read_calib\,
      I5 => \^pi_calib_done\,
      O => read_calib_i_1_n_0
    );
read_calib_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFDF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      O => read_calib_i_2_n_0
    );
read_calib_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => read_calib_i_1_n_0,
      Q => \^phy_read_calib\,
      R => '0'
    );
\reg_ctrl_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => reg_ctrl_cnt_r_reg(0),
      O => \p_0_in__7\(0)
    );
\reg_ctrl_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => reg_ctrl_cnt_r_reg(0),
      I1 => reg_ctrl_cnt_r_reg(1),
      O => \p_0_in__7\(1)
    );
\reg_ctrl_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => reg_ctrl_cnt_r_reg(2),
      I1 => reg_ctrl_cnt_r_reg(1),
      I2 => reg_ctrl_cnt_r_reg(0),
      O => \p_0_in__7\(2)
    );
\reg_ctrl_cnt_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \wrcal_reads[7]_i_5_n_0\,
      O => \reg_ctrl_cnt_r[3]_i_1_n_0\
    );
\reg_ctrl_cnt_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => init_state_r(6),
      O => reg_ctrl_cnt_r
    );
\reg_ctrl_cnt_r[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => reg_ctrl_cnt_r_reg(3),
      I1 => reg_ctrl_cnt_r_reg(0),
      I2 => reg_ctrl_cnt_r_reg(1),
      I3 => reg_ctrl_cnt_r_reg(2),
      O => \p_0_in__7\(3)
    );
\reg_ctrl_cnt_r[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      O => \reg_ctrl_cnt_r[3]_i_4_n_0\
    );
\reg_ctrl_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => reg_ctrl_cnt_r,
      D => \p_0_in__7\(0),
      Q => reg_ctrl_cnt_r_reg(0),
      R => \reg_ctrl_cnt_r[3]_i_1_n_0\
    );
\reg_ctrl_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => reg_ctrl_cnt_r,
      D => \p_0_in__7\(1),
      Q => reg_ctrl_cnt_r_reg(1),
      R => \reg_ctrl_cnt_r[3]_i_1_n_0\
    );
\reg_ctrl_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => reg_ctrl_cnt_r,
      D => \p_0_in__7\(2),
      Q => reg_ctrl_cnt_r_reg(2),
      R => \reg_ctrl_cnt_r[3]_i_1_n_0\
    );
\reg_ctrl_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => reg_ctrl_cnt_r,
      D => \p_0_in__7\(3),
      Q => reg_ctrl_cnt_r_reg(3),
      R => \reg_ctrl_cnt_r[3]_i_1_n_0\
    );
reset_rd_addr_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_ocal_reset_rd_addr,
      Q => reset_rd_addr_r1,
      R => '0'
    );
\row_cnt_victim_rotate.complex_row_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0455"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      I2 => \^one_rank.stg1_wr_done_reg_0\,
      I3 => complex_sample_cnt_inc_r2,
      O => \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00606666"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      I3 => \^one_rank.stg1_wr_done_reg_0\,
      I4 => complex_sample_cnt_inc_r2,
      O => \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000780078787878"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      I4 => \^one_rank.stg1_wr_done_reg_0\,
      I5 => complex_sample_cnt_inc_r2,
      O => \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => complex_sample_cnt_inc_r2,
      I1 => \^one_rank.stg1_wr_done_reg_0\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAFFABAAAA"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      I2 => complex_sample_cnt_inc_r2,
      I3 => reset_rd_addr_r1,
      I4 => \^one_rank.stg1_wr_done_reg_0\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      I1 => \^one_rank.stg1_wr_done_reg_0\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\,
      O => complex_row_cnt
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => complex_sample_cnt_inc_r2,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBAAAFFFF"
    )
        port map (
      I0 => \wrcal_reads_reg[0]_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0\,
      I2 => wr_victim_inc,
      I3 => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\,
      I4 => \^rdlvl_stg1_done_r1\,
      I5 => D(2),
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010101"
    )
        port map (
      I0 => reset_rd_addr_r1,
      I1 => complex_sample_cnt_inc_r2,
      I2 => wr_victim_inc,
      I3 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\,
      I4 => \complex_row_cnt_ocal[3]_i_5_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000004000000"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I5 => \complex_row_cnt_ocal[3]_i_7_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000022226AAA"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      I1 => complex_row_cnt,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\,
      I4 => complex_sample_cnt_inc_r2,
      I5 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000262A"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      I1 => complex_row_cnt,
      I2 => complex_sample_cnt_inc_r2,
      I3 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000022226AAA"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      I1 => complex_row_cnt,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      I4 => complex_sample_cnt_inc_r2,
      I5 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABABAAABABABABA"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\,
      I2 => \^one_rank.stg1_wr_done_reg_0\,
      I3 => reset_rd_addr_r1,
      I4 => complex_sample_cnt_inc_r2,
      I5 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      R => '0'
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      R => '0'
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      R => '0'
    );
\stable_pass_cnt[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^detect_pi_found_dqs\,
      I1 => pi_dqs_found_all_bank,
      O => detect_pi_found_dqs_reg_0
    );
\stg1_wr_rd_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[6]_i_2_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      O => \stg1_wr_rd_cnt[0]_i_1_n_0\
    );
\stg1_wr_rd_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D00000D0D0D0D0D"
    )
        port map (
      I0 => \^stg1_wr_done\,
      I1 => D(2),
      I2 => \wrcal_reads_reg[0]_0\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I5 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      O => \stg1_wr_rd_cnt[1]_i_1_n_0\
    );
\stg1_wr_rd_cnt[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_4_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => init_state_r(6),
      O => \^stg1_wr_done\
    );
\stg1_wr_rd_cnt[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FD57"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \stg1_wr_rd_cnt[2]_i_1_n_0\
    );
\stg1_wr_rd_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"008AAA8AAA8A008A"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg[3]_0\,
      I1 => D(2),
      I2 => \stg1_wr_rd_cnt[3]_i_2_n_0\,
      I3 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      I4 => \stg1_wr_rd_cnt[5]_i_2_n_0\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      O => \stg1_wr_rd_cnt[3]_i_1_n_0\
    );
\stg1_wr_rd_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00005D00"
    )
        port map (
      I0 => complex_row1_wr_done,
      I1 => complex_row0_rd_done,
      I2 => complex_row1_rd_done,
      I3 => complex_row0_wr_done,
      I4 => wr_victim_inc,
      O => \stg1_wr_rd_cnt[3]_i_2_n_0\
    );
\stg1_wr_rd_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8288AAAA"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg[3]_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \stg1_wr_rd_cnt[5]_i_2_n_0\,
      I4 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      O => \stg1_wr_rd_cnt[4]_i_1_n_0\
    );
\stg1_wr_rd_cnt[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => complex_sample_cnt_inc_i_2_n_0,
      I1 => complex_ocal_reset_rd_addr_i_2_n_0,
      I2 => rdlvl_last_byte_done,
      O => \stg1_wr_rd_cnt[4]_i_3_n_0\
    );
\stg1_wr_rd_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEBEEEEAAAAAAAA"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[6]_i_2_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I4 => \stg1_wr_rd_cnt[5]_i_2_n_0\,
      I5 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      O => \stg1_wr_rd_cnt[5]_i_1_n_0\
    );
\stg1_wr_rd_cnt[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      O => \stg1_wr_rd_cnt[5]_i_2_n_0\
    );
\stg1_wr_rd_cnt[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BEAA"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[6]_i_2_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I2 => \stg1_wr_rd_cnt[7]_i_2_n_0\,
      I3 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      O => \stg1_wr_rd_cnt[6]_i_1_n_0\
    );
\stg1_wr_rd_cnt[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000000D"
    )
        port map (
      I0 => \^stg1_wr_done\,
      I1 => D(2),
      I2 => \wrcal_reads_reg[0]_0\,
      I3 => \stg1_wr_rd_cnt[3]_i_2_n_0\,
      I4 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      O => \stg1_wr_rd_cnt[6]_i_2_n_0\
    );
\stg1_wr_rd_cnt[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A20"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I2 => \stg1_wr_rd_cnt[7]_i_2_n_0\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      O => \stg1_wr_rd_cnt[7]_i_1_n_0\
    );
\stg1_wr_rd_cnt[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      O => \stg1_wr_rd_cnt[7]_i_2_n_0\
    );
\stg1_wr_rd_cnt[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFFFFFFFFFF"
    )
        port map (
      I0 => D(2),
      I1 => \^q\(0),
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I4 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I5 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      O => \stg1_wr_rd_cnt[8]_i_1_n_0\
    );
\stg1_wr_rd_cnt[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA200000008"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I1 => \stg1_wr_rd_cnt[8]_i_6_n_0\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I4 => \stg1_wr_rd_cnt[8]_i_7_n_0\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      O => \stg1_wr_rd_cnt[8]_i_2_n_0\
    );
\stg1_wr_rd_cnt[8]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      O => \stg1_wr_rd_cnt[8]_i_3_n_0\
    );
\stg1_wr_rd_cnt[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFBFFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => init_complete_r_i_2_n_0,
      O => \stg1_wr_rd_cnt[8]_i_4_n_0\
    );
\stg1_wr_rd_cnt[8]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0D00"
    )
        port map (
      I0 => \^stg1_wr_done\,
      I1 => D(2),
      I2 => \wrcal_reads_reg[0]_0\,
      I3 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      O => \stg1_wr_rd_cnt[8]_i_5_n_0\
    );
\stg1_wr_rd_cnt[8]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      O => \stg1_wr_rd_cnt[8]_i_6_n_0\
    );
\stg1_wr_rd_cnt[8]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      O => \stg1_wr_rd_cnt[8]_i_7_n_0\
    );
\stg1_wr_rd_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[0]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[1]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[2]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[3]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[4]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[5]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[6]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[7]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[8]_i_2_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      R => '0'
    );
\wr_done_victim_rotate.complex_row0_wr_done_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => complex_row0_wr_done,
      I1 => \^rdlvl_stg1_done_r1\,
      I2 => \wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0\,
      I3 => complex_row0_wr_done0,
      O => \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0\
    );
\wr_done_victim_rotate.complex_row0_wr_done_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => wr_victim_inc_i_2_n_0,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0\
    );
\wr_done_victim_rotate.complex_row0_wr_done_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF50C0"
    )
        port map (
      I0 => \complex_row_cnt_ocal[3]_i_4_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\,
      I2 => wr_victim_inc,
      I3 => D(2),
      I4 => \wr_done_victim_rotate.complex_row0_wr_done_i_4_n_0\,
      O => complex_row0_wr_done0
    );
\wr_done_victim_rotate.complex_row0_wr_done_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \wrcal_reads_reg[0]_0\,
      I1 => complex_byte_rd_done,
      I2 => \^prbs_rdlvl_done_pulse_reg_0\,
      O => \wr_done_victim_rotate.complex_row0_wr_done_i_4_n_0\
    );
\wr_done_victim_rotate.complex_row0_wr_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0\,
      Q => complex_row0_wr_done,
      R => '0'
    );
\wr_done_victim_rotate.complex_row1_wr_done_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => complex_row1_wr_done,
      I1 => complex_row0_wr_done,
      I2 => \wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0\,
      I3 => complex_row0_wr_done0,
      O => \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0\
    );
\wr_done_victim_rotate.complex_row1_wr_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0\,
      Q => complex_row1_wr_done,
      R => '0'
    );
\wr_en_inferred__0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \wr_en_inferred__0_i_1_0\,
      I1 => \^calib_ctl_wren_reg_0\,
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \my_empty_reg[3]\
    );
\wr_en_inferred__0_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \wr_en_inferred__0_i_1__0_0\,
      I1 => \^calib_ctl_wren_reg_0\,
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \my_empty_reg[3]_0\
    );
\wr_en_inferred__0_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \wr_en_inferred__0_i_1__1_0\,
      I1 => \^calib_ctl_wren_reg_0\,
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \my_empty_reg[3]_1\
    );
\wr_ptr[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \wr_ptr_timing_reg[0]\,
      I1 => \^calib_ctl_wren_reg_0\,
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => E(0)
    );
\wr_ptr[2]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \wr_ptr_timing_reg[0]_1\,
      I1 => \^calib_ctl_wren_reg_0\,
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \my_empty_reg[5]\(0)
    );
\wr_ptr[2]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \wr_ptr_timing_reg[0]_2\,
      I1 => \^calib_ctl_wren_reg_0\,
      I2 => \wr_ptr_timing_reg[0]_0\,
      O => \my_empty_reg[5]_0\(0)
    );
wr_victim_inc_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => complex_row0_wr_done,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => wr_victim_inc_i_2_n_0,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I5 => \^one_rank.stg1_wr_done_reg_0\,
      O => wr_victim_inc0
    );
wr_victim_inc_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      O => wr_victim_inc_i_2_n_0
    );
wr_victim_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_victim_inc0,
      Q => wr_victim_inc,
      R => \complex_address_reg[9]_0\(0)
    );
wrcal_rd_wait_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[5]\,
      O => wrcal_rd_wait_i_1_n_0
    );
wrcal_rd_wait_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_rd_wait_i_1_n_0,
      Q => wrcal_rd_wait,
      R => rdlvl_stg1_start_reg_1
    );
\wrcal_reads[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => wrcal_reads,
      I1 => \wrcal_reads_reg_n_0_[0]\,
      O => \wrcal_reads[0]_i_1_n_0\
    );
\wrcal_reads[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F9"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[1]\,
      I1 => \wrcal_reads_reg_n_0_[0]\,
      I2 => wrcal_reads,
      O => \wrcal_reads[1]_i_1_n_0\
    );
\wrcal_reads[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFE1"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[0]\,
      I1 => \wrcal_reads_reg_n_0_[1]\,
      I2 => \wrcal_reads_reg_n_0_[2]\,
      I3 => wrcal_reads,
      O => \wrcal_reads[2]_i_1_n_0\
    );
\wrcal_reads[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFE01"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[1]\,
      I1 => \wrcal_reads_reg_n_0_[0]\,
      I2 => \wrcal_reads_reg_n_0_[2]\,
      I3 => \wrcal_reads_reg_n_0_[3]\,
      I4 => wrcal_reads,
      O => \wrcal_reads[3]_i_1_n_0\
    );
\wrcal_reads[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFE0001"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[2]\,
      I1 => \wrcal_reads_reg_n_0_[0]\,
      I2 => \wrcal_reads_reg_n_0_[1]\,
      I3 => \wrcal_reads_reg_n_0_[3]\,
      I4 => \wrcal_reads_reg_n_0_[4]\,
      I5 => wrcal_reads,
      O => \wrcal_reads[4]_i_1_n_0\
    );
\wrcal_reads[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFD2"
    )
        port map (
      I0 => \wrcal_reads[7]_i_6_n_0\,
      I1 => \wrcal_reads_reg_n_0_[4]\,
      I2 => \wrcal_reads_reg_n_0_[5]\,
      I3 => wrcal_reads,
      O => \wrcal_reads[5]_i_1_n_0\
    );
\wrcal_reads[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFD02"
    )
        port map (
      I0 => \wrcal_reads[7]_i_6_n_0\,
      I1 => \wrcal_reads_reg_n_0_[4]\,
      I2 => \wrcal_reads_reg_n_0_[5]\,
      I3 => \wrcal_reads_reg_n_0_[6]\,
      I4 => wrcal_reads,
      O => \wrcal_reads[6]_i_1_n_0\
    );
\wrcal_reads[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAEAAAAAAAAAA"
    )
        port map (
      I0 => \wrcal_reads_reg[0]_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \wrcal_reads[7]_i_4_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \wrcal_reads[7]_i_5_n_0\,
      O => wrcal_reads05_out
    );
\wrcal_reads[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFD"
    )
        port map (
      I0 => \wrcal_reads[7]_i_6_n_0\,
      I1 => \wrcal_reads_reg_n_0_[4]\,
      I2 => \wrcal_reads_reg_n_0_[5]\,
      I3 => \wrcal_reads_reg_n_0_[6]\,
      I4 => \wrcal_reads_reg_n_0_[7]\,
      I5 => wrcal_reads,
      O => \wrcal_reads[7]_i_2_n_0\
    );
\wrcal_reads[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEF0010"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[5]\,
      I1 => \wrcal_reads_reg_n_0_[4]\,
      I2 => \wrcal_reads[7]_i_6_n_0\,
      I3 => \wrcal_reads_reg_n_0_[6]\,
      I4 => \wrcal_reads_reg_n_0_[7]\,
      I5 => wrcal_reads,
      O => \wrcal_reads[7]_i_3_n_0\
    );
\wrcal_reads[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      O => \wrcal_reads[7]_i_4_n_0\
    );
\wrcal_reads[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      I1 => \init_state_r_reg_n_0_[0]\,
      O => \wrcal_reads[7]_i_5_n_0\
    );
\wrcal_reads[7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[2]\,
      I1 => \wrcal_reads_reg_n_0_[0]\,
      I2 => \wrcal_reads_reg_n_0_[1]\,
      I3 => \wrcal_reads_reg_n_0_[3]\,
      O => \wrcal_reads[7]_i_6_n_0\
    );
\wrcal_reads[7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \wrcal_reads[7]_i_8_n_0\,
      I1 => \wrcal_reads[7]_i_6_n_0\,
      I2 => \wrcal_reads_reg_n_0_[4]\,
      I3 => \wrcal_reads_reg_n_0_[5]\,
      I4 => \wrcal_reads_reg_n_0_[6]\,
      I5 => \wrcal_reads_reg_n_0_[7]\,
      O => wrcal_reads
    );
\wrcal_reads[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \wrcal_reads[7]_i_8_n_0\
    );
\wrcal_reads_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[0]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[0]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[1]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[1]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[2]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[2]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[3]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[3]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[4]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[4]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[5]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[5]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[6]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[6]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[7]_i_3_n_0\,
      Q => \wrcal_reads_reg_n_0_[7]\,
      R => wrcal_reads05_out
    );
\wrcal_start_dly_r_reg[4]_srl5\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '0',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => wrcal_start_pre,
      Q => \wrcal_start_dly_r_reg[4]_srl5_n_0\
    );
\wrcal_start_dly_r_reg[4]_srl5_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000200000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \wrcal_start_dly_r_reg[4]_srl5_i_2_n_0\,
      I4 => \^q\(0),
      I5 => \init_state_r_reg_n_0_[0]\,
      O => wrcal_start_pre
    );
\wrcal_start_dly_r_reg[4]_srl5_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[5]\,
      O => \wrcal_start_dly_r_reg[4]_srl5_i_2_n_0\
    );
\wrcal_start_dly_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wrcal_start_dly_r_reg[4]_srl5_n_0\,
      Q => wrcal_start_dly_r(5),
      R => '0'
    );
wrcal_start_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000E"
    )
        port map (
      I0 => \^wrcal_start_reg_0\,
      I1 => wrcal_start_dly_r(5),
      I2 => wrlvl_byte_redo,
      I3 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      O => wrcal_start_i_1_n_0
    );
wrcal_start_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_start_i_1_n_0,
      Q => \^wrcal_start_reg_0\,
      R => '0'
    );
\wrcal_wr_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wrcal_wr_cnt_reg(0),
      O => \wrcal_wr_cnt[0]_i_1_n_0\
    );
\wrcal_wr_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wrcal_wr_cnt_reg(1),
      I1 => wrcal_wr_cnt_reg(0),
      O => \wrcal_wr_cnt[1]_i_1_n_0\
    );
\wrcal_wr_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wrcal_wr_cnt_reg(2),
      I1 => wrcal_wr_cnt_reg(0),
      I2 => wrcal_wr_cnt_reg(1),
      O => \wrcal_wr_cnt[2]_i_1_n_0\
    );
\wrcal_wr_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAAAB"
    )
        port map (
      I0 => \wrcal_wr_cnt[3]_i_4_n_0\,
      I1 => wrcal_wr_cnt_reg(0),
      I2 => wrcal_wr_cnt_reg(1),
      I3 => wrcal_wr_cnt_reg(3),
      I4 => wrcal_wr_cnt_reg(2),
      I5 => \wrcal_reads_reg[0]_0\,
      O => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrcal_wr_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => p_0_in1_in
    );
\wrcal_wr_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wrcal_wr_cnt_reg(3),
      I1 => wrcal_wr_cnt_reg(1),
      I2 => wrcal_wr_cnt_reg(0),
      I3 => wrcal_wr_cnt_reg(2),
      O => wrcal_wr_cnt0(3)
    );
\wrcal_wr_cnt[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => init_complete_r_i_2_n_0,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \wrcal_wr_cnt[3]_i_4_n_0\
    );
\wrcal_wr_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_0_in1_in,
      D => \wrcal_wr_cnt[0]_i_1_n_0\,
      Q => wrcal_wr_cnt_reg(0),
      R => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrcal_wr_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_0_in1_in,
      D => \wrcal_wr_cnt[1]_i_1_n_0\,
      Q => wrcal_wr_cnt_reg(1),
      R => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrcal_wr_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => p_0_in1_in,
      D => \wrcal_wr_cnt[2]_i_1_n_0\,
      Q => wrcal_wr_cnt_reg(2),
      S => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrcal_wr_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_0_in1_in,
      D => wrcal_wr_cnt0(3),
      Q => wrcal_wr_cnt_reg(3),
      R => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^first_wrcal_pat_r\,
      I1 => D(2),
      O => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1_n_0\
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^first_rdlvl_pat_r\,
      I1 => D(2),
      O => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[29]_i_1_n_0\
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[46]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^first_wrcal_pat_r\,
      I1 => D(2),
      O => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[46]_i_1_n_0\
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]_0\(0),
      D => D(1),
      Q => phy_wrdata(109),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]_0\(0),
      D => D(2),
      Q => phy_wrdata(111),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]_0\(0),
      D => D(3),
      Q => phy_wrdata(125),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]_0\(0),
      D => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1_n_0\,
      Q => phy_wrdata(126),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]_0\(0),
      D => D(4),
      Q => phy_wrdata(127),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]_0\(0),
      D => D(0),
      Q => phy_wrdata(13),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]_0\(0),
      D => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[29]_i_1_n_0\,
      Q => phy_wrdata(29),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]_0\(0),
      D => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[46]_i_1_n_0\,
      Q => phy_wrdata(46),
      R => '0'
    );
wrlvl_final_if_rst_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011101010"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => \back_to_back_reads_4_1.num_reads_reg[1]_0\,
      I2 => \^wrlvl_final_if_rst\,
      I3 => wrlvl_final_if_rst_i_2_n_0,
      I4 => \^q\(0),
      I5 => \num_refresh[3]_i_7_n_0\,
      O => wrlvl_final_if_rst_i_1_n_0
    );
wrlvl_final_if_rst_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => wrlvl_final_if_rst_i_2_n_0
    );
wrlvl_final_if_rst_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_final_if_rst_i_1_n_0,
      Q => \^wrlvl_final_if_rst\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_phy_rdlvl is
  port (
    \rd_mux_sel_r_reg[0]_0\ : out STD_LOGIC;
    new_cnt_cpt_r_reg_0 : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    idelay_ce_int : out STD_LOGIC;
    idelay_inc_int : out STD_LOGIC;
    rdlvl_prech_req : out STD_LOGIC;
    pi_fine_dly_dec_done : out STD_LOGIC;
    pi_cnt_dec_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 4 downto 0 );
    rdlvl_stg1_rank_done : out STD_LOGIC;
    rdlvl_last_byte_done : out STD_LOGIC;
    rdlvl_pi_incdec : out STD_LOGIC;
    \calib_sel_reg[1]\ : out STD_LOGIC;
    \calib_sel_reg[1]_0\ : out STD_LOGIC;
    \calib_sel_reg[1]_1\ : out STD_LOGIC;
    tempmon_pi_f_en_r_reg : out STD_LOGIC;
    tempmon_pi_f_inc_r_reg : out STD_LOGIC;
    pi_stg2_load_reg_0 : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__14\ : out STD_LOGIC;
    pi_fine_dly_dec_done_reg_0 : out STD_LOGIC;
    prbs_rdlvl_done_pulse0 : out STD_LOGIC;
    \cal1_cnt_cpt_r_reg[0]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    rdlvl_stg1_done_int_reg_0 : out STD_LOGIC;
    rdlvl_stg1_done_int_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    rdlvl_last_byte_done_int_reg_0 : out STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__13\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__14_0\ : out STD_LOGIC;
    COUNTERLOADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_stg2_reg_l_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CLK : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    mpr_rdlvl_start_r_reg_0 : in STD_LOGIC;
    rdlvl_stg1_start_r_reg_0 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    dqs_po_dec_done_r1_reg_0 : in STD_LOGIC;
    \FSM_onehot_cal1_state_r_reg[7]_0\ : in STD_LOGIC;
    \samp_edge_cnt1_r_reg[0]_0\ : in STD_LOGIC;
    found_second_edge_r_reg_0 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC;
    tempmon_pi_f_en_r : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC;
    calib_zero_inputs : in STD_LOGIC;
    tempmon_pi_f_inc_r : in STD_LOGIC;
    \done_cnt_reg[2]_0\ : in STD_LOGIC;
    reset_if_reg : in STD_LOGIC;
    stg1_wr_done : in STD_LOGIC;
    \init_state_r[6]_i_19\ : in STD_LOGIC;
    rdlvl_stg1_done_r1 : in STD_LOGIC;
    \cnt_idel_dec_cpt_r_reg[0]_0\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][0][0]_0\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][0][0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    prech_done : in STD_LOGIC;
    \cnt_idel_dec_cpt_r_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    store_sr_req_r_reg_0 : in STD_LOGIC;
    pi_dqs_found_done : in STD_LOGIC;
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]\ : in STD_LOGIC;
    \init_state_r[3]_i_13\ : in STD_LOGIC;
    first_rdlvl_pat_r : in STD_LOGIC;
    first_wrcal_pat_r : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]_1\ : in STD_LOGIC;
    RSTB : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ : in STD_LOGIC;
    reset_if_r9 : in STD_LOGIC;
    reset_if : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][1][4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \tap_cnt_cpt_r_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_shift_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_phy_rdlvl : entity is "mig_7series_v4_2_ddr_phy_rdlvl";
end mig_7series_0_mig_7series_v4_2_ddr_phy_rdlvl;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_phy_rdlvl is
  signal \^d\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \FSM_onehot_cal1_state_r[10]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[11]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[13]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[14]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[14]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[15]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[15]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[15]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[16]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[16]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[16]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[20]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[21]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[21]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[21]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[22]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[22]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[29]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[34]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[6]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[6]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[9]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[12]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[16]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[22]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[29]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal cal1_cnt_cpt_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \cal1_cnt_cpt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal cal1_dlyce_cpt_r : STD_LOGIC;
  signal cal1_dlyce_cpt_r_reg_n_0 : STD_LOGIC;
  signal cal1_dlyinc_cpt_r : STD_LOGIC;
  signal cal1_dlyinc_cpt_r_reg_n_0 : STD_LOGIC;
  signal cal1_dq_idel_ce : STD_LOGIC;
  signal cal1_dq_idel_inc : STD_LOGIC;
  signal cal1_prech_req_r : STD_LOGIC;
  signal \cal1_prech_req_r__0\ : STD_LOGIC;
  signal \cal1_state_r1[0]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[0]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[0]_i_3_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[1]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[1]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[2]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[2]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[3]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[3]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[3]_i_3_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[4]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[5]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[0]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[1]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[2]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[3]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[4]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[5]\ : STD_LOGIC;
  signal cal1_wait_cnt_en_r : STD_LOGIC;
  signal cal1_wait_cnt_en_r0 : STD_LOGIC;
  signal cal1_wait_cnt_en_r_i_2_n_0 : STD_LOGIC;
  signal \cal1_wait_cnt_r[4]_i_1_n_0\ : STD_LOGIC;
  signal cal1_wait_cnt_r_reg : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal cal1_wait_r : STD_LOGIC;
  signal cal1_wait_r_i_1_n_0 : STD_LOGIC;
  signal cnt_idel_dec_cpt_r : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal cnt_idel_dec_cpt_r1 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \cnt_idel_dec_cpt_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_11_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_12_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_13_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_14_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_15_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_6_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_7_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_8_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_9_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_10_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_11_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_12_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_13_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_14_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_6_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_7_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_9_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_6_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_1\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_2\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_3\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_4\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_5\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_6\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_2_n_1\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_2_n_2\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_2_n_3\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_2_n_1\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_2_n_3\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_8_n_3\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_8_n_6\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_8_n_7\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[5]\ : STD_LOGIC;
  signal cnt_shift_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal detect_edge_done_r : STD_LOGIC;
  signal detect_edge_done_r_i_1_n_0 : STD_LOGIC;
  signal detect_edge_done_r_i_2_n_0 : STD_LOGIC;
  signal done_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal done_cnt1 : STD_LOGIC;
  signal \done_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \done_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \done_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \done_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal dqs_po_dec_done_r1 : STD_LOGIC;
  signal dqs_po_dec_done_r2 : STD_LOGIC;
  signal fine_dly_dec_done_r1 : STD_LOGIC;
  signal fine_dly_dec_done_r1_i_1_n_0 : STD_LOGIC;
  signal fine_dly_dec_done_r1_i_2_n_0 : STD_LOGIC;
  signal fine_dly_dec_done_r1_i_3_n_0 : STD_LOGIC;
  signal fine_dly_dec_done_r2 : STD_LOGIC;
  signal \first_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \first_edge_taps_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \first_edge_taps_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[5]\ : STD_LOGIC;
  signal found_edge_r_i_1_n_0 : STD_LOGIC;
  signal found_edge_r_i_2_n_0 : STD_LOGIC;
  signal found_edge_r_reg_n_0 : STD_LOGIC;
  signal found_first_edge_r_i_1_n_0 : STD_LOGIC;
  signal found_first_edge_r_reg_n_0 : STD_LOGIC;
  signal found_second_edge_r_i_1_n_0 : STD_LOGIC;
  signal found_second_edge_r_reg_n_0 : STD_LOGIC;
  signal found_stable_eye_last_r : STD_LOGIC;
  signal found_stable_eye_last_r_i_1_n_0 : STD_LOGIC;
  signal found_stable_eye_r_i_1_n_0 : STD_LOGIC;
  signal found_stable_eye_r_i_2_n_0 : STD_LOGIC;
  signal found_stable_eye_r_reg_n_0 : STD_LOGIC;
  signal \gen_byte_sel_div2.byte_sel_cnt[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_146\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_162\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_130\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_138\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_178\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_154\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_170\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_186\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_98\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_74\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_82\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_106\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_114\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_66\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_90\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_122\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_147\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_163\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_131\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_139\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_179\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_155\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_171\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_187\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_99\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_75\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_83\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_107\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_115\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_67\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_91\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_123\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_148\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_164\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_132\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_140\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_180\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_156\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_172\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_188\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_100\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_76\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_84\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_108\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_116\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_68\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_92\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_124\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_149\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_165\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_133\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_141\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_181\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_157\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_173\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_189\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_101\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_77\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_85\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_109\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_117\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_69\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_93\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_125\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_150\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_166\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_134\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_142\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_182\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_158\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_174\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_190\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_102\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_78\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_86\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_110\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_118\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_70\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_94\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_126\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_151\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_167\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_135\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_143\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_183\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_159\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_175\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_191\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_103\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_79\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_87\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_111\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_119\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_71\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_95\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_127\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_152\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_168\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_136\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_144\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_184\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_160\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_176\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_192\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_104\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_80\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_88\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_112\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_120\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_72\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_96\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_128\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_153\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_169\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_137\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_145\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_185\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_161\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_177\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_193\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_105\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_81\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_89\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_113\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_121\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_73\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_97\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_129\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_50\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_26\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_34\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_10\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_2\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_42\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_18\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_58\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_51\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_27\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_35\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_11\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_3\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_43\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_19\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_59\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_52\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_28\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_36\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_12\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_4\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_44\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_20\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_60\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_53\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_29\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_37\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_13\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_5\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_45\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_21\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_61\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_54\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_30\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_38\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_14\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_6\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_46\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_22\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_62\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_55\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_31\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_39\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_15\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_7\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_47\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_23\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_63\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_56\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_32\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_40\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_16\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_8\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_48\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_24\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_64\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_57\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_33\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_41\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_17\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_9\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_49\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_25\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_65\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_edge_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_edge_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_edge_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_edge_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_edge_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_edge_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_edge_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_edge_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0\ : STD_LOGIC;
  signal idel_adj_inc_i_1_n_0 : STD_LOGIC;
  signal idel_adj_inc_reg_n_0 : STD_LOGIC;
  signal idel_dec_cnt : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \idel_dec_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_4_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_5_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \idel_dec_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \idel_dec_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \idel_dec_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \idel_dec_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal idel_mpr_pat_detect_r : STD_LOGIC;
  signal idel_pat0_data_match_r0 : STD_LOGIC;
  signal idel_pat0_match_fall0_and_r : STD_LOGIC;
  signal idel_pat0_match_fall1_and_r : STD_LOGIC;
  signal idel_pat0_match_fall2_and_r : STD_LOGIC;
  signal idel_pat0_match_fall3_and_r : STD_LOGIC;
  signal idel_pat0_match_rise0_and_r : STD_LOGIC;
  signal idel_pat0_match_rise1_and_r : STD_LOGIC;
  signal idel_pat0_match_rise2_and_r : STD_LOGIC;
  signal idel_pat0_match_rise3_and_r : STD_LOGIC;
  signal idel_pat0_match_rise3_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal idel_pat1_data_match_r0 : STD_LOGIC;
  signal idel_pat1_match_fall0_and_r : STD_LOGIC;
  signal idel_pat1_match_fall1_and_r : STD_LOGIC;
  signal idel_pat1_match_fall2_and_r : STD_LOGIC;
  signal idel_pat1_match_fall3_and_r : STD_LOGIC;
  signal idel_pat1_match_rise0_and_r : STD_LOGIC;
  signal idel_pat1_match_rise1_and_r : STD_LOGIC;
  signal idel_pat1_match_rise1_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal idel_pat1_match_rise2_and_r : STD_LOGIC;
  signal idel_pat1_match_rise3_and_r : STD_LOGIC;
  signal idel_pat_detect_valid_r_i_1_n_0 : STD_LOGIC;
  signal idel_pat_detect_valid_r_reg_n_0 : STD_LOGIC;
  signal \^idelay_ce_int\ : STD_LOGIC;
  signal \^idelay_inc_int\ : STD_LOGIC;
  signal idelay_tap_cnt_r : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \idelay_tap_cnt_r[0][0][4]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][1][0]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][1][1]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][1][2]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][1][3]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][1][3]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][1][4]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][1][4]_i_4_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][4]\ : STD_LOGIC;
  signal idelay_tap_cnt_slice_r : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal idelay_tap_limit_r_i_1_n_0 : STD_LOGIC;
  signal idelay_tap_limit_r_i_2_n_0 : STD_LOGIC;
  signal idelay_tap_limit_r_reg_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r : STD_LOGIC;
  signal \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0\ : STD_LOGIC;
  signal \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_5_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_6_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_5_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_6_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_7_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal mpr_dec_cpt_r_i_1_n_0 : STD_LOGIC;
  signal mpr_dec_cpt_r_reg_n_0 : STD_LOGIC;
  signal mpr_rd_fall0_prev_r : STD_LOGIC;
  signal mpr_rd_fall1_prev_r : STD_LOGIC;
  signal mpr_rd_fall2_prev_r : STD_LOGIC;
  signal mpr_rd_fall3_prev_r : STD_LOGIC;
  signal mpr_rd_rise0_prev_r : STD_LOGIC;
  signal mpr_rd_rise0_prev_r0 : STD_LOGIC;
  signal mpr_rd_rise1_prev_r : STD_LOGIC;
  signal mpr_rd_rise2_prev_r : STD_LOGIC;
  signal mpr_rd_rise3_prev_r : STD_LOGIC;
  signal mpr_rdlvl_start_r : STD_LOGIC;
  signal new_cnt_cpt_r : STD_LOGIC;
  signal new_cnt_cpt_r_i_2_n_0 : STD_LOGIC;
  signal \^new_cnt_cpt_r_reg_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_0_in100_in : STD_LOGIC;
  signal p_0_in103_in : STD_LOGIC;
  signal p_0_in10_in : STD_LOGIC;
  signal p_0_in135_in : STD_LOGIC;
  signal p_0_in13_in : STD_LOGIC;
  signal p_0_in157_in : STD_LOGIC;
  signal p_0_in16_in : STD_LOGIC;
  signal p_0_in182_in : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal p_0_in207_in : STD_LOGIC;
  signal p_0_in232_in : STD_LOGIC;
  signal p_0_in257_in : STD_LOGIC;
  signal p_0_in282_in : STD_LOGIC;
  signal p_0_in307_in : STD_LOGIC;
  signal p_0_in332_in : STD_LOGIC;
  signal p_0_in357_in : STD_LOGIC;
  signal p_0_in382_in : STD_LOGIC;
  signal p_0_in407_in : STD_LOGIC;
  signal p_0_in432_in : STD_LOGIC;
  signal p_0_in457_in : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_0_in541_in : STD_LOGIC;
  signal p_0_in549_in : STD_LOGIC;
  signal p_0_in7_in : STD_LOGIC;
  signal p_0_in88_in : STD_LOGIC;
  signal p_0_in91_in : STD_LOGIC;
  signal p_0_in94_in : STD_LOGIC;
  signal p_0_in97_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__6\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__7\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__8\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__9\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal p_12_in : STD_LOGIC;
  signal p_139_out : STD_LOGIC;
  signal p_13_in : STD_LOGIC;
  signal p_14_in : STD_LOGIC;
  signal p_165_out : STD_LOGIC;
  signal p_190_out : STD_LOGIC;
  signal p_1_in11_in : STD_LOGIC;
  signal p_1_in138_in : STD_LOGIC;
  signal p_1_in14_in : STD_LOGIC;
  signal p_1_in164_in : STD_LOGIC;
  signal p_1_in17_in : STD_LOGIC;
  signal p_1_in189_in : STD_LOGIC;
  signal p_1_in214_in : STD_LOGIC;
  signal p_1_in239_in : STD_LOGIC;
  signal p_1_in264_in : STD_LOGIC;
  signal p_1_in26_in : STD_LOGIC;
  signal p_1_in289_in : STD_LOGIC;
  signal p_1_in2_in : STD_LOGIC;
  signal p_1_in314_in : STD_LOGIC;
  signal p_1_in339_in : STD_LOGIC;
  signal p_1_in364_in : STD_LOGIC;
  signal p_1_in389_in : STD_LOGIC;
  signal p_1_in414_in : STD_LOGIC;
  signal p_1_in439_in : STD_LOGIC;
  signal p_1_in464_in : STD_LOGIC;
  signal p_1_in5_in : STD_LOGIC;
  signal p_1_in8_in : STD_LOGIC;
  signal p_215_out : STD_LOGIC;
  signal p_240_out : STD_LOGIC;
  signal p_265_out : STD_LOGIC;
  signal p_290_out : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_2_in158_in : STD_LOGIC;
  signal p_2_in183_in : STD_LOGIC;
  signal p_2_in208_in : STD_LOGIC;
  signal p_2_in233_in : STD_LOGIC;
  signal p_2_in258_in : STD_LOGIC;
  signal p_2_in283_in : STD_LOGIC;
  signal p_2_in308_in : STD_LOGIC;
  signal p_2_in333_in : STD_LOGIC;
  signal p_2_in358_in : STD_LOGIC;
  signal p_2_in383_in : STD_LOGIC;
  signal p_2_in408_in : STD_LOGIC;
  signal p_2_in433_in : STD_LOGIC;
  signal p_2_in458_in : STD_LOGIC;
  signal p_315_out : STD_LOGIC;
  signal p_340_out : STD_LOGIC;
  signal p_34_in : STD_LOGIC;
  signal p_365_out : STD_LOGIC;
  signal p_390_out : STD_LOGIC;
  signal p_3_in136_in : STD_LOGIC;
  signal p_3_in159_in : STD_LOGIC;
  signal p_3_in184_in : STD_LOGIC;
  signal p_3_in209_in : STD_LOGIC;
  signal p_3_in234_in : STD_LOGIC;
  signal p_3_in259_in : STD_LOGIC;
  signal p_3_in284_in : STD_LOGIC;
  signal p_3_in309_in : STD_LOGIC;
  signal p_3_in334_in : STD_LOGIC;
  signal p_3_in359_in : STD_LOGIC;
  signal p_3_in384_in : STD_LOGIC;
  signal p_3_in409_in : STD_LOGIC;
  signal p_3_in434_in : STD_LOGIC;
  signal p_3_in459_in : STD_LOGIC;
  signal p_415_out : STD_LOGIC;
  signal p_440_out : STD_LOGIC;
  signal p_465_out : STD_LOGIC;
  signal p_490_out : STD_LOGIC;
  signal p_4_in160_in : STD_LOGIC;
  signal p_4_in185_in : STD_LOGIC;
  signal p_4_in210_in : STD_LOGIC;
  signal p_4_in235_in : STD_LOGIC;
  signal p_4_in260_in : STD_LOGIC;
  signal p_4_in285_in : STD_LOGIC;
  signal p_4_in310_in : STD_LOGIC;
  signal p_4_in335_in : STD_LOGIC;
  signal p_4_in360_in : STD_LOGIC;
  signal p_4_in385_in : STD_LOGIC;
  signal p_4_in410_in : STD_LOGIC;
  signal p_4_in435_in : STD_LOGIC;
  signal p_4_in460_in : STD_LOGIC;
  signal p_515_out : STD_LOGIC;
  signal p_5_in161_in : STD_LOGIC;
  signal p_5_in186_in : STD_LOGIC;
  signal p_5_in211_in : STD_LOGIC;
  signal p_5_in236_in : STD_LOGIC;
  signal p_5_in261_in : STD_LOGIC;
  signal p_5_in286_in : STD_LOGIC;
  signal p_5_in311_in : STD_LOGIC;
  signal p_5_in336_in : STD_LOGIC;
  signal p_5_in361_in : STD_LOGIC;
  signal p_5_in386_in : STD_LOGIC;
  signal p_5_in411_in : STD_LOGIC;
  signal p_5_in436_in : STD_LOGIC;
  signal p_5_in461_in : STD_LOGIC;
  signal p_6_in137_in : STD_LOGIC;
  signal p_6_in162_in : STD_LOGIC;
  signal p_6_in187_in : STD_LOGIC;
  signal p_6_in212_in : STD_LOGIC;
  signal p_6_in237_in : STD_LOGIC;
  signal p_6_in262_in : STD_LOGIC;
  signal p_6_in287_in : STD_LOGIC;
  signal p_6_in312_in : STD_LOGIC;
  signal p_6_in337_in : STD_LOGIC;
  signal p_6_in362_in : STD_LOGIC;
  signal p_6_in387_in : STD_LOGIC;
  signal p_6_in412_in : STD_LOGIC;
  signal p_6_in437_in : STD_LOGIC;
  signal p_6_in462_in : STD_LOGIC;
  signal p_7_in : STD_LOGIC;
  signal p_7_in163_in : STD_LOGIC;
  signal p_7_in188_in : STD_LOGIC;
  signal p_7_in213_in : STD_LOGIC;
  signal p_7_in238_in : STD_LOGIC;
  signal p_7_in263_in : STD_LOGIC;
  signal p_7_in288_in : STD_LOGIC;
  signal p_7_in313_in : STD_LOGIC;
  signal p_7_in338_in : STD_LOGIC;
  signal p_7_in363_in : STD_LOGIC;
  signal p_7_in388_in : STD_LOGIC;
  signal p_7_in413_in : STD_LOGIC;
  signal p_7_in438_in : STD_LOGIC;
  signal p_7_in463_in : STD_LOGIC;
  signal p_8_in : STD_LOGIC;
  signal p_9_in : STD_LOGIC;
  signal pat0_data_match_r0 : STD_LOGIC;
  signal pat0_match_fall0_and_r : STD_LOGIC;
  signal pat0_match_fall0_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_fall1_and_r : STD_LOGIC;
  signal pat0_match_fall1_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_fall2_and_r : STD_LOGIC;
  signal pat0_match_fall2_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_fall3_and_r : STD_LOGIC;
  signal pat0_match_fall3_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_rise0_and_r : STD_LOGIC;
  signal pat0_match_rise0_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_rise1_and_r : STD_LOGIC;
  signal pat0_match_rise1_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_rise2_and_r : STD_LOGIC;
  signal pat0_match_rise2_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat0_match_rise3_and_r : STD_LOGIC;
  signal pat0_match_rise3_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pat1_data_match_r0 : STD_LOGIC;
  signal pat1_match_fall0_and_r : STD_LOGIC;
  signal pat1_match_fall1_and_r : STD_LOGIC;
  signal pat1_match_fall2_and_r : STD_LOGIC;
  signal pat1_match_fall3_and_r : STD_LOGIC;
  signal pat1_match_rise0_and_r : STD_LOGIC;
  signal pat1_match_rise1_and_r : STD_LOGIC;
  signal pat1_match_rise2_and_r : STD_LOGIC;
  signal pat1_match_rise3_and_r : STD_LOGIC;
  signal pb_cnt_eye_size_r : STD_LOGIC;
  signal pb_detect_edge : STD_LOGIC;
  signal pb_detect_edge_done_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pb_found_stable_eye_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pi_cnt_dec_i_1_n_0 : STD_LOGIC;
  signal pi_cnt_dec_i_2_n_0 : STD_LOGIC;
  signal \^pi_cnt_dec_reg_0\ : STD_LOGIC;
  signal pi_counter_load_en : STD_LOGIC;
  signal pi_counter_load_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal pi_en_stg2_f_timing : STD_LOGIC;
  signal pi_en_stg2_f_timing_i_1_n_0 : STD_LOGIC;
  signal \^pi_fine_dly_dec_done\ : STD_LOGIC;
  signal pi_rdval_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \pi_rdval_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[2]_i_2_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_4_n_0\ : STD_LOGIC;
  signal pi_stg2_f_incdec_timing : STD_LOGIC;
  signal pi_stg2_f_incdec_timing_i_1_n_0 : STD_LOGIC;
  signal pi_stg2_load_timing : STD_LOGIC;
  signal pi_stg2_load_timing_i_1_n_0 : STD_LOGIC;
  signal pi_stg2_reg_l_timing : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \pi_stg2_reg_l_timing[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[1]_i_1_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[2]_i_1_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[3]_i_1_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[4]_i_1_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[5]_i_1_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[5]_i_2_n_0\ : STD_LOGIC;
  signal \^rd_mux_sel_r_reg[0]_0\ : STD_LOGIC;
  signal rdlvl_dqs_tap_cnt_r : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5]\ : STD_LOGIC;
  signal \^rdlvl_last_byte_done\ : STD_LOGIC;
  signal rdlvl_last_byte_done_int_i_1_n_0 : STD_LOGIC;
  signal \^rdlvl_pi_incdec\ : STD_LOGIC;
  signal rdlvl_pi_incdec_i_1_n_0 : STD_LOGIC;
  signal rdlvl_pi_incdec_i_2_n_0 : STD_LOGIC;
  signal rdlvl_pi_incdec_i_3_n_0 : STD_LOGIC;
  signal rdlvl_pi_incdec_i_4_n_0 : STD_LOGIC;
  signal rdlvl_pi_incdec_i_5_n_0 : STD_LOGIC;
  signal rdlvl_pi_stg2_f_en : STD_LOGIC;
  signal rdlvl_pi_stg2_f_incdec : STD_LOGIC;
  signal rdlvl_rank_done_r : STD_LOGIC;
  signal rdlvl_rank_done_r_i_1_n_0 : STD_LOGIC;
  signal rdlvl_stg1_done_int : STD_LOGIC;
  signal rdlvl_stg1_done_int_i_1_n_0 : STD_LOGIC;
  signal \^rdlvl_stg1_rank_done\ : STD_LOGIC;
  signal rdlvl_stg1_start_r : STD_LOGIC;
  signal \regl_dqs_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \regl_dqs_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal regl_dqs_cnt_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \regl_dqs_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \regl_dqs_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal regl_rank_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \regl_rank_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \regl_rank_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \regl_rank_cnt[1]_i_2_n_0\ : STD_LOGIC;
  signal right_edge_taps_r : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \right_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \right_edge_taps_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \right_edge_taps_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \right_edge_taps_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \right_edge_taps_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \right_edge_taps_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \right_edge_taps_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \rnk_cnt_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rnk_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal samp_cnt_done_r_i_1_n_0 : STD_LOGIC;
  signal samp_cnt_done_r_i_2_n_0 : STD_LOGIC;
  signal samp_cnt_done_r_i_3_n_0 : STD_LOGIC;
  signal samp_cnt_done_r_i_4_n_0 : STD_LOGIC;
  signal samp_cnt_done_r_reg_n_0 : STD_LOGIC;
  signal \^samp_edge_cnt0_en_r\ : STD_LOGIC;
  signal \samp_edge_cnt0_r[0]_i_3_n_0\ : STD_LOGIC;
  signal samp_edge_cnt0_r_reg : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal samp_edge_cnt1_en_r : STD_LOGIC;
  signal samp_edge_cnt1_en_r0 : STD_LOGIC;
  signal samp_edge_cnt1_en_r_i_2_n_0 : STD_LOGIC;
  signal samp_edge_cnt1_en_r_i_3_n_0 : STD_LOGIC;
  signal \samp_edge_cnt1_r[0]_i_2_n_0\ : STD_LOGIC;
  signal samp_edge_cnt1_r_reg : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_7\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \second_edge_taps_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[5]\ : STD_LOGIC;
  signal sr_valid_r1 : STD_LOGIC;
  signal sr_valid_r2 : STD_LOGIC;
  signal sr_valid_r_i_1_n_0 : STD_LOGIC;
  signal sr_valid_r_reg_n_0 : STD_LOGIC;
  signal stable_idel_cnt : STD_LOGIC;
  signal stable_idel_cnt0 : STD_LOGIC;
  signal store_sr_r0 : STD_LOGIC;
  signal store_sr_r_i_1_n_0 : STD_LOGIC;
  signal store_sr_r_reg_n_0 : STD_LOGIC;
  signal store_sr_req_pulsed_r : STD_LOGIC;
  signal \store_sr_req_pulsed_r__0\ : STD_LOGIC;
  signal store_sr_req_r : STD_LOGIC;
  signal store_sr_req_r_reg_n_0 : STD_LOGIC;
  signal tap_cnt_cpt_r : STD_LOGIC;
  signal tap_cnt_cpt_r0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \tap_cnt_cpt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \tap_cnt_cpt_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \tap_cnt_cpt_r[5]_i_5_n_0\ : STD_LOGIC;
  signal \tap_cnt_cpt_r[5]_i_6_n_0\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[5]\ : STD_LOGIC;
  signal tap_limit_cpt_r : STD_LOGIC;
  signal tap_limit_cpt_r_i_1_n_0 : STD_LOGIC;
  signal tap_limit_cpt_r_i_2_n_0 : STD_LOGIC;
  signal wait_cnt_r0 : STD_LOGIC;
  signal \wait_cnt_r0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wait_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal wait_cnt_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[2]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[2]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[10]_i_1\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[11]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[13]_i_1\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[14]_i_1\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[15]_i_1\ : label is "soft_lutpair143";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[15]_i_2\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[16]_i_2\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[16]_i_3\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[21]_i_2\ : label is "soft_lutpair143";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[22]_i_2\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[29]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[5]_i_1\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[6]_i_2\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[6]_i_3\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[6]_i_4\ : label is "soft_lutpair136";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[7]_i_1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[8]_i_1\ : label is "soft_lutpair150";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[9]_i_1\ : label is "soft_lutpair60";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[0]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[10]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[11]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[12]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[13]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[14]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[15]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[16]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[1]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[20]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[21]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[22]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[29]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[2]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[31]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[32]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[34]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[3]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[4]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[5]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[6]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[7]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[8]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[9]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000";
  attribute SOFT_HLUTNM of cal1_dlyce_cpt_r_i_1 : label is "soft_lutpair153";
  attribute SOFT_HLUTNM of cal1_dlyinc_cpt_r_i_1 : label is "soft_lutpair153";
  attribute SOFT_HLUTNM of \cal1_state_r1[0]_i_2\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \cal1_state_r1[1]_i_2\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \cal1_state_r1[3]_i_3\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \cal1_state_r1[5]_i_1\ : label is "soft_lutpair141";
  attribute SOFT_HLUTNM of \cal1_wait_cnt_r[1]_i_1\ : label is "soft_lutpair151";
  attribute SOFT_HLUTNM of \cal1_wait_cnt_r[2]_i_1\ : label is "soft_lutpair151";
  attribute SOFT_HLUTNM of \cal1_wait_cnt_r[3]_i_1\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \cal1_wait_cnt_r[4]_i_2\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[0]_i_3\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[1]_i_4\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[3]_i_2\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[3]_i_5\ : label is "soft_lutpair146";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[4]_i_10\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[4]_i_3\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[5]_i_6\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \cnt_shift_r[2]_i_1\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \cnt_shift_r[3]_i_2\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \done_cnt[1]_i_1\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \done_cnt[3]_i_1\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of fine_dly_dec_done_r1_i_3 : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \first_edge_taps_r[5]_i_3\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[0]_i_1\ : label is "soft_lutpair145";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1\ : label is "soft_lutpair137";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1\ : label is "soft_lutpair135";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1\ : label is "soft_lutpair144";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat0_match_fall0_and_r_i_1\ : label is "soft_lutpair144";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat0_match_rise2_and_r_i_1\ : label is "soft_lutpair135";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat1_match_fall2_and_r_i_1\ : label is "soft_lutpair137";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1\ : label is "soft_lutpair131";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1\ : label is "soft_lutpair131";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1\ : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1\ : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1\ : label is "soft_lutpair132";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1\ : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1\ : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1\ : label is "soft_lutpair132";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1\ : label is "soft_lutpair129";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1\ : label is "soft_lutpair133";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1\ : label is "soft_lutpair129";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1\ : label is "soft_lutpair133";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1\ : label is "soft_lutpair130";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1\ : label is "soft_lutpair134";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1\ : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1\ : label is "soft_lutpair130";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1\ : label is "soft_lutpair134";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1\ : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1\ : label is "soft_lutpair157";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1\ : label is "soft_lutpair157";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_found_edge_r[0]_i_2\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1\ : label is "soft_lutpair154";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1\ : label is "soft_lutpair154";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1\ : label is "soft_lutpair155";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1\ : label is "soft_lutpair155";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1\ : label is "soft_lutpair158";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1\ : label is "soft_lutpair158";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1\ : label is "soft_lutpair156";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1\ : label is "soft_lutpair156";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1\ : label is "soft_lutpair163";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1\ : label is "soft_lutpair163";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1\ : label is "soft_lutpair162";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1\ : label is "soft_lutpair162";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1\ : label is "soft_lutpair161";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1\ : label is "soft_lutpair161";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \idel_dec_cnt[4]_i_3\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \idel_dec_cnt[4]_i_4\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \idel_dec_cnt[4]_i_5\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of idel_pat_detect_valid_r_i_1 : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][1][0]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][1][1]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][1][3]_i_2\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][1][4]_i_2\ : label is "soft_lutpair145";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][1][4]_i_3\ : label is "soft_lutpair136";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_slice_r[0]_i_1\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_slice_r[1]_i_1\ : label is "soft_lutpair139";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_slice_r[2]_i_1\ : label is "soft_lutpair140";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_slice_r[3]_i_1\ : label is "soft_lutpair139";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_slice_r[4]_i_1\ : label is "soft_lutpair150";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_14\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_19\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \mpr_4to1.idel_mpr_pat_detect_r_i_2\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \mpr_4to1.inhibit_edge_detect_r_i_5\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \mpr_4to1.inhibit_edge_detect_r_i_6\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \mpr_4to1.stable_idel_cnt[1]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \mpr_4to1.stable_idel_cnt[2]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \mpr_4to1.stable_idel_cnt[2]_i_3\ : label is "soft_lutpair141";
  attribute SOFT_HLUTNM of new_cnt_cpt_r_i_2 : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__0\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__0\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__0\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_3\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_3__0\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_4\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_4__0\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__0\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__0\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__0\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__0\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of pi_cnt_dec_i_2 : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \pi_rdval_cnt[0]_i_1\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \pi_rdval_cnt[2]_i_2\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \pi_rdval_cnt[3]_i_2\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \pi_rdval_cnt[4]_i_2\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \pi_rdval_cnt[5]_i_4\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of pi_stg2_f_incdec_timing_i_1 : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of pi_stg2_load_timing_i_1 : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \pi_stg2_reg_l_timing[0]_i_1\ : label is "soft_lutpair147";
  attribute SOFT_HLUTNM of \pi_stg2_reg_l_timing[1]_i_1\ : label is "soft_lutpair149";
  attribute SOFT_HLUTNM of \pi_stg2_reg_l_timing[2]_i_1\ : label is "soft_lutpair148";
  attribute SOFT_HLUTNM of \pi_stg2_reg_l_timing[3]_i_1\ : label is "soft_lutpair149";
  attribute SOFT_HLUTNM of \pi_stg2_reg_l_timing[4]_i_1\ : label is "soft_lutpair148";
  attribute SOFT_HLUTNM of \pi_stg2_reg_l_timing[5]_i_2\ : label is "soft_lutpair147";
  attribute SOFT_HLUTNM of prbs_rdlvl_done_pulse_i_1 : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of rdlvl_rank_done_r_i_2 : label is "soft_lutpair140";
  attribute SOFT_HLUTNM of rdlvl_stg1_done_int_i_1 : label is "soft_lutpair43";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rdlvl_stg1_done_int_reg : label is "30";
  attribute SOFT_HLUTNM of \regl_dqs_cnt[1]_i_1\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \regl_rank_cnt[1]_i_2\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of reset_if_i_1 : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \right_edge_taps_r[0]_i_1\ : label is "soft_lutpair160";
  attribute SOFT_HLUTNM of \right_edge_taps_r[1]_i_1\ : label is "soft_lutpair160";
  attribute SOFT_HLUTNM of \right_edge_taps_r[2]_i_1\ : label is "soft_lutpair159";
  attribute SOFT_HLUTNM of \right_edge_taps_r[3]_i_1\ : label is "soft_lutpair146";
  attribute SOFT_HLUTNM of \right_edge_taps_r[4]_i_1\ : label is "soft_lutpair159";
  attribute SOFT_HLUTNM of \right_edge_taps_r[5]_i_2\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of samp_edge_cnt0_en_r_i_1 : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \second_edge_taps_r[1]_i_1\ : label is "soft_lutpair138";
  attribute SOFT_HLUTNM of \second_edge_taps_r[2]_i_1\ : label is "soft_lutpair138";
  attribute SOFT_HLUTNM of \second_edge_taps_r[3]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \second_edge_taps_r[4]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[4]_i_2\ : label is "soft_lutpair142";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[1]_i_1\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[2]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[3]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[5]_i_4\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[5]_i_6\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \wait_cnt_r[1]_i_1\ : label is "soft_lutpair152";
  attribute SOFT_HLUTNM of \wait_cnt_r[2]_i_1\ : label is "soft_lutpair152";
  attribute SOFT_HLUTNM of \wait_cnt_r[3]_i_3\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[109]_i_1\ : label is "soft_lutpair165";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[125]_i_1\ : label is "soft_lutpair164";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[127]_i_1\ : label is "soft_lutpair142";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[127]_i_2\ : label is "soft_lutpair164";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[13]_i_1\ : label is "soft_lutpair165";
begin
  D(4 downto 0) <= \^d\(4 downto 0);
  Q(0) <= \^q\(0);
  idelay_ce_int <= \^idelay_ce_int\;
  idelay_inc_int <= \^idelay_inc_int\;
  new_cnt_cpt_r_reg_0 <= \^new_cnt_cpt_r_reg_0\;
  pi_cnt_dec_reg_0 <= \^pi_cnt_dec_reg_0\;
  pi_fine_dly_dec_done <= \^pi_fine_dly_dec_done\;
  \rd_mux_sel_r_reg[0]_0\ <= \^rd_mux_sel_r_reg[0]_0\;
  rdlvl_last_byte_done <= \^rdlvl_last_byte_done\;
  rdlvl_pi_incdec <= \^rdlvl_pi_incdec\;
  rdlvl_stg1_rank_done <= \^rdlvl_stg1_rank_done\;
  samp_edge_cnt0_en_r <= \^samp_edge_cnt0_en_r\;
\FSM_onehot_cal1_state_r[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_1_in26_in,
      I1 => p_2_in,
      O => \FSM_onehot_cal1_state_r[10]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002AAA"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => found_edge_r_reg_n_0,
      I2 => found_stable_eye_last_r,
      I3 => found_first_edge_r_reg_n_0,
      I4 => tap_limit_cpt_r,
      O => \FSM_onehot_cal1_state_r[11]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I1 => mpr_rdlvl_start_r_reg_0,
      I2 => mpr_rdlvl_start_r,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      O => \FSM_onehot_cal1_state_r[13]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => \FSM_onehot_cal1_state_r[14]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[14]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      I1 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[5]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      I5 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      O => \FSM_onehot_cal1_state_r[14]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[15]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r[15]_i_3_n_0\,
      I2 => p_12_in,
      O => \FSM_onehot_cal1_state_r[15]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[15]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[16]_i_2_n_0\,
      I1 => mpr_dec_cpt_r_reg_n_0,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I3 => \FSM_onehot_cal1_state_r[14]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[15]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \pi_rdval_cnt[5]_i_3_n_0\,
      I1 => \idel_dec_cnt_reg_n_0_[4]\,
      I2 => \idel_dec_cnt_reg_n_0_[2]\,
      I3 => \idel_dec_cnt_reg_n_0_[1]\,
      I4 => \idel_dec_cnt_reg_n_0_[0]\,
      I5 => \idel_dec_cnt_reg_n_0_[3]\,
      O => \FSM_onehot_cal1_state_r[15]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44F444F4FFFF44F4"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[21]_i_2_n_0\,
      I1 => mpr_dec_cpt_r_reg_n_0,
      I2 => \FSM_onehot_cal1_state_r[16]_i_2_n_0\,
      I3 => \FSM_onehot_cal1_state_r[16]_i_3_n_0\,
      I4 => \^q\(0),
      I5 => store_sr_req_r_reg_0,
      O => \FSM_onehot_cal1_state_r[16]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[16]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"001D"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][0][0]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \idelay_tap_cnt_r_reg_n_0_[0][1][0]\,
      I3 => \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[16]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[16]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[14]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I2 => mpr_dec_cpt_r_reg_n_0,
      O => \FSM_onehot_cal1_state_r[16]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[0]_0\,
      I1 => p_9_in,
      I2 => p_13_in,
      O => \FSM_onehot_cal1_state_r[1]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => idel_adj_inc_reg_n_0,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      O => \FSM_onehot_cal1_state_r[20]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF1FFF1FFF1F1F1"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[21]_i_2_n_0\,
      I1 => mpr_dec_cpt_r_reg_n_0,
      I2 => \FSM_onehot_cal1_state_r[21]_i_3_n_0\,
      I3 => p_34_in,
      I4 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      I5 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      O => \FSM_onehot_cal1_state_r[21]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[21]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => p_12_in,
      I1 => \FSM_onehot_cal1_state_r[15]_i_3_n_0\,
      O => \FSM_onehot_cal1_state_r[21]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[21]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF808080"
    )
        port map (
      I0 => idel_pat_detect_valid_r_reg_n_0,
      I1 => p_0_in549_in,
      I2 => idel_mpr_pat_detect_r,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I4 => idel_adj_inc_reg_n_0,
      I5 => p_8_in,
      O => \FSM_onehot_cal1_state_r[21]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080808080808AA08"
    )
        port map (
      I0 => idelay_tap_limit_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r[22]_i_2_n_0\,
      I2 => idel_mpr_pat_detect_r,
      I3 => p_34_in,
      I4 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      I5 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      O => \FSM_onehot_cal1_state_r[22]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[22]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => idel_pat_detect_valid_r_reg_n_0,
      I1 => p_0_in549_in,
      O => \FSM_onehot_cal1_state_r[22]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => found_edge_r_reg_n_0,
      I2 => found_stable_eye_last_r,
      I3 => found_first_edge_r_reg_n_0,
      I4 => tap_limit_cpt_r,
      O => \FSM_onehot_cal1_state_r[29]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404040404045504"
    )
        port map (
      I0 => idelay_tap_limit_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r[22]_i_2_n_0\,
      I2 => idel_mpr_pat_detect_r,
      I3 => p_34_in,
      I4 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      I5 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      O => \FSM_onehot_cal1_state_r[2]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFD0"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[34]_i_3_n_0\,
      I1 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\,
      I2 => \FSM_onehot_cal1_state_r[34]_i_5_n_0\,
      I3 => \FSM_onehot_cal1_state_r[34]_i_6_n_0\,
      I4 => \FSM_onehot_cal1_state_r[34]_i_7_n_0\,
      I5 => \cnt_idel_dec_cpt_r_reg[0]_0\,
      O => \FSM_onehot_cal1_state_r[34]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_0_in549_in,
      I1 => idel_pat_detect_valid_r_reg_n_0,
      O => \FSM_onehot_cal1_state_r[34]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => p_14_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      I2 => p_12_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I4 => p_13_in,
      I5 => p_2_in,
      O => \FSM_onehot_cal1_state_r[34]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I2 => \cal1_state_r1[0]_i_2_n_0\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I4 => p_8_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      O => \FSM_onehot_cal1_state_r[34]_i_4_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      I1 => p_0_in549_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I3 => cal1_wait_r,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => \FSM_onehot_cal1_state_r[34]_i_5_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF2"
    )
        port map (
      I0 => \^q\(0),
      I1 => cal1_wait_r,
      I2 => p_0_in541_in,
      I3 => \FSM_onehot_cal1_state_r[34]_i_9_n_0\,
      I4 => cal1_dq_idel_inc,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      O => \FSM_onehot_cal1_state_r[34]_i_6_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF08FF08FFFFFF08"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I1 => rdlvl_stg1_start_r_reg_0,
      I2 => rdlvl_stg1_start_r,
      I3 => \FSM_onehot_cal1_state_r[9]_i_1_n_0\,
      I4 => detect_edge_done_r,
      I5 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[34]_i_7_n_0\
    );
\FSM_onehot_cal1_state_r[34]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => prech_done,
      O => \FSM_onehot_cal1_state_r[34]_i_9_n_0\
    );
\FSM_onehot_cal1_state_r[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => mpr_dec_cpt_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r[14]_i_2_n_0\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      O => \FSM_onehot_cal1_state_r[4]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00020000"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\,
      I1 => regl_rank_cnt(0),
      I2 => regl_rank_cnt(1),
      I3 => \regl_dqs_cnt_reg_n_0_[1]\,
      I4 => \regl_dqs_cnt_reg_n_0_[0]\,
      O => \FSM_onehot_cal1_state_r[5]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00020000"
    )
        port map (
      I0 => p_0_in541_in,
      I1 => done_cnt(2),
      I2 => done_cnt(3),
      I3 => done_cnt(1),
      I4 => done_cnt(0),
      O => \FSM_onehot_cal1_state_r[5]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE0E0E0E0E0E0E0"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[6]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r[6]_i_3_n_0\,
      I2 => p_0_in541_in,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I4 => \FSM_onehot_cal1_state_r[6]_i_4_n_0\,
      I5 => cal1_prech_req_r,
      O => \FSM_onehot_cal1_state_r[6]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => done_cnt(0),
      I1 => done_cnt(1),
      I2 => done_cnt(3),
      I3 => done_cnt(2),
      O => \FSM_onehot_cal1_state_r[6]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[6]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \regl_dqs_cnt_reg_n_0_[0]\,
      I1 => \regl_dqs_cnt_reg_n_0_[1]\,
      I2 => regl_rank_cnt(1),
      I3 => regl_rank_cnt(0),
      O => \FSM_onehot_cal1_state_r[6]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[6]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[1]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      O => \FSM_onehot_cal1_state_r[6]_i_4_n_0\
    );
\FSM_onehot_cal1_state_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \FSM_onehot_cal1_state_r[7]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      O => cal1_cnt_cpt_r(0)
    );
\FSM_onehot_cal1_state_r[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => mpr_rdlvl_start_r,
      I1 => mpr_rdlvl_start_r_reg_0,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      O => \FSM_onehot_cal1_state_r[9]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      Q => p_13_in,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[10]_i_1_n_0\,
      Q => p_0_in549_in,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[11]_i_1_n_0\,
      Q => p_14_in,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => p_14_in,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[13]_i_1_n_0\,
      Q => \^q\(0),
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[14]_i_1_n_0\,
      Q => p_9_in,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[15]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[16]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[1]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[20]_i_1_n_0\,
      Q => p_34_in,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[21]_i_1_n_0\,
      Q => store_sr_req_pulsed_r,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[22]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[29]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[2]_i_1_n_0\,
      Q => cal1_dq_idel_inc,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      Q => p_8_in,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      Q => p_12_in,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[34]_i_2_n_0\,
      Q => p_2_in,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => cal1_dq_idel_inc,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[4]_i_1_n_0\,
      Q => cal1_prech_req_r,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[5]_i_1_n_0\,
      Q => rdlvl_stg1_done_int,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[6]_i_1_n_0\,
      Q => p_0_in541_in,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[7]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      S => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => cal1_cnt_cpt_r(0),
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\FSM_onehot_cal1_state_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[9]_i_1_n_0\,
      Q => p_1_in26_in,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\cal1_cnt_cpt_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"15C815C815C855C8"
    )
        port map (
      I0 => p_0_in541_in,
      I1 => cal1_prech_req_r,
      I2 => prech_done,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I4 => \rnk_cnt_r_reg_n_0_[0]\,
      I5 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \cal1_cnt_cpt_r[0]_i_1_n_0\
    );
\cal1_cnt_cpt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_cnt_cpt_r[0]_i_1_n_0\,
      Q => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
cal1_dlyce_cpt_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => tap_limit_cpt_r,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      O => cal1_dlyce_cpt_r
    );
cal1_dlyce_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_dlyce_cpt_r,
      Q => cal1_dlyce_cpt_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
cal1_dlyinc_cpt_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      I1 => tap_limit_cpt_r,
      O => cal1_dlyinc_cpt_r
    );
cal1_dlyinc_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_dlyinc_cpt_r,
      Q => cal1_dlyinc_cpt_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
cal1_dq_idel_ce_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => cal1_dq_idel_inc,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => cal1_dq_idel_ce
    );
cal1_dq_idel_ce_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_dq_idel_ce,
      Q => \^idelay_ce_int\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
cal1_dq_idel_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_dq_idel_inc,
      Q => \^idelay_inc_int\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
cal1_prech_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_prech_req_r,
      Q => \cal1_prech_req_r__0\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\cal1_state_r1[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => p_34_in,
      I1 => \cal1_state_r1[0]_i_2_n_0\,
      I2 => \^q\(0),
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I4 => p_1_in26_in,
      I5 => \cal1_state_r1[0]_i_3_n_0\,
      O => \cal1_state_r1[0]_i_1_n_0\
    );
\cal1_state_r1[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in549_in,
      I1 => p_9_in,
      O => \cal1_state_r1[0]_i_2_n_0\
    );
\cal1_state_r1[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => rdlvl_stg1_done_int,
      I1 => p_0_in541_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I3 => p_14_in,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      I5 => p_12_in,
      O => \cal1_state_r1[0]_i_3_n_0\
    );
\cal1_state_r1[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \cal1_state_r1[3]_i_3_n_0\,
      I1 => \cal1_state_r1[1]_i_2_n_0\,
      I2 => p_13_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I4 => p_0_in549_in,
      I5 => p_34_in,
      O => \cal1_state_r1[1]_i_1_n_0\
    );
\cal1_state_r1[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => p_2_in,
      I1 => p_12_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      I3 => cal1_prech_req_r,
      O => \cal1_state_r1[1]_i_2_n_0\
    );
\cal1_state_r1[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => rdlvl_stg1_done_int,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I2 => cal1_dq_idel_inc,
      I3 => p_12_in,
      I4 => p_2_in,
      I5 => \cal1_state_r1[2]_i_2_n_0\,
      O => \cal1_state_r1[2]_i_1_n_0\
    );
\cal1_state_r1[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      I2 => p_1_in26_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I5 => \cal1_state_r1[0]_i_2_n_0\,
      O => \cal1_state_r1[2]_i_2_n_0\
    );
\cal1_state_r1[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \cal1_state_r1[3]_i_2_n_0\,
      I1 => p_9_in,
      I2 => p_0_in549_in,
      I3 => p_2_in,
      I4 => store_sr_req_pulsed_r,
      I5 => \cal1_state_r1[3]_i_3_n_0\,
      O => \cal1_state_r1[3]_i_1_n_0\
    );
\cal1_state_r1[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => p_1_in26_in,
      I2 => cal1_prech_req_r,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\,
      O => \cal1_state_r1[3]_i_2_n_0\
    );
\cal1_state_r1[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => p_8_in,
      I1 => rdlvl_stg1_done_int,
      I2 => p_0_in541_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      O => \cal1_state_r1[3]_i_3_n_0\
    );
\cal1_state_r1[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => p_2_in,
      I1 => p_1_in26_in,
      I2 => p_0_in541_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      I4 => p_0_in549_in,
      O => \cal1_state_r1[4]_i_1_n_0\
    );
\cal1_state_r1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I1 => p_14_in,
      I2 => p_13_in,
      O => \cal1_state_r1[5]_i_1_n_0\
    );
\cal1_state_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_state_r1[0]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[0]\,
      R => '0'
    );
\cal1_state_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_state_r1[1]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[1]\,
      R => '0'
    );
\cal1_state_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_state_r1[2]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[2]\,
      R => '0'
    );
\cal1_state_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_state_r1[3]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[3]\,
      R => '0'
    );
\cal1_state_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_state_r1[4]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[4]\,
      R => '0'
    );
\cal1_state_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_state_r1[5]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[5]\,
      R => '0'
    );
cal1_wait_cnt_en_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => p_9_in,
      I1 => p_8_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I3 => p_12_in,
      I4 => p_2_in,
      I5 => cal1_wait_cnt_en_r_i_2_n_0,
      O => cal1_wait_cnt_en_r0
    );
cal1_wait_cnt_en_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => p_13_in,
      I1 => p_14_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I3 => p_1_in26_in,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I5 => \^q\(0),
      O => cal1_wait_cnt_en_r_i_2_n_0
    );
cal1_wait_cnt_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_wait_cnt_en_r0,
      Q => cal1_wait_cnt_en_r,
      R => '0'
    );
\cal1_wait_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cal1_wait_cnt_r_reg(0),
      O => \p_0_in__0__0\(0)
    );
\cal1_wait_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cal1_wait_cnt_r_reg(1),
      I1 => cal1_wait_cnt_r_reg(0),
      O => \p_0_in__0__0\(1)
    );
\cal1_wait_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cal1_wait_cnt_r_reg(2),
      I1 => cal1_wait_cnt_r_reg(0),
      I2 => cal1_wait_cnt_r_reg(1),
      O => \p_0_in__0__0\(2)
    );
\cal1_wait_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cal1_wait_cnt_r_reg(3),
      I1 => cal1_wait_cnt_r_reg(1),
      I2 => cal1_wait_cnt_r_reg(0),
      I3 => cal1_wait_cnt_r_reg(2),
      O => \p_0_in__0__0\(3)
    );
\cal1_wait_cnt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40000000FFFFFFFF"
    )
        port map (
      I0 => cal1_wait_cnt_r_reg(4),
      I1 => cal1_wait_cnt_r_reg(3),
      I2 => cal1_wait_cnt_r_reg(1),
      I3 => cal1_wait_cnt_r_reg(0),
      I4 => cal1_wait_cnt_r_reg(2),
      I5 => cal1_wait_cnt_en_r,
      O => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => cal1_wait_cnt_r_reg(4),
      I1 => cal1_wait_cnt_r_reg(2),
      I2 => cal1_wait_cnt_r_reg(0),
      I3 => cal1_wait_cnt_r_reg(1),
      I4 => cal1_wait_cnt_r_reg(3),
      O => \p_0_in__0__0\(4)
    );
\cal1_wait_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0__0\(0),
      Q => cal1_wait_cnt_r_reg(0),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0__0\(1),
      Q => cal1_wait_cnt_r_reg(1),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0__0\(2),
      Q => cal1_wait_cnt_r_reg(2),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0__0\(3),
      Q => cal1_wait_cnt_r_reg(3),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0__0\(4),
      Q => cal1_wait_cnt_r_reg(4),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
cal1_wait_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => cal1_wait_cnt_en_r,
      I1 => cal1_wait_cnt_r_reg(4),
      I2 => cal1_wait_cnt_r_reg(3),
      I3 => cal1_wait_cnt_r_reg(1),
      I4 => cal1_wait_cnt_r_reg(0),
      I5 => cal1_wait_cnt_r_reg(2),
      O => cal1_wait_r_i_1_n_0
    );
cal1_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_wait_r_i_1_n_0,
      Q => cal1_wait_r,
      R => '0'
    );
\cnt_idel_dec_cpt_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7020"
    )
        port map (
      I0 => found_second_edge_r_reg_n_0,
      I1 => cnt_idel_dec_cpt_r1(0),
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I3 => \cnt_idel_dec_cpt_r[0]_i_2_n_0\,
      I4 => \cnt_idel_dec_cpt_r[0]_i_3_n_0\,
      O => cnt_idel_dec_cpt_r(0)
    );
\cnt_idel_dec_cpt_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800B8FFB8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_6\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \right_edge_taps_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[0]_i_2_n_0\
    );
\cnt_idel_dec_cpt_r[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[5]_0\(0),
      I1 => \^q\(0),
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[0]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF28AA2800"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => cnt_idel_dec_cpt_r1(1),
      I2 => cnt_idel_dec_cpt_r1(0),
      I3 => found_second_edge_r_reg_n_0,
      I4 => \cnt_idel_dec_cpt_r[1]_i_2_n_0\,
      I5 => \cnt_idel_dec_cpt_r[1]_i_3_n_0\,
      O => cnt_idel_dec_cpt_r(1)
    );
\cnt_idel_dec_cpt_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_5\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\,
      I4 => \cnt_idel_dec_cpt_r[1]_i_4_n_0\,
      O => \cnt_idel_dec_cpt_r[1]_i_2_n_0\
    );
\cnt_idel_dec_cpt_r[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F88F8888"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[5]_0\(1),
      I1 => \^q\(0),
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[1]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4BB4"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \right_edge_taps_r_reg_n_0_[1]\,
      I2 => \right_edge_taps_r_reg_n_0_[2]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[1]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF28AA2800"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => cnt_idel_dec_cpt_r1(2),
      I2 => \cnt_idel_dec_cpt_r[2]_i_3_n_0\,
      I3 => found_second_edge_r_reg_n_0,
      I4 => \cnt_idel_dec_cpt_r[2]_i_4_n_0\,
      I5 => \cnt_idel_dec_cpt_r[2]_i_5_n_0\,
      O => cnt_idel_dec_cpt_r(2)
    );
\cnt_idel_dec_cpt_r[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4D44B2BBB2BB4D44"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I1 => \right_edge_taps_r_reg_n_0_[2]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \right_edge_taps_r_reg_n_0_[1]\,
      I4 => \right_edge_taps_r_reg_n_0_[3]\,
      I5 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      O => \cnt_idel_dec_cpt_r[2]_i_11_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => \first_edge_taps_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[2]_i_12_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \first_edge_taps_r_reg_n_0_[2]\,
      O => \cnt_idel_dec_cpt_r[2]_i_13_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I1 => \first_edge_taps_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[2]_i_14_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \first_edge_taps_r_reg_n_0_[0]\,
      O => \cnt_idel_dec_cpt_r[2]_i_15_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => cnt_idel_dec_cpt_r1(1),
      I1 => cnt_idel_dec_cpt_r1(0),
      O => \cnt_idel_dec_cpt_r[2]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_4\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\,
      I4 => \cnt_idel_dec_cpt_r[2]_i_11_n_0\,
      O => \cnt_idel_dec_cpt_r[2]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888F888F88888F8"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[5]_0\(2),
      I1 => \^q\(0),
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I5 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[2]_i_5_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[3]\,
      I1 => \first_edge_taps_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[2]_i_6_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[2]\,
      I1 => \first_edge_taps_r_reg_n_0_[2]\,
      O => \cnt_idel_dec_cpt_r[2]_i_7_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[1]\,
      I1 => \first_edge_taps_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[2]_i_8_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[0]\,
      I1 => \first_edge_taps_r_reg_n_0_[0]\,
      O => \cnt_idel_dec_cpt_r[2]_i_9_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF28AA2800"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => cnt_idel_dec_cpt_r1(3),
      I2 => \cnt_idel_dec_cpt_r[3]_i_2_n_0\,
      I3 => found_second_edge_r_reg_n_0,
      I4 => \cnt_idel_dec_cpt_r[3]_i_3_n_0\,
      I5 => \cnt_idel_dec_cpt_r[3]_i_4_n_0\,
      O => cnt_idel_dec_cpt_r(3)
    );
\cnt_idel_dec_cpt_r[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => cnt_idel_dec_cpt_r1(2),
      I1 => cnt_idel_dec_cpt_r1(0),
      I2 => cnt_idel_dec_cpt_r1(1),
      O => \cnt_idel_dec_cpt_r[3]_i_2_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_7\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\,
      I4 => \cnt_idel_dec_cpt_r[3]_i_5_n_0\,
      O => \cnt_idel_dec_cpt_r[3]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8FF88888"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[5]_0\(3),
      I1 => \^q\(0),
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_11_n_0\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[3]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r[4]_i_14_n_0\,
      I1 => \right_edge_taps_r_reg_n_0_[4]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[3]_i_5_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF28AA2800"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => cnt_idel_dec_cpt_r1(4),
      I2 => \cnt_idel_dec_cpt_r[4]_i_3_n_0\,
      I3 => found_second_edge_r_reg_n_0,
      I4 => \cnt_idel_dec_cpt_r[4]_i_4_n_0\,
      I5 => \cnt_idel_dec_cpt_r[4]_i_5_n_0\,
      O => cnt_idel_dec_cpt_r(4)
    );
\cnt_idel_dec_cpt_r[4]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B24D4DB2"
    )
        port map (
      I0 => \right_edge_taps_r_reg_n_0_[4]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I2 => \cnt_idel_dec_cpt_r[4]_i_14_n_0\,
      I3 => \right_edge_taps_r_reg_n_0_[5]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[4]_i_10_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I1 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      O => \cnt_idel_dec_cpt_r[4]_i_11_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I1 => \first_edge_taps_r_reg_n_0_[5]\,
      O => \cnt_idel_dec_cpt_r[4]_i_12_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I1 => \first_edge_taps_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[4]_i_13_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2B22BB2B2B222B22"
    )
        port map (
      I0 => \right_edge_taps_r_reg_n_0_[3]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \right_edge_taps_r_reg_n_0_[2]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \right_edge_taps_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[4]_i_14_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => cnt_idel_dec_cpt_r1(3),
      I1 => cnt_idel_dec_cpt_r1(1),
      I2 => cnt_idel_dec_cpt_r1(0),
      I3 => cnt_idel_dec_cpt_r1(2),
      O => \cnt_idel_dec_cpt_r[4]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_6\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\,
      I4 => \cnt_idel_dec_cpt_r[4]_i_10_n_0\,
      O => \cnt_idel_dec_cpt_r[4]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F88FF888888888"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[5]_0\(4),
      I1 => \^q\(0),
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_11_n_0\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[4]_i_5_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[5]\,
      I1 => \first_edge_taps_r_reg_n_0_[5]\,
      O => \cnt_idel_dec_cpt_r[4]_i_6_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[4]\,
      I1 => \first_edge_taps_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[4]_i_7_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \right_edge_taps_r_reg_n_0_[5]\,
      I1 => \right_edge_taps_r_reg_n_0_[4]\,
      I2 => \right_edge_taps_r_reg_n_0_[1]\,
      I3 => \right_edge_taps_r_reg_n_0_[0]\,
      I4 => \right_edge_taps_r_reg_n_0_[2]\,
      I5 => \right_edge_taps_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[4]_i_9_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => \cnt_idel_dec_cpt_r_reg[0]_0\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      O => \cnt_idel_dec_cpt_r[5]_i_1_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFAEAEAE"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r[5]_i_3_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I2 => \cnt_idel_dec_cpt_r[5]_i_4_n_0\,
      I3 => \^q\(0),
      I4 => \cnt_idel_dec_cpt_r_reg[5]_0\(5),
      O => cnt_idel_dec_cpt_r(5)
    );
\cnt_idel_dec_cpt_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8808080808888888"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r[5]_i_5_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I2 => found_second_edge_r_reg_n_0,
      I3 => cnt_idel_dec_cpt_r1(4),
      I4 => \cnt_idel_dec_cpt_r[4]_i_3_n_0\,
      I5 => \cnt_idel_dec_cpt_r_reg[4]_i_2_n_1\,
      O => \cnt_idel_dec_cpt_r[5]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555556"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg_n_0_[5]\,
      I1 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      I5 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[5]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABEBBEEBE"
    )
        port map (
      I0 => found_second_edge_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I2 => \right_edge_taps_r_reg_n_0_[5]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I4 => \cnt_idel_dec_cpt_r[5]_i_6_n_0\,
      I5 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\,
      O => \cnt_idel_dec_cpt_r[5]_i_5_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B2"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r[4]_i_14_n_0\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I2 => \right_edge_taps_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[5]_i_6_n_0\
    );
\cnt_idel_dec_cpt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(0),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(1),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(2),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[2]_i_10\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_0\,
      CO(2) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_1\,
      CO(1) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_2\,
      CO(0) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_3\,
      CYINIT => '1',
      DI(3) => \tap_cnt_cpt_r_reg_n_0_[3]\,
      DI(2) => \tap_cnt_cpt_r_reg_n_0_[2]\,
      DI(1) => \tap_cnt_cpt_r_reg_n_0_[1]\,
      DI(0) => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O(3) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_4\,
      O(2) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_5\,
      O(1) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_6\,
      O(0) => \NLW_cnt_idel_dec_cpt_r_reg[2]_i_10_O_UNCONNECTED\(0),
      S(3) => \cnt_idel_dec_cpt_r[2]_i_12_n_0\,
      S(2) => \cnt_idel_dec_cpt_r[2]_i_13_n_0\,
      S(1) => \cnt_idel_dec_cpt_r[2]_i_14_n_0\,
      S(0) => \cnt_idel_dec_cpt_r[2]_i_15_n_0\
    );
\cnt_idel_dec_cpt_r_reg[2]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_0\,
      CO(2) => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_1\,
      CO(1) => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_2\,
      CO(0) => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_3\,
      CYINIT => '1',
      DI(3) => \second_edge_taps_r_reg_n_0_[3]\,
      DI(2) => \second_edge_taps_r_reg_n_0_[2]\,
      DI(1) => \second_edge_taps_r_reg_n_0_[1]\,
      DI(0) => \second_edge_taps_r_reg_n_0_[0]\,
      O(3 downto 1) => cnt_idel_dec_cpt_r1(2 downto 0),
      O(0) => \NLW_cnt_idel_dec_cpt_r_reg[2]_i_2_O_UNCONNECTED\(0),
      S(3) => \cnt_idel_dec_cpt_r[2]_i_6_n_0\,
      S(2) => \cnt_idel_dec_cpt_r[2]_i_7_n_0\,
      S(1) => \cnt_idel_dec_cpt_r[2]_i_8_n_0\,
      S(0) => \cnt_idel_dec_cpt_r[2]_i_9_n_0\
    );
\cnt_idel_dec_cpt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(3),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(4),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[4]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_0\,
      CO(3) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED\(3),
      CO(2) => \cnt_idel_dec_cpt_r_reg[4]_i_2_n_1\,
      CO(1) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED\(1),
      CO(0) => \cnt_idel_dec_cpt_r_reg[4]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \second_edge_taps_r_reg_n_0_[5]\,
      DI(0) => \second_edge_taps_r_reg_n_0_[4]\,
      O(3 downto 2) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => cnt_idel_dec_cpt_r1(4 downto 3),
      S(3 downto 2) => B"01",
      S(1) => \cnt_idel_dec_cpt_r[4]_i_6_n_0\,
      S(0) => \cnt_idel_dec_cpt_r[4]_i_7_n_0\
    );
\cnt_idel_dec_cpt_r_reg[4]_i_8\: unisim.vcomponents.CARRY4
     port map (
      CI => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_0\,
      CO(3 downto 1) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O(3 downto 2) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_O_UNCONNECTED\(3 downto 2),
      O(1) => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_6\,
      O(0) => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_7\,
      S(3 downto 2) => B"00",
      S(1) => \cnt_idel_dec_cpt_r[4]_i_12_n_0\,
      S(0) => \cnt_idel_dec_cpt_r[4]_i_13_n_0\
    );
\cnt_idel_dec_cpt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(5),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[5]\,
      R => '0'
    );
\cnt_shift_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3332"
    )
        port map (
      I0 => cnt_shift_r_reg(1),
      I1 => cnt_shift_r_reg(0),
      I2 => cnt_shift_r_reg(2),
      I3 => cnt_shift_r_reg(3),
      O => \p_0_in__1\(0)
    );
\cnt_shift_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_shift_r_reg(0),
      I1 => cnt_shift_r_reg(1),
      O => \p_0_in__1\(1)
    );
\cnt_shift_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => cnt_shift_r_reg(2),
      I1 => cnt_shift_r_reg(1),
      I2 => cnt_shift_r_reg(0),
      O => \p_0_in__1\(2)
    );
\cnt_shift_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => cnt_shift_r_reg(3),
      I1 => cnt_shift_r_reg(0),
      I2 => cnt_shift_r_reg(1),
      I3 => cnt_shift_r_reg(2),
      O => \p_0_in__1\(3)
    );
\cnt_shift_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__1\(0),
      Q => cnt_shift_r_reg(0),
      S => \cnt_shift_r_reg[0]_0\(0)
    );
\cnt_shift_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__1\(1),
      Q => cnt_shift_r_reg(1),
      R => \cnt_shift_r_reg[0]_0\(0)
    );
\cnt_shift_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__1\(2),
      Q => cnt_shift_r_reg(2),
      R => \cnt_shift_r_reg[0]_0\(0)
    );
\cnt_shift_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__1\(3),
      Q => cnt_shift_r_reg(3),
      R => \cnt_shift_r_reg[0]_0\(0)
    );
detect_edge_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pb_detect_edge_done_r(2),
      I1 => pb_detect_edge_done_r(3),
      I2 => pb_detect_edge_done_r(0),
      I3 => pb_detect_edge_done_r(1),
      I4 => detect_edge_done_r_i_2_n_0,
      O => detect_edge_done_r_i_1_n_0
    );
detect_edge_done_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pb_detect_edge_done_r(5),
      I1 => pb_detect_edge_done_r(4),
      I2 => pb_detect_edge_done_r(7),
      I3 => pb_detect_edge_done_r(6),
      O => detect_edge_done_r_i_2_n_0
    );
detect_edge_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => detect_edge_done_r_i_1_n_0,
      Q => detect_edge_done_r,
      R => '0'
    );
\done_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000005554"
    )
        port map (
      I0 => done_cnt(0),
      I1 => done_cnt(3),
      I2 => done_cnt(1),
      I3 => done_cnt(2),
      I4 => done_cnt1,
      I5 => \done_cnt_reg[2]_0\,
      O => \done_cnt[0]_i_1_n_0\
    );
\done_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FAAFFAAE"
    )
        port map (
      I0 => done_cnt1,
      I1 => done_cnt(3),
      I2 => done_cnt(1),
      I3 => done_cnt(0),
      I4 => done_cnt(2),
      O => \done_cnt[1]_i_1_n_0\
    );
\done_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000A9A8"
    )
        port map (
      I0 => done_cnt(2),
      I1 => done_cnt(0),
      I2 => done_cnt(1),
      I3 => done_cnt(3),
      I4 => done_cnt1,
      I5 => \done_cnt_reg[2]_0\,
      O => \done_cnt[2]_i_1_n_0\
    );
\done_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEEA"
    )
        port map (
      I0 => done_cnt1,
      I1 => done_cnt(3),
      I2 => done_cnt(1),
      I3 => done_cnt(0),
      I4 => done_cnt(2),
      O => \done_cnt[3]_i_1_n_0\
    );
\done_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F111"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[6]_i_2_n_0\,
      I1 => rdlvl_stg1_done_int,
      I2 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I3 => p_0_in541_in,
      O => done_cnt1
    );
\done_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \done_cnt[0]_i_1_n_0\,
      Q => done_cnt(0),
      R => '0'
    );
\done_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \done_cnt[1]_i_1_n_0\,
      Q => done_cnt(1),
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\done_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \done_cnt[2]_i_1_n_0\,
      Q => done_cnt(2),
      R => '0'
    );
\done_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \done_cnt[3]_i_1_n_0\,
      Q => done_cnt(3),
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
dqs_po_dec_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => dqs_po_dec_done_r1_reg_0,
      Q => dqs_po_dec_done_r1,
      R => '0'
    );
dqs_po_dec_done_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => dqs_po_dec_done_r1,
      Q => dqs_po_dec_done_r2,
      R => '0'
    );
fine_dly_dec_done_r1_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF222"
    )
        port map (
      I0 => fine_dly_dec_done_r1_i_2_n_0,
      I1 => fine_dly_dec_done_r1_i_3_n_0,
      I2 => dqs_po_dec_done_r2,
      I3 => \pi_rdval_cnt[5]_i_3_n_0\,
      I4 => fine_dly_dec_done_r1,
      O => fine_dly_dec_done_r1_i_1_n_0
    );
fine_dly_dec_done_r1_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => pi_rdval_cnt(5),
      I1 => pi_rdval_cnt(2),
      I2 => pi_rdval_cnt(3),
      O => fine_dly_dec_done_r1_i_2_n_0
    );
fine_dly_dec_done_r1_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => pi_rdval_cnt(0),
      I1 => pi_rdval_cnt(1),
      I2 => \^pi_cnt_dec_reg_0\,
      I3 => pi_rdval_cnt(4),
      O => fine_dly_dec_done_r1_i_3_n_0
    );
fine_dly_dec_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fine_dly_dec_done_r1_i_1_n_0,
      Q => fine_dly_dec_done_r1,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
fine_dly_dec_done_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fine_dly_dec_done_r1,
      Q => fine_dly_dec_done_r2,
      R => '0'
    );
\first_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BFAA"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => found_first_edge_r_reg_n_0,
      I2 => found_stable_eye_last_r,
      I3 => \first_edge_taps_r[5]_i_3_n_0\,
      I4 => store_sr_req_pulsed_r,
      O => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFAA"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => found_first_edge_r_reg_n_0,
      I2 => found_stable_eye_last_r,
      I3 => \first_edge_taps_r[5]_i_3_n_0\,
      O => \first_edge_taps_r[5]_i_2_n_0\
    );
\first_edge_taps_r[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => found_edge_r_reg_n_0,
      I1 => store_sr_req_pulsed_r,
      I2 => detect_edge_done_r,
      I3 => tap_limit_cpt_r,
      O => \first_edge_taps_r[5]_i_3_n_0\
    );
\first_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \first_edge_taps_r_reg_n_0_[0]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \first_edge_taps_r_reg_n_0_[1]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \first_edge_taps_r_reg_n_0_[2]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \first_edge_taps_r_reg_n_0_[3]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \first_edge_taps_r_reg_n_0_[4]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \first_edge_taps_r_reg_n_0_[5]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
found_edge_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      I1 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      I2 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      I3 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      I4 => found_edge_r_i_2_n_0,
      O => found_edge_r_i_1_n_0
    );
found_edge_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      I1 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      I2 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      I3 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      O => found_edge_r_i_2_n_0
    );
found_edge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => found_edge_r_i_1_n_0,
      Q => found_edge_r_reg_n_0,
      R => '0'
    );
found_first_edge_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF555555BA000000"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => tap_limit_cpt_r,
      I2 => detect_edge_done_r,
      I3 => store_sr_req_pulsed_r,
      I4 => found_edge_r_reg_n_0,
      I5 => found_first_edge_r_reg_n_0,
      O => found_first_edge_r_i_1_n_0
    );
found_first_edge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => found_first_edge_r_i_1_n_0,
      Q => found_first_edge_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
found_second_edge_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5551555E0000000"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => \first_edge_taps_r[5]_i_3_n_0\,
      I2 => found_first_edge_r_reg_n_0,
      I3 => found_stable_eye_last_r,
      I4 => store_sr_req_pulsed_r,
      I5 => found_second_edge_r_reg_n_0,
      O => found_second_edge_r_i_1_n_0
    );
found_second_edge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => found_second_edge_r_i_1_n_0,
      Q => found_second_edge_r_reg_n_0,
      R => found_second_edge_r_reg_0
    );
found_stable_eye_last_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => found_stable_eye_r_reg_n_0,
      I1 => detect_edge_done_r,
      I2 => found_stable_eye_last_r,
      O => found_stable_eye_last_r_i_1_n_0
    );
found_stable_eye_last_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => found_stable_eye_last_r_i_1_n_0,
      Q => found_stable_eye_last_r,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
found_stable_eye_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pb_found_stable_eye_r(2),
      I1 => pb_found_stable_eye_r(3),
      I2 => pb_found_stable_eye_r(0),
      I3 => pb_found_stable_eye_r(1),
      I4 => found_stable_eye_r_i_2_n_0,
      O => found_stable_eye_r_i_1_n_0
    );
found_stable_eye_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pb_found_stable_eye_r(5),
      I1 => pb_found_stable_eye_r(4),
      I2 => pb_found_stable_eye_r(7),
      I3 => pb_found_stable_eye_r(6),
      O => found_stable_eye_r_i_2_n_0
    );
found_stable_eye_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => found_stable_eye_r_i_1_n_0,
      Q => found_stable_eye_r_reg_n_0,
      R => '0'
    );
\gen_byte_sel_div2.byte_sel_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt[0]_i_2_n_0\,
      I1 => \done_cnt_reg[2]_0\,
      I2 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      O => \rstdiv0_sync_r1_reg_rep__13\
    );
\gen_byte_sel_div2.byte_sel_cnt[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E2FFFF00E20000"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I1 => p_0_in541_in,
      I2 => regl_dqs_cnt_r(0),
      I3 => \^d\(2),
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]_1\,
      I5 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\,
      O => \gen_byte_sel_div2.byte_sel_cnt[0]_i_2_n_0\
    );
\gen_byte_sel_div2.byte_sel_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000002E222222"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]_1\,
      I2 => \^d\(2),
      I3 => p_0_in541_in,
      I4 => regl_dqs_cnt_r(1),
      I5 => RSTB,
      O => \gen_byte_sel_div2.byte_sel_cnt_reg[1]\
    );
\gen_mux_rd[0].mux_rd_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      Q => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      Q => \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      Q => \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\,
      Q => \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      Q => \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      Q => \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      Q => \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\,
      Q => \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_50\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_146\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_26\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_162\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r[0][0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => store_sr_r_reg_n_0,
      I1 => sr_valid_r_reg_n_0,
      O => store_sr_r0
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_34\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_130\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_10\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_138\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_2\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_178\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_42\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_154\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_18\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_170\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_58\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_186\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_50\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_98\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_26\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_74\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_34\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_82\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_10\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_106\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_2\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_114\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_42\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_66\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_18\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_90\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_58\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_122\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_51\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_147\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_27\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_163\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_35\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_131\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_11\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_139\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_3\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_179\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_43\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_155\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_19\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_171\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_59\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_187\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_51\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_99\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_27\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_75\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_35\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_83\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_11\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_107\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_3\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_115\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_43\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_67\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_19\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_91\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_59\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_123\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_52\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_148\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_28\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_164\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_36\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_132\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_12\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_140\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_4\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_180\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_44\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_156\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_20\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_172\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_60\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_188\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_52\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_100\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_28\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_76\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_36\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_84\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_12\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_108\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_4\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_116\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_44\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_68\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_20\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_92\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_60\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_124\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_53\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_149\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_29\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_165\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_37\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_133\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_13\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_141\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_5\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_181\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_45\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_157\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_21\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_173\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_61\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_189\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_53\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_101\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_29\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_77\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_37\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_85\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_13\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_109\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_5\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_117\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_45\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_69\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_21\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_93\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_61\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_125\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_54\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_150\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_30\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_166\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_38\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_134\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_14\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_142\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_6\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_182\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_46\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_158\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_22\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_174\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_62\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_190\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_54\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_102\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_30\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_78\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_38\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_86\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_14\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_110\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_6\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_118\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_46\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_70\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_22\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_94\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_62\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_126\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_55\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_151\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_31\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_167\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_39\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_135\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_15\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_143\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_7\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_183\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_47\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_159\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_23\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_175\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_63\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_191\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_55\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_103\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_31\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_79\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_39\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_87\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_15\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_111\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_7\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_119\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_47\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_71\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_23\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_95\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_63\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_127\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_56\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_152\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_32\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_168\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_40\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_136\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_16\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_144\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_8\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_184\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_48\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_160\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_24\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_176\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_64\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_192\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_56\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_104\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_32\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_80\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_40\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_88\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_16\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_112\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_8\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_120\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_48\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_72\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_24\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_96\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_64\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_128\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_57\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_153\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_33\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_169\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_41\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_137\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_17\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_145\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_9\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_185\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_49\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_161\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_25\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_177\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_65\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_193\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_57\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_105\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_33\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_81\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_41\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_89\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_17\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_113\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_9\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_121\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_49\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_73\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_25\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_97\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_65\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_129\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_50\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_26\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_34\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0\,
      Q => pat0_match_fall2_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_10\,
      Q => pat0_match_fall3_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_2\,
      Q => pat0_match_rise0_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_42\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0\,
      Q => pat0_match_rise1_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_18\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_58\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0\,
      Q => idel_pat0_match_rise3_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_26\,
      Q => pat0_match_fall1_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_10\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_2\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_42\,
      Q => idel_pat1_match_rise1_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_18\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0\,
      Q => pat0_match_rise2_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_58\,
      Q => pat0_match_rise3_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_50\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0\,
      Q => pat0_match_fall0_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_34\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_51\,
      Q => pat0_match_fall0_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_27\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0\,
      Q => pat0_match_fall1_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_35\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_11\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_3\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_43\,
      Q => idel_pat1_match_rise1_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_19\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_59\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0\,
      Q => idel_pat0_match_rise3_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_51\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_27\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_35\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0\,
      Q => pat0_match_fall2_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_19\,
      Q => pat0_match_rise2_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_11\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0\,
      Q => pat0_match_fall3_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_3\,
      Q => pat0_match_rise0_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_43\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0\,
      Q => pat0_match_rise1_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_59\,
      Q => pat0_match_rise3_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_52\,
      Q => pat0_match_fall0_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_28\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_36\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_12\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0\,
      Q => pat0_match_fall3_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_4\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_44\,
      Q => pat0_match_rise1_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_20\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0\,
      Q => pat0_match_rise2_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_60\,
      Q => idel_pat0_match_rise3_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_52\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_36\,
      Q => pat0_match_fall2_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_4\,
      Q => pat0_match_rise0_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_44\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0\,
      Q => idel_pat1_match_rise1_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_20\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_60\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0\,
      Q => pat0_match_rise3_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_28\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0\,
      Q => pat0_match_fall1_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_12\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_53\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_29\,
      Q => pat0_match_fall1_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_37\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0\,
      Q => pat0_match_fall2_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_13\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_5\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0\,
      Q => pat0_match_rise0_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_45\,
      Q => pat0_match_rise1_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_21\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_61\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0\,
      Q => idel_pat0_match_rise3_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_53\,
      Q => pat0_match_fall0_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_29\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_37\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_13\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0\,
      Q => pat0_match_fall3_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_45\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0\,
      Q => idel_pat1_match_rise1_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_61\,
      Q => pat0_match_rise3_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_21\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0\,
      Q => pat0_match_rise2_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_5\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_54\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_30\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_38\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0\,
      Q => pat0_match_fall2_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_14\,
      Q => pat0_match_fall3_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_6\,
      Q => pat0_match_rise0_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_46\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0\,
      Q => pat0_match_rise1_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_22\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_62\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0\,
      Q => idel_pat0_match_rise3_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_30\,
      Q => pat0_match_fall1_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_14\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_6\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_46\,
      Q => idel_pat1_match_rise1_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_22\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0\,
      Q => pat0_match_rise2_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_62\,
      Q => pat0_match_rise3_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_54\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0\,
      Q => pat0_match_fall0_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_38\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_55\,
      Q => pat0_match_fall0_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_31\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0\,
      Q => pat0_match_fall1_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_39\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_15\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_7\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_47\,
      Q => idel_pat1_match_rise1_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_23\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_63\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0\,
      Q => idel_pat0_match_rise3_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_55\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_31\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_39\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0\,
      Q => pat0_match_fall2_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_23\,
      Q => pat0_match_rise2_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_15\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0\,
      Q => pat0_match_fall3_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_7\,
      Q => pat0_match_rise0_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_47\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0\,
      Q => pat0_match_rise1_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_63\,
      Q => pat0_match_rise3_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_56\,
      Q => pat0_match_fall0_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_32\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_40\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_16\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0\,
      Q => pat0_match_fall3_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_8\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_48\,
      Q => pat0_match_rise1_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_24\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0\,
      Q => pat0_match_rise2_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_64\,
      Q => idel_pat0_match_rise3_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_56\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_40\,
      Q => pat0_match_fall2_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_8\,
      Q => pat0_match_rise0_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_48\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0\,
      Q => idel_pat1_match_rise1_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_24\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_64\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0\,
      Q => pat0_match_rise3_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_32\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0\,
      Q => pat0_match_fall1_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_16\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_57\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_33\,
      Q => pat0_match_fall1_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_41\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0\,
      Q => pat0_match_fall2_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_17\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_9\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0\,
      Q => pat0_match_rise0_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_49\,
      Q => pat0_match_rise1_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_25\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_65\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0\,
      Q => idel_pat0_match_rise3_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_57\,
      Q => pat0_match_fall0_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_33\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_41\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_17\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0\,
      Q => pat0_match_fall3_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_49\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0\,
      Q => idel_pat1_match_rise1_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_65\,
      Q => pat0_match_rise3_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_25\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0\,
      Q => pat0_match_rise2_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_9\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => idel_pat0_match_fall0_and_r,
      I1 => idel_pat0_match_rise1_and_r,
      I2 => idel_pat0_match_rise3_and_r,
      I3 => idel_pat0_match_fall3_and_r,
      I4 => \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0\,
      O => idel_pat0_data_match_r0
    );
\gen_pat_match_div4.idel_pat0_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => idel_pat0_match_fall1_and_r,
      I1 => idel_pat0_match_fall2_and_r,
      I2 => idel_pat0_match_rise0_and_r,
      I3 => idel_pat0_match_rise2_and_r,
      O => \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat0_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idel_pat0_data_match_r0,
      Q => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\,
      I3 => pat0_match_fall0_r(2),
      I4 => pat0_match_fall0_r(5),
      I5 => pat0_match_fall0_r(6),
      O => \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0\,
      Q => idel_pat0_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\,
      I3 => pat0_match_fall1_r(1),
      I4 => pat0_match_fall1_r(5),
      I5 => pat0_match_fall1_r(7),
      O => \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0\,
      Q => idel_pat0_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0\,
      I2 => pat0_match_fall2_r(3),
      O => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\,
      I2 => pat0_match_fall2_r(0),
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg\,
      I4 => pat0_match_fall2_r(4),
      I5 => pat0_match_fall2_r(7),
      O => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0\,
      Q => idel_pat0_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\,
      I2 => pat0_match_fall3_r(6),
      I3 => pat0_match_fall3_r(4),
      I4 => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat0_match_fall3_r(0),
      I1 => pat0_match_fall3_r(2),
      I2 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0\,
      Q => idel_pat0_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\,
      I3 => pat0_match_rise0_r(7),
      I4 => pat0_match_rise0_r(3),
      O => \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0\,
      Q => idel_pat0_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\,
      I1 => idel_pat1_match_rise1_r(5),
      I2 => idel_pat1_match_rise1_r(1),
      I3 => pat0_match_rise1_r(4),
      I4 => pat0_match_rise1_r(0),
      O => \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0\,
      Q => idel_pat0_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pat0_match_rise2_r(6),
      I1 => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\,
      I3 => pat0_match_rise2_r(2),
      I4 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0\,
      Q => idel_pat0_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\,
      I1 => idel_pat0_match_rise3_r(6),
      I2 => idel_pat0_match_rise3_r(2),
      I3 => idel_pat0_match_rise3_r(5),
      I4 => idel_pat0_match_rise3_r(1),
      O => \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0\,
      Q => idel_pat0_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => idel_pat1_match_rise1_and_r,
      I1 => idel_pat1_match_fall1_and_r,
      I2 => idel_pat1_match_rise3_and_r,
      I3 => idel_pat1_match_fall0_and_r,
      I4 => \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0\,
      O => idel_pat1_data_match_r0
    );
\gen_pat_match_div4.idel_pat1_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => idel_pat1_match_fall2_and_r,
      I1 => idel_pat1_match_rise2_and_r,
      I2 => idel_pat1_match_rise0_and_r,
      I3 => idel_pat1_match_fall3_and_r,
      O => \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat1_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idel_pat1_data_match_r0,
      Q => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0\,
      I2 => pat0_match_fall0_r(7),
      O => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg\,
      I1 => pat0_match_fall0_r(3),
      I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0\,
      Q => idel_pat1_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => pat0_match_fall1_r(4),
      I1 => pat0_match_fall1_r(0),
      I2 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0\,
      Q => idel_pat1_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => pat0_match_fall2_r(6),
      I1 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\,
      I3 => pat0_match_fall2_r(5),
      I4 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0\,
      Q => idel_pat1_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0\,
      Q => idel_pat1_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0\,
      Q => idel_pat1_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\,
      I1 => idel_pat1_match_rise1_r(6),
      I2 => idel_pat1_match_rise1_r(2),
      I3 => idel_pat1_match_rise1_r(7),
      I4 => idel_pat1_match_rise1_r(3),
      O => \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0\,
      Q => idel_pat1_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\,
      I1 => pat0_match_rise2_r(4),
      I2 => \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\,
      I3 => pat0_match_rise2_r(1),
      I4 => pat0_match_rise2_r(5),
      I5 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0\,
      Q => idel_pat1_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\,
      I1 => idel_pat0_match_rise3_r(5),
      I2 => idel_pat0_match_rise3_r(1),
      I3 => pat0_match_rise3_r(6),
      I4 => pat0_match_rise3_r(2),
      O => \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0\,
      Q => idel_pat1_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pat0_match_rise1_and_r,
      I1 => pat0_match_fall2_and_r,
      I2 => pat0_match_rise3_and_r,
      I3 => pat0_match_fall0_and_r,
      I4 => \gen_pat_match_div4.pat0_data_match_r_i_2_n_0\,
      O => pat0_data_match_r0
    );
\gen_pat_match_div4.pat0_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat0_match_rise2_and_r,
      I1 => pat0_match_fall1_and_r,
      I2 => pat0_match_rise0_and_r,
      I3 => pat0_match_fall3_and_r,
      O => \gen_pat_match_div4.pat0_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pat0_data_match_r0,
      Q => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_fall0_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pat0_match_fall0_r(6),
      I1 => \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0\,
      I2 => pat0_match_fall0_r(7),
      O => \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_fall0_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => pat0_match_fall0_r(4),
      I1 => pat0_match_fall0_r(2),
      I2 => pat0_match_fall0_r(0),
      I3 => pat0_match_fall0_r(1),
      I4 => pat0_match_fall0_r(3),
      I5 => pat0_match_fall0_r(5),
      O => \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0\,
      Q => pat0_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_fall1_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pat0_match_fall1_r(6),
      I1 => \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0\,
      I2 => pat0_match_fall1_r(7),
      O => \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_fall1_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => pat0_match_fall1_r(4),
      I1 => pat0_match_fall1_r(1),
      I2 => pat0_match_fall1_r(3),
      I3 => pat0_match_fall1_r(2),
      I4 => pat0_match_fall1_r(0),
      I5 => pat0_match_fall1_r(5),
      O => \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0\,
      Q => pat0_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => pat0_match_fall2_r(7),
      I1 => pat0_match_fall2_r(5),
      I2 => \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\,
      I3 => pat0_match_fall2_r(6),
      I4 => pat0_match_fall2_r(3),
      O => \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pat0_match_fall2_r(2),
      I1 => pat0_match_fall2_r(1),
      I2 => pat0_match_fall2_r(0),
      I3 => pat0_match_fall2_r(4),
      O => \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0\,
      Q => pat0_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\,
      I1 => pat0_match_fall3_r(4),
      I2 => pat0_match_fall3_r(1),
      I3 => pat0_match_fall3_r(5),
      I4 => pat0_match_fall3_r(0),
      O => \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pat0_match_fall3_r(2),
      I1 => pat0_match_fall3_r(7),
      I2 => pat0_match_fall3_r(3),
      I3 => pat0_match_fall3_r(6),
      O => \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0\,
      Q => pat0_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\,
      I1 => pat0_match_rise0_r(5),
      I2 => pat0_match_rise0_r(1),
      I3 => pat0_match_rise0_r(4),
      I4 => pat0_match_rise0_r(0),
      O => \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pat0_match_rise0_r(2),
      I1 => pat0_match_rise0_r(6),
      I2 => pat0_match_rise0_r(3),
      I3 => pat0_match_rise0_r(7),
      O => \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0\,
      Q => pat0_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\,
      I1 => pat0_match_rise1_r(5),
      I2 => pat0_match_rise1_r(1),
      I3 => pat0_match_rise1_r(4),
      I4 => pat0_match_rise1_r(0),
      O => \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pat0_match_rise1_r(3),
      I1 => pat0_match_rise1_r(7),
      I2 => pat0_match_rise1_r(2),
      I3 => pat0_match_rise1_r(6),
      O => \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0\,
      Q => pat0_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_rise2_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pat0_match_rise2_r(7),
      I1 => \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0\,
      I2 => pat0_match_rise2_r(6),
      O => \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_rise2_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => pat0_match_rise2_r(4),
      I1 => pat0_match_rise2_r(2),
      I2 => pat0_match_rise2_r(0),
      I3 => pat0_match_rise2_r(1),
      I4 => pat0_match_rise2_r(3),
      I5 => pat0_match_rise2_r(5),
      O => \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0\,
      Q => pat0_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => pat0_match_rise3_r(6),
      I1 => pat0_match_rise3_r(2),
      I2 => pat0_match_rise3_r(5),
      I3 => pat0_match_rise3_r(1),
      I4 => \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pat0_match_rise3_r(3),
      I1 => pat0_match_rise3_r(7),
      I2 => pat0_match_rise3_r(0),
      I3 => pat0_match_rise3_r(4),
      O => \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0\,
      Q => pat0_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pat1_match_fall0_and_r,
      I1 => pat1_match_rise1_and_r,
      I2 => pat1_match_rise3_and_r,
      I3 => pat1_match_fall2_and_r,
      I4 => \gen_pat_match_div4.pat1_data_match_r_i_2_n_0\,
      O => pat1_data_match_r0
    );
\gen_pat_match_div4.pat1_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat1_match_rise2_and_r,
      I1 => pat1_match_fall1_and_r,
      I2 => pat1_match_rise0_and_r,
      I3 => pat1_match_fall3_and_r,
      O => \gen_pat_match_div4.pat1_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pat1_data_match_r0,
      Q => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_fall0_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\,
      I4 => pat0_match_fall0_r(5),
      I5 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_fall0_and_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\,
      I1 => pat0_match_fall0_r(1),
      I2 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0\,
      Q => pat1_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_fall1_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\,
      I5 => pat0_match_fall1_r(7),
      O => \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_fall1_and_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pat0_match_fall1_r(3),
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0\,
      Q => pat1_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_fall2_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_fall2_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\,
      I2 => pat0_match_fall2_r(1),
      I3 => \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\,
      I5 => pat0_match_fall2_r(5),
      O => \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0\,
      Q => pat1_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\,
      I2 => pat0_match_fall3_r(7),
      I3 => pat0_match_fall3_r(5),
      I4 => \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat0_match_fall3_r(1),
      I1 => pat0_match_fall3_r(3),
      I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0\,
      Q => pat1_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pat0_match_rise0_r(0),
      I1 => pat0_match_rise0_r(4),
      I2 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0\,
      Q => pat1_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\,
      I1 => idel_pat1_match_rise1_r(7),
      I2 => idel_pat1_match_rise1_r(3),
      I3 => pat0_match_rise1_r(6),
      I4 => pat0_match_rise1_r(2),
      O => \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => idel_pat1_match_rise1_r(0),
      I1 => idel_pat1_match_rise1_r(4),
      I2 => idel_pat1_match_rise1_r(1),
      I3 => idel_pat1_match_rise1_r(5),
      O => \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0\,
      Q => pat1_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_rise2_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\,
      I1 => pat0_match_rise2_r(4),
      I2 => \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_rise2_and_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg\,
      I2 => pat0_match_rise2_r(0),
      O => \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0\,
      Q => pat1_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => pat0_match_rise3_r(6),
      I1 => pat0_match_rise3_r(2),
      I2 => pat0_match_rise3_r(5),
      I3 => pat0_match_rise3_r(1),
      I4 => \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => idel_pat0_match_rise3_r(4),
      I1 => idel_pat0_match_rise3_r(7),
      I2 => idel_pat0_match_rise3_r(0),
      I3 => idel_pat0_match_rise3_r(3),
      O => \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0\,
      Q => pat1_match_rise3_and_r,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_50\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_26\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_34\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_10\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_2\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_42\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_18\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_58\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_51\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_27\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_35\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_11\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_3\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_43\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_19\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_59\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_52\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_28\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_36\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_12\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_4\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_44\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_20\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_60\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_53\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_29\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_37\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_13\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_5\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_45\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_21\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_61\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_54\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_30\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_38\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_14\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_6\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_46\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_22\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_62\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_55\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_31\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_39\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_15\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_7\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_47\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_23\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_63\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_56\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_32\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_40\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_16\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_8\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_48\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_24\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_64\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_57\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_33\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_41\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_17\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_9\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_49\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_25\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_65\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0]\,
      I4 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0\,
      O => p_490_out
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0]\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_490_out,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_50\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_146\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_26\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_162\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_34\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_130\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_10\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_138\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_2\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_178\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_42\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_154\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_18\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_170\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_58\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_186\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sr_valid_r2,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0]\,
      I4 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0\,
      O => p_515_out
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0]\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_515_out,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_50\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_98\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_26\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_74\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_34\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_82\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_10\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_106\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_2\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_114\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_42\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_66\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_18\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_90\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_58\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_122\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_diff_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0\,
      Q => p_1_in17_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in438_in,
      I1 => p_5_in436_in,
      I2 => p_6_in437_in,
      I3 => p_1_in439_in,
      I4 => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0\,
      O => p_440_out
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_3_in434_in,
      I1 => p_4_in435_in,
      I2 => p_2_in433_in,
      I3 => p_0_in432_in,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_440_out,
      Q => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_51\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_147\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0\,
      Q => p_0_in432_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_27\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_163\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0\,
      Q => p_3_in434_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_35\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_131\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0\,
      Q => p_5_in436_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_11\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_139\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0\,
      Q => p_7_in438_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_3\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_179\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0\,
      Q => p_1_in439_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_43\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_155\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0\,
      Q => p_2_in433_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_19\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_171\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0\,
      Q => p_4_in435_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_59\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_187\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0\,
      Q => p_6_in437_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_diff_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0\,
      Q => p_0_in103_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_6_in462_in,
      I1 => p_5_in461_in,
      I2 => p_7_in463_in,
      I3 => p_1_in464_in,
      I4 => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0\,
      O => p_465_out
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_3_in459_in,
      I1 => p_4_in460_in,
      I2 => p_2_in458_in,
      I3 => p_0_in457_in,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_465_out,
      Q => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_51\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_99\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0\,
      Q => p_0_in457_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_27\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_75\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0\,
      Q => p_3_in459_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_35\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_83\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0\,
      Q => p_5_in461_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_11\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_107\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0\,
      Q => p_7_in463_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_3\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_115\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0\,
      Q => p_1_in464_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_43\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_67\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0\,
      Q => p_2_in458_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_19\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_91\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0\,
      Q => p_4_in460_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_59\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_123\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0\,
      Q => p_6_in462_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_diff_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0\,
      Q => p_1_in14_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in388_in,
      I1 => p_6_in387_in,
      I2 => p_5_in386_in,
      I3 => p_1_in389_in,
      I4 => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0\,
      O => p_390_out
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_3_in384_in,
      I1 => p_4_in385_in,
      I2 => p_0_in382_in,
      I3 => p_2_in383_in,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_390_out,
      Q => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_52\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_148\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0\,
      Q => p_0_in382_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_28\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_164\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0\,
      Q => p_3_in384_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_36\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_132\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0\,
      Q => p_5_in386_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_12\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_140\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0\,
      Q => p_7_in388_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_4\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_180\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0\,
      Q => p_1_in389_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_44\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_156\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0\,
      Q => p_2_in383_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_20\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_172\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0\,
      Q => p_4_in385_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_60\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_188\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0\,
      Q => p_6_in387_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_diff_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0\,
      Q => p_0_in100_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in413_in,
      I1 => p_5_in411_in,
      I2 => p_6_in412_in,
      I3 => p_1_in414_in,
      I4 => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0\,
      O => p_415_out
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_3_in409_in,
      I1 => p_4_in410_in,
      I2 => p_2_in408_in,
      I3 => p_0_in407_in,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_415_out,
      Q => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_52\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_100\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0\,
      Q => p_0_in407_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_28\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_76\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0\,
      Q => p_3_in409_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_36\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_84\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0\,
      Q => p_5_in411_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_12\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_108\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0\,
      Q => p_7_in413_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_4\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_116\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0\,
      Q => p_1_in414_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_44\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_68\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0\,
      Q => p_2_in408_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_20\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_92\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0\,
      Q => p_4_in410_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_60\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_124\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0\,
      Q => p_6_in412_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_diff_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0\,
      Q => p_1_in11_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in338_in,
      I1 => p_6_in337_in,
      I2 => p_3_in334_in,
      I3 => p_1_in339_in,
      I4 => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0\,
      O => p_340_out
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in335_in,
      I1 => p_5_in336_in,
      I2 => p_0_in332_in,
      I3 => p_2_in333_in,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_340_out,
      Q => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_53\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_149\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0\,
      Q => p_0_in332_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_29\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_165\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0\,
      Q => p_3_in334_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_37\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_133\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0\,
      Q => p_5_in336_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_13\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_141\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0\,
      Q => p_7_in338_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_5\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_181\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0\,
      Q => p_1_in339_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_45\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_157\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0\,
      Q => p_2_in333_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_21\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_173\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0\,
      Q => p_4_in335_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_61\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_189\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0\,
      Q => p_6_in337_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_diff_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0\,
      Q => p_0_in97_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_5_in361_in,
      I1 => p_4_in360_in,
      I2 => p_7_in363_in,
      I3 => p_6_in362_in,
      I4 => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0\,
      O => p_365_out
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_0_in357_in,
      I1 => p_3_in359_in,
      I2 => p_2_in358_in,
      I3 => p_1_in364_in,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_365_out,
      Q => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_53\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_101\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0\,
      Q => p_0_in357_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_29\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_77\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0\,
      Q => p_3_in359_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_37\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_85\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0\,
      Q => p_5_in361_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_13\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_109\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0\,
      Q => p_7_in363_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_5\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_117\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0\,
      Q => p_1_in364_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_45\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_69\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0\,
      Q => p_2_in358_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_21\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_93\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0\,
      Q => p_4_in360_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_61\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_125\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0\,
      Q => p_6_in362_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_diff_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0\,
      Q => p_1_in8_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in288_in,
      I1 => p_6_in287_in,
      I2 => p_0_in282_in,
      I3 => p_1_in289_in,
      I4 => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0\,
      O => p_290_out
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in285_in,
      I1 => p_5_in286_in,
      I2 => p_2_in283_in,
      I3 => p_3_in284_in,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_290_out,
      Q => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_54\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_150\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0\,
      Q => p_0_in282_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_30\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_166\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0\,
      Q => p_3_in284_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_38\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_134\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0\,
      Q => p_5_in286_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_14\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_142\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0\,
      Q => p_7_in288_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_6\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_182\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0\,
      Q => p_1_in289_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_46\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_158\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0\,
      Q => p_2_in283_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_22\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_174\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0\,
      Q => p_4_in285_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_62\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_190\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0\,
      Q => p_6_in287_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_diff_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0\,
      Q => p_0_in94_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_6_in312_in,
      I1 => p_5_in311_in,
      I2 => p_7_in313_in,
      I3 => p_1_in314_in,
      I4 => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0\,
      O => p_315_out
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_3_in309_in,
      I1 => p_4_in310_in,
      I2 => p_0_in307_in,
      I3 => p_2_in308_in,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_315_out,
      Q => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_54\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_102\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0\,
      Q => p_0_in307_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_30\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_78\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0\,
      Q => p_3_in309_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_38\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_86\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0\,
      Q => p_5_in311_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_14\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_110\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0\,
      Q => p_7_in313_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_6\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_118\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0\,
      Q => p_1_in314_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_46\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_70\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0\,
      Q => p_2_in308_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_22\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_94\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0\,
      Q => p_4_in310_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_62\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_126\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0\,
      Q => p_6_in312_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_diff_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0\,
      Q => p_1_in5_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in238_in,
      I1 => p_6_in237_in,
      I2 => p_0_in232_in,
      I3 => p_1_in239_in,
      I4 => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0\,
      O => p_240_out
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in235_in,
      I1 => p_5_in236_in,
      I2 => p_2_in233_in,
      I3 => p_3_in234_in,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_240_out,
      Q => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_55\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_151\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0\,
      Q => p_0_in232_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_31\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_167\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0\,
      Q => p_3_in234_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_39\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_135\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0\,
      Q => p_5_in236_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_15\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_143\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0\,
      Q => p_7_in238_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_7\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_183\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0\,
      Q => p_1_in239_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_47\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_159\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0\,
      Q => p_2_in233_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_23\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_175\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0\,
      Q => p_4_in235_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_63\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_191\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0\,
      Q => p_6_in237_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_diff_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0\,
      Q => p_0_in91_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in263_in,
      I1 => p_6_in262_in,
      I2 => p_0_in257_in,
      I3 => p_1_in264_in,
      I4 => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0\,
      O => p_265_out
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in260_in,
      I1 => p_5_in261_in,
      I2 => p_2_in258_in,
      I3 => p_3_in259_in,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_265_out,
      Q => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_55\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_103\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0\,
      Q => p_0_in257_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_31\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_79\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0\,
      Q => p_3_in259_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_39\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_87\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0\,
      Q => p_5_in261_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_15\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_111\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0\,
      Q => p_7_in263_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_7\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_119\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0\,
      Q => p_1_in264_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_47\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_71\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0\,
      Q => p_2_in258_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_23\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_95\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0\,
      Q => p_4_in260_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_63\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_127\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0\,
      Q => p_6_in262_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_diff_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0\,
      Q => p_1_in2_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in188_in,
      I1 => p_6_in187_in,
      I2 => p_0_in182_in,
      I3 => p_1_in189_in,
      I4 => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0\,
      O => p_190_out
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in185_in,
      I1 => p_5_in186_in,
      I2 => p_2_in183_in,
      I3 => p_3_in184_in,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_190_out,
      Q => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_56\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_152\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0\,
      Q => p_0_in182_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_32\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_168\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0\,
      Q => p_3_in184_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_40\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_136\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0\,
      Q => p_5_in186_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_16\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_144\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0\,
      Q => p_7_in188_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_8\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_184\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0\,
      Q => p_1_in189_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_48\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_160\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0\,
      Q => p_2_in183_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_24\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_176\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0\,
      Q => p_4_in185_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_64\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_192\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0\,
      Q => p_6_in187_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_diff_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0\,
      Q => p_0_in88_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in213_in,
      I1 => p_6_in212_in,
      I2 => p_0_in207_in,
      I3 => p_1_in214_in,
      I4 => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0\,
      O => p_215_out
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in210_in,
      I1 => p_5_in211_in,
      I2 => p_2_in208_in,
      I3 => p_3_in209_in,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_215_out,
      Q => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_56\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_104\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0\,
      Q => p_0_in207_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_32\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_80\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0\,
      Q => p_3_in209_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_40\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_88\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0\,
      Q => p_5_in211_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_16\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_112\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0\,
      Q => p_7_in213_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_8\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_120\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0\,
      Q => p_1_in214_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_48\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_72\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0\,
      Q => p_2_in208_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_24\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_96\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0\,
      Q => p_4_in210_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_64\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_128\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0\,
      Q => p_6_in212_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7]\,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in,
      I1 => p_6_in137_in,
      I2 => p_0_in135_in,
      I3 => p_1_in138_in,
      I4 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0\,
      O => p_139_out
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7]\,
      I1 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7]\,
      I2 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7]\,
      I3 => p_3_in136_in,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_139_out,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_57\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_153\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0\,
      Q => p_0_in135_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_33\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_169\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0\,
      Q => p_3_in136_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_41\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_137\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_17\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_145\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0\,
      Q => p_7_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_9\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_185\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0\,
      Q => p_1_in138_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_49\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_161\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_25\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_177\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_65\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_193\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0\,
      Q => p_6_in137_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_7_in163_in,
      I1 => p_6_in162_in,
      I2 => p_0_in157_in,
      I3 => p_1_in164_in,
      I4 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0\,
      O => p_165_out
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_4_in160_in,
      I1 => p_5_in161_in,
      I2 => p_2_in158_in,
      I3 => p_3_in159_in,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_165_out,
      Q => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_57\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_105\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0\,
      Q => p_0_in157_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_33\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_81\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0\,
      Q => p_3_in159_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_41\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_89\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0\,
      Q => p_5_in161_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_17\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_113\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0\,
      Q => p_7_in163_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_9\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_121\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0\,
      Q => p_1_in164_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_49\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_73\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0\,
      Q => p_2_in158_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_25\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_97\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0\,
      Q => p_4_in160_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_65\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_129\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0\,
      Q => p_6_in162_in,
      R => '0'
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(0),
      O => \p_0_in__2\(0)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(1),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(0),
      O => \p_0_in__2\(1)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(2),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(0),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(1),
      O => \p_0_in__2\(2)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(3),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(1),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(0),
      I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(2),
      O => \p_0_in__2\(3)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      I4 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\,
      O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(0),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => pb_cnt_eye_size_r
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(4),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(2),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(0),
      I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(1),
      I4 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(3),
      O => \p_0_in__2\(4)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(0),
      I2 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\,
      I4 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(2),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(0),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(1),
      I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(3),
      I4 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(4),
      O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__2\(0),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(0),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__2\(1),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(1),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__2\(2),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(2),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__2\(3),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(3),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__2\(4),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_194\(4),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(0),
      O => \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0\,
      Q => pb_detect_edge_done_r(0),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[0].pb_found_edge_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555501000101"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(0),
      I2 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_3_n_0\,
      I3 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      O => \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_found_edge_r[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_34_in,
      I1 => store_sr_req_pulsed_r,
      O => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\
    );
\gen_track_left_edge[0].pb_found_edge_r[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\,
      I3 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      O => \gen_track_left_edge[0].pb_found_edge_r[0]_i_3_n_0\
    );
\gen_track_left_edge[0].pb_found_edge_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0\,
      Q => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      I5 => pb_found_stable_eye_r(0),
      O => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0\,
      Q => pb_found_stable_eye_r(0),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(0),
      I2 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      I4 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0\,
      Q => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(0),
      O => \p_0_in__3\(0)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(1),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(0),
      O => \p_0_in__3\(1)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(2),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(0),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(1),
      O => \p_0_in__3\(2)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(3),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(1),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(0),
      I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(2),
      O => \p_0_in__3\(3)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in16_in,
      I4 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\,
      O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(1),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(4),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(2),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(0),
      I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(1),
      I4 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(3),
      O => \p_0_in__3\(4)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(1),
      I2 => p_0_in16_in,
      I3 => p_1_in17_in,
      I4 => p_0_in103_in,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(2),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(0),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(1),
      I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(3),
      I4 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(4),
      O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__3\(0),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(0),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__3\(1),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(1),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__3\(2),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(2),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__3\(3),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(3),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__3\(4),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_195\(4),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => p_0_in103_in,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(1),
      O => \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0\,
      Q => pb_detect_edge_done_r(1),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[1].pb_found_edge_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(1),
      I2 => \gen_track_left_edge[1].pb_found_edge_r[1]_i_2_n_0\,
      I3 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in16_in,
      O => \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_found_edge_r[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in103_in,
      I2 => p_1_in17_in,
      I3 => p_0_in16_in,
      O => \gen_track_left_edge[1].pb_found_edge_r[1]_i_2_n_0\
    );
\gen_track_left_edge[1].pb_found_edge_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0\,
      Q => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in16_in,
      I5 => pb_found_stable_eye_r(1),
      O => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0\,
      Q => pb_found_stable_eye_r(1),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(1),
      I2 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I3 => p_0_in103_in,
      I4 => p_0_in16_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_last_tap_jitter_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0\,
      Q => p_0_in16_in,
      R => '0'
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(0),
      O => \p_0_in__4\(0)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(1),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(0),
      O => \p_0_in__4\(1)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(2),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(0),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(1),
      O => \p_0_in__4\(2)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(3),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(1),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(0),
      I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(2),
      O => \p_0_in__4\(3)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in13_in,
      I4 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\,
      O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(2),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(4),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(2),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(0),
      I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(1),
      I4 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(3),
      O => \p_0_in__4\(4)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(2),
      I2 => p_0_in13_in,
      I3 => p_1_in14_in,
      I4 => p_0_in100_in,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(2),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(0),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(1),
      I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(3),
      I4 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(4),
      O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__4\(0),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(0),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__4\(1),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(1),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__4\(2),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(2),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__4\(3),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(3),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__4\(4),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_196\(4),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => p_0_in100_in,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(2),
      O => \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0\,
      Q => pb_detect_edge_done_r(2),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[2].pb_found_edge_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(2),
      I2 => \gen_track_left_edge[2].pb_found_edge_r[2]_i_2_n_0\,
      I3 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in13_in,
      O => \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_found_edge_r[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in100_in,
      I2 => p_1_in14_in,
      I3 => p_0_in13_in,
      O => \gen_track_left_edge[2].pb_found_edge_r[2]_i_2_n_0\
    );
\gen_track_left_edge[2].pb_found_edge_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0\,
      Q => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in13_in,
      I5 => pb_found_stable_eye_r(2),
      O => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0\,
      Q => pb_found_stable_eye_r(2),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(2),
      I2 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I3 => p_0_in100_in,
      I4 => p_0_in13_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_last_tap_jitter_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0\,
      Q => p_0_in13_in,
      R => '0'
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(0),
      O => \p_0_in__5\(0)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(1),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(0),
      O => \p_0_in__5\(1)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(2),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(0),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(1),
      O => \p_0_in__5\(2)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(3),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(1),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(0),
      I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(2),
      O => \p_0_in__5\(3)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in10_in,
      I4 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\,
      O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(3),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(4),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(2),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(0),
      I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(1),
      I4 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(3),
      O => \p_0_in__5\(4)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(3),
      I2 => p_0_in10_in,
      I3 => p_1_in11_in,
      I4 => p_0_in97_in,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(2),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(0),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(1),
      I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(3),
      I4 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(4),
      O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__5\(0),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(0),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__5\(1),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(1),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__5\(2),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(2),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__5\(3),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(3),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__5\(4),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_197\(4),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => p_0_in97_in,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(3),
      O => \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0\,
      Q => pb_detect_edge_done_r(3),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[3].pb_found_edge_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(3),
      I2 => \gen_track_left_edge[3].pb_found_edge_r[3]_i_2_n_0\,
      I3 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in10_in,
      O => \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_found_edge_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in97_in,
      I2 => p_1_in11_in,
      I3 => p_0_in10_in,
      O => \gen_track_left_edge[3].pb_found_edge_r[3]_i_2_n_0\
    );
\gen_track_left_edge[3].pb_found_edge_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0\,
      Q => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in10_in,
      I5 => pb_found_stable_eye_r(3),
      O => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0\,
      Q => pb_found_stable_eye_r(3),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(3),
      I2 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I3 => p_0_in97_in,
      I4 => p_0_in10_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_last_tap_jitter_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0\,
      Q => p_0_in10_in,
      R => '0'
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(0),
      O => \p_0_in__6\(0)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(1),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(0),
      O => \p_0_in__6\(1)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(2),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(0),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(1),
      O => \p_0_in__6\(2)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(3),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(1),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(0),
      I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(2),
      O => \p_0_in__6\(3)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in7_in,
      I4 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\,
      O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(4),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(4),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(2),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(0),
      I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(1),
      I4 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(3),
      O => \p_0_in__6\(4)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(4),
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      I4 => p_0_in94_in,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(2),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(0),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(1),
      I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(3),
      I4 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(4),
      O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__6\(0),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(0),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__6\(1),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(1),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__6\(2),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(2),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__6\(3),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(3),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__6\(4),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_198\(4),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => p_0_in94_in,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(4),
      O => \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0\,
      Q => pb_detect_edge_done_r(4),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[4].pb_found_edge_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(4),
      I2 => \gen_track_left_edge[4].pb_found_edge_r[4]_i_2_n_0\,
      I3 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in7_in,
      O => \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_found_edge_r[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in94_in,
      I2 => p_1_in8_in,
      I3 => p_0_in7_in,
      O => \gen_track_left_edge[4].pb_found_edge_r[4]_i_2_n_0\
    );
\gen_track_left_edge[4].pb_found_edge_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0\,
      Q => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in7_in,
      I5 => pb_found_stable_eye_r(4),
      O => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0\,
      Q => pb_found_stable_eye_r(4),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(4),
      I2 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I3 => p_0_in94_in,
      I4 => p_0_in7_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_last_tap_jitter_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0\,
      Q => p_0_in7_in,
      R => '0'
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(0),
      O => \p_0_in__7\(0)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(1),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(0),
      O => \p_0_in__7\(1)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(2),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(0),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(1),
      O => \p_0_in__7\(2)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(3),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(1),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(0),
      I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(2),
      O => \p_0_in__7\(3)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in4_in,
      I4 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\,
      O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(5),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(4),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(2),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(0),
      I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(1),
      I4 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(3),
      O => \p_0_in__7\(4)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(5),
      I2 => p_0_in4_in,
      I3 => p_1_in5_in,
      I4 => p_0_in91_in,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(2),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(0),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(1),
      I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(3),
      I4 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(4),
      O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__7\(0),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(0),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__7\(1),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(1),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__7\(2),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(2),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__7\(3),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(3),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__7\(4),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_199\(4),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => p_0_in91_in,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(5),
      O => \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0\,
      Q => pb_detect_edge_done_r(5),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[5].pb_found_edge_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(5),
      I2 => \gen_track_left_edge[5].pb_found_edge_r[5]_i_2_n_0\,
      I3 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in4_in,
      O => \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_found_edge_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in91_in,
      I2 => p_1_in5_in,
      I3 => p_0_in4_in,
      O => \gen_track_left_edge[5].pb_found_edge_r[5]_i_2_n_0\
    );
\gen_track_left_edge[5].pb_found_edge_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0\,
      Q => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in4_in,
      I5 => pb_found_stable_eye_r(5),
      O => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0\,
      Q => pb_found_stable_eye_r(5),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(5),
      I2 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I3 => p_0_in91_in,
      I4 => p_0_in4_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_last_tap_jitter_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0\,
      Q => p_0_in4_in,
      R => '0'
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(0),
      O => \p_0_in__8\(0)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(1),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(0),
      O => \p_0_in__8\(1)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(2),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(0),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(1),
      O => \p_0_in__8\(2)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(3),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(1),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(0),
      I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(2),
      O => \p_0_in__8\(3)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in1_in,
      I4 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\,
      O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(6),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(4),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(2),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(0),
      I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(1),
      I4 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(3),
      O => \p_0_in__8\(4)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(6),
      I2 => p_0_in1_in,
      I3 => p_1_in2_in,
      I4 => p_0_in88_in,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(2),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(0),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(1),
      I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(3),
      I4 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(4),
      O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__8\(0),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(0),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__8\(1),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(1),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__8\(2),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(2),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__8\(3),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(3),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__8\(4),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_200\(4),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => p_0_in88_in,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(6),
      O => \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0\,
      Q => pb_detect_edge_done_r(6),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[6].pb_found_edge_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(6),
      I2 => \gen_track_left_edge[6].pb_found_edge_r[6]_i_2_n_0\,
      I3 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in1_in,
      O => \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_found_edge_r[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in88_in,
      I2 => p_1_in2_in,
      I3 => p_0_in1_in,
      O => \gen_track_left_edge[6].pb_found_edge_r[6]_i_2_n_0\
    );
\gen_track_left_edge[6].pb_found_edge_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0\,
      Q => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in1_in,
      I5 => pb_found_stable_eye_r(6),
      O => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0\,
      Q => pb_found_stable_eye_r(6),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(6),
      I2 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I3 => p_0_in88_in,
      I4 => p_0_in1_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_last_tap_jitter_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0\,
      Q => p_0_in1_in,
      R => '0'
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(0),
      O => \p_0_in__9\(0)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(1),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(0),
      O => \p_0_in__9\(1)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(2),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(0),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(1),
      O => \p_0_in__9\(2)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(3),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(1),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(0),
      I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(2),
      O => \p_0_in__9\(3)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => p_0_in,
      I4 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\,
      O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\,
      I1 => pb_detect_edge_done_r(7),
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(4),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(2),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(0),
      I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(1),
      I4 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(3),
      O => \p_0_in__9\(4)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(7),
      I2 => p_0_in,
      I3 => \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7]\,
      I4 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      I5 => samp_cnt_done_r_reg_n_0,
      O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(2),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(0),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(1),
      I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(3),
      I4 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(4),
      O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__9\(0),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(0),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__9\(1),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(1),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__9\(2),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(2),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__9\(3),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(3),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__9\(4),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_201\(4),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      I2 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => pb_detect_edge_done_r(7),
      O => \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0\,
      Q => pb_detect_edge_done_r(7),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[7].pb_found_edge_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5501550155005501"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(7),
      I2 => \gen_track_left_edge[7].pb_found_edge_r[7]_i_2_n_0\,
      I3 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      I4 => samp_cnt_done_r_reg_n_0,
      I5 => p_0_in,
      O => \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_found_edge_r[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      I2 => \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7]\,
      I3 => p_0_in,
      O => \gen_track_left_edge[7].pb_found_edge_r[7]_i_2_n_0\
    );
\gen_track_left_edge[7].pb_found_edge_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0\,
      Q => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555F5500000800"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\,
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\,
      I2 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in,
      I5 => pb_found_stable_eye_r(7),
      O => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0\,
      Q => pb_found_stable_eye_r(7),
      R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\
    );
\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(7),
      I2 => \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0\,
      I3 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      I4 => p_0_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      O => \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0\,
      Q => p_0_in,
      R => '0'
    );
idel_adj_inc_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C580"
    )
        port map (
      I0 => \idel_dec_cnt[4]_i_3_n_0\,
      I1 => cal1_wait_r,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I3 => idel_adj_inc_reg_n_0,
      O => idel_adj_inc_i_1_n_0
    );
idel_adj_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idel_adj_inc_i_1_n_0,
      Q => idel_adj_inc_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\idel_dec_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80FFFF8A808A80"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][1][0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][0][0]\,
      I4 => \idel_dec_cnt_reg_n_0_[0]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => idel_dec_cnt(0)
    );
\idel_dec_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F88F8888"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => idelay_tap_cnt_r(1),
      I2 => \idel_dec_cnt_reg_n_0_[1]\,
      I3 => \idel_dec_cnt_reg_n_0_[0]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => idel_dec_cnt(1)
    );
\idel_dec_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F88F88888888"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => idelay_tap_cnt_r(2),
      I2 => \idel_dec_cnt_reg_n_0_[2]\,
      I3 => \idel_dec_cnt_reg_n_0_[0]\,
      I4 => \idel_dec_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => idel_dec_cnt(2)
    );
\idel_dec_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8FF88888"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => idelay_tap_cnt_r(3),
      I2 => \idel_dec_cnt_reg_n_0_[3]\,
      I3 => \idel_dec_cnt[3]_i_2_n_0\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => idel_dec_cnt(3)
    );
\idel_dec_cnt[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \idel_dec_cnt_reg_n_0_[0]\,
      I1 => \idel_dec_cnt_reg_n_0_[1]\,
      I2 => \idel_dec_cnt_reg_n_0_[2]\,
      O => \idel_dec_cnt[3]_i_2_n_0\
    );
\idel_dec_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEEFEEEFFFFFEEE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[15]_i_2_n_0\,
      I1 => \idel_dec_cnt[4]_i_3_n_0\,
      I2 => \FSM_onehot_cal1_state_r[22]_i_2_n_0\,
      I3 => idel_mpr_pat_detect_r,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      I5 => \idel_dec_cnt[4]_i_4_n_0\,
      O => \idel_dec_cnt[4]_i_1_n_0\
    );
\idel_dec_cnt[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8FF88888"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\,
      I1 => idelay_tap_cnt_r(4),
      I2 => \idel_dec_cnt_reg_n_0_[4]\,
      I3 => \idel_dec_cnt[4]_i_5_n_0\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      O => idel_dec_cnt(4)
    );
\idel_dec_cnt[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => detect_edge_done_r,
      I1 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      I2 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      I3 => p_34_in,
      O => \idel_dec_cnt[4]_i_3_n_0\
    );
\idel_dec_cnt[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \idel_dec_cnt_reg_n_0_[3]\,
      I1 => \idel_dec_cnt_reg_n_0_[0]\,
      I2 => \idel_dec_cnt_reg_n_0_[1]\,
      I3 => \idel_dec_cnt_reg_n_0_[2]\,
      I4 => \idel_dec_cnt_reg_n_0_[4]\,
      O => \idel_dec_cnt[4]_i_4_n_0\
    );
\idel_dec_cnt[4]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \idel_dec_cnt_reg_n_0_[2]\,
      I1 => \idel_dec_cnt_reg_n_0_[1]\,
      I2 => \idel_dec_cnt_reg_n_0_[0]\,
      I3 => \idel_dec_cnt_reg_n_0_[3]\,
      O => \idel_dec_cnt[4]_i_5_n_0\
    );
\idel_dec_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(0),
      Q => \idel_dec_cnt_reg_n_0_[0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\idel_dec_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(1),
      Q => \idel_dec_cnt_reg_n_0_[1]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\idel_dec_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(2),
      Q => \idel_dec_cnt_reg_n_0_[2]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\idel_dec_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(3),
      Q => \idel_dec_cnt_reg_n_0_[3]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\idel_dec_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(4),
      Q => \idel_dec_cnt_reg_n_0_[4]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
idel_pat_detect_valid_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCCE"
    )
        port map (
      I0 => idel_pat_detect_valid_r_reg_n_0,
      I1 => p_0_in549_in,
      I2 => cal1_dq_idel_inc,
      I3 => store_sr_req_pulsed_r,
      O => idel_pat_detect_valid_r_i_1_n_0
    );
idel_pat_detect_valid_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idel_pat_detect_valid_r_i_1_n_0,
      Q => idel_pat_detect_valid_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\idelay_tap_cnt_r[0][0][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF1111F111"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg[0][0][0]_0\,
      I1 => \idelay_tap_cnt_r_reg[0][0][0]_1\(0),
      I2 => \FSM_onehot_cal1_state_r[6]_i_4_n_0\,
      I3 => \^idelay_ce_int\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \done_cnt_reg[2]_0\,
      O => \idelay_tap_cnt_r[0][0][4]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][1][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \done_cnt_reg[2]_0\,
      I1 => \^idelay_ce_int\,
      I2 => idelay_tap_cnt_slice_r(0),
      O => \idelay_tap_cnt_r[0][1][0]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][1][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404004"
    )
        port map (
      I0 => \done_cnt_reg[2]_0\,
      I1 => \^idelay_ce_int\,
      I2 => idelay_tap_cnt_slice_r(0),
      I3 => idelay_tap_cnt_slice_r(1),
      I4 => \^idelay_inc_int\,
      O => \idelay_tap_cnt_r[0][1][1]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][1][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0444400044400004"
    )
        port map (
      I0 => \done_cnt_reg[2]_0\,
      I1 => \^idelay_ce_int\,
      I2 => \^idelay_inc_int\,
      I3 => idelay_tap_cnt_slice_r(0),
      I4 => idelay_tap_cnt_slice_r(2),
      I5 => idelay_tap_cnt_slice_r(1),
      O => \idelay_tap_cnt_r[0][1][2]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][1][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"28A0A0A0A0A0A082"
    )
        port map (
      I0 => \idelay_tap_cnt_r[0][1][3]_i_2_n_0\,
      I1 => idelay_tap_cnt_slice_r(2),
      I2 => idelay_tap_cnt_slice_r(3),
      I3 => idelay_tap_cnt_slice_r(0),
      I4 => \^idelay_inc_int\,
      I5 => idelay_tap_cnt_slice_r(1),
      O => \idelay_tap_cnt_r[0][1][3]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][1][3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ce_int\,
      I1 => \done_cnt_reg[2]_0\,
      O => \idelay_tap_cnt_r[0][1][3]_i_2_n_0\
    );
\idelay_tap_cnt_r[0][1][4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \done_cnt_reg[2]_0\,
      I1 => \^idelay_ce_int\,
      I2 => \idelay_tap_cnt_r[0][1][4]_i_4_n_0\,
      O => \idelay_tap_cnt_r[0][1][4]_i_2_n_0\
    );
\idelay_tap_cnt_r[0][1][4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \cal1_cnt_cpt_r_reg[0]_0\
    );
\idelay_tap_cnt_r[0][1][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555556"
    )
        port map (
      I0 => idelay_tap_cnt_slice_r(4),
      I1 => idelay_tap_cnt_slice_r(0),
      I2 => \^idelay_inc_int\,
      I3 => idelay_tap_cnt_slice_r(1),
      I4 => idelay_tap_cnt_slice_r(3),
      I5 => idelay_tap_cnt_slice_r(2),
      O => \idelay_tap_cnt_r[0][1][4]_i_4_n_0\
    );
\idelay_tap_cnt_r_reg[0][0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idelay_tap_cnt_r[0][0][4]_i_1_n_0\,
      D => \idelay_tap_cnt_r[0][1][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idelay_tap_cnt_r[0][0][4]_i_1_n_0\,
      D => \idelay_tap_cnt_r[0][1][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idelay_tap_cnt_r[0][0][4]_i_1_n_0\,
      D => \idelay_tap_cnt_r[0][1][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idelay_tap_cnt_r[0][0][4]_i_1_n_0\,
      D => \idelay_tap_cnt_r[0][1][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idelay_tap_cnt_r[0][0][4]_i_1_n_0\,
      D => \idelay_tap_cnt_r[0][1][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0),
      D => \idelay_tap_cnt_r[0][1][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0),
      D => \idelay_tap_cnt_r[0][1][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0),
      D => \idelay_tap_cnt_r[0][1][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0),
      D => \idelay_tap_cnt_r[0][1][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0),
      D => \idelay_tap_cnt_r[0][1][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][4]\,
      R => '0'
    );
\idelay_tap_cnt_slice_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][1][0]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \idelay_tap_cnt_r_reg_n_0_[0][0][0]\,
      O => idelay_tap_cnt_r(0)
    );
\idelay_tap_cnt_slice_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][1][1]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \idelay_tap_cnt_r_reg_n_0_[0][0][1]\,
      O => idelay_tap_cnt_r(1)
    );
\idelay_tap_cnt_slice_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][1][2]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \idelay_tap_cnt_r_reg_n_0_[0][0][2]\,
      O => idelay_tap_cnt_r(2)
    );
\idelay_tap_cnt_slice_r[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][1][3]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \idelay_tap_cnt_r_reg_n_0_[0][0][3]\,
      O => idelay_tap_cnt_r(3)
    );
\idelay_tap_cnt_slice_r[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][1][4]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \idelay_tap_cnt_r_reg_n_0_[0][0][4]\,
      O => idelay_tap_cnt_r(4)
    );
\idelay_tap_cnt_slice_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_tap_cnt_r(0),
      Q => idelay_tap_cnt_slice_r(0),
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\idelay_tap_cnt_slice_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_tap_cnt_r(1),
      Q => idelay_tap_cnt_slice_r(1),
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\idelay_tap_cnt_slice_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_tap_cnt_r(2),
      Q => idelay_tap_cnt_slice_r(2),
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\idelay_tap_cnt_slice_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_tap_cnt_r(3),
      Q => idelay_tap_cnt_slice_r(3),
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\idelay_tap_cnt_slice_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_tap_cnt_r(4),
      Q => idelay_tap_cnt_slice_r(4),
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
idelay_tap_limit_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000AAEA"
    )
        port map (
      I0 => idelay_tap_limit_r_reg_n_0,
      I1 => idelay_tap_cnt_r(0),
      I2 => idelay_tap_cnt_r(3),
      I3 => idelay_tap_limit_r_i_2_n_0,
      I4 => \^new_cnt_cpt_r_reg_0\,
      I5 => \done_cnt_reg[2]_0\,
      O => idelay_tap_limit_r_i_1_n_0
    );
idelay_tap_limit_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3FFF5F5F3FFFFFFF"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][0][4]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][1][4]\,
      I2 => idelay_tap_cnt_r(1),
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][2]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][0][2]\,
      O => idelay_tap_limit_r_i_2_n_0
    );
idelay_tap_limit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_tap_limit_r_i_1_n_0,
      Q => idelay_tap_limit_r_reg_n_0,
      R => '0'
    );
\init_state_r[3]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00B0"
    )
        port map (
      I0 => \^rdlvl_last_byte_done\,
      I1 => \init_state_r[3]_i_13\,
      I2 => pi_dqs_found_done,
      I3 => \^d\(2),
      O => rdlvl_last_byte_done_int_reg_0
    );
\init_state_r[4]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^d\(2),
      I1 => pi_dqs_found_done,
      O => rdlvl_stg1_done_int_reg_0
    );
\init_state_r[6]_i_29\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pi_fine_dly_dec_done\,
      I1 => \init_state_r[6]_i_19\,
      O => pi_fine_dly_dec_done_reg_0
    );
\mpr_4to1.idel_mpr_pat_detect_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\,
      I1 => \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0\,
      I2 => p_1_in26_in,
      I3 => \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0\,
      I4 => inhibit_edge_detect_r,
      O => \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0\
    );
\mpr_4to1.idel_mpr_pat_detect_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => p_0_in549_in,
      I1 => idel_pat_detect_valid_r_reg_n_0,
      I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      O => \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0\
    );
\mpr_4to1.idel_mpr_pat_detect_r_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00100000"
    )
        port map (
      I0 => \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\,
      I1 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      I4 => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\,
      I5 => idel_mpr_pat_detect_r,
      O => \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0\
    );
\mpr_4to1.idel_mpr_pat_detect_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0\,
      Q => idel_mpr_pat_detect_r,
      R => '0'
    );
\mpr_4to1.inhibit_edge_detect_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F700FFFF"
    )
        port map (
      I0 => \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\,
      I1 => p_0_in549_in,
      I2 => \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\,
      I3 => inhibit_edge_detect_r,
      I4 => \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\,
      O => \mpr_4to1.inhibit_edge_detect_r_i_1_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEFEA"
    )
        port map (
      I0 => idelay_tap_cnt_r(3),
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][1][4]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][0][4]\,
      I4 => idelay_tap_cnt_r(1),
      I5 => idelay_tap_cnt_r(2),
      O => \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEFFF"
    )
        port map (
      I0 => mpr_rd_rise0_prev_r,
      I1 => mpr_rd_rise1_prev_r,
      I2 => mpr_rd_fall3_prev_r,
      I3 => mpr_rd_fall2_prev_r,
      I4 => \mpr_4to1.inhibit_edge_detect_r_i_5_n_0\,
      O => \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555545555555"
    )
        port map (
      I0 => \done_cnt_reg[2]_0\,
      I1 => \mpr_4to1.inhibit_edge_detect_r_i_6_n_0\,
      I2 => mpr_rd_rise2_prev_r,
      I3 => mpr_rd_rise0_prev_r,
      I4 => mpr_rd_rise1_prev_r,
      I5 => mpr_rd_fall2_prev_r,
      O => \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => mpr_rd_rise3_prev_r,
      I1 => mpr_rd_rise2_prev_r,
      I2 => mpr_rd_fall0_prev_r,
      I3 => mpr_rd_fall1_prev_r,
      O => \mpr_4to1.inhibit_edge_detect_r_i_5_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => mpr_rd_rise3_prev_r,
      I1 => mpr_rd_fall0_prev_r,
      I2 => mpr_rd_fall3_prev_r,
      I3 => mpr_rd_fall1_prev_r,
      O => \mpr_4to1.inhibit_edge_detect_r_i_6_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \mpr_4to1.inhibit_edge_detect_r_i_1_n_0\,
      Q => inhibit_edge_detect_r,
      R => '0'
    );
\mpr_4to1.stable_idel_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      I1 => stable_idel_cnt,
      I2 => stable_idel_cnt0,
      O => \mpr_4to1.stable_idel_cnt[0]_i_1_n_0\
    );
\mpr_4to1.stable_idel_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I1 => stable_idel_cnt,
      I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      I3 => stable_idel_cnt0,
      O => \mpr_4to1.stable_idel_cnt[1]_i_1_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      I1 => stable_idel_cnt,
      I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      I4 => stable_idel_cnt0,
      O => \mpr_4to1.stable_idel_cnt[2]_i_1_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\,
      I1 => p_0_in549_in,
      I2 => idel_pat_detect_valid_r_reg_n_0,
      I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I4 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_cal1_state_r[16]_i_2_n_0\,
      O => stable_idel_cnt
    );
\mpr_4to1.stable_idel_cnt[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I2 => \done_cnt_reg[2]_0\,
      O => stable_idel_cnt0
    );
\mpr_4to1.stable_idel_cnt[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt[2]_i_5_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      I2 => mpr_rd_fall3_prev_r,
      I3 => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      I4 => mpr_rd_rise0_prev_r,
      I5 => \mpr_4to1.stable_idel_cnt[2]_i_6_n_0\,
      O => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      I1 => mpr_rd_fall1_prev_r,
      I2 => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      I3 => mpr_rd_rise3_prev_r,
      O => \mpr_4to1.stable_idel_cnt[2]_i_5_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6FF6"
    )
        port map (
      I0 => mpr_rd_rise2_prev_r,
      I1 => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      I2 => mpr_rd_fall0_prev_r,
      I3 => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      I4 => \mpr_4to1.stable_idel_cnt[2]_i_7_n_0\,
      O => \mpr_4to1.stable_idel_cnt[2]_i_6_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      I1 => mpr_rd_fall2_prev_r,
      I2 => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      I3 => mpr_rd_rise1_prev_r,
      O => \mpr_4to1.stable_idel_cnt[2]_i_7_n_0\
    );
\mpr_4to1.stable_idel_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \mpr_4to1.stable_idel_cnt[0]_i_1_n_0\,
      Q => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      R => '0'
    );
\mpr_4to1.stable_idel_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \mpr_4to1.stable_idel_cnt[1]_i_1_n_0\,
      Q => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      R => '0'
    );
\mpr_4to1.stable_idel_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \mpr_4to1.stable_idel_cnt[2]_i_1_n_0\,
      Q => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      R => '0'
    );
mpr_dec_cpt_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DC"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\,
      I1 => \cnt_idel_dec_cpt_r_reg[0]_0\,
      I2 => mpr_dec_cpt_r_reg_n_0,
      O => mpr_dec_cpt_r_i_1_n_0
    );
mpr_dec_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mpr_dec_cpt_r_i_1_n_0,
      Q => mpr_dec_cpt_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
mpr_rd_fall0_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      Q => mpr_rd_fall0_prev_r,
      R => '0'
    );
mpr_rd_fall1_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      Q => mpr_rd_fall1_prev_r,
      R => '0'
    );
mpr_rd_fall2_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      Q => mpr_rd_fall2_prev_r,
      R => '0'
    );
mpr_rd_fall3_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      Q => mpr_rd_fall3_prev_r,
      R => '0'
    );
mpr_rd_rise0_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      Q => mpr_rd_rise0_prev_r,
      R => '0'
    );
mpr_rd_rise1_prev_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => p_1_in26_in,
      I1 => p_0_in549_in,
      I2 => idel_pat_detect_valid_r_reg_n_0,
      O => mpr_rd_rise0_prev_r0
    );
mpr_rd_rise1_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      Q => mpr_rd_rise1_prev_r,
      R => '0'
    );
mpr_rd_rise2_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      Q => mpr_rd_rise2_prev_r,
      R => '0'
    );
mpr_rd_rise3_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      Q => mpr_rd_rise3_prev_r,
      R => '0'
    );
mpr_rdlvl_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mpr_rdlvl_start_r_reg_0,
      Q => mpr_rdlvl_start_r,
      R => '0'
    );
new_cnt_cpt_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAEAEEAAAA"
    )
        port map (
      I0 => new_cnt_cpt_r_i_2_n_0,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I2 => mpr_rdlvl_start_r,
      I3 => mpr_rdlvl_start_r_reg_0,
      I4 => rdlvl_stg1_start_r_reg_0,
      I5 => rdlvl_stg1_start_r,
      O => new_cnt_cpt_r
    );
new_cnt_cpt_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EF000000"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[1]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I3 => prech_done,
      I4 => cal1_prech_req_r,
      O => new_cnt_cpt_r_i_2_n_0
    );
new_cnt_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => new_cnt_cpt_r,
      Q => \^new_cnt_cpt_r_reg_0\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\phaser_in_gen.phaser_in_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C4"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[2]\,
      I1 => pi_counter_load_en,
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => \calib_sel_reg[1]_1\
    );
\phaser_in_gen.phaser_in_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C4"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[2]\,
      I1 => pi_counter_load_val(1),
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => COUNTERLOADVAL(1)
    );
\phaser_in_gen.phaser_in_i_10__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => pi_counter_load_val(1),
      I1 => \pi_dqs_found_lanes_r1_reg[2]\,
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => \pi_stg2_reg_l_reg[5]_0\(1)
    );
\phaser_in_gen.phaser_in_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C4"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[2]\,
      I1 => pi_counter_load_val(0),
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => COUNTERLOADVAL(0)
    );
\phaser_in_gen.phaser_in_i_11__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => pi_counter_load_val(0),
      I1 => \pi_dqs_found_lanes_r1_reg[2]\,
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => \pi_stg2_reg_l_reg[5]_0\(0)
    );
\phaser_in_gen.phaser_in_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => pi_counter_load_en,
      I1 => \pi_dqs_found_lanes_r1_reg[2]\,
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => pi_stg2_load_reg_0
    );
\phaser_in_gen.phaser_in_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FC54"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[2]\,
      I1 => tempmon_pi_f_en_r,
      I2 => rdlvl_pi_stg2_f_en,
      I3 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I4 => calib_zero_inputs,
      O => \calib_sel_reg[1]\
    );
\phaser_in_gen.phaser_in_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EEE0"
    )
        port map (
      I0 => tempmon_pi_f_en_r,
      I1 => rdlvl_pi_stg2_f_en,
      I2 => \pi_dqs_found_lanes_r1_reg[2]\,
      I3 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I4 => calib_zero_inputs,
      O => tempmon_pi_f_en_r_reg
    );
\phaser_in_gen.phaser_in_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FC54"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[2]\,
      I1 => tempmon_pi_f_inc_r,
      I2 => rdlvl_pi_stg2_f_incdec,
      I3 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I4 => calib_zero_inputs,
      O => \calib_sel_reg[1]_0\
    );
\phaser_in_gen.phaser_in_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EEE0"
    )
        port map (
      I0 => tempmon_pi_f_inc_r,
      I1 => rdlvl_pi_stg2_f_incdec,
      I2 => \pi_dqs_found_lanes_r1_reg[2]\,
      I3 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I4 => calib_zero_inputs,
      O => tempmon_pi_f_inc_r_reg
    );
\phaser_in_gen.phaser_in_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C4"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[2]\,
      I1 => pi_counter_load_val(5),
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => COUNTERLOADVAL(5)
    );
\phaser_in_gen.phaser_in_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => pi_counter_load_val(5),
      I1 => \pi_dqs_found_lanes_r1_reg[2]\,
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => \pi_stg2_reg_l_reg[5]_0\(5)
    );
\phaser_in_gen.phaser_in_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C4"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[2]\,
      I1 => pi_counter_load_val(4),
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => COUNTERLOADVAL(4)
    );
\phaser_in_gen.phaser_in_i_7__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => pi_counter_load_val(4),
      I1 => \pi_dqs_found_lanes_r1_reg[2]\,
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => \pi_stg2_reg_l_reg[5]_0\(4)
    );
\phaser_in_gen.phaser_in_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C4"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[2]\,
      I1 => pi_counter_load_val(3),
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => COUNTERLOADVAL(3)
    );
\phaser_in_gen.phaser_in_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => pi_counter_load_val(3),
      I1 => \pi_dqs_found_lanes_r1_reg[2]\,
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => \pi_stg2_reg_l_reg[5]_0\(3)
    );
\phaser_in_gen.phaser_in_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C4"
    )
        port map (
      I0 => \pi_dqs_found_lanes_r1_reg[2]\,
      I1 => pi_counter_load_val(2),
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => COUNTERLOADVAL(2)
    );
\phaser_in_gen.phaser_in_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => pi_counter_load_val(2),
      I1 => \pi_dqs_found_lanes_r1_reg[2]\,
      I2 => \pi_dqs_found_lanes_r1_reg[2]_0\,
      I3 => calib_zero_inputs,
      O => \pi_stg2_reg_l_reg[5]_0\(2)
    );
pi_cnt_dec_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => wait_cnt_r_reg(0),
      I1 => \done_cnt_reg[2]_0\,
      I2 => dqs_po_dec_done_r2,
      I3 => wait_cnt_r_reg(1),
      I4 => pi_cnt_dec_i_2_n_0,
      I5 => \pi_rdval_cnt[5]_i_3_n_0\,
      O => pi_cnt_dec_i_1_n_0
    );
pi_cnt_dec_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => wait_cnt_r_reg(2),
      I1 => wait_cnt_r_reg(3),
      O => pi_cnt_dec_i_2_n_0
    );
pi_cnt_dec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_cnt_dec_i_1_n_0,
      Q => \^pi_cnt_dec_reg_0\,
      R => '0'
    );
pi_en_stg2_f_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_en_stg2_f_timing,
      Q => rdlvl_pi_stg2_f_en,
      R => '0'
    );
pi_en_stg2_f_timing_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => cal1_dlyce_cpt_r_reg_n_0,
      I1 => \^pi_cnt_dec_reg_0\,
      O => pi_en_stg2_f_timing_i_1_n_0
    );
pi_en_stg2_f_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_en_stg2_f_timing_i_1_n_0,
      Q => pi_en_stg2_f_timing,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
pi_fine_dly_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fine_dly_dec_done_r2,
      Q => \^pi_fine_dly_dec_done\,
      R => '0'
    );
\pi_rdval_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"080808FB"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[5]_0\(0),
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => pi_rdval_cnt(0),
      I4 => \pi_rdval_cnt[5]_i_3_n_0\,
      O => \pi_rdval_cnt[0]_i_1_n_0\
    );
\pi_rdval_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080808FB0808FB"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[5]_0\(1),
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => pi_rdval_cnt(0),
      I4 => pi_rdval_cnt(1),
      I5 => \pi_rdval_cnt[5]_i_3_n_0\,
      O => \pi_rdval_cnt[1]_i_1_n_0\
    );
\pi_rdval_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BBB8888B"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[5]_0\(2),
      I1 => \pi_rdval_cnt[2]_i_2_n_0\,
      I2 => pi_rdval_cnt(1),
      I3 => pi_rdval_cnt(0),
      I4 => pi_rdval_cnt(2),
      I5 => \pi_rdval_cnt[5]_i_3_n_0\,
      O => \pi_rdval_cnt[2]_i_1_n_0\
    );
\pi_rdval_cnt[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dqs_po_dec_done_r1,
      I1 => dqs_po_dec_done_r2,
      O => \pi_rdval_cnt[2]_i_2_n_0\
    );
\pi_rdval_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080808FBFB08"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[5]_0\(3),
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => \pi_rdval_cnt[3]_i_2_n_0\,
      I4 => pi_rdval_cnt(3),
      I5 => \pi_rdval_cnt[5]_i_3_n_0\,
      O => \pi_rdval_cnt[3]_i_1_n_0\
    );
\pi_rdval_cnt[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => pi_rdval_cnt(0),
      I1 => pi_rdval_cnt(1),
      I2 => pi_rdval_cnt(2),
      O => \pi_rdval_cnt[3]_i_2_n_0\
    );
\pi_rdval_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808FBFBFB080808"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[5]_0\(4),
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => pi_rdval_cnt(5),
      I4 => \pi_rdval_cnt[4]_i_2_n_0\,
      I5 => pi_rdval_cnt(4),
      O => \pi_rdval_cnt[4]_i_1_n_0\
    );
\pi_rdval_cnt[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => pi_rdval_cnt(2),
      I1 => pi_rdval_cnt(1),
      I2 => pi_rdval_cnt(0),
      I3 => pi_rdval_cnt(3),
      O => \pi_rdval_cnt[4]_i_2_n_0\
    );
\pi_rdval_cnt[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFAE"
    )
        port map (
      I0 => \^pi_cnt_dec_reg_0\,
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => \pi_rdval_cnt[5]_i_3_n_0\,
      O => \pi_rdval_cnt[5]_i_1_n_0\
    );
\pi_rdval_cnt[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0808FB08"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[5]_0\(5),
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => pi_rdval_cnt(5),
      I4 => \pi_rdval_cnt[5]_i_4_n_0\,
      O => \pi_rdval_cnt[5]_i_2_n_0\
    );
\pi_rdval_cnt[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => pi_rdval_cnt(4),
      I1 => pi_rdval_cnt(2),
      I2 => pi_rdval_cnt(1),
      I3 => pi_rdval_cnt(0),
      I4 => pi_rdval_cnt(3),
      I5 => pi_rdval_cnt(5),
      O => \pi_rdval_cnt[5]_i_3_n_0\
    );
\pi_rdval_cnt[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => pi_rdval_cnt(3),
      I1 => pi_rdval_cnt(0),
      I2 => pi_rdval_cnt(1),
      I3 => pi_rdval_cnt(2),
      I4 => pi_rdval_cnt(4),
      O => \pi_rdval_cnt[5]_i_4_n_0\
    );
\pi_rdval_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[0]_i_1_n_0\,
      Q => pi_rdval_cnt(0),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\pi_rdval_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[1]_i_1_n_0\,
      Q => pi_rdval_cnt(1),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\pi_rdval_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[2]_i_1_n_0\,
      Q => pi_rdval_cnt(2),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\pi_rdval_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[3]_i_1_n_0\,
      Q => pi_rdval_cnt(3),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\pi_rdval_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[4]_i_1_n_0\,
      Q => pi_rdval_cnt(4),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\pi_rdval_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[5]_i_2_n_0\,
      Q => pi_rdval_cnt(5),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
pi_stg2_f_incdec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_f_incdec_timing,
      Q => rdlvl_pi_stg2_f_incdec,
      R => '0'
    );
pi_stg2_f_incdec_timing_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => cal1_dlyce_cpt_r_reg_n_0,
      I1 => cal1_dlyinc_cpt_r_reg_n_0,
      I2 => \^pi_cnt_dec_reg_0\,
      I3 => \done_cnt_reg[2]_0\,
      O => pi_stg2_f_incdec_timing_i_1_n_0
    );
pi_stg2_f_incdec_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_f_incdec_timing_i_1_n_0,
      Q => pi_stg2_f_incdec_timing,
      R => '0'
    );
pi_stg2_load_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_load_timing,
      Q => pi_counter_load_en,
      R => '0'
    );
pi_stg2_load_timing_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \regl_dqs_cnt_reg_n_0_[1]\,
      I1 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\,
      I2 => \regl_rank_cnt[1]_i_2_n_0\,
      O => pi_stg2_load_timing_i_1_n_0
    );
pi_stg2_load_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_load_timing_i_1_n_0,
      Q => pi_stg2_load_timing,
      R => '0'
    );
\pi_stg2_reg_l_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_reg_l_timing(0),
      Q => pi_counter_load_val(0),
      R => '0'
    );
\pi_stg2_reg_l_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_reg_l_timing(1),
      Q => pi_counter_load_val(1),
      R => '0'
    );
\pi_stg2_reg_l_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_reg_l_timing(2),
      Q => pi_counter_load_val(2),
      R => '0'
    );
\pi_stg2_reg_l_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_reg_l_timing(3),
      Q => pi_counter_load_val(3),
      R => '0'
    );
\pi_stg2_reg_l_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_reg_l_timing(4),
      Q => pi_counter_load_val(4),
      R => '0'
    );
\pi_stg2_reg_l_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_reg_l_timing(5),
      Q => pi_counter_load_val(5),
      R => '0'
    );
\pi_stg2_reg_l_timing[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0]\,
      I1 => \regl_dqs_cnt_reg_n_0_[0]\,
      I2 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0]\,
      O => \pi_stg2_reg_l_timing[0]_i_1_n_0\
    );
\pi_stg2_reg_l_timing[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1]\,
      I1 => \regl_dqs_cnt_reg_n_0_[0]\,
      I2 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1]\,
      O => \pi_stg2_reg_l_timing[1]_i_1_n_0\
    );
\pi_stg2_reg_l_timing[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2]\,
      I1 => \regl_dqs_cnt_reg_n_0_[0]\,
      I2 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2]\,
      O => \pi_stg2_reg_l_timing[2]_i_1_n_0\
    );
\pi_stg2_reg_l_timing[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3]\,
      I1 => \regl_dqs_cnt_reg_n_0_[0]\,
      I2 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3]\,
      O => \pi_stg2_reg_l_timing[3]_i_1_n_0\
    );
\pi_stg2_reg_l_timing[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4]\,
      I1 => \regl_dqs_cnt_reg_n_0_[0]\,
      I2 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4]\,
      O => \pi_stg2_reg_l_timing[4]_i_1_n_0\
    );
\pi_stg2_reg_l_timing[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \regl_rank_cnt[1]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\,
      I2 => \regl_dqs_cnt_reg_n_0_[1]\,
      O => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5]\,
      I1 => \regl_dqs_cnt_reg_n_0_[0]\,
      I2 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5]\,
      O => \pi_stg2_reg_l_timing[5]_i_2_n_0\
    );
\pi_stg2_reg_l_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_stg2_reg_l_timing[0]_i_1_n_0\,
      Q => pi_stg2_reg_l_timing(0),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_stg2_reg_l_timing[1]_i_1_n_0\,
      Q => pi_stg2_reg_l_timing(1),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_stg2_reg_l_timing[2]_i_1_n_0\,
      Q => pi_stg2_reg_l_timing(2),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_stg2_reg_l_timing[3]_i_1_n_0\,
      Q => pi_stg2_reg_l_timing(3),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_stg2_reg_l_timing[4]_i_1_n_0\,
      Q => pi_stg2_reg_l_timing(4),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_stg2_reg_l_timing[5]_i_2_n_0\,
      Q => pi_stg2_reg_l_timing(5),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
prbs_rdlvl_done_pulse_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^d\(2),
      I1 => rdlvl_stg1_done_r1,
      O => prbs_rdlvl_done_pulse0
    );
\rd_mux_sel_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      Q => \^rd_mux_sel_r_reg[0]_0\,
      R => '0'
    );
\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \^rd_mux_sel_r_reg[0]_0\,
      O => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => \cal1_state_r1_reg_n_0_[4]\,
      I1 => \cal1_state_r1_reg_n_0_[5]\,
      I2 => \cal1_state_r1_reg_n_0_[0]\,
      I3 => \cal1_state_r1_reg_n_0_[2]\,
      I4 => \cal1_state_r1_reg_n_0_[1]\,
      I5 => \cal1_state_r1_reg_n_0_[3]\,
      O => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \^rd_mux_sel_r_reg[0]_0\,
      O => rdlvl_dqs_tap_cnt_r
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rdlvl_dqs_tap_cnt_r,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rdlvl_dqs_tap_cnt_r,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rdlvl_dqs_tap_cnt_r,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rdlvl_dqs_tap_cnt_r,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rdlvl_dqs_tap_cnt_r,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rdlvl_dqs_tap_cnt_r,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5]\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
rdlvl_last_byte_done_int_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0101FFFE0000"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[5]_i_1_n_0\,
      I1 => \^q\(0),
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I4 => cal1_prech_req_r,
      I5 => \^rdlvl_last_byte_done\,
      O => rdlvl_last_byte_done_int_i_1_n_0
    );
rdlvl_last_byte_done_int_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_last_byte_done_int_i_1_n_0,
      Q => \^rdlvl_last_byte_done\,
      R => \FSM_onehot_cal1_state_r_reg[7]_0\
    );
rdlvl_pi_incdec_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFE00"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[0]_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I2 => rdlvl_pi_incdec_i_2_n_0,
      I3 => rdlvl_pi_incdec_i_3_n_0,
      I4 => \^rdlvl_pi_incdec\,
      O => rdlvl_pi_incdec_i_1_n_0
    );
rdlvl_pi_incdec_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEEEEEEEEE"
    )
        port map (
      I0 => rdlvl_pi_incdec_i_4_n_0,
      I1 => p_14_in,
      I2 => \^q\(0),
      I3 => p_8_in,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I5 => cal1_wait_r,
      O => rdlvl_pi_incdec_i_2_n_0
    );
rdlvl_pi_incdec_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFAAFE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => p_8_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      I3 => cal1_wait_r,
      I4 => rdlvl_pi_incdec_i_5_n_0,
      O => rdlvl_pi_incdec_i_3_n_0
    );
rdlvl_pi_incdec_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I1 => mpr_rdlvl_start_r,
      I2 => mpr_rdlvl_start_r_reg_0,
      O => rdlvl_pi_incdec_i_4_n_0
    );
rdlvl_pi_incdec_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => p_0_in549_in,
      I1 => p_34_in,
      I2 => \^q\(0),
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I4 => p_14_in,
      O => rdlvl_pi_incdec_i_5_n_0
    );
rdlvl_pi_incdec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_pi_incdec_i_1_n_0,
      Q => \^rdlvl_pi_incdec\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(0)
    );
rdlvl_prech_req_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_prech_req_r__0\,
      Q => rdlvl_prech_req,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
rdlvl_rank_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAFAAAAAAA8"
    )
        port map (
      I0 => rdlvl_rank_done_r,
      I1 => prech_done,
      I2 => \^q\(0),
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I4 => p_0_in541_in,
      I5 => \^rdlvl_stg1_rank_done\,
      O => rdlvl_rank_done_r_i_1_n_0
    );
rdlvl_rank_done_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I1 => cal1_prech_req_r,
      O => rdlvl_rank_done_r
    );
rdlvl_rank_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_rank_done_r_i_1_n_0,
      Q => \^rdlvl_stg1_rank_done\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
rdlvl_stg1_done_int_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rdlvl_stg1_done_int,
      I1 => \^d\(2),
      O => rdlvl_stg1_done_int_i_1_n_0
    );
rdlvl_stg1_done_int_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_stg1_done_int_i_1_n_0,
      Q => \^d\(2),
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
rdlvl_stg1_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_stg1_start_r_reg_0,
      Q => rdlvl_stg1_start_r,
      R => '0'
    );
\regl_dqs_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000006666666E"
    )
        port map (
      I0 => \regl_dqs_cnt_reg_n_0_[0]\,
      I1 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\,
      I2 => regl_rank_cnt(0),
      I3 => regl_rank_cnt(1),
      I4 => \regl_dqs_cnt_reg_n_0_[1]\,
      I5 => \regl_rank_cnt[1]_i_2_n_0\,
      O => \regl_dqs_cnt[0]_i_1_n_0\
    );
\regl_dqs_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0444"
    )
        port map (
      I0 => \regl_rank_cnt[1]_i_2_n_0\,
      I1 => \regl_dqs_cnt_reg_n_0_[1]\,
      I2 => \regl_dqs_cnt_reg_n_0_[0]\,
      I3 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\,
      O => \regl_dqs_cnt[1]_i_1_n_0\
    );
\regl_dqs_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \regl_dqs_cnt_reg_n_0_[0]\,
      Q => regl_dqs_cnt_r(0),
      R => '0'
    );
\regl_dqs_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \regl_dqs_cnt_reg_n_0_[1]\,
      Q => regl_dqs_cnt_r(1),
      R => '0'
    );
\regl_dqs_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \regl_dqs_cnt[0]_i_1_n_0\,
      Q => \regl_dqs_cnt_reg_n_0_[0]\,
      R => '0'
    );
\regl_dqs_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \regl_dqs_cnt[1]_i_1_n_0\,
      Q => \regl_dqs_cnt_reg_n_0_[1]\,
      R => '0'
    );
\regl_rank_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000009AAA8AAA"
    )
        port map (
      I0 => regl_rank_cnt(0),
      I1 => \regl_dqs_cnt_reg_n_0_[1]\,
      I2 => \regl_dqs_cnt_reg_n_0_[0]\,
      I3 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\,
      I4 => regl_rank_cnt(1),
      I5 => \regl_rank_cnt[1]_i_2_n_0\,
      O => \regl_rank_cnt[0]_i_1_n_0\
    );
\regl_rank_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000009AAAAAAA"
    )
        port map (
      I0 => regl_rank_cnt(1),
      I1 => \regl_dqs_cnt_reg_n_0_[1]\,
      I2 => \regl_dqs_cnt_reg_n_0_[0]\,
      I3 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\,
      I4 => regl_rank_cnt(0),
      I5 => \regl_rank_cnt[1]_i_2_n_0\,
      O => \regl_rank_cnt[1]_i_1_n_0\
    );
\regl_rank_cnt[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAAB"
    )
        port map (
      I0 => \done_cnt_reg[2]_0\,
      I1 => done_cnt(3),
      I2 => done_cnt(1),
      I3 => done_cnt(0),
      I4 => done_cnt(2),
      O => \regl_rank_cnt[1]_i_2_n_0\
    );
\regl_rank_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \regl_rank_cnt[0]_i_1_n_0\,
      Q => regl_rank_cnt(0),
      R => '0'
    );
\regl_rank_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \regl_rank_cnt[1]_i_1_n_0\,
      Q => regl_rank_cnt(1),
      R => '0'
    );
reset_if_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10101110"
    )
        port map (
      I0 => reset_if_reg,
      I1 => reset_if_r9,
      I2 => reset_if,
      I3 => \^d\(2),
      I4 => rdlvl_stg1_done_r1,
      O => \rstdiv0_sync_r1_reg_rep__14_0\
    );
\right_edge_taps_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I1 => store_sr_req_pulsed_r,
      O => right_edge_taps_r(0)
    );
\right_edge_taps_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I1 => store_sr_req_pulsed_r,
      O => right_edge_taps_r(1)
    );
\right_edge_taps_r[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I1 => store_sr_req_pulsed_r,
      O => right_edge_taps_r(2)
    );
\right_edge_taps_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => store_sr_req_pulsed_r,
      O => right_edge_taps_r(3)
    );
\right_edge_taps_r[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I1 => store_sr_req_pulsed_r,
      O => right_edge_taps_r(4)
    );
\right_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BAAA"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => found_first_edge_r_reg_n_0,
      I2 => found_stable_eye_last_r,
      I3 => \first_edge_taps_r[5]_i_3_n_0\,
      O => \right_edge_taps_r[5]_i_1_n_0\
    );
\right_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I1 => store_sr_req_pulsed_r,
      O => right_edge_taps_r(5)
    );
\right_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(0),
      Q => \right_edge_taps_r_reg_n_0_[0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\right_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(1),
      Q => \right_edge_taps_r_reg_n_0_[1]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\right_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(2),
      Q => \right_edge_taps_r_reg_n_0_[2]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\right_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(3),
      Q => \right_edge_taps_r_reg_n_0_[3]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\right_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(4),
      Q => \right_edge_taps_r_reg_n_0_[4]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\right_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(5),
      Q => \right_edge_taps_r_reg_n_0_[5]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\rnk_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"15C8158855885588"
    )
        port map (
      I0 => p_0_in541_in,
      I1 => cal1_prech_req_r,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \rnk_cnt_r_reg_n_0_[1]\,
      I5 => prech_done,
      O => \rnk_cnt_r[0]_i_1__0_n_0\
    );
\rnk_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"15DDC80055DD8800"
    )
        port map (
      I0 => p_0_in541_in,
      I1 => cal1_prech_req_r,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \rnk_cnt_r_reg_n_0_[1]\,
      I5 => prech_done,
      O => \rnk_cnt_r[1]_i_1__0_n_0\
    );
\rnk_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rnk_cnt_r[0]_i_1__0_n_0\,
      Q => \rnk_cnt_r_reg_n_0_[0]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\rnk_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rnk_cnt_r[1]_i_1__0_n_0\,
      Q => \rnk_cnt_r_reg_n_0_[1]\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
samp_cnt_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAE0000"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => samp_cnt_done_r_i_2_n_0,
      I2 => samp_cnt_done_r_i_3_n_0,
      I3 => samp_cnt_done_r_i_4_n_0,
      I4 => \^samp_edge_cnt0_en_r\,
      I5 => \done_cnt_reg[2]_0\,
      O => samp_cnt_done_r_i_1_n_0
    );
samp_cnt_done_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => samp_edge_cnt1_r_reg(11),
      I1 => samp_edge_cnt1_r_reg(7),
      I2 => samp_edge_cnt1_r_reg(0),
      I3 => samp_edge_cnt1_r_reg(6),
      O => samp_cnt_done_r_i_2_n_0
    );
samp_cnt_done_r_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => samp_edge_cnt1_r_reg(1),
      I1 => samp_edge_cnt1_r_reg(10),
      I2 => samp_edge_cnt1_r_reg(8),
      I3 => samp_edge_cnt1_r_reg(3),
      O => samp_cnt_done_r_i_3_n_0
    );
samp_cnt_done_r_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => samp_edge_cnt1_r_reg(4),
      I1 => samp_edge_cnt1_r_reg(9),
      I2 => samp_edge_cnt1_r_reg(2),
      I3 => samp_edge_cnt1_r_reg(5),
      O => samp_cnt_done_r_i_4_n_0
    );
samp_cnt_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => samp_cnt_done_r_i_1_n_0,
      Q => samp_cnt_done_r_reg_n_0,
      R => '0'
    );
samp_edge_cnt0_en_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => p_34_in,
      O => pb_detect_edge
    );
samp_edge_cnt0_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pb_detect_edge,
      Q => \^samp_edge_cnt0_en_r\,
      R => '0'
    );
\samp_edge_cnt0_r[0]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => samp_edge_cnt0_r_reg(0),
      O => \samp_edge_cnt0_r[0]_i_3_n_0\
    );
\samp_edge_cnt0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[0]_i_2_n_7\,
      Q => samp_edge_cnt0_r_reg(0),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \samp_edge_cnt0_r_reg[0]_i_2_n_0\,
      CO(2) => \samp_edge_cnt0_r_reg[0]_i_2_n_1\,
      CO(1) => \samp_edge_cnt0_r_reg[0]_i_2_n_2\,
      CO(0) => \samp_edge_cnt0_r_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \samp_edge_cnt0_r_reg[0]_i_2_n_4\,
      O(2) => \samp_edge_cnt0_r_reg[0]_i_2_n_5\,
      O(1) => \samp_edge_cnt0_r_reg[0]_i_2_n_6\,
      O(0) => \samp_edge_cnt0_r_reg[0]_i_2_n_7\,
      S(3 downto 1) => samp_edge_cnt0_r_reg(3 downto 1),
      S(0) => \samp_edge_cnt0_r[0]_i_3_n_0\
    );
\samp_edge_cnt0_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[8]_i_1_n_5\,
      Q => samp_edge_cnt0_r_reg(10),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[8]_i_1_n_4\,
      Q => samp_edge_cnt0_r_reg(11),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[0]_i_2_n_6\,
      Q => samp_edge_cnt0_r_reg(1),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[0]_i_2_n_5\,
      Q => samp_edge_cnt0_r_reg(2),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[0]_i_2_n_4\,
      Q => samp_edge_cnt0_r_reg(3),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[4]_i_1_n_7\,
      Q => samp_edge_cnt0_r_reg(4),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \samp_edge_cnt0_r_reg[0]_i_2_n_0\,
      CO(3) => \samp_edge_cnt0_r_reg[4]_i_1_n_0\,
      CO(2) => \samp_edge_cnt0_r_reg[4]_i_1_n_1\,
      CO(1) => \samp_edge_cnt0_r_reg[4]_i_1_n_2\,
      CO(0) => \samp_edge_cnt0_r_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \samp_edge_cnt0_r_reg[4]_i_1_n_4\,
      O(2) => \samp_edge_cnt0_r_reg[4]_i_1_n_5\,
      O(1) => \samp_edge_cnt0_r_reg[4]_i_1_n_6\,
      O(0) => \samp_edge_cnt0_r_reg[4]_i_1_n_7\,
      S(3 downto 0) => samp_edge_cnt0_r_reg(7 downto 4)
    );
\samp_edge_cnt0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[4]_i_1_n_6\,
      Q => samp_edge_cnt0_r_reg(5),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[4]_i_1_n_5\,
      Q => samp_edge_cnt0_r_reg(6),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[4]_i_1_n_4\,
      Q => samp_edge_cnt0_r_reg(7),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[8]_i_1_n_7\,
      Q => samp_edge_cnt0_r_reg(8),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt0_r_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \samp_edge_cnt0_r_reg[4]_i_1_n_0\,
      CO(3) => \NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \samp_edge_cnt0_r_reg[8]_i_1_n_1\,
      CO(1) => \samp_edge_cnt0_r_reg[8]_i_1_n_2\,
      CO(0) => \samp_edge_cnt0_r_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \samp_edge_cnt0_r_reg[8]_i_1_n_4\,
      O(2) => \samp_edge_cnt0_r_reg[8]_i_1_n_5\,
      O(1) => \samp_edge_cnt0_r_reg[8]_i_1_n_6\,
      O(0) => \samp_edge_cnt0_r_reg[8]_i_1_n_7\,
      S(3 downto 0) => samp_edge_cnt0_r_reg(11 downto 8)
    );
\samp_edge_cnt0_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[8]_i_1_n_6\,
      Q => samp_edge_cnt0_r_reg(9),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
samp_edge_cnt1_en_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => samp_edge_cnt1_en_r_i_2_n_0,
      I1 => samp_edge_cnt1_en_r_i_3_n_0,
      I2 => samp_edge_cnt0_r_reg(2),
      I3 => samp_edge_cnt0_r_reg(0),
      I4 => samp_edge_cnt0_r_reg(5),
      O => samp_edge_cnt1_en_r0
    );
samp_edge_cnt1_en_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => samp_edge_cnt0_r_reg(10),
      I1 => samp_edge_cnt0_r_reg(4),
      I2 => samp_edge_cnt0_r_reg(9),
      I3 => samp_edge_cnt0_r_reg(7),
      I4 => samp_edge_cnt0_r_reg(11),
      I5 => samp_edge_cnt0_r_reg(6),
      O => samp_edge_cnt1_en_r_i_2_n_0
    );
samp_edge_cnt1_en_r_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => samp_edge_cnt0_r_reg(8),
      I1 => samp_edge_cnt0_r_reg(3),
      I2 => sr_valid_r2,
      I3 => samp_edge_cnt0_r_reg(1),
      O => samp_edge_cnt1_en_r_i_3_n_0
    );
samp_edge_cnt1_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => samp_edge_cnt1_en_r0,
      Q => samp_edge_cnt1_en_r,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\samp_edge_cnt1_r[0]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => samp_edge_cnt1_r_reg(0),
      O => \samp_edge_cnt1_r[0]_i_2_n_0\
    );
\samp_edge_cnt1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[0]_i_1_n_7\,
      Q => samp_edge_cnt1_r_reg(0),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[0]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \samp_edge_cnt1_r_reg[0]_i_1_n_0\,
      CO(2) => \samp_edge_cnt1_r_reg[0]_i_1_n_1\,
      CO(1) => \samp_edge_cnt1_r_reg[0]_i_1_n_2\,
      CO(0) => \samp_edge_cnt1_r_reg[0]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \samp_edge_cnt1_r_reg[0]_i_1_n_4\,
      O(2) => \samp_edge_cnt1_r_reg[0]_i_1_n_5\,
      O(1) => \samp_edge_cnt1_r_reg[0]_i_1_n_6\,
      O(0) => \samp_edge_cnt1_r_reg[0]_i_1_n_7\,
      S(3 downto 1) => samp_edge_cnt1_r_reg(3 downto 1),
      S(0) => \samp_edge_cnt1_r[0]_i_2_n_0\
    );
\samp_edge_cnt1_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[8]_i_1_n_5\,
      Q => samp_edge_cnt1_r_reg(10),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[8]_i_1_n_4\,
      Q => samp_edge_cnt1_r_reg(11),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[0]_i_1_n_6\,
      Q => samp_edge_cnt1_r_reg(1),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[0]_i_1_n_5\,
      Q => samp_edge_cnt1_r_reg(2),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[0]_i_1_n_4\,
      Q => samp_edge_cnt1_r_reg(3),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[4]_i_1_n_7\,
      Q => samp_edge_cnt1_r_reg(4),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \samp_edge_cnt1_r_reg[0]_i_1_n_0\,
      CO(3) => \samp_edge_cnt1_r_reg[4]_i_1_n_0\,
      CO(2) => \samp_edge_cnt1_r_reg[4]_i_1_n_1\,
      CO(1) => \samp_edge_cnt1_r_reg[4]_i_1_n_2\,
      CO(0) => \samp_edge_cnt1_r_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \samp_edge_cnt1_r_reg[4]_i_1_n_4\,
      O(2) => \samp_edge_cnt1_r_reg[4]_i_1_n_5\,
      O(1) => \samp_edge_cnt1_r_reg[4]_i_1_n_6\,
      O(0) => \samp_edge_cnt1_r_reg[4]_i_1_n_7\,
      S(3 downto 0) => samp_edge_cnt1_r_reg(7 downto 4)
    );
\samp_edge_cnt1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[4]_i_1_n_6\,
      Q => samp_edge_cnt1_r_reg(5),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[4]_i_1_n_5\,
      Q => samp_edge_cnt1_r_reg(6),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[4]_i_1_n_4\,
      Q => samp_edge_cnt1_r_reg(7),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[8]_i_1_n_7\,
      Q => samp_edge_cnt1_r_reg(8),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\samp_edge_cnt1_r_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \samp_edge_cnt1_r_reg[4]_i_1_n_0\,
      CO(3) => \NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \samp_edge_cnt1_r_reg[8]_i_1_n_1\,
      CO(1) => \samp_edge_cnt1_r_reg[8]_i_1_n_2\,
      CO(0) => \samp_edge_cnt1_r_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \samp_edge_cnt1_r_reg[8]_i_1_n_4\,
      O(2) => \samp_edge_cnt1_r_reg[8]_i_1_n_5\,
      O(1) => \samp_edge_cnt1_r_reg[8]_i_1_n_6\,
      O(0) => \samp_edge_cnt1_r_reg[8]_i_1_n_7\,
      S(3 downto 0) => samp_edge_cnt1_r_reg(11 downto 8)
    );
\samp_edge_cnt1_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[8]_i_1_n_6\,
      Q => samp_edge_cnt1_r_reg(9),
      R => \samp_edge_cnt1_r_reg[0]_0\
    );
\second_edge_taps_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O => tap_cnt_cpt_r0(0)
    );
\second_edge_taps_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O => \second_edge_taps_r[1]_i_1_n_0\
    );
\second_edge_taps_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      O => \second_edge_taps_r[2]_i_1_n_0\
    );
\second_edge_taps_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      O => \second_edge_taps_r[3]_i_1_n_0\
    );
\second_edge_taps_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O => \second_edge_taps_r[4]_i_1_n_0\
    );
\second_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EAAA"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => \first_edge_taps_r[5]_i_3_n_0\,
      I2 => found_first_edge_r_reg_n_0,
      I3 => found_stable_eye_last_r,
      I4 => store_sr_req_pulsed_r,
      O => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => cal1_prech_req_r,
      I1 => \first_edge_taps_r[5]_i_3_n_0\,
      I2 => found_first_edge_r_reg_n_0,
      I3 => found_stable_eye_last_r,
      O => \second_edge_taps_r[5]_i_2_n_0\
    );
\second_edge_taps_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I5 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      O => \second_edge_taps_r[5]_i_3_n_0\
    );
\second_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => tap_cnt_cpt_r0(0),
      Q => \second_edge_taps_r_reg_n_0_[0]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[1]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[1]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[2]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[2]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[3]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[3]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[4]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[4]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[5]_i_3_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[5]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
sr_valid_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sr_valid_r_reg_n_0,
      Q => sr_valid_r1,
      R => '0'
    );
sr_valid_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sr_valid_r1,
      Q => sr_valid_r2,
      R => '0'
    );
sr_valid_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => rdlvl_stg1_start_r_reg_0,
      I1 => E(0),
      I2 => cnt_shift_r_reg(3),
      I3 => cnt_shift_r_reg(2),
      I4 => cnt_shift_r_reg(0),
      I5 => cnt_shift_r_reg(1),
      O => sr_valid_r_i_1_n_0
    );
sr_valid_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sr_valid_r_i_1_n_0,
      Q => sr_valid_r_reg_n_0,
      R => found_second_edge_r_reg_0
    );
\stg1_wr_rd_cnt[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => reset_if_reg,
      I1 => \^d\(2),
      I2 => stg1_wr_done,
      O => \rstdiv0_sync_r1_reg_rep__14\
    );
store_sr_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => store_sr_req_r_reg_n_0,
      I1 => sr_valid_r_reg_n_0,
      I2 => store_sr_r_reg_n_0,
      O => store_sr_r_i_1_n_0
    );
store_sr_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => store_sr_r_i_1_n_0,
      Q => store_sr_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
store_sr_req_pulsed_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => store_sr_req_pulsed_r,
      Q => \store_sr_req_pulsed_r__0\,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
store_sr_req_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44444F44"
    )
        port map (
      I0 => \store_sr_req_pulsed_r__0\,
      I1 => store_sr_req_pulsed_r,
      I2 => cal1_wait_r,
      I3 => \^q\(0),
      I4 => store_sr_req_r_reg_0,
      O => store_sr_req_r
    );
store_sr_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => store_sr_req_r,
      Q => store_sr_req_r_reg_n_0,
      R => \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1)
    );
\tap_cnt_cpt_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => cal1_dlyinc_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O => \tap_cnt_cpt_r[1]_i_1_n_0\
    );
\tap_cnt_cpt_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AA9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I3 => cal1_dlyinc_cpt_r_reg_n_0,
      O => \p_0_in__0\(2)
    );
\tap_cnt_cpt_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6CCCCCC9"
    )
        port map (
      I0 => cal1_dlyinc_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      O => \p_0_in__0\(3)
    );
\tap_cnt_cpt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCC9"
    )
        port map (
      I0 => cal1_dlyinc_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      O => \p_0_in__0\(4)
    );
\tap_cnt_cpt_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA8A"
    )
        port map (
      I0 => cal1_dlyce_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I2 => \tap_cnt_cpt_r[5]_i_4_n_0\,
      I3 => cal1_dlyinc_cpt_r_reg_n_0,
      O => tap_cnt_cpt_r
    );
\tap_cnt_cpt_r[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1DD1"
    )
        port map (
      I0 => \tap_cnt_cpt_r[5]_i_5_n_0\,
      I1 => cal1_dlyinc_cpt_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I3 => \tap_cnt_cpt_r[5]_i_6_n_0\,
      O => \p_0_in__0\(5)
    );
\tap_cnt_cpt_r[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O => \tap_cnt_cpt_r[5]_i_4_n_0\
    );
\tap_cnt_cpt_r[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555556"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I5 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      O => \tap_cnt_cpt_r[5]_i_5_n_0\
    );
\tap_cnt_cpt_r[5]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O => \tap_cnt_cpt_r[5]_i_6_n_0\
    );
\tap_cnt_cpt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tap_cnt_cpt_r,
      D => tap_cnt_cpt_r0(0),
      Q => \tap_cnt_cpt_r_reg_n_0_[0]\,
      R => \tap_cnt_cpt_r_reg[5]_0\(0)
    );
\tap_cnt_cpt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tap_cnt_cpt_r,
      D => \tap_cnt_cpt_r[1]_i_1_n_0\,
      Q => \tap_cnt_cpt_r_reg_n_0_[1]\,
      R => \tap_cnt_cpt_r_reg[5]_0\(0)
    );
\tap_cnt_cpt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tap_cnt_cpt_r,
      D => \p_0_in__0\(2),
      Q => \tap_cnt_cpt_r_reg_n_0_[2]\,
      R => \tap_cnt_cpt_r_reg[5]_0\(0)
    );
\tap_cnt_cpt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tap_cnt_cpt_r,
      D => \p_0_in__0\(3),
      Q => \tap_cnt_cpt_r_reg_n_0_[3]\,
      R => \tap_cnt_cpt_r_reg[5]_0\(0)
    );
\tap_cnt_cpt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tap_cnt_cpt_r,
      D => \p_0_in__0\(4),
      Q => \tap_cnt_cpt_r_reg_n_0_[4]\,
      R => \tap_cnt_cpt_r_reg[5]_0\(0)
    );
\tap_cnt_cpt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tap_cnt_cpt_r,
      D => \p_0_in__0\(5),
      Q => \tap_cnt_cpt_r_reg_n_0_[5]\,
      R => \tap_cnt_cpt_r_reg[5]_0\(0)
    );
tap_limit_cpt_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000AA80"
    )
        port map (
      I0 => tap_limit_cpt_r_i_2_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I2 => \tap_cnt_cpt_r[5]_i_6_n_0\,
      I3 => tap_limit_cpt_r,
      I4 => \done_cnt_reg[2]_0\,
      I5 => \^new_cnt_cpt_r_reg_0\,
      O => tap_limit_cpt_r_i_1_n_0
    );
tap_limit_cpt_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \cal1_state_r1_reg_n_0_[4]\,
      I1 => \cal1_state_r1_reg_n_0_[5]\,
      I2 => \cal1_state_r1_reg_n_0_[0]\,
      I3 => \cal1_state_r1_reg_n_0_[2]\,
      I4 => \cal1_state_r1_reg_n_0_[1]\,
      I5 => \cal1_state_r1_reg_n_0_[3]\,
      O => tap_limit_cpt_r_i_2_n_0
    );
tap_limit_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tap_limit_cpt_r_i_1_n_0,
      Q => tap_limit_cpt_r,
      R => '0'
    );
\wait_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_cnt_r_reg(0),
      O => \wait_cnt_r0__0\(0)
    );
\wait_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_cnt_r_reg(1),
      I1 => wait_cnt_r_reg(0),
      O => \wait_cnt_r[1]_i_1_n_0\
    );
\wait_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_cnt_r_reg(2),
      I1 => wait_cnt_r_reg(0),
      I2 => wait_cnt_r_reg(1),
      O => \wait_cnt_r0__0\(2)
    );
\wait_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => dqs_po_dec_done_r2,
      I1 => wait_cnt_r_reg(2),
      I2 => wait_cnt_r_reg(3),
      I3 => wait_cnt_r_reg(1),
      I4 => wait_cnt_r_reg(0),
      O => wait_cnt_r0
    );
\wait_cnt_r[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_cnt_r_reg(3),
      I1 => wait_cnt_r_reg(2),
      I2 => wait_cnt_r_reg(1),
      I3 => wait_cnt_r_reg(0),
      O => \wait_cnt_r0__0\(3)
    );
\wait_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wait_cnt_r0,
      D => \wait_cnt_r0__0\(0),
      Q => wait_cnt_r_reg(0),
      R => SS(0)
    );
\wait_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wait_cnt_r0,
      D => \wait_cnt_r[1]_i_1_n_0\,
      Q => wait_cnt_r_reg(1),
      R => SS(0)
    );
\wait_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wait_cnt_r0,
      D => \wait_cnt_r0__0\(2),
      Q => wait_cnt_r_reg(2),
      R => SS(0)
    );
\wait_cnt_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => wait_cnt_r0,
      D => \wait_cnt_r0__0\(3),
      Q => wait_cnt_r_reg(3),
      S => SS(0)
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[109]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^d\(2),
      O => \^d\(1)
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[125]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^d\(2),
      I1 => first_wrcal_pat_r,
      O => \^d\(3)
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[127]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^d\(2),
      I1 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]\,
      O => rdlvl_stg1_done_int_reg_1(0)
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[127]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^d\(2),
      I1 => first_wrcal_pat_r,
      O => \^d\(4)
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^d\(2),
      I1 => first_rdlvl_pat_r,
      O => \^d\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_phy_tempmon is
  port (
    pi_f_inc_reg_0 : out STD_LOGIC;
    pi_f_dec_reg_0 : out STD_LOGIC;
    pi_f_dec_reg_1 : out STD_LOGIC;
    calib_sel0 : out STD_LOGIC;
    init_calib_complete_reg : out STD_LOGIC;
    CLK : in STD_LOGIC;
    \one_inc_min_limit_reg[2]_0\ : in STD_LOGIC;
    tempmon_sample_en : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \four_inc_max_limit_reg[11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \three_dec_max_limit_reg[11]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    pi_fine_dly_dec_done : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ : in STD_LOGIC;
    \calib_zero_inputs_reg[0]\ : in STD_LOGIC;
    \calib_zero_ctrl_reg[0]\ : in STD_LOGIC;
    \two_inc_max_limit_reg[2]_0\ : in STD_LOGIC;
    \device_temp_101_reg[11]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
    \four_dec_min_limit_reg[11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_phy_tempmon : entity is "mig_7series_v4_2_ddr_phy_tempmon";
end mig_7series_0_mig_7series_v4_2_ddr_phy_tempmon;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_phy_tempmon is
  signal device_temp_101 : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal device_temp_init : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \device_temp_init[11]_i_2_n_0\ : STD_LOGIC;
  signal \device_temp_init[11]_i_3_n_0\ : STD_LOGIC;
  signal four_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \four_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal four_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \four_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal four_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \four_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[4]_i_4_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[4]_i_5_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal four_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \four_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal neutral_max_limit : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \neutral_max_limit[1]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[4]_i_4_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal neutral_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \neutral_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \neutral_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \neutral_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \neutral_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \neutral_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal neutral_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \neutral_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal neutral_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \neutral_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \neutral_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \neutral_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \neutral_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \neutral_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal one_dec_max_limit : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \one_dec_max_limit[1]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit[8]_i_4_n_0\ : STD_LOGIC;
  signal one_dec_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_dec_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal one_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal one_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal one_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[11]_i_4_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal one_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal one_inc_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_inc_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal one_inc_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_inc_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal pi_f_dec_i_2_n_0 : STD_LOGIC;
  signal pi_f_dec_nxt : STD_LOGIC;
  signal \^pi_f_dec_reg_0\ : STD_LOGIC;
  signal pi_f_inc_i_2_n_0 : STD_LOGIC;
  signal pi_f_inc_i_3_n_0 : STD_LOGIC;
  signal pi_f_inc_i_4_n_0 : STD_LOGIC;
  signal pi_f_inc_i_5_n_0 : STD_LOGIC;
  signal pi_f_inc_i_6_n_0 : STD_LOGIC;
  signal pi_f_inc_i_7_n_0 : STD_LOGIC;
  signal pi_f_inc_nxt : STD_LOGIC;
  signal \^pi_f_inc_reg_0\ : STD_LOGIC;
  signal temp_cmp_four_dec_min_101 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_four_inc_max_101 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_neutral_max_101 : STD_LOGIC;
  signal temp_cmp_neutral_max_102 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_neutral_min_101 : STD_LOGIC;
  signal temp_cmp_neutral_min_102 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_one_dec_max_101 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_one_dec_min_101 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_one_inc_max_101 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_one_inc_min_101 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_three_dec_max_101 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_three_dec_min_101 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_three_inc_max_101 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_three_inc_min_101 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_two_dec_max_101 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_two_dec_min_101 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_two_inc_max_101 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_two_inc_min_101 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal tempmon_init_complete : STD_LOGIC;
  signal tempmon_sample_en_101 : STD_LOGIC;
  signal tempmon_sample_en_102 : STD_LOGIC;
  signal tempmon_state : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \tempmon_state[10]_i_10_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_11_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_12_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_13_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_14_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_15_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_1_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_3_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_4_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_5_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_6_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_7_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_8_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_9_n_0\ : STD_LOGIC;
  signal \tempmon_state[6]_i_2_n_0\ : STD_LOGIC;
  signal tempmon_state_init : STD_LOGIC;
  signal tempmon_state_nxt : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal three_dec_max_limit : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \three_dec_max_limit[0]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[10]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[11]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[1]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[2]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[3]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[4]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[5]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[6]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[7]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[8]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[8]_i_4_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[9]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_2\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_3\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_5\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_6\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_7\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_1\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_2\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_3\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_4\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_5\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_6\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_4\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_5\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_6\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_7\ : STD_LOGIC;
  signal three_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \three_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal three_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \three_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal three_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \three_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[8]_i_4_n_0\ : STD_LOGIC;
  signal three_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \three_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal three_inc_min_limit : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \three_inc_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal three_inc_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \three_inc_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal two_dec_max_limit : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \two_dec_max_limit[0]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal two_dec_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \two_dec_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal two_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal two_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal two_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[11]_i_4_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[4]_i_4_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal two_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal two_inc_min_limit : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \two_inc_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal two_inc_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_inc_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal \update_temp_101__0\ : STD_LOGIC;
  signal update_temp_102 : STD_LOGIC;
  signal \NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \calib_zero_ctrl[0]_i_2\ : label is "soft_lutpair171";
  attribute SOFT_HLUTNM of \calib_zero_inputs[0]_i_1\ : label is "soft_lutpair171";
  attribute SOFT_HLUTNM of \device_temp_init[11]_i_3\ : label is "soft_lutpair170";
  attribute SOFT_HLUTNM of \neutral_max_limit[1]_i_1\ : label is "soft_lutpair178";
  attribute SOFT_HLUTNM of pi_f_inc_i_7 : label is "soft_lutpair168";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_10\ : label is "soft_lutpair166";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_11\ : label is "soft_lutpair166";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_15\ : label is "soft_lutpair169";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_4\ : label is "soft_lutpair167";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_7\ : label is "soft_lutpair168";
  attribute SOFT_HLUTNM of \tempmon_state[1]_i_1\ : label is "soft_lutpair167";
  attribute SOFT_HLUTNM of \tempmon_state[6]_i_2\ : label is "soft_lutpair170";
  attribute SOFT_HLUTNM of \tempmon_state[9]_i_1\ : label is "soft_lutpair169";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[0]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[10]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[1]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[2]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[3]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[4]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[5]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[6]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[7]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[8]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute FSM_ENCODED_STATES of \tempmon_state_reg[9]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000";
  attribute SOFT_HLUTNM of \three_dec_max_limit[0]_i_1\ : label is "soft_lutpair177";
  attribute SOFT_HLUTNM of \three_dec_max_limit[10]_i_1\ : label is "soft_lutpair172";
  attribute SOFT_HLUTNM of \three_dec_max_limit[11]_i_1\ : label is "soft_lutpair173";
  attribute SOFT_HLUTNM of \three_dec_max_limit[1]_i_1\ : label is "soft_lutpair177";
  attribute SOFT_HLUTNM of \three_dec_max_limit[2]_i_1\ : label is "soft_lutpair172";
  attribute SOFT_HLUTNM of \three_dec_max_limit[3]_i_1\ : label is "soft_lutpair174";
  attribute SOFT_HLUTNM of \three_dec_max_limit[4]_i_1\ : label is "soft_lutpair173";
  attribute SOFT_HLUTNM of \three_dec_max_limit[5]_i_1\ : label is "soft_lutpair176";
  attribute SOFT_HLUTNM of \three_dec_max_limit[6]_i_1\ : label is "soft_lutpair176";
  attribute SOFT_HLUTNM of \three_dec_max_limit[7]_i_1\ : label is "soft_lutpair175";
  attribute SOFT_HLUTNM of \three_dec_max_limit[8]_i_1\ : label is "soft_lutpair175";
  attribute SOFT_HLUTNM of \three_dec_max_limit[9]_i_1\ : label is "soft_lutpair174";
  attribute SOFT_HLUTNM of \two_dec_max_limit[0]_i_1\ : label is "soft_lutpair178";
begin
  pi_f_dec_reg_0 <= \^pi_f_dec_reg_0\;
  pi_f_inc_reg_0 <= \^pi_f_inc_reg_0\;
\calib_zero_ctrl[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF10"
    )
        port map (
      I0 => \^pi_f_inc_reg_0\,
      I1 => \^pi_f_dec_reg_0\,
      I2 => \calib_zero_inputs_reg[0]\,
      I3 => \calib_zero_ctrl_reg[0]\,
      O => calib_sel0
    );
\calib_zero_inputs[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \calib_zero_inputs_reg[0]\,
      I1 => \^pi_f_dec_reg_0\,
      I2 => \^pi_f_inc_reg_0\,
      O => init_calib_complete_reg
    );
\device_temp_101_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(0),
      Q => device_temp_101(0),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_101_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(10),
      Q => device_temp_101(10),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_101_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(11),
      Q => device_temp_101(11),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_101_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(1),
      Q => device_temp_101(1),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_101_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(2),
      Q => device_temp_101(2),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_101_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(3),
      Q => device_temp_101(3),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_101_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(4),
      Q => device_temp_101(4),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_101_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(5),
      Q => device_temp_101(5),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_101_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(6),
      Q => device_temp_101(6),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_101_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(7),
      Q => device_temp_101(7),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_101_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(8),
      Q => device_temp_101(8),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_101_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_101_reg[11]_0\(9),
      Q => device_temp_101(9),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_init[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => tempmon_state(9),
      I1 => tempmon_state(7),
      I2 => tempmon_state(8),
      I3 => \device_temp_init[11]_i_2_n_0\,
      I4 => \device_temp_init[11]_i_3_n_0\,
      O => tempmon_state_init
    );
\device_temp_init[11]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => tempmon_state(1),
      I1 => tempmon_state(2),
      I2 => tempmon_state(3),
      I3 => tempmon_state(10),
      O => \device_temp_init[11]_i_2_n_0\
    );
\device_temp_init[11]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => tempmon_state(0),
      I1 => tempmon_state(4),
      I2 => tempmon_state(5),
      I3 => tempmon_state(6),
      O => \device_temp_init[11]_i_3_n_0\
    );
\device_temp_init_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(0),
      Q => device_temp_init(0),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_init_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(10),
      Q => device_temp_init(10),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_init_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(11),
      Q => device_temp_init(11),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_init_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(1),
      Q => device_temp_init(1),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_init_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(2),
      Q => device_temp_init(2),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_init_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(3),
      Q => device_temp_init(3),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_init_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(4),
      Q => device_temp_init(4),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_init_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(5),
      Q => device_temp_init(5),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_init_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(6),
      Q => device_temp_init(6),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_init_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(7),
      Q => device_temp_init(7),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_init_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(8),
      Q => device_temp_init(8),
      R => \two_inc_max_limit_reg[2]_0\
    );
\device_temp_init_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(9),
      Q => device_temp_init(9),
      R => \two_inc_max_limit_reg[2]_0\
    );
\four_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(11),
      O => \four_dec_min_limit[11]_i_2_n_0\
    );
\four_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(10),
      O => \four_dec_min_limit[11]_i_3_n_0\
    );
\four_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(5),
      O => \four_dec_min_limit[5]_i_2_n_0\
    );
\four_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(4),
      O => \four_dec_min_limit[5]_i_3_n_0\
    );
\four_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(3),
      O => \four_dec_min_limit[5]_i_4_n_0\
    );
\four_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(9),
      O => \four_dec_min_limit[9]_i_2_n_0\
    );
\four_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(8),
      O => \four_dec_min_limit[9]_i_3_n_0\
    );
\four_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(7),
      O => \four_dec_min_limit[9]_i_4_n_0\
    );
\four_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(6),
      O => \four_dec_min_limit[9]_i_5_n_0\
    );
\four_dec_min_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_max_limit(0),
      Q => four_dec_min_limit(0),
      R => \four_dec_min_limit_reg[11]_0\(0)
    );
\four_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(10),
      Q => four_dec_min_limit(10),
      R => \four_dec_min_limit_reg[11]_0\(0)
    );
\four_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(11),
      Q => four_dec_min_limit(11),
      R => \four_dec_min_limit_reg[11]_0\(0)
    );
\four_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \four_dec_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \four_dec_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => three_dec_max_limit(10),
      O(3 downto 2) => \NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => four_dec_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \four_dec_min_limit[11]_i_2_n_0\,
      S(0) => \four_dec_min_limit[11]_i_3_n_0\
    );
\four_dec_min_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_max_limit(1),
      Q => four_dec_min_limit(1),
      R => \four_dec_min_limit_reg[11]_0\(0)
    );
\four_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(2),
      Q => four_dec_min_limit(2),
      R => \four_dec_min_limit_reg[11]_0\(0)
    );
\four_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(3),
      Q => four_dec_min_limit(3),
      R => \four_dec_min_limit_reg[11]_0\(0)
    );
\four_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(4),
      Q => four_dec_min_limit(4),
      R => \four_dec_min_limit_reg[11]_0\(0)
    );
\four_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(5),
      Q => four_dec_min_limit(5),
      R => \four_dec_min_limit_reg[11]_0\(0)
    );
\four_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \four_dec_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \four_dec_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \four_dec_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \four_dec_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => three_dec_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => four_dec_min_limit_nxt(5 downto 2),
      S(3) => \four_dec_min_limit[5]_i_2_n_0\,
      S(2) => \four_dec_min_limit[5]_i_3_n_0\,
      S(1) => \four_dec_min_limit[5]_i_4_n_0\,
      S(0) => three_dec_max_limit(2)
    );
\four_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(6),
      Q => four_dec_min_limit(6),
      R => \four_dec_min_limit_reg[11]_0\(0)
    );
\four_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(7),
      Q => four_dec_min_limit(7),
      R => \four_dec_min_limit_reg[11]_0\(0)
    );
\four_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(8),
      Q => four_dec_min_limit(8),
      R => \four_dec_min_limit_reg[11]_0\(0)
    );
\four_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(9),
      Q => four_dec_min_limit(9),
      R => \four_dec_min_limit_reg[11]_0\(0)
    );
\four_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \four_dec_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \four_dec_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \four_dec_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \four_dec_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \four_dec_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => three_dec_max_limit(9 downto 6),
      O(3 downto 0) => four_dec_min_limit_nxt(9 downto 6),
      S(3) => \four_dec_min_limit[9]_i_2_n_0\,
      S(2) => \four_dec_min_limit[9]_i_3_n_0\,
      S(1) => \four_dec_min_limit[9]_i_4_n_0\,
      S(0) => \four_dec_min_limit[9]_i_5_n_0\
    );
\four_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(11),
      O => \four_inc_max_limit[11]_i_2_n_0\
    );
\four_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(10),
      O => \four_inc_max_limit[11]_i_3_n_0\
    );
\four_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(4),
      O => \four_inc_max_limit[4]_i_2_n_0\
    );
\four_inc_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(3),
      O => \four_inc_max_limit[4]_i_3_n_0\
    );
\four_inc_max_limit[4]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(2),
      O => \four_inc_max_limit[4]_i_4_n_0\
    );
\four_inc_max_limit[4]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(1),
      O => \four_inc_max_limit[4]_i_5_n_0\
    );
\four_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(7),
      O => \four_inc_max_limit[8]_i_2_n_0\
    );
\four_inc_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(5),
      O => \four_inc_max_limit[8]_i_3_n_0\
    );
\four_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(10),
      Q => four_inc_max_limit(10),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\four_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(11),
      Q => four_inc_max_limit(11),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\four_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \four_inc_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \four_inc_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \four_inc_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => device_temp_init(10),
      DI(0) => '0',
      O(3) => \NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => four_inc_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2) => \four_inc_max_limit[11]_i_2_n_0\,
      S(1) => \four_inc_max_limit[11]_i_3_n_0\,
      S(0) => device_temp_init(9)
    );
\four_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(2),
      Q => four_inc_max_limit(2),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\four_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(3),
      Q => four_inc_max_limit(3),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\four_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(4),
      Q => four_inc_max_limit(4),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\four_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \four_inc_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \four_inc_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \four_inc_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \four_inc_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3 downto 0) => device_temp_init(4 downto 1),
      O(3 downto 1) => four_inc_max_limit_nxt(4 downto 2),
      O(0) => two_dec_max_limit_nxt(1),
      S(3) => \four_inc_max_limit[4]_i_2_n_0\,
      S(2) => \four_inc_max_limit[4]_i_3_n_0\,
      S(1) => \four_inc_max_limit[4]_i_4_n_0\,
      S(0) => \four_inc_max_limit[4]_i_5_n_0\
    );
\four_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(5),
      Q => four_inc_max_limit(5),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\four_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(6),
      Q => four_inc_max_limit(6),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\four_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(7),
      Q => four_inc_max_limit(7),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\four_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(8),
      Q => four_inc_max_limit(8),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\four_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \four_inc_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \four_inc_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \four_inc_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \four_inc_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \four_inc_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => device_temp_init(7),
      DI(1) => '0',
      DI(0) => device_temp_init(5),
      O(3 downto 0) => four_inc_max_limit_nxt(8 downto 5),
      S(3) => device_temp_init(8),
      S(2) => \four_inc_max_limit[8]_i_2_n_0\,
      S(1) => device_temp_init(6),
      S(0) => \four_inc_max_limit[8]_i_3_n_0\
    );
\four_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(9),
      Q => four_inc_max_limit(9),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\gen_byte_sel_div2.byte_sel_cnt[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EF000000"
    )
        port map (
      I0 => \^pi_f_dec_reg_0\,
      I1 => \^pi_f_inc_reg_0\,
      I2 => D(0),
      I3 => pi_fine_dly_dec_done,
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]\,
      O => pi_f_dec_reg_1
    );
\neutral_max_limit[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => device_temp_init(0),
      I1 => device_temp_init(1),
      O => \neutral_max_limit[1]_i_1_n_0\
    );
\neutral_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(4),
      O => \neutral_max_limit[4]_i_2_n_0\
    );
\neutral_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(2),
      O => \neutral_max_limit[4]_i_3_n_0\
    );
\neutral_max_limit[4]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(1),
      O => \neutral_max_limit[4]_i_4_n_0\
    );
\neutral_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(6),
      O => \neutral_max_limit[8]_i_2_n_0\
    );
\neutral_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(5),
      O => \neutral_max_limit[8]_i_3_n_0\
    );
\neutral_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(10),
      Q => neutral_max_limit(10),
      R => \one_inc_min_limit_reg[2]_0\
    );
\neutral_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(11),
      Q => neutral_max_limit(11),
      R => \one_inc_min_limit_reg[2]_0\
    );
\neutral_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \neutral_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \neutral_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \neutral_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => neutral_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2 downto 0) => device_temp_init(11 downto 9)
    );
\neutral_max_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \neutral_max_limit[1]_i_1_n_0\,
      Q => neutral_max_limit(1),
      R => \one_inc_min_limit_reg[2]_0\
    );
\neutral_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(2),
      Q => neutral_max_limit(2),
      R => \one_inc_min_limit_reg[2]_0\
    );
\neutral_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(3),
      Q => neutral_max_limit(3),
      R => \one_inc_min_limit_reg[2]_0\
    );
\neutral_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(4),
      Q => neutral_max_limit(4),
      R => \one_inc_min_limit_reg[2]_0\
    );
\neutral_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \neutral_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \neutral_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \neutral_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \neutral_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3) => device_temp_init(4),
      DI(2) => '0',
      DI(1 downto 0) => device_temp_init(2 downto 1),
      O(3 downto 1) => neutral_max_limit_nxt(4 downto 2),
      O(0) => \NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => \neutral_max_limit[4]_i_2_n_0\,
      S(2) => device_temp_init(3),
      S(1) => \neutral_max_limit[4]_i_3_n_0\,
      S(0) => \neutral_max_limit[4]_i_4_n_0\
    );
\neutral_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(5),
      Q => neutral_max_limit(5),
      R => \one_inc_min_limit_reg[2]_0\
    );
\neutral_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(6),
      Q => neutral_max_limit(6),
      R => \one_inc_min_limit_reg[2]_0\
    );
\neutral_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(7),
      Q => neutral_max_limit(7),
      R => \one_inc_min_limit_reg[2]_0\
    );
\neutral_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(8),
      Q => neutral_max_limit(8),
      R => \one_inc_min_limit_reg[2]_0\
    );
\neutral_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \neutral_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \neutral_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \neutral_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \neutral_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \neutral_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => device_temp_init(6 downto 5),
      O(3 downto 0) => neutral_max_limit_nxt(8 downto 5),
      S(3 downto 2) => device_temp_init(8 downto 7),
      S(1) => \neutral_max_limit[8]_i_2_n_0\,
      S(0) => \neutral_max_limit[8]_i_3_n_0\
    );
\neutral_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(9),
      Q => neutral_max_limit(9),
      R => \one_inc_min_limit_reg[2]_0\
    );
\neutral_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(11),
      O => \neutral_min_limit[11]_i_2_n_0\
    );
\neutral_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(10),
      O => \neutral_min_limit[11]_i_3_n_0\
    );
\neutral_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(5),
      O => \neutral_min_limit[5]_i_2_n_0\
    );
\neutral_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(4),
      O => \neutral_min_limit[5]_i_3_n_0\
    );
\neutral_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(3),
      O => \neutral_min_limit[5]_i_4_n_0\
    );
\neutral_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(9),
      O => \neutral_min_limit[9]_i_2_n_0\
    );
\neutral_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(8),
      O => \neutral_min_limit[9]_i_3_n_0\
    );
\neutral_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(7),
      O => \neutral_min_limit[9]_i_4_n_0\
    );
\neutral_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(6),
      O => \neutral_min_limit[9]_i_5_n_0\
    );
\neutral_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(10),
      Q => neutral_min_limit(10),
      R => \three_dec_max_limit_reg[11]_0\
    );
\neutral_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(11),
      Q => neutral_min_limit(11),
      R => \three_dec_max_limit_reg[11]_0\
    );
\neutral_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \neutral_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \neutral_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => one_inc_max_limit(10),
      O(3 downto 2) => \NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => neutral_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \neutral_min_limit[11]_i_2_n_0\,
      S(0) => \neutral_min_limit[11]_i_3_n_0\
    );
\neutral_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(2),
      Q => neutral_min_limit(2),
      R => \three_dec_max_limit_reg[11]_0\
    );
\neutral_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(3),
      Q => neutral_min_limit(3),
      R => \three_dec_max_limit_reg[11]_0\
    );
\neutral_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(4),
      Q => neutral_min_limit(4),
      R => \three_dec_max_limit_reg[11]_0\
    );
\neutral_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(5),
      Q => neutral_min_limit(5),
      R => \three_dec_max_limit_reg[11]_0\
    );
\neutral_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \neutral_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \neutral_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \neutral_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \neutral_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => one_inc_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => neutral_min_limit_nxt(5 downto 2),
      S(3) => \neutral_min_limit[5]_i_2_n_0\,
      S(2) => \neutral_min_limit[5]_i_3_n_0\,
      S(1) => \neutral_min_limit[5]_i_4_n_0\,
      S(0) => one_inc_max_limit(2)
    );
\neutral_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(6),
      Q => neutral_min_limit(6),
      R => \three_dec_max_limit_reg[11]_0\
    );
\neutral_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(7),
      Q => neutral_min_limit(7),
      R => \three_dec_max_limit_reg[11]_0\
    );
\neutral_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(8),
      Q => neutral_min_limit(8),
      R => \three_dec_max_limit_reg[11]_0\
    );
\neutral_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(9),
      Q => neutral_min_limit(9),
      R => \three_dec_max_limit_reg[11]_0\
    );
\neutral_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \neutral_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \neutral_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \neutral_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \neutral_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \neutral_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => one_inc_max_limit(9 downto 6),
      O(3 downto 0) => neutral_min_limit_nxt(9 downto 6),
      S(3) => \neutral_min_limit[9]_i_2_n_0\,
      S(2) => \neutral_min_limit[9]_i_3_n_0\,
      S(1) => \neutral_min_limit[9]_i_4_n_0\,
      S(0) => \neutral_min_limit[9]_i_5_n_0\
    );
\one_dec_max_limit[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => device_temp_init(1),
      I1 => device_temp_init(0),
      O => \one_dec_max_limit[1]_i_1_n_0\
    );
\one_dec_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(2),
      O => \one_dec_max_limit[4]_i_2_n_0\
    );
\one_dec_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(8),
      O => \one_dec_max_limit[8]_i_2_n_0\
    );
\one_dec_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(6),
      O => \one_dec_max_limit[8]_i_3_n_0\
    );
\one_dec_max_limit[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(5),
      O => \one_dec_max_limit[8]_i_4_n_0\
    );
\one_dec_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(10),
      Q => one_dec_max_limit(10),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_dec_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(11),
      Q => one_dec_max_limit(11),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_dec_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_dec_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \one_dec_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \one_dec_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => one_dec_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2 downto 0) => device_temp_init(11 downto 9)
    );
\one_dec_max_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \one_dec_max_limit[1]_i_1_n_0\,
      Q => one_dec_max_limit(1),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_dec_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(2),
      Q => one_dec_max_limit(2),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_dec_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(3),
      Q => one_dec_max_limit(3),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_dec_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(4),
      Q => one_dec_max_limit(4),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_dec_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \one_dec_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \one_dec_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \one_dec_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \one_dec_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3 downto 2) => B"00",
      DI(1) => device_temp_init(2),
      DI(0) => '0',
      O(3 downto 1) => one_dec_max_limit_nxt(4 downto 2),
      O(0) => \NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3 downto 2) => device_temp_init(4 downto 3),
      S(1) => \one_dec_max_limit[4]_i_2_n_0\,
      S(0) => device_temp_init(1)
    );
\one_dec_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(5),
      Q => one_dec_max_limit(5),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_dec_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(6),
      Q => one_dec_max_limit(6),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_dec_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(7),
      Q => one_dec_max_limit(7),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_dec_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(8),
      Q => one_dec_max_limit(8),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_dec_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_dec_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \one_dec_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \one_dec_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \one_dec_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \one_dec_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => device_temp_init(8),
      DI(2) => '0',
      DI(1 downto 0) => device_temp_init(6 downto 5),
      O(3 downto 0) => one_dec_max_limit_nxt(8 downto 5),
      S(3) => \one_dec_max_limit[8]_i_2_n_0\,
      S(2) => device_temp_init(7),
      S(1) => \one_dec_max_limit[8]_i_3_n_0\,
      S(0) => \one_dec_max_limit[8]_i_4_n_0\
    );
\one_dec_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(9),
      Q => one_dec_max_limit(9),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(11),
      O => \one_dec_min_limit[11]_i_2_n_0\
    );
\one_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(10),
      O => \one_dec_min_limit[11]_i_3_n_0\
    );
\one_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(5),
      O => \one_dec_min_limit[5]_i_2_n_0\
    );
\one_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(4),
      O => \one_dec_min_limit[5]_i_3_n_0\
    );
\one_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(3),
      O => \one_dec_min_limit[5]_i_4_n_0\
    );
\one_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(9),
      O => \one_dec_min_limit[9]_i_2_n_0\
    );
\one_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(8),
      O => \one_dec_min_limit[9]_i_3_n_0\
    );
\one_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(7),
      O => \one_dec_min_limit[9]_i_4_n_0\
    );
\one_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(6),
      O => \one_dec_min_limit[9]_i_5_n_0\
    );
\one_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(10),
      Q => one_dec_min_limit(10),
      R => SR(0)
    );
\one_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(11),
      Q => one_dec_min_limit(11),
      R => SR(0)
    );
\one_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_dec_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \one_dec_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => neutral_max_limit(10),
      O(3 downto 2) => \NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => one_dec_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \one_dec_min_limit[11]_i_2_n_0\,
      S(0) => \one_dec_min_limit[11]_i_3_n_0\
    );
\one_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(2),
      Q => one_dec_min_limit(2),
      R => SR(0)
    );
\one_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(3),
      Q => one_dec_min_limit(3),
      R => SR(0)
    );
\one_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(4),
      Q => one_dec_min_limit(4),
      R => SR(0)
    );
\one_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(5),
      Q => one_dec_min_limit(5),
      R => SR(0)
    );
\one_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \one_dec_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \one_dec_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \one_dec_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \one_dec_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => neutral_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => one_dec_min_limit_nxt(5 downto 2),
      S(3) => \one_dec_min_limit[5]_i_2_n_0\,
      S(2) => \one_dec_min_limit[5]_i_3_n_0\,
      S(1) => \one_dec_min_limit[5]_i_4_n_0\,
      S(0) => neutral_max_limit(2)
    );
\one_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(6),
      Q => one_dec_min_limit(6),
      R => SR(0)
    );
\one_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(7),
      Q => one_dec_min_limit(7),
      R => SR(0)
    );
\one_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(8),
      Q => one_dec_min_limit(8),
      R => SR(0)
    );
\one_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(9),
      Q => one_dec_min_limit(9),
      R => SR(0)
    );
\one_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_dec_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \one_dec_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \one_dec_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \one_dec_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \one_dec_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => neutral_max_limit(9 downto 6),
      O(3 downto 0) => one_dec_min_limit_nxt(9 downto 6),
      S(3) => \one_dec_min_limit[9]_i_2_n_0\,
      S(2) => \one_dec_min_limit[9]_i_3_n_0\,
      S(1) => \one_dec_min_limit[9]_i_4_n_0\,
      S(0) => \one_dec_min_limit[9]_i_5_n_0\
    );
\one_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(11),
      O => \one_inc_max_limit[11]_i_2_n_0\
    );
\one_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(10),
      O => \one_inc_max_limit[11]_i_3_n_0\
    );
\one_inc_max_limit[11]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(9),
      O => \one_inc_max_limit[11]_i_4_n_0\
    );
\one_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(3),
      O => \one_inc_max_limit[4]_i_2_n_0\
    );
\one_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(8),
      O => \one_inc_max_limit[8]_i_2_n_0\
    );
\one_inc_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(7),
      O => \one_inc_max_limit[8]_i_3_n_0\
    );
\one_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(10),
      Q => one_inc_max_limit(10),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(11),
      Q => one_inc_max_limit(11),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_inc_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \one_inc_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \one_inc_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => device_temp_init(10 downto 9),
      O(3) => \NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => one_inc_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2) => \one_inc_max_limit[11]_i_2_n_0\,
      S(1) => \one_inc_max_limit[11]_i_3_n_0\,
      S(0) => \one_inc_max_limit[11]_i_4_n_0\
    );
\one_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(2),
      Q => one_inc_max_limit(2),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(3),
      Q => one_inc_max_limit(3),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(4),
      Q => one_inc_max_limit(4),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \one_inc_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \one_inc_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \one_inc_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \one_inc_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3) => '0',
      DI(2) => device_temp_init(3),
      DI(1 downto 0) => B"00",
      O(3 downto 1) => one_inc_max_limit_nxt(4 downto 2),
      O(0) => \NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => device_temp_init(4),
      S(2) => \one_inc_max_limit[4]_i_2_n_0\,
      S(1 downto 0) => device_temp_init(2 downto 1)
    );
\one_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(5),
      Q => one_inc_max_limit(5),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(6),
      Q => one_inc_max_limit(6),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(7),
      Q => one_inc_max_limit(7),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(8),
      Q => one_inc_max_limit(8),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_inc_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \one_inc_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \one_inc_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \one_inc_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \one_inc_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => device_temp_init(8 downto 7),
      DI(1 downto 0) => B"00",
      O(3 downto 0) => one_inc_max_limit_nxt(8 downto 5),
      S(3) => \one_inc_max_limit[8]_i_2_n_0\,
      S(2) => \one_inc_max_limit[8]_i_3_n_0\,
      S(1 downto 0) => device_temp_init(6 downto 5)
    );
\one_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(9),
      Q => one_inc_max_limit(9),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\one_inc_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(11),
      O => \one_inc_min_limit[11]_i_2_n_0\
    );
\one_inc_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(10),
      O => \one_inc_min_limit[11]_i_3_n_0\
    );
\one_inc_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(5),
      O => \one_inc_min_limit[5]_i_2_n_0\
    );
\one_inc_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(4),
      O => \one_inc_min_limit[5]_i_3_n_0\
    );
\one_inc_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(3),
      O => \one_inc_min_limit[5]_i_4_n_0\
    );
\one_inc_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(9),
      O => \one_inc_min_limit[9]_i_2_n_0\
    );
\one_inc_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(8),
      O => \one_inc_min_limit[9]_i_3_n_0\
    );
\one_inc_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(7),
      O => \one_inc_min_limit[9]_i_4_n_0\
    );
\one_inc_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(6),
      O => \one_inc_min_limit[9]_i_5_n_0\
    );
\one_inc_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(10),
      Q => one_inc_min_limit(10),
      R => \one_inc_min_limit_reg[2]_0\
    );
\one_inc_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(11),
      Q => one_inc_min_limit(11),
      R => \one_inc_min_limit_reg[2]_0\
    );
\one_inc_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_inc_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \one_inc_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => two_inc_max_limit(10),
      O(3 downto 2) => \NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => one_inc_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \one_inc_min_limit[11]_i_2_n_0\,
      S(0) => \one_inc_min_limit[11]_i_3_n_0\
    );
\one_inc_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(2),
      Q => one_inc_min_limit(2),
      R => \one_inc_min_limit_reg[2]_0\
    );
\one_inc_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(3),
      Q => one_inc_min_limit(3),
      R => \one_inc_min_limit_reg[2]_0\
    );
\one_inc_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(4),
      Q => one_inc_min_limit(4),
      R => \one_inc_min_limit_reg[2]_0\
    );
\one_inc_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(5),
      Q => one_inc_min_limit(5),
      R => \one_inc_min_limit_reg[2]_0\
    );
\one_inc_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \one_inc_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \one_inc_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \one_inc_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \one_inc_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => two_inc_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => one_inc_min_limit_nxt(5 downto 2),
      S(3) => \one_inc_min_limit[5]_i_2_n_0\,
      S(2) => \one_inc_min_limit[5]_i_3_n_0\,
      S(1) => \one_inc_min_limit[5]_i_4_n_0\,
      S(0) => two_inc_max_limit(2)
    );
\one_inc_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(6),
      Q => one_inc_min_limit(6),
      R => \one_inc_min_limit_reg[2]_0\
    );
\one_inc_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(7),
      Q => one_inc_min_limit(7),
      R => \one_inc_min_limit_reg[2]_0\
    );
\one_inc_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(8),
      Q => one_inc_min_limit(8),
      R => \one_inc_min_limit_reg[2]_0\
    );
\one_inc_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(9),
      Q => one_inc_min_limit(9),
      R => \one_inc_min_limit_reg[2]_0\
    );
\one_inc_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_inc_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \one_inc_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \one_inc_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \one_inc_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \one_inc_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => two_inc_max_limit(9 downto 6),
      O(3 downto 0) => one_inc_min_limit_nxt(9 downto 6),
      S(3) => \one_inc_min_limit[9]_i_2_n_0\,
      S(2) => \one_inc_min_limit[9]_i_3_n_0\,
      S(1) => \one_inc_min_limit[9]_i_4_n_0\,
      S(0) => \one_inc_min_limit[9]_i_5_n_0\
    );
pi_f_dec_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \tempmon_state[10]_i_6_n_0\,
      I1 => \tempmon_state[10]_i_5_n_0\,
      I2 => pi_f_dec_i_2_n_0,
      I3 => update_temp_102,
      O => pi_f_dec_nxt
    );
pi_f_dec_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000077707770777"
    )
        port map (
      I0 => tempmon_state(3),
      I1 => temp_cmp_three_inc_max_102,
      I2 => temp_cmp_two_inc_max_102,
      I3 => tempmon_state(4),
      I4 => temp_cmp_one_inc_max_102,
      I5 => tempmon_state(5),
      O => pi_f_dec_i_2_n_0
    );
pi_f_dec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_f_dec_nxt,
      Q => \^pi_f_dec_reg_0\,
      R => \one_inc_min_limit_reg[2]_0\
    );
pi_f_inc_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF7555500000000"
    )
        port map (
      I0 => pi_f_inc_i_2_n_0,
      I1 => pi_f_inc_i_3_n_0,
      I2 => pi_f_inc_i_4_n_0,
      I3 => pi_f_inc_i_5_n_0,
      I4 => update_temp_102,
      I5 => \tempmon_state[10]_i_6_n_0\,
      O => pi_f_inc_nxt
    );
pi_f_inc_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FFF7FFF7FFF7FF"
    )
        port map (
      I0 => temp_cmp_one_inc_min_102,
      I1 => tempmon_state(5),
      I2 => temp_cmp_one_inc_max_102,
      I3 => update_temp_102,
      I4 => temp_cmp_four_dec_min_102,
      I5 => tempmon_state(10),
      O => pi_f_inc_i_2_n_0
    );
pi_f_inc_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7000000F777F777"
    )
        port map (
      I0 => tempmon_state(8),
      I1 => temp_cmp_two_dec_min_102,
      I2 => temp_cmp_two_dec_max_102,
      I3 => update_temp_102,
      I4 => temp_cmp_one_dec_max_102,
      I5 => pi_f_inc_i_6_n_0,
      O => pi_f_inc_i_3_n_0
    );
pi_f_inc_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40FF404040404040"
    )
        port map (
      I0 => temp_cmp_three_inc_max_102,
      I1 => tempmon_state(3),
      I2 => temp_cmp_three_inc_min_102,
      I3 => temp_cmp_two_inc_max_102,
      I4 => tempmon_state(4),
      I5 => temp_cmp_two_inc_min_102,
      O => pi_f_inc_i_4_n_0
    );
pi_f_inc_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808FF88FF08FF88"
    )
        port map (
      I0 => tempmon_state(9),
      I1 => temp_cmp_three_dec_min_102,
      I2 => temp_cmp_three_dec_max_102,
      I3 => pi_f_inc_i_7_n_0,
      I4 => update_temp_102,
      I5 => temp_cmp_neutral_max_102,
      O => pi_f_inc_i_5_n_0
    );
pi_f_inc_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => tempmon_state(7),
      I1 => temp_cmp_one_dec_min_102,
      O => pi_f_inc_i_6_n_0
    );
pi_f_inc_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => tempmon_state(6),
      I1 => temp_cmp_neutral_min_102,
      O => pi_f_inc_i_7_n_0
    );
pi_f_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_f_inc_nxt,
      Q => \^pi_f_inc_reg_0\,
      R => SR(0)
    );
temp_cmp_four_dec_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => four_dec_min_limit(1),
      O => temp_cmp_four_dec_min_102_i_10_n_0
    );
temp_cmp_four_dec_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => four_dec_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_four_dec_min_102_i_11_n_0
    );
temp_cmp_four_dec_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => four_dec_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_four_dec_min_102_i_12_n_0
    );
temp_cmp_four_dec_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => four_dec_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_four_dec_min_102_i_13_n_0
    );
temp_cmp_four_dec_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => four_dec_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_four_dec_min_102_i_14_n_0
    );
temp_cmp_four_dec_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => four_dec_min_limit(11),
      O => temp_cmp_four_dec_min_102_i_3_n_0
    );
temp_cmp_four_dec_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => four_dec_min_limit(9),
      O => temp_cmp_four_dec_min_102_i_4_n_0
    );
temp_cmp_four_dec_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => four_dec_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_four_dec_min_102_i_5_n_0
    );
temp_cmp_four_dec_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => four_dec_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_four_dec_min_102_i_6_n_0
    );
temp_cmp_four_dec_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => four_dec_min_limit(7),
      O => temp_cmp_four_dec_min_102_i_7_n_0
    );
temp_cmp_four_dec_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => four_dec_min_limit(5),
      O => temp_cmp_four_dec_min_102_i_8_n_0
    );
temp_cmp_four_dec_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => four_dec_min_limit(3),
      O => temp_cmp_four_dec_min_102_i_9_n_0
    );
temp_cmp_four_dec_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_four_dec_min_101,
      Q => temp_cmp_four_dec_min_102,
      R => '0'
    );
temp_cmp_four_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_four_dec_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_four_dec_min_101,
      CO(0) => temp_cmp_four_dec_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_four_dec_min_102_i_3_n_0,
      DI(0) => temp_cmp_four_dec_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_four_dec_min_102_i_5_n_0,
      S(0) => temp_cmp_four_dec_min_102_i_6_n_0
    );
temp_cmp_four_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_four_dec_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_four_dec_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_four_dec_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_four_dec_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_four_dec_min_102_i_7_n_0,
      DI(2) => temp_cmp_four_dec_min_102_i_8_n_0,
      DI(1) => temp_cmp_four_dec_min_102_i_9_n_0,
      DI(0) => temp_cmp_four_dec_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_four_dec_min_102_i_11_n_0,
      S(2) => temp_cmp_four_dec_min_102_i_12_n_0,
      S(1) => temp_cmp_four_dec_min_102_i_13_n_0,
      S(0) => temp_cmp_four_dec_min_102_i_14_n_0
    );
temp_cmp_four_inc_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => neutral_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_four_inc_max_102_i_10_n_0
    );
temp_cmp_four_inc_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => four_inc_max_limit(6),
      I2 => device_temp_101(7),
      I3 => four_inc_max_limit(7),
      O => temp_cmp_four_inc_max_102_i_11_n_0
    );
temp_cmp_four_inc_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => four_inc_max_limit(4),
      I2 => device_temp_101(5),
      I3 => four_inc_max_limit(5),
      O => temp_cmp_four_inc_max_102_i_12_n_0
    );
temp_cmp_four_inc_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => four_inc_max_limit(2),
      I2 => device_temp_101(3),
      I3 => four_inc_max_limit(3),
      O => temp_cmp_four_inc_max_102_i_13_n_0
    );
temp_cmp_four_inc_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => neutral_max_limit(1),
      O => temp_cmp_four_inc_max_102_i_14_n_0
    );
temp_cmp_four_inc_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => four_inc_max_limit(10),
      I2 => four_inc_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_four_inc_max_102_i_3_n_0
    );
temp_cmp_four_inc_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => four_inc_max_limit(8),
      I2 => four_inc_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_four_inc_max_102_i_4_n_0
    );
temp_cmp_four_inc_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => four_inc_max_limit(10),
      I2 => device_temp_101(11),
      I3 => four_inc_max_limit(11),
      O => temp_cmp_four_inc_max_102_i_5_n_0
    );
temp_cmp_four_inc_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => four_inc_max_limit(8),
      I2 => device_temp_101(9),
      I3 => four_inc_max_limit(9),
      O => temp_cmp_four_inc_max_102_i_6_n_0
    );
temp_cmp_four_inc_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => four_inc_max_limit(6),
      I2 => four_inc_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_four_inc_max_102_i_7_n_0
    );
temp_cmp_four_inc_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => four_inc_max_limit(4),
      I2 => four_inc_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_four_inc_max_102_i_8_n_0
    );
temp_cmp_four_inc_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => four_inc_max_limit(2),
      I2 => four_inc_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_four_inc_max_102_i_9_n_0
    );
temp_cmp_four_inc_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_four_inc_max_101,
      Q => temp_cmp_four_inc_max_102,
      R => '0'
    );
temp_cmp_four_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_four_inc_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_four_inc_max_101,
      CO(0) => temp_cmp_four_inc_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_four_inc_max_102_i_3_n_0,
      DI(0) => temp_cmp_four_inc_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_four_inc_max_102_i_5_n_0,
      S(0) => temp_cmp_four_inc_max_102_i_6_n_0
    );
temp_cmp_four_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_four_inc_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_four_inc_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_four_inc_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_four_inc_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_four_inc_max_102_i_7_n_0,
      DI(2) => temp_cmp_four_inc_max_102_i_8_n_0,
      DI(1) => temp_cmp_four_inc_max_102_i_9_n_0,
      DI(0) => temp_cmp_four_inc_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_four_inc_max_102_i_11_n_0,
      S(2) => temp_cmp_four_inc_max_102_i_12_n_0,
      S(1) => temp_cmp_four_inc_max_102_i_13_n_0,
      S(0) => temp_cmp_four_inc_max_102_i_14_n_0
    );
temp_cmp_neutral_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => neutral_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_neutral_max_102_i_10_n_0
    );
temp_cmp_neutral_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => neutral_max_limit(6),
      I2 => device_temp_101(7),
      I3 => neutral_max_limit(7),
      O => temp_cmp_neutral_max_102_i_11_n_0
    );
temp_cmp_neutral_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => neutral_max_limit(4),
      I2 => device_temp_101(5),
      I3 => neutral_max_limit(5),
      O => temp_cmp_neutral_max_102_i_12_n_0
    );
temp_cmp_neutral_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => neutral_max_limit(2),
      I2 => device_temp_101(3),
      I3 => neutral_max_limit(3),
      O => temp_cmp_neutral_max_102_i_13_n_0
    );
temp_cmp_neutral_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => neutral_max_limit(1),
      O => temp_cmp_neutral_max_102_i_14_n_0
    );
temp_cmp_neutral_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => neutral_max_limit(10),
      I2 => neutral_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_neutral_max_102_i_3_n_0
    );
temp_cmp_neutral_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => neutral_max_limit(8),
      I2 => neutral_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_neutral_max_102_i_4_n_0
    );
temp_cmp_neutral_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => neutral_max_limit(10),
      I2 => device_temp_101(11),
      I3 => neutral_max_limit(11),
      O => temp_cmp_neutral_max_102_i_5_n_0
    );
temp_cmp_neutral_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => neutral_max_limit(8),
      I2 => device_temp_101(9),
      I3 => neutral_max_limit(9),
      O => temp_cmp_neutral_max_102_i_6_n_0
    );
temp_cmp_neutral_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => neutral_max_limit(6),
      I2 => neutral_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_neutral_max_102_i_7_n_0
    );
temp_cmp_neutral_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => neutral_max_limit(4),
      I2 => neutral_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_neutral_max_102_i_8_n_0
    );
temp_cmp_neutral_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => neutral_max_limit(2),
      I2 => neutral_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_neutral_max_102_i_9_n_0
    );
temp_cmp_neutral_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_neutral_max_101,
      Q => temp_cmp_neutral_max_102,
      R => '0'
    );
temp_cmp_neutral_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_neutral_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_neutral_max_101,
      CO(0) => temp_cmp_neutral_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_neutral_max_102_i_3_n_0,
      DI(0) => temp_cmp_neutral_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_neutral_max_102_i_5_n_0,
      S(0) => temp_cmp_neutral_max_102_i_6_n_0
    );
temp_cmp_neutral_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_neutral_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_neutral_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_neutral_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_neutral_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_neutral_max_102_i_7_n_0,
      DI(2) => temp_cmp_neutral_max_102_i_8_n_0,
      DI(1) => temp_cmp_neutral_max_102_i_9_n_0,
      DI(0) => temp_cmp_neutral_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_neutral_max_102_i_11_n_0,
      S(2) => temp_cmp_neutral_max_102_i_12_n_0,
      S(1) => temp_cmp_neutral_max_102_i_13_n_0,
      S(0) => temp_cmp_neutral_max_102_i_14_n_0
    );
temp_cmp_neutral_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => two_inc_min_limit(1),
      O => temp_cmp_neutral_min_102_i_10_n_0
    );
temp_cmp_neutral_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(6),
      I1 => device_temp_101(6),
      I2 => neutral_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_neutral_min_102_i_11_n_0
    );
temp_cmp_neutral_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(4),
      I1 => device_temp_101(4),
      I2 => neutral_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_neutral_min_102_i_12_n_0
    );
temp_cmp_neutral_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(2),
      I1 => device_temp_101(2),
      I2 => neutral_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_neutral_min_102_i_13_n_0
    );
temp_cmp_neutral_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => two_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_neutral_min_102_i_14_n_0
    );
temp_cmp_neutral_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => neutral_min_limit(11),
      O => temp_cmp_neutral_min_102_i_3_n_0
    );
temp_cmp_neutral_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => neutral_min_limit(9),
      O => temp_cmp_neutral_min_102_i_4_n_0
    );
temp_cmp_neutral_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(10),
      I1 => device_temp_101(10),
      I2 => neutral_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_neutral_min_102_i_5_n_0
    );
temp_cmp_neutral_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(8),
      I1 => device_temp_101(8),
      I2 => neutral_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_neutral_min_102_i_6_n_0
    );
temp_cmp_neutral_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => neutral_min_limit(7),
      O => temp_cmp_neutral_min_102_i_7_n_0
    );
temp_cmp_neutral_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => neutral_min_limit(5),
      O => temp_cmp_neutral_min_102_i_8_n_0
    );
temp_cmp_neutral_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => neutral_min_limit(3),
      O => temp_cmp_neutral_min_102_i_9_n_0
    );
temp_cmp_neutral_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_neutral_min_101,
      Q => temp_cmp_neutral_min_102,
      R => '0'
    );
temp_cmp_neutral_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_neutral_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_neutral_min_101,
      CO(0) => temp_cmp_neutral_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_neutral_min_102_i_3_n_0,
      DI(0) => temp_cmp_neutral_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_neutral_min_102_i_5_n_0,
      S(0) => temp_cmp_neutral_min_102_i_6_n_0
    );
temp_cmp_neutral_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_neutral_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_neutral_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_neutral_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_neutral_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_neutral_min_102_i_7_n_0,
      DI(2) => temp_cmp_neutral_min_102_i_8_n_0,
      DI(1) => temp_cmp_neutral_min_102_i_9_n_0,
      DI(0) => temp_cmp_neutral_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_neutral_min_102_i_11_n_0,
      S(2) => temp_cmp_neutral_min_102_i_12_n_0,
      S(1) => temp_cmp_neutral_min_102_i_13_n_0,
      S(0) => temp_cmp_neutral_min_102_i_14_n_0
    );
temp_cmp_one_dec_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => one_dec_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_one_dec_max_102_i_10_n_0
    );
temp_cmp_one_dec_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => one_dec_max_limit(6),
      I2 => device_temp_101(7),
      I3 => one_dec_max_limit(7),
      O => temp_cmp_one_dec_max_102_i_11_n_0
    );
temp_cmp_one_dec_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => one_dec_max_limit(4),
      I2 => device_temp_101(5),
      I3 => one_dec_max_limit(5),
      O => temp_cmp_one_dec_max_102_i_12_n_0
    );
temp_cmp_one_dec_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => one_dec_max_limit(2),
      I2 => device_temp_101(3),
      I3 => one_dec_max_limit(3),
      O => temp_cmp_one_dec_max_102_i_13_n_0
    );
temp_cmp_one_dec_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => one_dec_max_limit(1),
      O => temp_cmp_one_dec_max_102_i_14_n_0
    );
temp_cmp_one_dec_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => one_dec_max_limit(10),
      I2 => one_dec_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_one_dec_max_102_i_3_n_0
    );
temp_cmp_one_dec_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => one_dec_max_limit(8),
      I2 => one_dec_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_one_dec_max_102_i_4_n_0
    );
temp_cmp_one_dec_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => one_dec_max_limit(10),
      I2 => device_temp_101(11),
      I3 => one_dec_max_limit(11),
      O => temp_cmp_one_dec_max_102_i_5_n_0
    );
temp_cmp_one_dec_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => one_dec_max_limit(8),
      I2 => device_temp_101(9),
      I3 => one_dec_max_limit(9),
      O => temp_cmp_one_dec_max_102_i_6_n_0
    );
temp_cmp_one_dec_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => one_dec_max_limit(6),
      I2 => one_dec_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_one_dec_max_102_i_7_n_0
    );
temp_cmp_one_dec_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => one_dec_max_limit(4),
      I2 => one_dec_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_one_dec_max_102_i_8_n_0
    );
temp_cmp_one_dec_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => one_dec_max_limit(2),
      I2 => one_dec_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_one_dec_max_102_i_9_n_0
    );
temp_cmp_one_dec_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_one_dec_max_101,
      Q => temp_cmp_one_dec_max_102,
      R => '0'
    );
temp_cmp_one_dec_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_one_dec_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_one_dec_max_101,
      CO(0) => temp_cmp_one_dec_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_one_dec_max_102_i_3_n_0,
      DI(0) => temp_cmp_one_dec_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_one_dec_max_102_i_5_n_0,
      S(0) => temp_cmp_one_dec_max_102_i_6_n_0
    );
temp_cmp_one_dec_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_one_dec_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_one_dec_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_one_dec_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_one_dec_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_one_dec_max_102_i_7_n_0,
      DI(2) => temp_cmp_one_dec_max_102_i_8_n_0,
      DI(1) => temp_cmp_one_dec_max_102_i_9_n_0,
      DI(0) => temp_cmp_one_dec_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_one_dec_max_102_i_11_n_0,
      S(2) => temp_cmp_one_dec_max_102_i_12_n_0,
      S(1) => temp_cmp_one_dec_max_102_i_13_n_0,
      S(0) => temp_cmp_one_dec_max_102_i_14_n_0
    );
temp_cmp_one_dec_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => three_inc_min_limit(1),
      O => temp_cmp_one_dec_min_102_i_10_n_0
    );
temp_cmp_one_dec_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => one_dec_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_one_dec_min_102_i_11_n_0
    );
temp_cmp_one_dec_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => one_dec_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_one_dec_min_102_i_12_n_0
    );
temp_cmp_one_dec_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => one_dec_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_one_dec_min_102_i_13_n_0
    );
temp_cmp_one_dec_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => three_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_one_dec_min_102_i_14_n_0
    );
temp_cmp_one_dec_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => one_dec_min_limit(11),
      O => temp_cmp_one_dec_min_102_i_3_n_0
    );
temp_cmp_one_dec_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => one_dec_min_limit(9),
      O => temp_cmp_one_dec_min_102_i_4_n_0
    );
temp_cmp_one_dec_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => one_dec_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_one_dec_min_102_i_5_n_0
    );
temp_cmp_one_dec_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => one_dec_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_one_dec_min_102_i_6_n_0
    );
temp_cmp_one_dec_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => one_dec_min_limit(7),
      O => temp_cmp_one_dec_min_102_i_7_n_0
    );
temp_cmp_one_dec_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => one_dec_min_limit(5),
      O => temp_cmp_one_dec_min_102_i_8_n_0
    );
temp_cmp_one_dec_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => one_dec_min_limit(3),
      O => temp_cmp_one_dec_min_102_i_9_n_0
    );
temp_cmp_one_dec_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_one_dec_min_101,
      Q => temp_cmp_one_dec_min_102,
      R => '0'
    );
temp_cmp_one_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_one_dec_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_one_dec_min_101,
      CO(0) => temp_cmp_one_dec_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_one_dec_min_102_i_3_n_0,
      DI(0) => temp_cmp_one_dec_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_one_dec_min_102_i_5_n_0,
      S(0) => temp_cmp_one_dec_min_102_i_6_n_0
    );
temp_cmp_one_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_one_dec_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_one_dec_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_one_dec_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_one_dec_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_one_dec_min_102_i_7_n_0,
      DI(2) => temp_cmp_one_dec_min_102_i_8_n_0,
      DI(1) => temp_cmp_one_dec_min_102_i_9_n_0,
      DI(0) => temp_cmp_one_dec_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_one_dec_min_102_i_11_n_0,
      S(2) => temp_cmp_one_dec_min_102_i_12_n_0,
      S(1) => temp_cmp_one_dec_min_102_i_13_n_0,
      S(0) => temp_cmp_one_dec_min_102_i_14_n_0
    );
temp_cmp_one_inc_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => one_dec_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_one_inc_max_102_i_10_n_0
    );
temp_cmp_one_inc_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => one_inc_max_limit(6),
      I2 => device_temp_101(7),
      I3 => one_inc_max_limit(7),
      O => temp_cmp_one_inc_max_102_i_11_n_0
    );
temp_cmp_one_inc_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => one_inc_max_limit(4),
      I2 => device_temp_101(5),
      I3 => one_inc_max_limit(5),
      O => temp_cmp_one_inc_max_102_i_12_n_0
    );
temp_cmp_one_inc_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => one_inc_max_limit(2),
      I2 => device_temp_101(3),
      I3 => one_inc_max_limit(3),
      O => temp_cmp_one_inc_max_102_i_13_n_0
    );
temp_cmp_one_inc_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => one_dec_max_limit(1),
      O => temp_cmp_one_inc_max_102_i_14_n_0
    );
temp_cmp_one_inc_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => one_inc_max_limit(10),
      I2 => one_inc_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_one_inc_max_102_i_3_n_0
    );
temp_cmp_one_inc_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => one_inc_max_limit(8),
      I2 => one_inc_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_one_inc_max_102_i_4_n_0
    );
temp_cmp_one_inc_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => one_inc_max_limit(10),
      I2 => device_temp_101(11),
      I3 => one_inc_max_limit(11),
      O => temp_cmp_one_inc_max_102_i_5_n_0
    );
temp_cmp_one_inc_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => one_inc_max_limit(8),
      I2 => device_temp_101(9),
      I3 => one_inc_max_limit(9),
      O => temp_cmp_one_inc_max_102_i_6_n_0
    );
temp_cmp_one_inc_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => one_inc_max_limit(6),
      I2 => one_inc_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_one_inc_max_102_i_7_n_0
    );
temp_cmp_one_inc_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => one_inc_max_limit(4),
      I2 => one_inc_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_one_inc_max_102_i_8_n_0
    );
temp_cmp_one_inc_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => one_inc_max_limit(2),
      I2 => one_inc_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_one_inc_max_102_i_9_n_0
    );
temp_cmp_one_inc_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_one_inc_max_101,
      Q => temp_cmp_one_inc_max_102,
      R => '0'
    );
temp_cmp_one_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_one_inc_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_one_inc_max_101,
      CO(0) => temp_cmp_one_inc_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_one_inc_max_102_i_3_n_0,
      DI(0) => temp_cmp_one_inc_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_one_inc_max_102_i_5_n_0,
      S(0) => temp_cmp_one_inc_max_102_i_6_n_0
    );
temp_cmp_one_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_one_inc_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_one_inc_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_one_inc_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_one_inc_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_one_inc_max_102_i_7_n_0,
      DI(2) => temp_cmp_one_inc_max_102_i_8_n_0,
      DI(1) => temp_cmp_one_inc_max_102_i_9_n_0,
      DI(0) => temp_cmp_one_inc_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_one_inc_max_102_i_11_n_0,
      S(2) => temp_cmp_one_inc_max_102_i_12_n_0,
      S(1) => temp_cmp_one_inc_max_102_i_13_n_0,
      S(0) => temp_cmp_one_inc_max_102_i_14_n_0
    );
temp_cmp_one_inc_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => three_inc_min_limit(1),
      O => temp_cmp_one_inc_min_102_i_10_n_0
    );
temp_cmp_one_inc_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => one_inc_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_one_inc_min_102_i_11_n_0
    );
temp_cmp_one_inc_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => one_inc_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_one_inc_min_102_i_12_n_0
    );
temp_cmp_one_inc_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => one_inc_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_one_inc_min_102_i_13_n_0
    );
temp_cmp_one_inc_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => three_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_one_inc_min_102_i_14_n_0
    );
temp_cmp_one_inc_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => one_inc_min_limit(11),
      O => temp_cmp_one_inc_min_102_i_3_n_0
    );
temp_cmp_one_inc_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => one_inc_min_limit(9),
      O => temp_cmp_one_inc_min_102_i_4_n_0
    );
temp_cmp_one_inc_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => one_inc_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_one_inc_min_102_i_5_n_0
    );
temp_cmp_one_inc_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => one_inc_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_one_inc_min_102_i_6_n_0
    );
temp_cmp_one_inc_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => one_inc_min_limit(7),
      O => temp_cmp_one_inc_min_102_i_7_n_0
    );
temp_cmp_one_inc_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => one_inc_min_limit(5),
      O => temp_cmp_one_inc_min_102_i_8_n_0
    );
temp_cmp_one_inc_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => one_inc_min_limit(3),
      O => temp_cmp_one_inc_min_102_i_9_n_0
    );
temp_cmp_one_inc_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_one_inc_min_101,
      Q => temp_cmp_one_inc_min_102,
      R => '0'
    );
temp_cmp_one_inc_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_one_inc_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_one_inc_min_101,
      CO(0) => temp_cmp_one_inc_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_one_inc_min_102_i_3_n_0,
      DI(0) => temp_cmp_one_inc_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_one_inc_min_102_i_5_n_0,
      S(0) => temp_cmp_one_inc_min_102_i_6_n_0
    );
temp_cmp_one_inc_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_one_inc_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_one_inc_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_one_inc_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_one_inc_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_one_inc_min_102_i_7_n_0,
      DI(2) => temp_cmp_one_inc_min_102_i_8_n_0,
      DI(1) => temp_cmp_one_inc_min_102_i_9_n_0,
      DI(0) => temp_cmp_one_inc_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_one_inc_min_102_i_11_n_0,
      S(2) => temp_cmp_one_inc_min_102_i_12_n_0,
      S(1) => temp_cmp_one_inc_min_102_i_13_n_0,
      S(0) => temp_cmp_one_inc_min_102_i_14_n_0
    );
temp_cmp_three_dec_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => three_dec_max_limit(0),
      I2 => three_dec_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_three_dec_max_102_i_10_n_0
    );
temp_cmp_three_dec_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => three_dec_max_limit(6),
      I2 => device_temp_101(7),
      I3 => three_dec_max_limit(7),
      O => temp_cmp_three_dec_max_102_i_11_n_0
    );
temp_cmp_three_dec_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => three_dec_max_limit(4),
      I2 => device_temp_101(5),
      I3 => three_dec_max_limit(5),
      O => temp_cmp_three_dec_max_102_i_12_n_0
    );
temp_cmp_three_dec_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => three_dec_max_limit(2),
      I2 => device_temp_101(3),
      I3 => three_dec_max_limit(3),
      O => temp_cmp_three_dec_max_102_i_13_n_0
    );
temp_cmp_three_dec_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => three_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => three_dec_max_limit(1),
      O => temp_cmp_three_dec_max_102_i_14_n_0
    );
temp_cmp_three_dec_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => three_dec_max_limit(10),
      I2 => three_dec_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_three_dec_max_102_i_3_n_0
    );
temp_cmp_three_dec_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => three_dec_max_limit(8),
      I2 => three_dec_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_three_dec_max_102_i_4_n_0
    );
temp_cmp_three_dec_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => three_dec_max_limit(10),
      I2 => device_temp_101(11),
      I3 => three_dec_max_limit(11),
      O => temp_cmp_three_dec_max_102_i_5_n_0
    );
temp_cmp_three_dec_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => three_dec_max_limit(8),
      I2 => device_temp_101(9),
      I3 => three_dec_max_limit(9),
      O => temp_cmp_three_dec_max_102_i_6_n_0
    );
temp_cmp_three_dec_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => three_dec_max_limit(6),
      I2 => three_dec_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_three_dec_max_102_i_7_n_0
    );
temp_cmp_three_dec_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => three_dec_max_limit(4),
      I2 => three_dec_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_three_dec_max_102_i_8_n_0
    );
temp_cmp_three_dec_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => three_dec_max_limit(2),
      I2 => three_dec_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_three_dec_max_102_i_9_n_0
    );
temp_cmp_three_dec_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_three_dec_max_101,
      Q => temp_cmp_three_dec_max_102,
      R => '0'
    );
temp_cmp_three_dec_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_three_dec_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_three_dec_max_101,
      CO(0) => temp_cmp_three_dec_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_three_dec_max_102_i_3_n_0,
      DI(0) => temp_cmp_three_dec_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_three_dec_max_102_i_5_n_0,
      S(0) => temp_cmp_three_dec_max_102_i_6_n_0
    );
temp_cmp_three_dec_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_three_dec_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_three_dec_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_three_dec_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_three_dec_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_three_dec_max_102_i_7_n_0,
      DI(2) => temp_cmp_three_dec_max_102_i_8_n_0,
      DI(1) => temp_cmp_three_dec_max_102_i_9_n_0,
      DI(0) => temp_cmp_three_dec_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_three_dec_max_102_i_11_n_0,
      S(2) => temp_cmp_three_dec_max_102_i_12_n_0,
      S(1) => temp_cmp_three_dec_max_102_i_13_n_0,
      S(0) => temp_cmp_three_dec_max_102_i_14_n_0
    );
temp_cmp_three_dec_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => three_dec_min_limit(1),
      O => temp_cmp_three_dec_min_102_i_10_n_0
    );
temp_cmp_three_dec_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => three_dec_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_three_dec_min_102_i_11_n_0
    );
temp_cmp_three_dec_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => three_dec_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_three_dec_min_102_i_12_n_0
    );
temp_cmp_three_dec_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => three_dec_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_three_dec_min_102_i_13_n_0
    );
temp_cmp_three_dec_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => three_dec_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_three_dec_min_102_i_14_n_0
    );
temp_cmp_three_dec_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => three_dec_min_limit(11),
      O => temp_cmp_three_dec_min_102_i_3_n_0
    );
temp_cmp_three_dec_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => three_dec_min_limit(9),
      O => temp_cmp_three_dec_min_102_i_4_n_0
    );
temp_cmp_three_dec_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => three_dec_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_three_dec_min_102_i_5_n_0
    );
temp_cmp_three_dec_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => three_dec_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_three_dec_min_102_i_6_n_0
    );
temp_cmp_three_dec_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => three_dec_min_limit(7),
      O => temp_cmp_three_dec_min_102_i_7_n_0
    );
temp_cmp_three_dec_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => three_dec_min_limit(5),
      O => temp_cmp_three_dec_min_102_i_8_n_0
    );
temp_cmp_three_dec_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => three_dec_min_limit(3),
      O => temp_cmp_three_dec_min_102_i_9_n_0
    );
temp_cmp_three_dec_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_three_dec_min_101,
      Q => temp_cmp_three_dec_min_102,
      R => '0'
    );
temp_cmp_three_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_three_dec_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_three_dec_min_101,
      CO(0) => temp_cmp_three_dec_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_three_dec_min_102_i_3_n_0,
      DI(0) => temp_cmp_three_dec_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_three_dec_min_102_i_5_n_0,
      S(0) => temp_cmp_three_dec_min_102_i_6_n_0
    );
temp_cmp_three_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_three_dec_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_three_dec_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_three_dec_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_three_dec_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_three_dec_min_102_i_7_n_0,
      DI(2) => temp_cmp_three_dec_min_102_i_8_n_0,
      DI(1) => temp_cmp_three_dec_min_102_i_9_n_0,
      DI(0) => temp_cmp_three_dec_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_three_dec_min_102_i_11_n_0,
      S(2) => temp_cmp_three_dec_min_102_i_12_n_0,
      S(1) => temp_cmp_three_dec_min_102_i_13_n_0,
      S(0) => temp_cmp_three_dec_min_102_i_14_n_0
    );
temp_cmp_three_inc_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => one_dec_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_three_inc_max_102_i_10_n_0
    );
temp_cmp_three_inc_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => three_inc_max_limit(6),
      I2 => device_temp_101(7),
      I3 => three_inc_max_limit(7),
      O => temp_cmp_three_inc_max_102_i_11_n_0
    );
temp_cmp_three_inc_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => three_inc_max_limit(4),
      I2 => device_temp_101(5),
      I3 => three_inc_max_limit(5),
      O => temp_cmp_three_inc_max_102_i_12_n_0
    );
temp_cmp_three_inc_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => three_inc_max_limit(2),
      I2 => device_temp_101(3),
      I3 => three_inc_max_limit(3),
      O => temp_cmp_three_inc_max_102_i_13_n_0
    );
temp_cmp_three_inc_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => one_dec_max_limit(1),
      O => temp_cmp_three_inc_max_102_i_14_n_0
    );
temp_cmp_three_inc_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => three_inc_max_limit(10),
      I2 => three_inc_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_three_inc_max_102_i_3_n_0
    );
temp_cmp_three_inc_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => three_inc_max_limit(8),
      I2 => three_inc_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_three_inc_max_102_i_4_n_0
    );
temp_cmp_three_inc_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => three_inc_max_limit(10),
      I2 => device_temp_101(11),
      I3 => three_inc_max_limit(11),
      O => temp_cmp_three_inc_max_102_i_5_n_0
    );
temp_cmp_three_inc_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => three_inc_max_limit(8),
      I2 => device_temp_101(9),
      I3 => three_inc_max_limit(9),
      O => temp_cmp_three_inc_max_102_i_6_n_0
    );
temp_cmp_three_inc_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => three_inc_max_limit(6),
      I2 => three_inc_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_three_inc_max_102_i_7_n_0
    );
temp_cmp_three_inc_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => three_inc_max_limit(4),
      I2 => three_inc_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_three_inc_max_102_i_8_n_0
    );
temp_cmp_three_inc_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => three_inc_max_limit(2),
      I2 => three_inc_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_three_inc_max_102_i_9_n_0
    );
temp_cmp_three_inc_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_three_inc_max_101,
      Q => temp_cmp_three_inc_max_102,
      R => '0'
    );
temp_cmp_three_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_three_inc_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_three_inc_max_101,
      CO(0) => temp_cmp_three_inc_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_three_inc_max_102_i_3_n_0,
      DI(0) => temp_cmp_three_inc_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_three_inc_max_102_i_5_n_0,
      S(0) => temp_cmp_three_inc_max_102_i_6_n_0
    );
temp_cmp_three_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_three_inc_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_three_inc_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_three_inc_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_three_inc_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_three_inc_max_102_i_7_n_0,
      DI(2) => temp_cmp_three_inc_max_102_i_8_n_0,
      DI(1) => temp_cmp_three_inc_max_102_i_9_n_0,
      DI(0) => temp_cmp_three_inc_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_three_inc_max_102_i_11_n_0,
      S(2) => temp_cmp_three_inc_max_102_i_12_n_0,
      S(1) => temp_cmp_three_inc_max_102_i_13_n_0,
      S(0) => temp_cmp_three_inc_max_102_i_14_n_0
    );
temp_cmp_three_inc_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => three_inc_min_limit(1),
      O => temp_cmp_three_inc_min_102_i_10_n_0
    );
temp_cmp_three_inc_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => three_inc_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_three_inc_min_102_i_11_n_0
    );
temp_cmp_three_inc_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => three_inc_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_three_inc_min_102_i_12_n_0
    );
temp_cmp_three_inc_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => three_inc_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_three_inc_min_102_i_13_n_0
    );
temp_cmp_three_inc_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => three_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_three_inc_min_102_i_14_n_0
    );
temp_cmp_three_inc_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => three_inc_min_limit(11),
      O => temp_cmp_three_inc_min_102_i_3_n_0
    );
temp_cmp_three_inc_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => three_inc_min_limit(9),
      O => temp_cmp_three_inc_min_102_i_4_n_0
    );
temp_cmp_three_inc_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => three_inc_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_three_inc_min_102_i_5_n_0
    );
temp_cmp_three_inc_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => three_inc_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_three_inc_min_102_i_6_n_0
    );
temp_cmp_three_inc_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => three_inc_min_limit(7),
      O => temp_cmp_three_inc_min_102_i_7_n_0
    );
temp_cmp_three_inc_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => three_inc_min_limit(5),
      O => temp_cmp_three_inc_min_102_i_8_n_0
    );
temp_cmp_three_inc_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => three_inc_min_limit(3),
      O => temp_cmp_three_inc_min_102_i_9_n_0
    );
temp_cmp_three_inc_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_three_inc_min_101,
      Q => temp_cmp_three_inc_min_102,
      R => '0'
    );
temp_cmp_three_inc_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_three_inc_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_three_inc_min_101,
      CO(0) => temp_cmp_three_inc_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_three_inc_min_102_i_3_n_0,
      DI(0) => temp_cmp_three_inc_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_three_inc_min_102_i_5_n_0,
      S(0) => temp_cmp_three_inc_min_102_i_6_n_0
    );
temp_cmp_three_inc_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_three_inc_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_three_inc_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_three_inc_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_three_inc_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_three_inc_min_102_i_7_n_0,
      DI(2) => temp_cmp_three_inc_min_102_i_8_n_0,
      DI(1) => temp_cmp_three_inc_min_102_i_9_n_0,
      DI(0) => temp_cmp_three_inc_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_three_inc_min_102_i_11_n_0,
      S(2) => temp_cmp_three_inc_min_102_i_12_n_0,
      S(1) => temp_cmp_three_inc_min_102_i_13_n_0,
      S(0) => temp_cmp_three_inc_min_102_i_14_n_0
    );
temp_cmp_two_dec_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => two_dec_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_two_dec_max_102_i_10_n_0
    );
temp_cmp_two_dec_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => two_dec_max_limit(6),
      I2 => device_temp_101(7),
      I3 => two_dec_max_limit(7),
      O => temp_cmp_two_dec_max_102_i_11_n_0
    );
temp_cmp_two_dec_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => two_dec_max_limit(4),
      I2 => device_temp_101(5),
      I3 => two_dec_max_limit(5),
      O => temp_cmp_two_dec_max_102_i_12_n_0
    );
temp_cmp_two_dec_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => two_dec_max_limit(2),
      I2 => device_temp_101(3),
      I3 => two_dec_max_limit(3),
      O => temp_cmp_two_dec_max_102_i_13_n_0
    );
temp_cmp_two_dec_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => two_dec_max_limit(1),
      O => temp_cmp_two_dec_max_102_i_14_n_0
    );
temp_cmp_two_dec_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => two_dec_max_limit(10),
      I2 => two_dec_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_two_dec_max_102_i_3_n_0
    );
temp_cmp_two_dec_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => two_dec_max_limit(8),
      I2 => two_dec_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_two_dec_max_102_i_4_n_0
    );
temp_cmp_two_dec_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => two_dec_max_limit(10),
      I2 => device_temp_101(11),
      I3 => two_dec_max_limit(11),
      O => temp_cmp_two_dec_max_102_i_5_n_0
    );
temp_cmp_two_dec_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => two_dec_max_limit(8),
      I2 => device_temp_101(9),
      I3 => two_dec_max_limit(9),
      O => temp_cmp_two_dec_max_102_i_6_n_0
    );
temp_cmp_two_dec_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => two_dec_max_limit(6),
      I2 => two_dec_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_two_dec_max_102_i_7_n_0
    );
temp_cmp_two_dec_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => two_dec_max_limit(4),
      I2 => two_dec_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_two_dec_max_102_i_8_n_0
    );
temp_cmp_two_dec_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => two_dec_max_limit(2),
      I2 => two_dec_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_two_dec_max_102_i_9_n_0
    );
temp_cmp_two_dec_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_two_dec_max_101,
      Q => temp_cmp_two_dec_max_102,
      R => '0'
    );
temp_cmp_two_dec_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_two_dec_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_two_dec_max_101,
      CO(0) => temp_cmp_two_dec_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_two_dec_max_102_i_3_n_0,
      DI(0) => temp_cmp_two_dec_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_two_dec_max_102_i_5_n_0,
      S(0) => temp_cmp_two_dec_max_102_i_6_n_0
    );
temp_cmp_two_dec_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_two_dec_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_two_dec_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_two_dec_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_two_dec_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_two_dec_max_102_i_7_n_0,
      DI(2) => temp_cmp_two_dec_max_102_i_8_n_0,
      DI(1) => temp_cmp_two_dec_max_102_i_9_n_0,
      DI(0) => temp_cmp_two_dec_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_two_dec_max_102_i_11_n_0,
      S(2) => temp_cmp_two_dec_max_102_i_12_n_0,
      S(1) => temp_cmp_two_dec_max_102_i_13_n_0,
      S(0) => temp_cmp_two_dec_max_102_i_14_n_0
    );
temp_cmp_two_dec_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => two_inc_min_limit(1),
      O => temp_cmp_two_dec_min_102_i_10_n_0
    );
temp_cmp_two_dec_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => two_dec_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_two_dec_min_102_i_11_n_0
    );
temp_cmp_two_dec_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => two_dec_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_two_dec_min_102_i_12_n_0
    );
temp_cmp_two_dec_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => two_dec_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_two_dec_min_102_i_13_n_0
    );
temp_cmp_two_dec_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => two_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_two_dec_min_102_i_14_n_0
    );
temp_cmp_two_dec_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => two_dec_min_limit(11),
      O => temp_cmp_two_dec_min_102_i_3_n_0
    );
temp_cmp_two_dec_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => two_dec_min_limit(9),
      O => temp_cmp_two_dec_min_102_i_4_n_0
    );
temp_cmp_two_dec_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => two_dec_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_two_dec_min_102_i_5_n_0
    );
temp_cmp_two_dec_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => two_dec_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_two_dec_min_102_i_6_n_0
    );
temp_cmp_two_dec_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => two_dec_min_limit(7),
      O => temp_cmp_two_dec_min_102_i_7_n_0
    );
temp_cmp_two_dec_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => two_dec_min_limit(5),
      O => temp_cmp_two_dec_min_102_i_8_n_0
    );
temp_cmp_two_dec_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => two_dec_min_limit(3),
      O => temp_cmp_two_dec_min_102_i_9_n_0
    );
temp_cmp_two_dec_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_two_dec_min_101,
      Q => temp_cmp_two_dec_min_102,
      R => '0'
    );
temp_cmp_two_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_two_dec_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_two_dec_min_101,
      CO(0) => temp_cmp_two_dec_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_two_dec_min_102_i_3_n_0,
      DI(0) => temp_cmp_two_dec_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_two_dec_min_102_i_5_n_0,
      S(0) => temp_cmp_two_dec_min_102_i_6_n_0
    );
temp_cmp_two_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_two_dec_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_two_dec_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_two_dec_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_two_dec_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_two_dec_min_102_i_7_n_0,
      DI(2) => temp_cmp_two_dec_min_102_i_8_n_0,
      DI(1) => temp_cmp_two_dec_min_102_i_9_n_0,
      DI(0) => temp_cmp_two_dec_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_two_dec_min_102_i_11_n_0,
      S(2) => temp_cmp_two_dec_min_102_i_12_n_0,
      S(1) => temp_cmp_two_dec_min_102_i_13_n_0,
      S(0) => temp_cmp_two_dec_min_102_i_14_n_0
    );
temp_cmp_two_inc_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => neutral_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_two_inc_max_102_i_10_n_0
    );
temp_cmp_two_inc_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => two_inc_max_limit(6),
      I2 => device_temp_101(7),
      I3 => two_inc_max_limit(7),
      O => temp_cmp_two_inc_max_102_i_11_n_0
    );
temp_cmp_two_inc_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => two_inc_max_limit(4),
      I2 => device_temp_101(5),
      I3 => two_inc_max_limit(5),
      O => temp_cmp_two_inc_max_102_i_12_n_0
    );
temp_cmp_two_inc_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => two_inc_max_limit(2),
      I2 => device_temp_101(3),
      I3 => two_inc_max_limit(3),
      O => temp_cmp_two_inc_max_102_i_13_n_0
    );
temp_cmp_two_inc_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => neutral_max_limit(1),
      O => temp_cmp_two_inc_max_102_i_14_n_0
    );
temp_cmp_two_inc_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => two_inc_max_limit(10),
      I2 => two_inc_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_two_inc_max_102_i_3_n_0
    );
temp_cmp_two_inc_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => two_inc_max_limit(8),
      I2 => two_inc_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_two_inc_max_102_i_4_n_0
    );
temp_cmp_two_inc_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => two_inc_max_limit(10),
      I2 => device_temp_101(11),
      I3 => two_inc_max_limit(11),
      O => temp_cmp_two_inc_max_102_i_5_n_0
    );
temp_cmp_two_inc_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => two_inc_max_limit(8),
      I2 => device_temp_101(9),
      I3 => two_inc_max_limit(9),
      O => temp_cmp_two_inc_max_102_i_6_n_0
    );
temp_cmp_two_inc_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => two_inc_max_limit(6),
      I2 => two_inc_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_two_inc_max_102_i_7_n_0
    );
temp_cmp_two_inc_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => two_inc_max_limit(4),
      I2 => two_inc_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_two_inc_max_102_i_8_n_0
    );
temp_cmp_two_inc_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => two_inc_max_limit(2),
      I2 => two_inc_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_two_inc_max_102_i_9_n_0
    );
temp_cmp_two_inc_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_two_inc_max_101,
      Q => temp_cmp_two_inc_max_102,
      R => '0'
    );
temp_cmp_two_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_two_inc_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_two_inc_max_101,
      CO(0) => temp_cmp_two_inc_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_two_inc_max_102_i_3_n_0,
      DI(0) => temp_cmp_two_inc_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_two_inc_max_102_i_5_n_0,
      S(0) => temp_cmp_two_inc_max_102_i_6_n_0
    );
temp_cmp_two_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_two_inc_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_two_inc_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_two_inc_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_two_inc_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_two_inc_max_102_i_7_n_0,
      DI(2) => temp_cmp_two_inc_max_102_i_8_n_0,
      DI(1) => temp_cmp_two_inc_max_102_i_9_n_0,
      DI(0) => temp_cmp_two_inc_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_two_inc_max_102_i_11_n_0,
      S(2) => temp_cmp_two_inc_max_102_i_12_n_0,
      S(1) => temp_cmp_two_inc_max_102_i_13_n_0,
      S(0) => temp_cmp_two_inc_max_102_i_14_n_0
    );
temp_cmp_two_inc_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => two_inc_min_limit(1),
      O => temp_cmp_two_inc_min_102_i_10_n_0
    );
temp_cmp_two_inc_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => two_inc_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_two_inc_min_102_i_11_n_0
    );
temp_cmp_two_inc_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => two_inc_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_two_inc_min_102_i_12_n_0
    );
temp_cmp_two_inc_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => two_inc_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_two_inc_min_102_i_13_n_0
    );
temp_cmp_two_inc_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => two_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_two_inc_min_102_i_14_n_0
    );
temp_cmp_two_inc_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => two_inc_min_limit(11),
      O => temp_cmp_two_inc_min_102_i_3_n_0
    );
temp_cmp_two_inc_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => two_inc_min_limit(9),
      O => temp_cmp_two_inc_min_102_i_4_n_0
    );
temp_cmp_two_inc_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => two_inc_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_two_inc_min_102_i_5_n_0
    );
temp_cmp_two_inc_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => two_inc_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_two_inc_min_102_i_6_n_0
    );
temp_cmp_two_inc_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => two_inc_min_limit(7),
      O => temp_cmp_two_inc_min_102_i_7_n_0
    );
temp_cmp_two_inc_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => two_inc_min_limit(5),
      O => temp_cmp_two_inc_min_102_i_8_n_0
    );
temp_cmp_two_inc_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => two_inc_min_limit(3),
      O => temp_cmp_two_inc_min_102_i_9_n_0
    );
temp_cmp_two_inc_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_two_inc_min_101,
      Q => temp_cmp_two_inc_min_102,
      R => '0'
    );
temp_cmp_two_inc_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_two_inc_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_two_inc_min_101,
      CO(0) => temp_cmp_two_inc_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_two_inc_min_102_i_3_n_0,
      DI(0) => temp_cmp_two_inc_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_two_inc_min_102_i_5_n_0,
      S(0) => temp_cmp_two_inc_min_102_i_6_n_0
    );
temp_cmp_two_inc_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_two_inc_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_two_inc_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_two_inc_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_two_inc_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_two_inc_min_102_i_7_n_0,
      DI(2) => temp_cmp_two_inc_min_102_i_8_n_0,
      DI(1) => temp_cmp_two_inc_min_102_i_9_n_0,
      DI(0) => temp_cmp_two_inc_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_two_inc_min_102_i_11_n_0,
      S(2) => temp_cmp_two_inc_min_102_i_12_n_0,
      S(1) => temp_cmp_two_inc_min_102_i_13_n_0,
      S(0) => temp_cmp_two_inc_min_102_i_14_n_0
    );
tempmon_init_complete_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => tempmon_state_init,
      Q => tempmon_init_complete,
      R => \one_inc_min_limit_reg[2]_0\
    );
tempmon_sample_en_101_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tempmon_sample_en,
      Q => tempmon_sample_en_101,
      R => \one_inc_min_limit_reg[2]_0\
    );
tempmon_sample_en_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tempmon_sample_en_101,
      Q => tempmon_sample_en_102,
      R => \one_inc_min_limit_reg[2]_0\
    );
\tempmon_state[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tempmon_state[10]_i_6_n_0\,
      O => tempmon_state_nxt(0)
    );
\tempmon_state[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFC444"
    )
        port map (
      I0 => \tempmon_state[10]_i_3_n_0\,
      I1 => update_temp_102,
      I2 => temp_cmp_four_dec_min_102,
      I3 => tempmon_state(10),
      I4 => \tempmon_state[10]_i_4_n_0\,
      I5 => \tempmon_state[10]_i_5_n_0\,
      O => \tempmon_state[10]_i_1_n_0\
    );
\tempmon_state[10]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => tempmon_state(0),
      I1 => tempmon_state(1),
      I2 => tempmon_state(2),
      I3 => tempmon_state(3),
      I4 => tempmon_state(4),
      O => \tempmon_state[10]_i_10_n_0\
    );
\tempmon_state[10]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFEE8"
    )
        port map (
      I0 => tempmon_state(0),
      I1 => tempmon_state(1),
      I2 => tempmon_state(2),
      I3 => tempmon_state(3),
      I4 => tempmon_state(4),
      O => \tempmon_state[10]_i_11_n_0\
    );
\tempmon_state[10]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010116"
    )
        port map (
      I0 => tempmon_state(5),
      I1 => tempmon_state(6),
      I2 => tempmon_state(7),
      I3 => tempmon_state(8),
      I4 => tempmon_state(9),
      I5 => tempmon_state(10),
      O => \tempmon_state[10]_i_12_n_0\
    );
\tempmon_state[10]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFEFEE8"
    )
        port map (
      I0 => tempmon_state(5),
      I1 => tempmon_state(6),
      I2 => tempmon_state(7),
      I3 => tempmon_state(8),
      I4 => tempmon_state(9),
      I5 => tempmon_state(10),
      O => \tempmon_state[10]_i_13_n_0\
    );
\tempmon_state[10]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => temp_cmp_two_dec_min_102,
      I1 => tempmon_state(8),
      I2 => temp_cmp_three_inc_min_102,
      I3 => tempmon_state(3),
      O => \tempmon_state[10]_i_14_n_0\
    );
\tempmon_state[10]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => temp_cmp_two_dec_max_102,
      I1 => update_temp_102,
      I2 => tempmon_state(8),
      O => \tempmon_state[10]_i_15_n_0\
    );
\tempmon_state[10]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => update_temp_102,
      I1 => temp_cmp_three_dec_max_102,
      I2 => tempmon_state(9),
      I3 => \tempmon_state[10]_i_6_n_0\,
      O => tempmon_state_nxt(10)
    );
\tempmon_state[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000022202220222"
    )
        port map (
      I0 => pi_f_dec_i_2_n_0,
      I1 => \tempmon_state[10]_i_7_n_0\,
      I2 => temp_cmp_one_dec_min_102,
      I3 => tempmon_state(7),
      I4 => temp_cmp_three_dec_min_102,
      I5 => tempmon_state(9),
      O => \tempmon_state[10]_i_3_n_0\
    );
\tempmon_state[10]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFEFEF"
    )
        port map (
      I0 => \tempmon_state[10]_i_8_n_0\,
      I1 => tempmon_state(1),
      I2 => \tempmon_state[10]_i_6_n_0\,
      I3 => tempmon_state(0),
      I4 => \calib_zero_inputs_reg[0]\,
      O => \tempmon_state[10]_i_4_n_0\
    );
\tempmon_state[10]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAEAAAEAAAEAAA"
    )
        port map (
      I0 => \tempmon_state[10]_i_9_n_0\,
      I1 => tempmon_state(6),
      I2 => temp_cmp_neutral_max_102,
      I3 => update_temp_102,
      I4 => tempmon_state(7),
      I5 => temp_cmp_one_dec_max_102,
      O => \tempmon_state[10]_i_5_n_0\
    );
\tempmon_state[10]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0012"
    )
        port map (
      I0 => \tempmon_state[10]_i_10_n_0\,
      I1 => \tempmon_state[10]_i_11_n_0\,
      I2 => \tempmon_state[10]_i_12_n_0\,
      I3 => \tempmon_state[10]_i_13_n_0\,
      O => \tempmon_state[10]_i_6_n_0\
    );
\tempmon_state[10]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => tempmon_state(4),
      I1 => temp_cmp_two_inc_min_102,
      I2 => tempmon_state(6),
      I3 => temp_cmp_neutral_min_102,
      I4 => \tempmon_state[10]_i_14_n_0\,
      O => \tempmon_state[10]_i_7_n_0\
    );
\tempmon_state[10]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => temp_cmp_one_inc_min_102,
      I1 => tempmon_state(5),
      I2 => update_temp_102,
      O => \tempmon_state[10]_i_8_n_0\
    );
\tempmon_state[10]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF8F0F0F8F8F0F0"
    )
        port map (
      I0 => tempmon_state(2),
      I1 => temp_cmp_four_inc_max_102,
      I2 => \tempmon_state[10]_i_15_n_0\,
      I3 => tempmon_state(9),
      I4 => update_temp_102,
      I5 => temp_cmp_three_dec_max_102,
      O => \tempmon_state[10]_i_9_n_0\
    );
\tempmon_state[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tempmon_state[10]_i_6_n_0\,
      I1 => tempmon_state(0),
      O => tempmon_state_nxt(1)
    );
\tempmon_state[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => temp_cmp_three_inc_max_102,
      I1 => update_temp_102,
      I2 => tempmon_state(3),
      I3 => \tempmon_state[10]_i_6_n_0\,
      O => tempmon_state_nxt(2)
    );
\tempmon_state[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8AAA8888"
    )
        port map (
      I0 => \tempmon_state[10]_i_6_n_0\,
      I1 => tempmon_state(2),
      I2 => temp_cmp_two_inc_max_102,
      I3 => update_temp_102,
      I4 => tempmon_state(4),
      O => tempmon_state_nxt(3)
    );
\tempmon_state[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080F000F080F000"
    )
        port map (
      I0 => temp_cmp_three_inc_max_102,
      I1 => tempmon_state(3),
      I2 => \tempmon_state[10]_i_6_n_0\,
      I3 => tempmon_state(5),
      I4 => update_temp_102,
      I5 => temp_cmp_one_inc_max_102,
      O => tempmon_state_nxt(4)
    );
\tempmon_state[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080F000F080F000"
    )
        port map (
      I0 => temp_cmp_two_inc_max_102,
      I1 => tempmon_state(4),
      I2 => \tempmon_state[10]_i_6_n_0\,
      I3 => tempmon_state(6),
      I4 => update_temp_102,
      I5 => temp_cmp_neutral_max_102,
      O => tempmon_state_nxt(5)
    );
\tempmon_state[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000BFA00000"
    )
        port map (
      I0 => \tempmon_state[6]_i_2_n_0\,
      I1 => temp_cmp_one_dec_max_102,
      I2 => update_temp_102,
      I3 => tempmon_state(7),
      I4 => \tempmon_state[10]_i_6_n_0\,
      I5 => tempmon_state(1),
      O => tempmon_state_nxt(6)
    );
\tempmon_state[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => temp_cmp_one_inc_max_102,
      I1 => tempmon_state(5),
      O => \tempmon_state[6]_i_2_n_0\
    );
\tempmon_state[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80AAAAAA80008000"
    )
        port map (
      I0 => \tempmon_state[10]_i_6_n_0\,
      I1 => tempmon_state(6),
      I2 => temp_cmp_neutral_max_102,
      I3 => update_temp_102,
      I4 => temp_cmp_two_dec_max_102,
      I5 => tempmon_state(8),
      O => tempmon_state_nxt(7)
    );
\tempmon_state[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080F080F000F000"
    )
        port map (
      I0 => tempmon_state(7),
      I1 => temp_cmp_one_dec_max_102,
      I2 => \tempmon_state[10]_i_6_n_0\,
      I3 => tempmon_state(9),
      I4 => temp_cmp_three_dec_max_102,
      I5 => update_temp_102,
      O => tempmon_state_nxt(8)
    );
\tempmon_state[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => \tempmon_state[10]_i_6_n_0\,
      I1 => temp_cmp_two_dec_max_102,
      I2 => update_temp_102,
      I3 => tempmon_state(8),
      I4 => tempmon_state(10),
      O => tempmon_state_nxt(9)
    );
\tempmon_state_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(0),
      Q => tempmon_state(0),
      S => \two_inc_max_limit_reg[2]_0\
    );
\tempmon_state_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(10),
      Q => tempmon_state(10),
      R => \two_inc_max_limit_reg[2]_0\
    );
\tempmon_state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(1),
      Q => tempmon_state(1),
      R => \two_inc_max_limit_reg[2]_0\
    );
\tempmon_state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(2),
      Q => tempmon_state(2),
      R => \two_inc_max_limit_reg[2]_0\
    );
\tempmon_state_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(3),
      Q => tempmon_state(3),
      R => \two_inc_max_limit_reg[2]_0\
    );
\tempmon_state_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(4),
      Q => tempmon_state(4),
      R => \two_inc_max_limit_reg[2]_0\
    );
\tempmon_state_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(5),
      Q => tempmon_state(5),
      R => \two_inc_max_limit_reg[2]_0\
    );
\tempmon_state_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(6),
      Q => tempmon_state(6),
      R => \two_inc_max_limit_reg[2]_0\
    );
\tempmon_state_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(7),
      Q => tempmon_state(7),
      R => \two_inc_max_limit_reg[2]_0\
    );
\tempmon_state_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(8),
      Q => tempmon_state(8),
      R => \two_inc_max_limit_reg[2]_0\
    );
\tempmon_state_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \tempmon_state[10]_i_1_n_0\,
      D => tempmon_state_nxt(9),
      Q => tempmon_state(9),
      R => \two_inc_max_limit_reg[2]_0\
    );
\three_dec_max_limit[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => p_0_in,
      I1 => device_temp_init(0),
      O => \three_dec_max_limit[0]_i_1_n_0\
    );
\three_dec_max_limit[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[11]_i_2_n_6\,
      I1 => p_0_in,
      O => \three_dec_max_limit[10]_i_1_n_0\
    );
\three_dec_max_limit[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[11]_i_2_n_5\,
      I1 => p_0_in,
      O => \three_dec_max_limit[11]_i_1_n_0\
    );
\three_dec_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(9),
      O => \three_dec_max_limit[11]_i_3_n_0\
    );
\three_dec_max_limit[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_inc_max_limit_reg[4]_i_1_n_7\,
      I1 => p_0_in,
      O => \three_dec_max_limit[1]_i_1_n_0\
    );
\three_dec_max_limit[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[4]_i_2_n_6\,
      I1 => p_0_in,
      O => \three_dec_max_limit[2]_i_1_n_0\
    );
\three_dec_max_limit[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[4]_i_2_n_5\,
      I1 => p_0_in,
      O => \three_dec_max_limit[3]_i_1_n_0\
    );
\three_dec_max_limit[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[4]_i_2_n_4\,
      I1 => p_0_in,
      O => \three_dec_max_limit[4]_i_1_n_0\
    );
\three_dec_max_limit[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[8]_i_2_n_7\,
      I1 => p_0_in,
      O => \three_dec_max_limit[5]_i_1_n_0\
    );
\three_dec_max_limit[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[8]_i_2_n_6\,
      I1 => p_0_in,
      O => \three_dec_max_limit[6]_i_1_n_0\
    );
\three_dec_max_limit[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[8]_i_2_n_5\,
      I1 => p_0_in,
      O => \three_dec_max_limit[7]_i_1_n_0\
    );
\three_dec_max_limit[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[8]_i_2_n_4\,
      I1 => p_0_in,
      O => \three_dec_max_limit[8]_i_1_n_0\
    );
\three_dec_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(8),
      O => \three_dec_max_limit[8]_i_3_n_0\
    );
\three_dec_max_limit[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(6),
      O => \three_dec_max_limit[8]_i_4_n_0\
    );
\three_dec_max_limit[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[11]_i_2_n_7\,
      I1 => p_0_in,
      O => \three_dec_max_limit[9]_i_1_n_0\
    );
\three_dec_max_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[0]_i_1_n_0\,
      Q => three_dec_max_limit(0),
      R => \three_dec_max_limit_reg[11]_0\
    );
\three_dec_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[10]_i_1_n_0\,
      Q => three_dec_max_limit(10),
      R => \three_dec_max_limit_reg[11]_0\
    );
\three_dec_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[11]_i_1_n_0\,
      Q => three_dec_max_limit(11),
      R => \three_dec_max_limit_reg[11]_0\
    );
\three_dec_max_limit_reg[11]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_dec_max_limit_reg[8]_i_2_n_0\,
      CO(3) => p_0_in,
      CO(2) => \NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED\(2),
      CO(1) => \three_dec_max_limit_reg[11]_i_2_n_2\,
      CO(0) => \three_dec_max_limit_reg[11]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => device_temp_init(9),
      O(3) => \NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED\(3),
      O(2) => \three_dec_max_limit_reg[11]_i_2_n_5\,
      O(1) => \three_dec_max_limit_reg[11]_i_2_n_6\,
      O(0) => \three_dec_max_limit_reg[11]_i_2_n_7\,
      S(3) => '1',
      S(2 downto 1) => device_temp_init(11 downto 10),
      S(0) => \three_dec_max_limit[11]_i_3_n_0\
    );
\three_dec_max_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[1]_i_1_n_0\,
      Q => three_dec_max_limit(1),
      R => \three_dec_max_limit_reg[11]_0\
    );
\three_dec_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[2]_i_1_n_0\,
      Q => three_dec_max_limit(2),
      R => \three_dec_max_limit_reg[11]_0\
    );
\three_dec_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[3]_i_1_n_0\,
      Q => three_dec_max_limit(3),
      R => \three_dec_max_limit_reg[11]_0\
    );
\three_dec_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[4]_i_1_n_0\,
      Q => three_dec_max_limit(4),
      R => \three_dec_max_limit_reg[11]_0\
    );
\three_dec_max_limit_reg[4]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \three_dec_max_limit_reg[4]_i_2_n_0\,
      CO(2) => \three_dec_max_limit_reg[4]_i_2_n_1\,
      CO(1) => \three_dec_max_limit_reg[4]_i_2_n_2\,
      CO(0) => \three_dec_max_limit_reg[4]_i_2_n_3\,
      CYINIT => device_temp_init(0),
      DI(3 downto 0) => B"0000",
      O(3) => \three_dec_max_limit_reg[4]_i_2_n_4\,
      O(2) => \three_dec_max_limit_reg[4]_i_2_n_5\,
      O(1) => \three_dec_max_limit_reg[4]_i_2_n_6\,
      O(0) => \NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED\(0),
      S(3 downto 0) => device_temp_init(4 downto 1)
    );
\three_dec_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[5]_i_1_n_0\,
      Q => three_dec_max_limit(5),
      R => \three_dec_max_limit_reg[11]_0\
    );
\three_dec_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[6]_i_1_n_0\,
      Q => three_dec_max_limit(6),
      R => \three_dec_max_limit_reg[11]_0\
    );
\three_dec_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[7]_i_1_n_0\,
      Q => three_dec_max_limit(7),
      R => \three_dec_max_limit_reg[11]_0\
    );
\three_dec_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[8]_i_1_n_0\,
      Q => three_dec_max_limit(8),
      R => \three_dec_max_limit_reg[11]_0\
    );
\three_dec_max_limit_reg[8]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_dec_max_limit_reg[4]_i_2_n_0\,
      CO(3) => \three_dec_max_limit_reg[8]_i_2_n_0\,
      CO(2) => \three_dec_max_limit_reg[8]_i_2_n_1\,
      CO(1) => \three_dec_max_limit_reg[8]_i_2_n_2\,
      CO(0) => \three_dec_max_limit_reg[8]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => device_temp_init(8),
      DI(2) => '0',
      DI(1) => device_temp_init(6),
      DI(0) => '0',
      O(3) => \three_dec_max_limit_reg[8]_i_2_n_4\,
      O(2) => \three_dec_max_limit_reg[8]_i_2_n_5\,
      O(1) => \three_dec_max_limit_reg[8]_i_2_n_6\,
      O(0) => \three_dec_max_limit_reg[8]_i_2_n_7\,
      S(3) => \three_dec_max_limit[8]_i_3_n_0\,
      S(2) => device_temp_init(7),
      S(1) => \three_dec_max_limit[8]_i_4_n_0\,
      S(0) => device_temp_init(5)
    );
\three_dec_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[9]_i_1_n_0\,
      Q => three_dec_max_limit(9),
      R => \three_dec_max_limit_reg[11]_0\
    );
\three_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(11),
      O => \three_dec_min_limit[11]_i_2_n_0\
    );
\three_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(10),
      O => \three_dec_min_limit[11]_i_3_n_0\
    );
\three_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(5),
      O => \three_dec_min_limit[5]_i_2_n_0\
    );
\three_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(4),
      O => \three_dec_min_limit[5]_i_3_n_0\
    );
\three_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(3),
      O => \three_dec_min_limit[5]_i_4_n_0\
    );
\three_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(9),
      O => \three_dec_min_limit[9]_i_2_n_0\
    );
\three_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(8),
      O => \three_dec_min_limit[9]_i_3_n_0\
    );
\three_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(7),
      O => \three_dec_min_limit[9]_i_4_n_0\
    );
\three_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(6),
      O => \three_dec_min_limit[9]_i_5_n_0\
    );
\three_dec_min_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit(0),
      Q => three_dec_min_limit(0),
      R => SR(0)
    );
\three_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(10),
      Q => three_dec_min_limit(10),
      R => SR(0)
    );
\three_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(11),
      Q => three_dec_min_limit(11),
      R => SR(0)
    );
\three_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_dec_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \three_dec_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => two_dec_max_limit(10),
      O(3 downto 2) => \NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => three_dec_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \three_dec_min_limit[11]_i_2_n_0\,
      S(0) => \three_dec_min_limit[11]_i_3_n_0\
    );
\three_dec_min_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit(1),
      Q => three_dec_min_limit(1),
      R => SR(0)
    );
\three_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(2),
      Q => three_dec_min_limit(2),
      R => SR(0)
    );
\three_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(3),
      Q => three_dec_min_limit(3),
      R => SR(0)
    );
\three_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(4),
      Q => three_dec_min_limit(4),
      R => SR(0)
    );
\three_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(5),
      Q => three_dec_min_limit(5),
      R => SR(0)
    );
\three_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \three_dec_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \three_dec_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \three_dec_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \three_dec_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => two_dec_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => three_dec_min_limit_nxt(5 downto 2),
      S(3) => \three_dec_min_limit[5]_i_2_n_0\,
      S(2) => \three_dec_min_limit[5]_i_3_n_0\,
      S(1) => \three_dec_min_limit[5]_i_4_n_0\,
      S(0) => two_dec_max_limit(2)
    );
\three_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(6),
      Q => three_dec_min_limit(6),
      R => SR(0)
    );
\three_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(7),
      Q => three_dec_min_limit(7),
      R => SR(0)
    );
\three_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(8),
      Q => three_dec_min_limit(8),
      R => SR(0)
    );
\three_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(9),
      Q => three_dec_min_limit(9),
      R => SR(0)
    );
\three_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_dec_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \three_dec_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \three_dec_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \three_dec_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \three_dec_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => two_dec_max_limit(9 downto 6),
      O(3 downto 0) => three_dec_min_limit_nxt(9 downto 6),
      S(3) => \three_dec_min_limit[9]_i_2_n_0\,
      S(2) => \three_dec_min_limit[9]_i_3_n_0\,
      S(1) => \three_dec_min_limit[9]_i_4_n_0\,
      S(0) => \three_dec_min_limit[9]_i_5_n_0\
    );
\three_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(11),
      O => \three_inc_max_limit[11]_i_2_n_0\
    );
\three_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(10),
      O => \three_inc_max_limit[11]_i_3_n_0\
    );
\three_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(3),
      O => \three_inc_max_limit[4]_i_2_n_0\
    );
\three_inc_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(2),
      O => \three_inc_max_limit[4]_i_3_n_0\
    );
\three_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(8),
      O => \three_inc_max_limit[8]_i_2_n_0\
    );
\three_inc_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(7),
      O => \three_inc_max_limit[8]_i_3_n_0\
    );
\three_inc_max_limit[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(5),
      O => \three_inc_max_limit[8]_i_4_n_0\
    );
\three_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(10),
      Q => three_inc_max_limit(10),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\three_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(11),
      Q => three_inc_max_limit(11),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\three_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_inc_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \three_inc_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \three_inc_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => device_temp_init(10),
      DI(0) => '0',
      O(3) => \NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => three_inc_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2) => \three_inc_max_limit[11]_i_2_n_0\,
      S(1) => \three_inc_max_limit[11]_i_3_n_0\,
      S(0) => device_temp_init(9)
    );
\three_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(2),
      Q => three_inc_max_limit(2),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\three_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(3),
      Q => three_inc_max_limit(3),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\three_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(4),
      Q => three_inc_max_limit(4),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\three_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \three_inc_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \three_inc_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \three_inc_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \three_inc_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3) => '0',
      DI(2 downto 1) => device_temp_init(3 downto 2),
      DI(0) => '0',
      O(3 downto 1) => three_inc_max_limit_nxt(4 downto 2),
      O(0) => \three_inc_max_limit_reg[4]_i_1_n_7\,
      S(3) => device_temp_init(4),
      S(2) => \three_inc_max_limit[4]_i_2_n_0\,
      S(1) => \three_inc_max_limit[4]_i_3_n_0\,
      S(0) => device_temp_init(1)
    );
\three_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(5),
      Q => three_inc_max_limit(5),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\three_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(6),
      Q => three_inc_max_limit(6),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\three_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(7),
      Q => three_inc_max_limit(7),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\three_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(8),
      Q => three_inc_max_limit(8),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\three_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_inc_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \three_inc_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \three_inc_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \three_inc_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \three_inc_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => device_temp_init(8 downto 7),
      DI(1) => '0',
      DI(0) => device_temp_init(5),
      O(3 downto 0) => three_inc_max_limit_nxt(8 downto 5),
      S(3) => \three_inc_max_limit[8]_i_2_n_0\,
      S(2) => \three_inc_max_limit[8]_i_3_n_0\,
      S(1) => device_temp_init(6),
      S(0) => \three_inc_max_limit[8]_i_4_n_0\
    );
\three_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(9),
      Q => three_inc_max_limit(9),
      R => \four_inc_max_limit_reg[11]_0\(0)
    );
\three_inc_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(11),
      O => \three_inc_min_limit[11]_i_2_n_0\
    );
\three_inc_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(10),
      O => \three_inc_min_limit[11]_i_3_n_0\
    );
\three_inc_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(5),
      O => \three_inc_min_limit[5]_i_2_n_0\
    );
\three_inc_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(4),
      O => \three_inc_min_limit[5]_i_3_n_0\
    );
\three_inc_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(3),
      O => \three_inc_min_limit[5]_i_4_n_0\
    );
\three_inc_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(9),
      O => \three_inc_min_limit[9]_i_2_n_0\
    );
\three_inc_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(8),
      O => \three_inc_min_limit[9]_i_3_n_0\
    );
\three_inc_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(7),
      O => \three_inc_min_limit[9]_i_4_n_0\
    );
\three_inc_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(6),
      O => \three_inc_min_limit[9]_i_5_n_0\
    );
\three_inc_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(10),
      Q => three_inc_min_limit(10),
      R => \one_inc_min_limit_reg[2]_0\
    );
\three_inc_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(11),
      Q => three_inc_min_limit(11),
      R => \one_inc_min_limit_reg[2]_0\
    );
\three_inc_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_inc_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \three_inc_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => four_inc_max_limit(10),
      O(3 downto 2) => \NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => three_inc_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \three_inc_min_limit[11]_i_2_n_0\,
      S(0) => \three_inc_min_limit[11]_i_3_n_0\
    );
\three_inc_min_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit(1),
      Q => three_inc_min_limit(1),
      R => \one_inc_min_limit_reg[2]_0\
    );
\three_inc_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(2),
      Q => three_inc_min_limit(2),
      R => \one_inc_min_limit_reg[2]_0\
    );
\three_inc_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(3),
      Q => three_inc_min_limit(3),
      R => \one_inc_min_limit_reg[2]_0\
    );
\three_inc_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(4),
      Q => three_inc_min_limit(4),
      R => \one_inc_min_limit_reg[2]_0\
    );
\three_inc_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(5),
      Q => three_inc_min_limit(5),
      R => \one_inc_min_limit_reg[2]_0\
    );
\three_inc_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \three_inc_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \three_inc_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \three_inc_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \three_inc_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => four_inc_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => three_inc_min_limit_nxt(5 downto 2),
      S(3) => \three_inc_min_limit[5]_i_2_n_0\,
      S(2) => \three_inc_min_limit[5]_i_3_n_0\,
      S(1) => \three_inc_min_limit[5]_i_4_n_0\,
      S(0) => four_inc_max_limit(2)
    );
\three_inc_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(6),
      Q => three_inc_min_limit(6),
      R => \one_inc_min_limit_reg[2]_0\
    );
\three_inc_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(7),
      Q => three_inc_min_limit(7),
      R => \one_inc_min_limit_reg[2]_0\
    );
\three_inc_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(8),
      Q => three_inc_min_limit(8),
      R => \one_inc_min_limit_reg[2]_0\
    );
\three_inc_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(9),
      Q => three_inc_min_limit(9),
      R => \one_inc_min_limit_reg[2]_0\
    );
\three_inc_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_inc_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \three_inc_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \three_inc_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \three_inc_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \three_inc_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => four_inc_max_limit(9 downto 6),
      O(3 downto 0) => three_inc_min_limit_nxt(9 downto 6),
      S(3) => \three_inc_min_limit[9]_i_2_n_0\,
      S(2) => \three_inc_min_limit[9]_i_3_n_0\,
      S(1) => \three_inc_min_limit[9]_i_4_n_0\,
      S(0) => \three_inc_min_limit[9]_i_5_n_0\
    );
\two_dec_max_limit[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(0),
      O => \two_dec_max_limit[0]_i_1_n_0\
    );
\two_dec_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(9),
      O => \two_dec_max_limit[11]_i_2_n_0\
    );
\two_dec_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(4),
      O => \two_dec_max_limit[4]_i_2_n_0\
    );
\two_dec_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(1),
      O => \two_dec_max_limit[4]_i_3_n_0\
    );
\two_dec_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(6),
      O => \two_dec_max_limit[8]_i_2_n_0\
    );
\two_dec_max_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \two_dec_max_limit[0]_i_1_n_0\,
      Q => two_dec_max_limit(0),
      R => \one_inc_min_limit_reg[2]_0\
    );
\two_dec_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(10),
      Q => two_dec_max_limit(10),
      R => \one_inc_min_limit_reg[2]_0\
    );
\two_dec_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(11),
      Q => two_dec_max_limit(11),
      R => \one_inc_min_limit_reg[2]_0\
    );
\two_dec_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_dec_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \two_dec_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \two_dec_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => device_temp_init(9),
      O(3) => \NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => two_dec_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2 downto 1) => device_temp_init(11 downto 10),
      S(0) => \two_dec_max_limit[11]_i_2_n_0\
    );
\two_dec_max_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(1),
      Q => two_dec_max_limit(1),
      R => \one_inc_min_limit_reg[2]_0\
    );
\two_dec_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(2),
      Q => two_dec_max_limit(2),
      R => \one_inc_min_limit_reg[2]_0\
    );
\two_dec_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(3),
      Q => two_dec_max_limit(3),
      R => \one_inc_min_limit_reg[2]_0\
    );
\two_dec_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(4),
      Q => two_dec_max_limit(4),
      R => \one_inc_min_limit_reg[2]_0\
    );
\two_dec_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \two_dec_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \two_dec_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \two_dec_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \two_dec_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3) => device_temp_init(4),
      DI(2 downto 1) => B"00",
      DI(0) => device_temp_init(1),
      O(3 downto 1) => two_dec_max_limit_nxt(4 downto 2),
      O(0) => \NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => \two_dec_max_limit[4]_i_2_n_0\,
      S(2 downto 1) => device_temp_init(3 downto 2),
      S(0) => \two_dec_max_limit[4]_i_3_n_0\
    );
\two_dec_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(5),
      Q => two_dec_max_limit(5),
      R => \one_inc_min_limit_reg[2]_0\
    );
\two_dec_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(6),
      Q => two_dec_max_limit(6),
      R => \one_inc_min_limit_reg[2]_0\
    );
\two_dec_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(7),
      Q => two_dec_max_limit(7),
      R => \one_inc_min_limit_reg[2]_0\
    );
\two_dec_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(8),
      Q => two_dec_max_limit(8),
      R => \one_inc_min_limit_reg[2]_0\
    );
\two_dec_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_dec_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \two_dec_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \two_dec_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \two_dec_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \two_dec_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => device_temp_init(6),
      DI(0) => '0',
      O(3 downto 0) => two_dec_max_limit_nxt(8 downto 5),
      S(3 downto 2) => device_temp_init(8 downto 7),
      S(1) => \two_dec_max_limit[8]_i_2_n_0\,
      S(0) => device_temp_init(5)
    );
\two_dec_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(9),
      Q => two_dec_max_limit(9),
      R => \one_inc_min_limit_reg[2]_0\
    );
\two_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(11),
      O => \two_dec_min_limit[11]_i_2_n_0\
    );
\two_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(10),
      O => \two_dec_min_limit[11]_i_3_n_0\
    );
\two_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(5),
      O => \two_dec_min_limit[5]_i_2_n_0\
    );
\two_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(4),
      O => \two_dec_min_limit[5]_i_3_n_0\
    );
\two_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(3),
      O => \two_dec_min_limit[5]_i_4_n_0\
    );
\two_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(9),
      O => \two_dec_min_limit[9]_i_2_n_0\
    );
\two_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(8),
      O => \two_dec_min_limit[9]_i_3_n_0\
    );
\two_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(7),
      O => \two_dec_min_limit[9]_i_4_n_0\
    );
\two_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(6),
      O => \two_dec_min_limit[9]_i_5_n_0\
    );
\two_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(10),
      Q => two_dec_min_limit(10),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(11),
      Q => two_dec_min_limit(11),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_dec_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \two_dec_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => one_dec_max_limit(10),
      O(3 downto 2) => \NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => two_dec_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \two_dec_min_limit[11]_i_2_n_0\,
      S(0) => \two_dec_min_limit[11]_i_3_n_0\
    );
\two_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(2),
      Q => two_dec_min_limit(2),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(3),
      Q => two_dec_min_limit(3),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(4),
      Q => two_dec_min_limit(4),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(5),
      Q => two_dec_min_limit(5),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \two_dec_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \two_dec_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \two_dec_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \two_dec_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => one_dec_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => two_dec_min_limit_nxt(5 downto 2),
      S(3) => \two_dec_min_limit[5]_i_2_n_0\,
      S(2) => \two_dec_min_limit[5]_i_3_n_0\,
      S(1) => \two_dec_min_limit[5]_i_4_n_0\,
      S(0) => one_dec_max_limit(2)
    );
\two_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(6),
      Q => two_dec_min_limit(6),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(7),
      Q => two_dec_min_limit(7),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(8),
      Q => two_dec_min_limit(8),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(9),
      Q => two_dec_min_limit(9),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_dec_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \two_dec_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \two_dec_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \two_dec_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \two_dec_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => one_dec_max_limit(9 downto 6),
      O(3 downto 0) => two_dec_min_limit_nxt(9 downto 6),
      S(3) => \two_dec_min_limit[9]_i_2_n_0\,
      S(2) => \two_dec_min_limit[9]_i_3_n_0\,
      S(1) => \two_dec_min_limit[9]_i_4_n_0\,
      S(0) => \two_dec_min_limit[9]_i_5_n_0\
    );
\two_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(11),
      O => \two_inc_max_limit[11]_i_2_n_0\
    );
\two_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(10),
      O => \two_inc_max_limit[11]_i_3_n_0\
    );
\two_inc_max_limit[11]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(9),
      O => \two_inc_max_limit[11]_i_4_n_0\
    );
\two_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(4),
      O => \two_inc_max_limit[4]_i_2_n_0\
    );
\two_inc_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(3),
      O => \two_inc_max_limit[4]_i_3_n_0\
    );
\two_inc_max_limit[4]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(1),
      O => \two_inc_max_limit[4]_i_4_n_0\
    );
\two_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(7),
      O => \two_inc_max_limit[8]_i_2_n_0\
    );
\two_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(10),
      Q => two_inc_max_limit(10),
      R => \two_inc_max_limit_reg[2]_0\
    );
\two_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(11),
      Q => two_inc_max_limit(11),
      R => \two_inc_max_limit_reg[2]_0\
    );
\two_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_inc_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \two_inc_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \two_inc_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => device_temp_init(10 downto 9),
      O(3) => \NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => two_inc_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2) => \two_inc_max_limit[11]_i_2_n_0\,
      S(1) => \two_inc_max_limit[11]_i_3_n_0\,
      S(0) => \two_inc_max_limit[11]_i_4_n_0\
    );
\two_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(2),
      Q => two_inc_max_limit(2),
      R => \two_inc_max_limit_reg[2]_0\
    );
\two_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(3),
      Q => two_inc_max_limit(3),
      R => \two_inc_max_limit_reg[2]_0\
    );
\two_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(4),
      Q => two_inc_max_limit(4),
      R => \two_inc_max_limit_reg[2]_0\
    );
\two_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \two_inc_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \two_inc_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \two_inc_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \two_inc_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3 downto 2) => device_temp_init(4 downto 3),
      DI(1) => '0',
      DI(0) => device_temp_init(1),
      O(3 downto 1) => two_inc_max_limit_nxt(4 downto 2),
      O(0) => \NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => \two_inc_max_limit[4]_i_2_n_0\,
      S(2) => \two_inc_max_limit[4]_i_3_n_0\,
      S(1) => device_temp_init(2),
      S(0) => \two_inc_max_limit[4]_i_4_n_0\
    );
\two_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(5),
      Q => two_inc_max_limit(5),
      R => \two_inc_max_limit_reg[2]_0\
    );
\two_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(6),
      Q => two_inc_max_limit(6),
      R => \two_inc_max_limit_reg[2]_0\
    );
\two_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(7),
      Q => two_inc_max_limit(7),
      R => \two_inc_max_limit_reg[2]_0\
    );
\two_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(8),
      Q => two_inc_max_limit(8),
      R => \two_inc_max_limit_reg[2]_0\
    );
\two_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_inc_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \two_inc_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \two_inc_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \two_inc_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \two_inc_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => device_temp_init(7),
      DI(1 downto 0) => B"00",
      O(3 downto 0) => two_inc_max_limit_nxt(8 downto 5),
      S(3) => device_temp_init(8),
      S(2) => \two_inc_max_limit[8]_i_2_n_0\,
      S(1 downto 0) => device_temp_init(6 downto 5)
    );
\two_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(9),
      Q => two_inc_max_limit(9),
      R => \two_inc_max_limit_reg[2]_0\
    );
\two_inc_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(11),
      O => \two_inc_min_limit[11]_i_2_n_0\
    );
\two_inc_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(10),
      O => \two_inc_min_limit[11]_i_3_n_0\
    );
\two_inc_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(5),
      O => \two_inc_min_limit[5]_i_2_n_0\
    );
\two_inc_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(4),
      O => \two_inc_min_limit[5]_i_3_n_0\
    );
\two_inc_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(3),
      O => \two_inc_min_limit[5]_i_4_n_0\
    );
\two_inc_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(9),
      O => \two_inc_min_limit[9]_i_2_n_0\
    );
\two_inc_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(8),
      O => \two_inc_min_limit[9]_i_3_n_0\
    );
\two_inc_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(7),
      O => \two_inc_min_limit[9]_i_4_n_0\
    );
\two_inc_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(6),
      O => \two_inc_min_limit[9]_i_5_n_0\
    );
\two_inc_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(10),
      Q => two_inc_min_limit(10),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_inc_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(11),
      Q => two_inc_min_limit(11),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_inc_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_inc_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \two_inc_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => three_inc_max_limit(10),
      O(3 downto 2) => \NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => two_inc_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \two_inc_min_limit[11]_i_2_n_0\,
      S(0) => \two_inc_min_limit[11]_i_3_n_0\
    );
\two_inc_min_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit(1),
      Q => two_inc_min_limit(1),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_inc_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(2),
      Q => two_inc_min_limit(2),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_inc_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(3),
      Q => two_inc_min_limit(3),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_inc_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(4),
      Q => two_inc_min_limit(4),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_inc_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(5),
      Q => two_inc_min_limit(5),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_inc_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \two_inc_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \two_inc_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \two_inc_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \two_inc_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => three_inc_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => two_inc_min_limit_nxt(5 downto 2),
      S(3) => \two_inc_min_limit[5]_i_2_n_0\,
      S(2) => \two_inc_min_limit[5]_i_3_n_0\,
      S(1) => \two_inc_min_limit[5]_i_4_n_0\,
      S(0) => three_inc_max_limit(2)
    );
\two_inc_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(6),
      Q => two_inc_min_limit(6),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_inc_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(7),
      Q => two_inc_min_limit(7),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_inc_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(8),
      Q => two_inc_min_limit(8),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_inc_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(9),
      Q => two_inc_min_limit(9),
      R => \three_dec_max_limit_reg[11]_0\
    );
\two_inc_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_inc_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \two_inc_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \two_inc_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \two_inc_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \two_inc_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => three_inc_max_limit(9 downto 6),
      O(3 downto 0) => two_inc_min_limit_nxt(9 downto 6),
      S(3) => \two_inc_min_limit[9]_i_2_n_0\,
      S(2) => \two_inc_min_limit[9]_i_3_n_0\,
      S(1) => \two_inc_min_limit[9]_i_4_n_0\,
      S(0) => \two_inc_min_limit[9]_i_5_n_0\
    );
update_temp_101: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => tempmon_init_complete,
      I1 => tempmon_sample_en_102,
      I2 => tempmon_sample_en_101,
      O => \update_temp_101__0\
    );
update_temp_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \update_temp_101__0\,
      Q => update_temp_102,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_phy_wrcal is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    wrcal_prech_req : out STD_LOGIC;
    wrlvl_byte_redo : out STD_LOGIC;
    phy_if_reset_w : out STD_LOGIC;
    idelay_ld_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    cal1_dq_idel_ce_reg : out STD_LOGIC;
    LD0 : out STD_LOGIC;
    LD0_0 : out STD_LOGIC;
    wrcal_done_reg_0 : out STD_LOGIC;
    CLK : in STD_LOGIC;
    \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]_0\ : in STD_LOGIC;
    phy_rddata_en : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ : in STD_LOGIC;
    \wrcal_dqs_cnt_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    wrcal_done_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ce_int : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][1][4]\ : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][1][4]_0\ : in STD_LOGIC;
    calib_zero_inputs : in STD_LOGIC;
    \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : in STD_LOGIC;
    \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\ : in STD_LOGIC;
    idelay_ld_rst : in STD_LOGIC;
    \not_empty_wait_cnt_reg[4]_0\ : in STD_LOGIC;
    wrcal_rd_wait : in STD_LOGIC;
    \cal2_state_r[3]_i_3_0\ : in STD_LOGIC;
    prech_done : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_phy_wrcal : entity is "mig_7series_v4_2_ddr_phy_wrcal";
end mig_7series_0_mig_7series_v4_2_ddr_phy_wrcal;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_phy_wrcal is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal cal2_done_r : STD_LOGIC;
  signal cal2_done_r_i_1_n_0 : STD_LOGIC;
  signal cal2_if_reset : STD_LOGIC;
  signal cal2_if_reset_i_1_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_2_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_4_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_5_n_0 : STD_LOGIC;
  signal cal2_prech_req_r : STD_LOGIC;
  signal cal2_prech_req_r_i_1_n_0 : STD_LOGIC;
  signal cal2_state_r : STD_LOGIC;
  signal \cal2_state_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \cal2_state_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \cal2_state_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \cal2_state_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \cal2_state_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \cal2_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \cal2_state_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \cal2_state_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_10_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \cal2_state_r_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \cal2_state_r_reg[1]_i_1_n_0\ : STD_LOGIC;
  signal \cal2_state_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \cal2_state_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \cal2_state_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \cal2_state_r_reg_n_0_[3]\ : STD_LOGIC;
  signal early1_data_match_r0 : STD_LOGIC;
  signal early1_match_fall0_and_r : STD_LOGIC;
  signal early1_match_fall0_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early1_match_fall1_and_r : STD_LOGIC;
  signal early1_match_fall2_and_r : STD_LOGIC;
  signal early1_match_fall3_and_r : STD_LOGIC;
  signal early1_match_rise0_and_r : STD_LOGIC;
  signal early1_match_rise0_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early1_match_rise1_and_r : STD_LOGIC;
  signal early1_match_rise2_and_r : STD_LOGIC;
  signal early1_match_rise3_and_r : STD_LOGIC;
  signal early2_data_match_r0 : STD_LOGIC;
  signal early2_match_fall0_and_r : STD_LOGIC;
  signal early2_match_fall0_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_fall1_and_r : STD_LOGIC;
  signal early2_match_fall1_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_fall2_and_r : STD_LOGIC;
  signal early2_match_fall2_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_fall3_and_r : STD_LOGIC;
  signal early2_match_fall3_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_rise0_and_r : STD_LOGIC;
  signal early2_match_rise0_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_rise1_and_r : STD_LOGIC;
  signal early2_match_rise1_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_rise2_and_r : STD_LOGIC;
  signal early2_match_rise2_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal early2_match_rise3_and_r : STD_LOGIC;
  signal early2_match_rise3_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_219\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_255\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_233\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_211\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_247\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_203\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_241\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_220\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_256\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_234\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_212\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_248\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_204\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_227\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_242\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_221\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_257\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_235\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_213\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_249\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_205\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_228\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_243\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_222\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_258\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_236\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_214\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_250\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_206\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_229\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_223\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_259\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_237\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_215\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_251\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_207\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_244\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_224\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_260\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_238\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_216\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_252\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_208\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_230\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_245\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_225\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_261\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_239\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_217\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_253\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_209\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_231\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_246\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_226\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_262\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_240\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_218\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_254\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_210\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_232\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0\ : STD_LOGIC;
  signal idelay_ld : STD_LOGIC;
  signal idelay_ld_done_i_1_n_0 : STD_LOGIC;
  signal idelay_ld_done_i_2_n_0 : STD_LOGIC;
  signal idelay_ld_done_reg_n_0 : STD_LOGIC;
  signal idelay_ld_i_1_n_0 : STD_LOGIC;
  signal idelay_ld_i_2_n_0 : STD_LOGIC;
  signal \not_empty_wait_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal pat_data_match_r0 : STD_LOGIC;
  signal pat_match_fall0_and_r : STD_LOGIC;
  signal pat_match_fall1_and_r : STD_LOGIC;
  signal pat_match_fall2_and_r : STD_LOGIC;
  signal pat_match_fall3_and_r : STD_LOGIC;
  signal pat_match_rise0_and_r : STD_LOGIC;
  signal pat_match_rise1_and_r : STD_LOGIC;
  signal pat_match_rise2_and_r : STD_LOGIC;
  signal pat_match_rise3_and_r : STD_LOGIC;
  signal \^phy_if_reset_w\ : STD_LOGIC;
  signal po_stg2_wrcal_cnt : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^po_stg2_wrcal_cnt_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rd_active_r1 : STD_LOGIC;
  signal rd_active_r3_reg_srl2_n_0 : STD_LOGIC;
  signal \tap_inc_wait_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal tap_inc_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wrcal_done_i_1_n_0 : STD_LOGIC;
  signal \^wrcal_done_reg_0\ : STD_LOGIC;
  signal wrcal_dqs_cnt_r : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \wrcal_dqs_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \^wrlvl_byte_redo\ : STD_LOGIC;
  signal wrlvl_byte_redo_i_1_n_0 : STD_LOGIC;
  signal wrlvl_byte_redo_i_2_n_0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of cal2_if_reset_i_2 : label is "soft_lutpair365";
  attribute SOFT_HLUTNM of \cal2_state_r[0]_i_4\ : label is "soft_lutpair354";
  attribute SOFT_HLUTNM of \cal2_state_r[2]_i_2\ : label is "soft_lutpair363";
  attribute SOFT_HLUTNM of \cal2_state_r[2]_i_3\ : label is "soft_lutpair354";
  attribute SOFT_HLUTNM of \cal2_state_r[3]_i_8\ : label is "soft_lutpair365";
  attribute SOFT_HLUTNM of \cal2_state_r[3]_i_9\ : label is "soft_lutpair362";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_fall1_and_r_i_2\ : label is "soft_lutpair359";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_fall3_and_r_i_2\ : label is "soft_lutpair360";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_rise1_and_r_i_2\ : label is "soft_lutpair357";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_rise2_and_r_i_1\ : label is "soft_lutpair358";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_fall0_and_r_i_2\ : label is "soft_lutpair355";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_fall1_and_r_i_1\ : label is "soft_lutpair359";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_fall3_and_r_i_1\ : label is "soft_lutpair360";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_rise0_and_r_i_2\ : label is "soft_lutpair356";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_rise1_and_r_i_1\ : label is "soft_lutpair357";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_rise2_and_r_i_2\ : label is "soft_lutpair358";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat_match_fall0_and_r_i_1\ : label is "soft_lutpair355";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat_match_rise0_and_r_i_1\ : label is "soft_lutpair356";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0] ";
  attribute srl_name : string;
  attribute srl_name of \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2 ";
  attribute srl_bus_name of \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3] ";
  attribute srl_name of \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2 ";
  attribute srl_bus_name of \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4] ";
  attribute srl_name of \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2 ";
  attribute srl_bus_name of \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7] ";
  attribute srl_name of \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2 ";
  attribute SOFT_HLUTNM of idelay_ld_done_i_2 : label is "soft_lutpair362";
  attribute SOFT_HLUTNM of \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_2\ : label is "soft_lutpair352";
  attribute SOFT_HLUTNM of \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2\ : label is "soft_lutpair352";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[1]_i_1\ : label is "soft_lutpair366";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[2]_i_1\ : label is "soft_lutpair366";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[3]_i_1\ : label is "soft_lutpair353";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[4]_i_2\ : label is "soft_lutpair353";
  attribute srl_name of rd_active_r3_reg_srl2 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r3_reg_srl2 ";
  attribute SOFT_HLUTNM of \tap_inc_wait_cnt[0]_i_1\ : label is "soft_lutpair367";
  attribute SOFT_HLUTNM of \tap_inc_wait_cnt[1]_i_1\ : label is "soft_lutpair367";
  attribute SOFT_HLUTNM of \tap_inc_wait_cnt[2]_i_1\ : label is "soft_lutpair364";
  attribute SOFT_HLUTNM of \tap_inc_wait_cnt[3]_i_2\ : label is "soft_lutpair364";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[0]_i_1\ : label is "soft_lutpair361";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[1]_i_1\ : label is "soft_lutpair361";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[1]_i_3\ : label is "soft_lutpair363";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \wrcal_dqs_cnt_r_reg[0]\ : label is "10";
  attribute syn_maxfan of \wrcal_dqs_cnt_r_reg[1]\ : label is "10";
begin
  E(0) <= \^e\(0);
  phy_if_reset_w <= \^phy_if_reset_w\;
  \po_stg2_wrcal_cnt_reg[0]_0\(0) <= \^po_stg2_wrcal_cnt_reg[0]_0\(0);
  wrcal_done_reg_0 <= \^wrcal_done_reg_0\;
  wrlvl_byte_redo <= \^wrlvl_byte_redo\;
cal2_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0020"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[1]\,
      I1 => \cal2_state_r_reg_n_0_[0]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r_reg_n_0_[3]\,
      I4 => cal2_done_r,
      O => cal2_done_r_i_1_n_0
    );
cal2_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal2_done_r_i_1_n_0,
      Q => cal2_done_r,
      R => wrcal_done_reg_1(0)
    );
cal2_if_reset_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800FFFFB8000000"
    )
        port map (
      I0 => cal2_if_reset_i_2_n_0,
      I1 => \cal2_state_r_reg_n_0_[1]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r_reg_n_0_[0]\,
      I4 => cal2_if_reset,
      I5 => \^phy_if_reset_w\,
      O => cal2_if_reset_i_1_n_0
    );
cal2_if_reset_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^e\(0),
      I1 => rd_active_r1,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      O => cal2_if_reset_i_2_n_0
    );
cal2_if_reset_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EE2E"
    )
        port map (
      I0 => \cal2_state_r[3]_i_7_n_0\,
      I1 => \cal2_state_r_reg_n_0_[0]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => idelay_ld_done_i_2_n_0,
      I4 => \cal2_state_r_reg_n_0_[3]\,
      O => cal2_if_reset_i_4_n_0
    );
cal2_if_reset_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002262"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[2]\,
      I1 => \cal2_state_r_reg_n_0_[0]\,
      I2 => rd_active_r1,
      I3 => \^e\(0),
      I4 => \cal2_state_r_reg_n_0_[3]\,
      O => cal2_if_reset_i_5_n_0
    );
cal2_if_reset_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal2_if_reset_i_1_n_0,
      Q => \^phy_if_reset_w\,
      R => \wrcal_dqs_cnt_r_reg[1]_0\(0)
    );
cal2_if_reset_reg_i_3: unisim.vcomponents.MUXF7
     port map (
      I0 => cal2_if_reset_i_4_n_0,
      I1 => cal2_if_reset_i_5_n_0,
      O => cal2_if_reset,
      S => \cal2_state_r_reg_n_0_[1]\
    );
cal2_prech_req_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => \cal2_state_r_reg_n_0_[0]\,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      O => cal2_prech_req_r_i_1_n_0
    );
cal2_prech_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal2_prech_req_r_i_1_n_0,
      Q => cal2_prech_req_r,
      R => \wrcal_dqs_cnt_r_reg[1]_0\(0)
    );
\cal2_state_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDAD5D0D"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[2]\,
      I1 => idelay_ld_done_reg_n_0,
      I2 => \cal2_state_r_reg_n_0_[0]\,
      I3 => \cal2_state_r[0]_i_4_n_0\,
      I4 => tap_inc_wait_cnt_reg(0),
      I5 => \cal2_state_r_reg_n_0_[3]\,
      O => \cal2_state_r[0]_i_2_n_0\
    );
\cal2_state_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAA5155"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[2]\,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I2 => wrcal_dqs_cnt_r(1),
      I3 => prech_done,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => \cal2_state_r_reg_n_0_[3]\,
      O => \cal2_state_r[0]_i_3_n_0\
    );
\cal2_state_r[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EF00"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I2 => idelay_ld_done_reg_n_0,
      I3 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I4 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      O => \cal2_state_r[0]_i_4_n_0\
    );
\cal2_state_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFA200A200000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I1 => \cal2_state_r[3]_i_10_n_0\,
      I2 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => tap_inc_wait_cnt_reg(1),
      I5 => \cal2_state_r_reg_n_0_[0]\,
      O => \cal2_state_r[1]_i_2_n_0\
    );
\cal2_state_r[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001055"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[2]\,
      I1 => wrcal_dqs_cnt_r(1),
      I2 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I3 => prech_done,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      O => \cal2_state_r[1]_i_3_n_0\
    );
\cal2_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33FC00FC88888888"
    )
        port map (
      I0 => \cal2_state_r[2]_i_2_n_0\,
      I1 => \cal2_state_r_reg_n_0_[1]\,
      I2 => \cal2_state_r[2]_i_3_n_0\,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => tap_inc_wait_cnt_reg(2),
      I5 => \cal2_state_r_reg_n_0_[0]\,
      O => \cal2_state_r[2]_i_1_n_0\
    );
\cal2_state_r[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"005D"
    )
        port map (
      I0 => prech_done,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I2 => wrcal_dqs_cnt_r(1),
      I3 => \cal2_state_r_reg_n_0_[2]\,
      O => \cal2_state_r[2]_i_2_n_0\
    );
\cal2_state_r[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I2 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I3 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I4 => idelay_ld_done_reg_n_0,
      O => \cal2_state_r[2]_i_3_n_0\
    );
\cal2_state_r[3]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      O => \cal2_state_r[3]_i_10_n_0\
    );
\cal2_state_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"50CC"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[1]\,
      I1 => \cal2_state_r_reg_n_0_[3]\,
      I2 => \cal2_state_r[3]_i_5_n_0\,
      I3 => \cal2_state_r_reg_n_0_[0]\,
      O => \cal2_state_r[3]_i_2_n_0\
    );
\cal2_state_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45405F5F45400A0A"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => idelay_ld_done_i_2_n_0,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r[3]_i_6_n_0\,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => \cal2_state_r[3]_i_7_n_0\,
      O => \cal2_state_r[3]_i_3_n_0\
    );
\cal2_state_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F4A45404"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[2]\,
      I1 => prech_done,
      I2 => \cal2_state_r_reg_n_0_[0]\,
      I3 => \cal2_state_r[3]_i_8_n_0\,
      I4 => \cal2_state_r[3]_i_9_n_0\,
      I5 => \cal2_state_r_reg_n_0_[3]\,
      O => \cal2_state_r[3]_i_4_n_0\
    );
\cal2_state_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B888888BBBBBBBB"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(3),
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      I3 => \cal2_state_r[3]_i_10_n_0\,
      I4 => idelay_ld_done_reg_n_0,
      I5 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      O => \cal2_state_r[3]_i_5_n_0\
    );
\cal2_state_r[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[0]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[2]\,
      I3 => \not_empty_wait_cnt_reg_n_0_[3]\,
      I4 => \not_empty_wait_cnt_reg_n_0_[4]\,
      I5 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      O => \cal2_state_r[3]_i_6_n_0\
    );
\cal2_state_r[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(0),
      I1 => tap_inc_wait_cnt_reg(2),
      I2 => tap_inc_wait_cnt_reg(1),
      I3 => tap_inc_wait_cnt_reg(3),
      I4 => \cal2_state_r_reg_n_0_[2]\,
      I5 => \cal2_state_r[3]_i_3_0\,
      O => \cal2_state_r[3]_i_7_n_0\
    );
\cal2_state_r[3]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rd_active_r1,
      I1 => \^e\(0),
      O => \cal2_state_r[3]_i_8_n_0\
    );
\cal2_state_r[3]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(0),
      I1 => tap_inc_wait_cnt_reg(2),
      I2 => tap_inc_wait_cnt_reg(1),
      I3 => tap_inc_wait_cnt_reg(3),
      O => \cal2_state_r[3]_i_9_n_0\
    );
\cal2_state_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => cal2_state_r,
      D => \cal2_state_r_reg[0]_i_1_n_0\,
      Q => \cal2_state_r_reg_n_0_[0]\,
      R => wrcal_done_reg_1(0)
    );
\cal2_state_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \cal2_state_r[0]_i_2_n_0\,
      I1 => \cal2_state_r[0]_i_3_n_0\,
      O => \cal2_state_r_reg[0]_i_1_n_0\,
      S => \cal2_state_r_reg_n_0_[1]\
    );
\cal2_state_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => cal2_state_r,
      D => \cal2_state_r_reg[1]_i_1_n_0\,
      Q => \cal2_state_r_reg_n_0_[1]\,
      R => wrcal_done_reg_1(0)
    );
\cal2_state_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \cal2_state_r[1]_i_2_n_0\,
      I1 => \cal2_state_r[1]_i_3_n_0\,
      O => \cal2_state_r_reg[1]_i_1_n_0\,
      S => \cal2_state_r_reg_n_0_[1]\
    );
\cal2_state_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => cal2_state_r,
      D => \cal2_state_r[2]_i_1_n_0\,
      Q => \cal2_state_r_reg_n_0_[2]\,
      R => wrcal_done_reg_1(0)
    );
\cal2_state_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => cal2_state_r,
      D => \cal2_state_r[3]_i_2_n_0\,
      Q => \cal2_state_r_reg_n_0_[3]\,
      R => wrcal_done_reg_1(0)
    );
\cal2_state_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \cal2_state_r[3]_i_3_n_0\,
      I1 => \cal2_state_r[3]_i_4_n_0\,
      O => cal2_state_r,
      S => \cal2_state_r_reg_n_0_[1]\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_pat_match_div4.early1_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early1_match_rise0_and_r,
      I1 => early1_match_fall3_and_r,
      I2 => early1_match_fall0_and_r,
      I3 => early1_match_fall2_and_r,
      I4 => \gen_pat_match_div4.early1_data_match_r_i_2_n_0\,
      O => early1_data_match_r0
    );
\gen_pat_match_div4.early1_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early1_match_rise2_and_r,
      I1 => early1_match_rise3_and_r,
      I2 => early1_match_rise1_and_r,
      I3 => early1_match_fall1_and_r,
      O => \gen_pat_match_div4.early1_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => early1_data_match_r0,
      Q => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.early1_match_fall0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early1_match_fall0_r(2),
      I1 => early1_match_fall0_r(0),
      I2 => early1_match_fall0_r(6),
      I3 => early1_match_fall0_r(4),
      I4 => \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_fall0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early1_match_fall0_r(1),
      I1 => early1_match_fall0_r(3),
      I2 => early1_match_fall0_r(5),
      I3 => early1_match_fall0_r(7),
      O => \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0\,
      Q => early1_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_fall1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_fall1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_fall1_r(0),
      I1 => early2_match_fall1_r(5),
      I2 => early2_match_fall1_r(1),
      I3 => early2_match_fall1_r(4),
      O => \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0\,
      Q => early1_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg\,
      I3 => early2_match_fall2_r(7),
      I4 => early2_match_fall2_r(3),
      O => \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0\,
      Q => early1_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_fall3_r(1),
      I1 => early2_match_fall3_r(5),
      I2 => early2_match_fall3_r(3),
      I3 => early2_match_fall3_r(7),
      O => \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0\,
      Q => early1_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early1_match_rise0_r(2),
      I1 => early1_match_rise0_r(0),
      I2 => early1_match_rise0_r(6),
      I3 => early1_match_rise0_r(4),
      I4 => \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early1_match_rise0_r(1),
      I1 => early1_match_rise0_r(3),
      I2 => early1_match_rise0_r(5),
      I3 => early1_match_rise0_r(7),
      O => \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0\,
      Q => early1_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_rise1_r(0),
      I1 => early2_match_rise1_r(5),
      I2 => early2_match_rise1_r(1),
      I3 => early2_match_rise1_r(4),
      O => \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0\,
      Q => early1_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_rise2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => early2_match_rise2_r(7),
      I1 => early2_match_rise2_r(6),
      I2 => early2_match_rise2_r(3),
      I3 => early2_match_rise2_r(2),
      I4 => \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_rise2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_rise2_r(0),
      I1 => early2_match_rise2_r(4),
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0\,
      Q => early1_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\,
      I1 => early2_match_rise3_r(5),
      I2 => early2_match_rise3_r(1),
      I3 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg\,
      I1 => early2_match_rise3_r(7),
      I2 => early2_match_rise3_r(3),
      I3 => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0\,
      Q => early1_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early2_match_rise3_and_r,
      I1 => early2_match_fall2_and_r,
      I2 => early2_match_fall1_and_r,
      I3 => early2_match_rise0_and_r,
      I4 => \gen_pat_match_div4.early2_data_match_r_i_2_n_0\,
      O => early2_data_match_r0
    );
\gen_pat_match_div4.early2_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early2_match_fall0_and_r,
      I1 => early2_match_rise2_and_r,
      I2 => early2_match_rise1_and_r,
      I3 => early2_match_fall3_and_r,
      O => \gen_pat_match_div4.early2_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => early2_data_match_r0,
      Q => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.early2_match_fall0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0\,
      I1 => early2_match_fall0_r(3),
      I2 => early2_match_fall0_r(1),
      I3 => early2_match_fall0_r(7),
      I4 => early2_match_fall0_r(5),
      O => \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_fall0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_fall0_r(4),
      I1 => early2_match_fall0_r(6),
      I2 => early2_match_fall0_r(0),
      I3 => early2_match_fall0_r(2),
      O => \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0\,
      Q => early2_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_fall1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => early2_match_fall1_r(4),
      I1 => early2_match_fall1_r(1),
      I2 => early2_match_fall1_r(5),
      I3 => early2_match_fall1_r(0),
      I4 => \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_fall1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_fall1_r(2),
      I1 => early2_match_fall1_r(7),
      I2 => early2_match_fall1_r(3),
      I3 => early2_match_fall1_r(6),
      O => \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0\,
      Q => early2_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early2_match_fall2_r(6),
      I1 => early2_match_fall2_r(1),
      I2 => early2_match_fall2_r(7),
      I3 => early2_match_fall2_r(0),
      I4 => \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early2_match_fall2_r(2),
      I1 => early2_match_fall2_r(5),
      I2 => early2_match_fall2_r(3),
      I3 => early2_match_fall2_r(4),
      O => \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0\,
      Q => early2_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => early2_match_fall3_r(7),
      I1 => early2_match_fall3_r(3),
      I2 => early2_match_fall3_r(5),
      I3 => early2_match_fall3_r(1),
      I4 => \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_fall3_r(0),
      I1 => early2_match_fall3_r(6),
      I2 => early2_match_fall3_r(4),
      I3 => early2_match_fall3_r(2),
      O => \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0\,
      Q => early2_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0\,
      I1 => early2_match_rise0_r(3),
      I2 => early2_match_rise0_r(1),
      I3 => early2_match_rise0_r(7),
      I4 => early2_match_rise0_r(5),
      O => \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_rise0_r(4),
      I1 => early2_match_rise0_r(6),
      I2 => early2_match_rise0_r(0),
      I3 => early2_match_rise0_r(2),
      O => \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0\,
      Q => early2_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => early2_match_rise1_r(4),
      I1 => early2_match_rise1_r(1),
      I2 => early2_match_rise1_r(5),
      I3 => early2_match_rise1_r(0),
      I4 => \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_rise1_r(2),
      I1 => early2_match_rise1_r(7),
      I2 => early2_match_rise1_r(3),
      I3 => early2_match_rise1_r(6),
      O => \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0\,
      Q => early2_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_rise2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0\,
      I1 => early2_match_rise2_r(4),
      I2 => early2_match_rise2_r(0),
      I3 => early2_match_rise2_r(5),
      I4 => early2_match_rise2_r(1),
      O => \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_rise2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => early2_match_rise2_r(2),
      I1 => early2_match_rise2_r(3),
      I2 => early2_match_rise2_r(6),
      I3 => early2_match_rise2_r(7),
      O => \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0\,
      Q => early2_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early2_match_rise3_r(6),
      I1 => early2_match_rise3_r(5),
      I2 => early2_match_rise3_r(7),
      I3 => early2_match_rise3_r(4),
      I4 => \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early2_match_rise3_r(0),
      I1 => early2_match_rise3_r(3),
      I2 => early2_match_rise3_r(1),
      I3 => early2_match_rise3_r(2),
      O => \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0\,
      Q => early2_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_219\,
      Q => early1_match_fall0_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_255\,
      O => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0\,
      Q => early2_match_fall1_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_211\,
      Q => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_247\,
      O => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0\,
      Q => early1_match_rise0_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_203\,
      Q => early2_match_rise1_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_233\,
      Q => early2_match_fall2_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_241\,
      O => \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0\,
      Q => early2_match_rise3_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_219\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0\,
      Q => early2_match_fall0_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_255\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_233\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_211\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0\,
      Q => early2_match_fall3_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_247\,
      Q => early2_match_rise0_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_203\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0\,
      Q => early2_match_rise2_r(0),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_241\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_256\,
      Q => early2_match_fall1_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_212\,
      O => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0\,
      Q => early2_match_fall3_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_204\,
      O => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0\,
      Q => early2_match_rise1_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_242\,
      Q => early2_match_rise3_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_220\,
      Q => early2_match_fall0_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_234\,
      O => \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0\,
      Q => early2_match_fall2_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_248\,
      O => \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0\,
      Q => early2_match_rise0_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_227\,
      Q => early2_match_rise2_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_220\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0\,
      Q => early1_match_fall0_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_256\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_234\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_212\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_248\,
      Q => early1_match_rise0_r(1),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_204\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_227\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_242\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_221\,
      Q => early1_match_fall0_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_257\,
      O => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_235\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_213\,
      O => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_249\,
      O => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0\,
      Q => early1_match_rise0_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_205\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_228\,
      O => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0\,
      Q => early2_match_rise2_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_243\,
      Q => early2_match_rise3_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_221\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0\,
      Q => early2_match_fall0_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_257\,
      Q => early2_match_fall1_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_235\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0\,
      Q => early2_match_fall2_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_213\,
      Q => early2_match_fall3_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_249\,
      Q => early2_match_rise0_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_205\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0\,
      Q => early2_match_rise1_r(2),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_228\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_243\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_258\,
      Q => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_236\,
      O => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0\,
      Q => early2_match_fall2_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_206\,
      O => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_229\,
      Q => early2_match_rise2_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_222\,
      Q => early2_match_fall0_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_250\,
      O => \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0\,
      Q => early2_match_rise0_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_222\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0\,
      Q => early1_match_fall0_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_258\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0\,
      Q => early2_match_fall1_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_236\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_214\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0\,
      Q => early2_match_fall3_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_250\,
      Q => early1_match_rise0_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_206\,
      Q => early2_match_rise1_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_229\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0\,
      Q => early2_match_rise3_r(3),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_223\,
      Q => early1_match_fall0_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_259\,
      O => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0\,
      Q => early2_match_fall1_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_215\,
      Q => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_251\,
      O => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0\,
      Q => early1_match_rise0_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_207\,
      Q => early2_match_rise1_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_237\,
      Q => early2_match_fall2_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_244\,
      O => \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0\,
      Q => early2_match_rise3_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_223\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0\,
      Q => early2_match_fall0_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_259\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_237\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_215\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0\,
      Q => early2_match_fall3_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_251\,
      Q => early2_match_rise0_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_207\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0\,
      Q => early2_match_rise2_r(4),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_244\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_260\,
      Q => early2_match_fall1_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_216\,
      O => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0\,
      Q => early2_match_fall3_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_208\,
      O => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0\,
      Q => early2_match_rise1_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_245\,
      Q => early2_match_rise3_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_224\,
      Q => early2_match_fall0_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_238\,
      O => \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0\,
      Q => early2_match_fall2_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_252\,
      O => \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0\,
      Q => early2_match_rise0_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_230\,
      Q => early2_match_rise2_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_224\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0\,
      Q => early1_match_fall0_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_260\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_238\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_216\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_252\,
      Q => early1_match_rise0_r(5),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_208\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_230\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_245\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_225\,
      Q => early1_match_fall0_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_261\,
      O => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_239\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_217\,
      O => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_253\,
      O => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0\,
      Q => early1_match_rise0_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_209\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_231\,
      O => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0\,
      Q => early2_match_rise2_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_246\,
      Q => early2_match_rise3_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_225\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0\,
      Q => early2_match_fall0_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_261\,
      Q => early2_match_fall1_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_239\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0\,
      Q => early2_match_fall2_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_217\,
      Q => early2_match_fall3_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_253\,
      Q => early2_match_rise0_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_209\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0\,
      Q => early2_match_rise1_r(6),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_231\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_246\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_262\,
      Q => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_240\,
      O => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0\,
      Q => early2_match_fall2_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_210\,
      O => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_232\,
      Q => early2_match_rise2_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_226\,
      Q => early2_match_fall0_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_254\,
      O => \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0\,
      Q => early2_match_rise0_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_226\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0\,
      Q => early1_match_fall0_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_262\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0\,
      Q => early2_match_fall1_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_240\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_218\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0\,
      Q => early2_match_fall3_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_254\,
      Q => early1_match_rise0_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_210\,
      Q => early2_match_rise1_r(7),
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_232\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0\,
      Q => early2_match_rise3_r(7),
      R => '0'
    );
\gen_pat_match_div4.pat_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pat_match_fall0_and_r,
      I1 => pat_match_rise2_and_r,
      I2 => pat_match_rise1_and_r,
      I3 => pat_match_fall1_and_r,
      I4 => \gen_pat_match_div4.pat_data_match_r_i_2_n_0\,
      O => pat_data_match_r0
    );
\gen_pat_match_div4.pat_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat_match_rise0_and_r,
      I1 => pat_match_rise3_and_r,
      I2 => pat_match_fall3_and_r,
      I3 => pat_match_fall2_and_r,
      O => \gen_pat_match_div4.pat_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.pat_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pat_data_match_r0,
      Q => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.pat_data_match_valid_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_active_r3_reg_srl2_n_0,
      Q => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.pat_match_fall0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early2_match_fall0_r(2),
      I1 => early2_match_fall0_r(0),
      I2 => early2_match_fall0_r(6),
      I3 => early2_match_fall0_r(4),
      I4 => \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0\,
      Q => pat_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_fall1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg\,
      O => \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0\,
      Q => pat_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg\,
      I3 => early2_match_fall2_r(6),
      I4 => early2_match_fall2_r(2),
      O => \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0\,
      Q => pat_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg\,
      I3 => early2_match_fall3_r(7),
      I4 => early2_match_fall3_r(3),
      O => \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0\,
      Q => pat_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early2_match_rise0_r(2),
      I1 => early2_match_rise0_r(0),
      I2 => early2_match_rise0_r(6),
      I3 => early2_match_rise0_r(4),
      I4 => \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0\,
      Q => pat_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg\,
      O => \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0\,
      Q => pat_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_rise2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg\,
      O => \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0\,
      Q => pat_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\,
      O => \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0\,
      Q => pat_match_rise3_and_r,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_219\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_255\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_233\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_211\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_247\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_203\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0]_0\,
      Q => \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0\
    );
\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_241\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_220\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_256\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_234\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_212\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_248\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_204\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_227\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_242\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_221\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_257\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_235\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_213\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_249\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_205\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_228\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_243\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_222\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_258\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_236\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_214\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_250\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_206\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_229\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]_0\,
      Q => \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0\
    );
\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_223\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_259\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_237\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_215\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_251\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_207\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4]_0\,
      Q => \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0\
    );
\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_244\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_224\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_260\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_238\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_216\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_252\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_208\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_230\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_245\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_225\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_261\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_239\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_217\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_253\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_209\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_231\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_246\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_226\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_262\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_240\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_218\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_254\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_210\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_232\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]_0\,
      Q => \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0\
    );
idelay_ld_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFDD00004000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[1]\,
      I1 => \cal2_state_r_reg_n_0_[0]\,
      I2 => idelay_ld_done_i_2_n_0,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => \cal2_state_r_reg_n_0_[3]\,
      I5 => idelay_ld_done_reg_n_0,
      O => idelay_ld_done_i_1_n_0
    );
idelay_ld_done_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(0),
      I1 => tap_inc_wait_cnt_reg(2),
      I2 => tap_inc_wait_cnt_reg(1),
      I3 => tap_inc_wait_cnt_reg(3),
      O => idelay_ld_done_i_2_n_0
    );
idelay_ld_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_ld_done_i_1_n_0,
      Q => idelay_ld_done_reg_n_0,
      R => wrcal_done_reg_1(0)
    );
idelay_ld_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => idelay_ld_i_2_n_0,
      I3 => idelay_ld,
      O => idelay_ld_i_1_n_0
    );
idelay_ld_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000054040000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r[2]_i_3_n_0\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => idelay_ld_done_i_2_n_0,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => \cal2_state_r_reg_n_0_[1]\,
      O => idelay_ld_i_2_n_0
    );
idelay_ld_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_ld_i_1_n_0,
      Q => idelay_ld,
      R => \wrcal_dqs_cnt_r_reg[1]_0\(0)
    );
\idelay_tap_cnt_r[0][0][4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => idelay_ce_int,
      I1 => idelay_ld,
      I2 => po_stg2_wrcal_cnt(1),
      O => cal1_dq_idel_ce_reg
    );
\idelay_tap_cnt_r[0][1][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0020FF20"
    )
        port map (
      I0 => idelay_ld,
      I1 => po_stg2_wrcal_cnt(1),
      I2 => \^po_stg2_wrcal_cnt_reg[0]_0\(0),
      I3 => idelay_ce_int,
      I4 => \idelay_tap_cnt_r_reg[0][1][4]\,
      I5 => \idelay_tap_cnt_r_reg[0][1][4]_0\,
      O => idelay_ld_reg_0(0)
    );
\input_[0].iserdes_dq_.idelay_dq.idelaye2_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF5400"
    )
        port map (
      I0 => calib_zero_inputs,
      I1 => \input_[9].iserdes_dq_.idelay_dq.idelaye2\,
      I2 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\,
      I3 => idelay_ld,
      I4 => idelay_ld_rst,
      O => LD0_0
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4050"
    )
        port map (
      I0 => calib_zero_inputs,
      I1 => \input_[9].iserdes_dq_.idelay_dq.idelaye2\,
      I2 => idelay_ld,
      I3 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\,
      I4 => idelay_ld_rst,
      O => LD0
    );
\not_empty_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[0]\,
      O => p_0_in(0)
    );
\not_empty_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[0]\,
      O => p_0_in(1)
    );
\not_empty_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[2]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[0]\,
      O => p_0_in(2)
    );
\not_empty_wait_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[3]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[0]\,
      I3 => \not_empty_wait_cnt_reg_n_0_[2]\,
      O => p_0_in(3)
    );
\not_empty_wait_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFFFFFFFFFF"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg[4]_0\,
      I1 => \cal2_state_r_reg_n_0_[3]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r_reg_n_0_[0]\,
      I4 => \cal2_state_r_reg_n_0_[1]\,
      I5 => wrcal_rd_wait,
      O => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[4]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[2]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[0]\,
      I3 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I4 => \not_empty_wait_cnt_reg_n_0_[3]\,
      O => p_0_in(4)
    );
\not_empty_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(0),
      Q => \not_empty_wait_cnt_reg_n_0_[0]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(1),
      Q => \not_empty_wait_cnt_reg_n_0_[1]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(2),
      Q => \not_empty_wait_cnt_reg_n_0_[2]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(3),
      Q => \not_empty_wait_cnt_reg_n_0_[3]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(4),
      Q => \not_empty_wait_cnt_reg_n_0_[4]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\po_stg2_wrcal_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      Q => \^po_stg2_wrcal_cnt_reg[0]_0\(0),
      R => '0'
    );
\po_stg2_wrcal_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_dqs_cnt_r(1),
      Q => po_stg2_wrcal_cnt(1),
      R => '0'
    );
rd_active_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^e\(0),
      Q => rd_active_r1,
      R => '0'
    );
rd_active_r3_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => rd_active_r1,
      Q => rd_active_r3_reg_srl2_n_0
    );
rd_active_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_rddata_en,
      Q => \^e\(0),
      R => '0'
    );
\tap_inc_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(0),
      O => \p_0_in__0\(0)
    );
\tap_inc_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(0),
      I1 => tap_inc_wait_cnt_reg(1),
      O => \p_0_in__0\(1)
    );
\tap_inc_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(1),
      I1 => tap_inc_wait_cnt_reg(0),
      I2 => tap_inc_wait_cnt_reg(2),
      O => \p_0_in__0\(2)
    );
\tap_inc_wait_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDDFD"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[2]\,
      I1 => \cal2_state_r_reg_n_0_[3]\,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => \cal2_state_r_reg_n_0_[0]\,
      I4 => \not_empty_wait_cnt_reg[4]_0\,
      O => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\tap_inc_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => tap_inc_wait_cnt_reg(3),
      I1 => tap_inc_wait_cnt_reg(1),
      I2 => tap_inc_wait_cnt_reg(2),
      I3 => tap_inc_wait_cnt_reg(0),
      O => \p_0_in__0\(3)
    );
\tap_inc_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => tap_inc_wait_cnt_reg(0),
      R => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\tap_inc_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => tap_inc_wait_cnt_reg(1),
      R => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\tap_inc_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => tap_inc_wait_cnt_reg(2),
      R => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\tap_inc_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => tap_inc_wait_cnt_reg(3),
      R => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
wrcal_done_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => cal2_done_r,
      I1 => \^wrcal_done_reg_0\,
      O => wrcal_done_i_1_n_0
    );
wrcal_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_done_i_1_n_0,
      Q => \^wrcal_done_reg_0\,
      R => wrcal_done_reg_1(0)
    );
\wrcal_dqs_cnt_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"34"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[2]\,
      I1 => \wrcal_dqs_cnt_r[1]_i_2_n_0\,
      I2 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      O => \wrcal_dqs_cnt_r[0]_i_1_n_0\
    );
\wrcal_dqs_cnt_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1F20"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => \wrcal_dqs_cnt_r[1]_i_2_n_0\,
      I3 => wrcal_dqs_cnt_r(1),
      O => \wrcal_dqs_cnt_r[1]_i_1_n_0\
    );
\wrcal_dqs_cnt_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => \wrcal_dqs_cnt_r[1]_i_3_n_0\,
      I3 => prech_done,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => \cal2_state_r_reg_n_0_[1]\,
      O => \wrcal_dqs_cnt_r[1]_i_2_n_0\
    );
\wrcal_dqs_cnt_r[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I1 => wrcal_dqs_cnt_r(1),
      O => \wrcal_dqs_cnt_r[1]_i_3_n_0\
    );
\wrcal_dqs_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wrcal_dqs_cnt_r[0]_i_1_n_0\,
      Q => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      R => \wrcal_dqs_cnt_r_reg[1]_0\(0)
    );
\wrcal_dqs_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wrcal_dqs_cnt_r[1]_i_1_n_0\,
      Q => wrcal_dqs_cnt_r(1),
      R => \wrcal_dqs_cnt_r_reg[1]_0\(0)
    );
wrcal_prech_req_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal2_prech_req_r,
      Q => wrcal_prech_req,
      R => wrcal_done_reg_1(0)
    );
wrlvl_byte_redo_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFF00000E00"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I2 => \cal2_state_r_reg_n_0_[3]\,
      I3 => wrlvl_byte_redo_i_2_n_0,
      I4 => \cal2_state_r_reg_n_0_[1]\,
      I5 => \^wrlvl_byte_redo\,
      O => wrlvl_byte_redo_i_1_n_0
    );
wrlvl_byte_redo_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000444000000000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[2]\,
      I1 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I2 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I3 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I4 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      I5 => \cal2_state_r_reg_n_0_[0]\,
      O => wrlvl_byte_redo_i_2_n_0
    );
wrlvl_byte_redo_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_byte_redo_i_1_n_0,
      Q => \^wrlvl_byte_redo\,
      R => wrcal_done_reg_1(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_phy_wrlvl_off_delay is
  port (
    delay_done_r4_reg_0 : out STD_LOGIC;
    po_delay_done_r4_reg_0 : out STD_LOGIC;
    po_en_s2_c_reg_0 : out STD_LOGIC;
    \calib_sel_reg[1]\ : out STD_LOGIC;
    po_en_s2_f : out STD_LOGIC;
    \calib_sel_reg[1]_0\ : out STD_LOGIC;
    po_en_s2_f_reg_0 : out STD_LOGIC;
    po_en_s2_c_reg_1 : out STD_LOGIC;
    RSTB : out STD_LOGIC;
    init_dqsfound_done_r_reg : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    calib_zero_ctrl : in STD_LOGIC;
    phaser_out : in STD_LOGIC;
    calib_zero_inputs : in STD_LOGIC;
    phaser_out_0 : in STD_LOGIC;
    ck_po_stg2_f_en : in STD_LOGIC;
    delay_done_reg_0 : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ : in STD_LOGIC;
    rd_data_offset_cal_done : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ : in STD_LOGIC;
    pi_dqs_found_done : in STD_LOGIC;
    pi_calib_done : in STD_LOGIC;
    pi_fine_dly_dec_done : in STD_LOGIC;
    \lane_cnt_po_r_reg[0]_0\ : in STD_LOGIC;
    po_en_stg2_f_reg_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_phy_wrlvl_off_delay : entity is "mig_7series_v4_2_ddr_phy_wrlvl_off_delay";
end mig_7series_0_mig_7series_v4_2_ddr_phy_wrlvl_off_delay;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_phy_wrlvl_off_delay is
  signal cmd_delay_start_r5_reg_srl5_n_0 : STD_LOGIC;
  signal cmd_delay_start_r6_reg_n_0 : STD_LOGIC;
  signal delay_cnt_r0 : STD_LOGIC;
  signal \delay_cnt_r0__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \delay_cnt_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \delay_cnt_r[5]_i_4_n_0\ : STD_LOGIC;
  signal delay_cnt_r_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal delay_done : STD_LOGIC;
  signal delay_done_i_1_n_0 : STD_LOGIC;
  signal delay_done_i_2_n_0 : STD_LOGIC;
  signal delay_done_r3_reg_srl3_n_0 : STD_LOGIC;
  signal \^delay_done_r4_reg_0\ : STD_LOGIC;
  signal \gen_byte_sel_div2.byte_sel_cnt[1]_i_4_n_0\ : STD_LOGIC;
  signal lane_cnt_dqs_c_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal lane_cnt_dqs_c_r0 : STD_LOGIC;
  signal \lane_cnt_dqs_c_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \lane_cnt_dqs_c_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \lane_cnt_dqs_c_r[1]_i_1_n_0\ : STD_LOGIC;
  signal lane_cnt_po_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal lane_cnt_po_r0 : STD_LOGIC;
  signal \lane_cnt_po_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \lane_cnt_po_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \lane_cnt_po_r[1]_i_1_n_0\ : STD_LOGIC;
  signal pi_fine_dly_dec_done_r : STD_LOGIC;
  signal po_delay_cnt_r0 : STD_LOGIC;
  signal \po_delay_cnt_r0__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \po_delay_cnt_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \po_delay_cnt_r[5]_i_4_n_0\ : STD_LOGIC;
  signal po_delay_cnt_r_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal po_delay_done : STD_LOGIC;
  signal po_delay_done_i_1_n_0 : STD_LOGIC;
  signal po_delay_done_i_2_n_0 : STD_LOGIC;
  signal po_delay_done_r3_reg_srl3_n_0 : STD_LOGIC;
  signal \^po_delay_done_r4_reg_0\ : STD_LOGIC;
  signal \^po_en_s2_f\ : STD_LOGIC;
  signal po_en_stg2_c : STD_LOGIC;
  signal po_en_stg2_c0 : STD_LOGIC;
  signal po_en_stg2_c_i_1_n_0 : STD_LOGIC;
  signal po_en_stg2_f : STD_LOGIC;
  signal po_en_stg2_f0 : STD_LOGIC;
  signal po_en_stg2_f_i_1_n_0 : STD_LOGIC;
  signal po_enstg2_c : STD_LOGIC_VECTOR ( 2 to 2 );
  attribute srl_name : string;
  attribute srl_name of cmd_delay_start_r5_reg_srl5 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_off.u_phy_wrlvl_off_delay/cmd_delay_start_r5_reg_srl5 ";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \delay_cnt_r[2]_i_1\ : label is "soft_lutpair218";
  attribute SOFT_HLUTNM of \delay_cnt_r[3]_i_1\ : label is "soft_lutpair215";
  attribute SOFT_HLUTNM of \delay_cnt_r[4]_i_1\ : label is "soft_lutpair215";
  attribute SOFT_HLUTNM of \delay_cnt_r[5]_i_4\ : label is "soft_lutpair214";
  attribute SOFT_HLUTNM of delay_done_i_2 : label is "soft_lutpair218";
  attribute srl_name of delay_done_r3_reg_srl3 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_off.u_phy_wrlvl_off_delay/delay_done_r3_reg_srl3 ";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[0]_i_3\ : label is "soft_lutpair212";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[1]_i_3\ : label is "soft_lutpair212";
  attribute SOFT_HLUTNM of \lane_cnt_dqs_c_r[1]_i_2\ : label is "soft_lutpair214";
  attribute SOFT_HLUTNM of \lane_cnt_po_r[1]_i_2\ : label is "soft_lutpair216";
  attribute SOFT_HLUTNM of \phaser_out_i_1__0\ : label is "soft_lutpair219";
  attribute SOFT_HLUTNM of \phaser_out_i_1__1\ : label is "soft_lutpair219";
  attribute SOFT_HLUTNM of phaser_out_i_2 : label is "soft_lutpair211";
  attribute SOFT_HLUTNM of \phaser_out_i_2__0\ : label is "soft_lutpair211";
  attribute SOFT_HLUTNM of \po_delay_cnt_r[2]_i_1\ : label is "soft_lutpair217";
  attribute SOFT_HLUTNM of \po_delay_cnt_r[3]_i_1\ : label is "soft_lutpair213";
  attribute SOFT_HLUTNM of \po_delay_cnt_r[4]_i_1\ : label is "soft_lutpair213";
  attribute SOFT_HLUTNM of \po_delay_cnt_r[5]_i_4\ : label is "soft_lutpair216";
  attribute SOFT_HLUTNM of po_delay_done_i_2 : label is "soft_lutpair217";
  attribute srl_name of po_delay_done_r3_reg_srl3 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_off.u_phy_wrlvl_off_delay/po_delay_done_r3_reg_srl3 ";
begin
  delay_done_r4_reg_0 <= \^delay_done_r4_reg_0\;
  po_delay_done_r4_reg_0 <= \^po_delay_done_r4_reg_0\;
  po_en_s2_f <= \^po_en_s2_f\;
cmd_delay_start_r5_reg_srl5: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '0',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => Q(0),
      Q => cmd_delay_start_r5_reg_srl5_n_0
    );
cmd_delay_start_r6_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cmd_delay_start_r5_reg_srl5_n_0,
      Q => cmd_delay_start_r6_reg_n_0,
      R => '0'
    );
\delay_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => delay_cnt_r_reg(0),
      O => \delay_cnt_r0__0\(0)
    );
\delay_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => delay_cnt_r_reg(1),
      I1 => delay_cnt_r_reg(0),
      O => \delay_cnt_r0__0\(1)
    );
\delay_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => delay_cnt_r_reg(2),
      I1 => delay_cnt_r_reg(0),
      I2 => delay_cnt_r_reg(1),
      O => \delay_cnt_r0__0\(2)
    );
\delay_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => delay_cnt_r_reg(3),
      I1 => delay_cnt_r_reg(1),
      I2 => delay_cnt_r_reg(0),
      I3 => delay_cnt_r_reg(2),
      O => \delay_cnt_r0__0\(3)
    );
\delay_cnt_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => delay_cnt_r_reg(1),
      I1 => delay_cnt_r_reg(0),
      I2 => delay_cnt_r_reg(2),
      I3 => delay_cnt_r_reg(3),
      I4 => delay_cnt_r_reg(4),
      O => \delay_cnt_r0__0\(4)
    );
\delay_cnt_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDDDDDDDDDDDF"
    )
        port map (
      I0 => pi_fine_dly_dec_done_r,
      I1 => delay_done_reg_0,
      I2 => delay_cnt_r_reg(4),
      I3 => delay_cnt_r_reg(3),
      I4 => delay_cnt_r_reg(5),
      I5 => \delay_cnt_r[5]_i_4_n_0\,
      O => \delay_cnt_r[5]_i_1_n_0\
    );
\delay_cnt_r[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => po_en_stg2_c,
      I1 => delay_cnt_r_reg(4),
      I2 => delay_cnt_r_reg(3),
      I3 => delay_cnt_r_reg(5),
      I4 => \delay_cnt_r[5]_i_4_n_0\,
      O => delay_cnt_r0
    );
\delay_cnt_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF00FF00FE01"
    )
        port map (
      I0 => delay_cnt_r_reg(2),
      I1 => delay_cnt_r_reg(0),
      I2 => delay_cnt_r_reg(1),
      I3 => delay_cnt_r_reg(5),
      I4 => delay_cnt_r_reg(3),
      I5 => delay_cnt_r_reg(4),
      O => \delay_cnt_r0__0\(5)
    );
\delay_cnt_r[5]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => delay_cnt_r_reg(1),
      I1 => delay_cnt_r_reg(0),
      I2 => delay_cnt_r_reg(2),
      O => \delay_cnt_r[5]_i_4_n_0\
    );
\delay_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => delay_cnt_r0,
      D => \delay_cnt_r0__0\(0),
      Q => delay_cnt_r_reg(0),
      R => \delay_cnt_r[5]_i_1_n_0\
    );
\delay_cnt_r_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => delay_cnt_r0,
      D => \delay_cnt_r0__0\(1),
      Q => delay_cnt_r_reg(1),
      S => \delay_cnt_r[5]_i_1_n_0\
    );
\delay_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => delay_cnt_r0,
      D => \delay_cnt_r0__0\(2),
      Q => delay_cnt_r_reg(2),
      R => \delay_cnt_r[5]_i_1_n_0\
    );
\delay_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => delay_cnt_r0,
      D => \delay_cnt_r0__0\(3),
      Q => delay_cnt_r_reg(3),
      R => \delay_cnt_r[5]_i_1_n_0\
    );
\delay_cnt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => delay_cnt_r0,
      D => \delay_cnt_r0__0\(4),
      Q => delay_cnt_r_reg(4),
      R => \delay_cnt_r[5]_i_1_n_0\
    );
\delay_cnt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => delay_cnt_r0,
      D => \delay_cnt_r0__0\(5),
      Q => delay_cnt_r_reg(5),
      R => \delay_cnt_r[5]_i_1_n_0\
    );
delay_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AE00"
    )
        port map (
      I0 => delay_done,
      I1 => delay_done_i_2_n_0,
      I2 => \lane_cnt_dqs_c_r[0]_i_2_n_0\,
      I3 => pi_fine_dly_dec_done_r,
      I4 => delay_done_reg_0,
      O => delay_done_i_1_n_0
    );
delay_done_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => lane_cnt_dqs_c_r(0),
      I1 => delay_cnt_r_reg(0),
      I2 => lane_cnt_dqs_c_r(1),
      I3 => delay_cnt_r_reg(2),
      I4 => delay_cnt_r_reg(1),
      O => delay_done_i_2_n_0
    );
delay_done_r3_reg_srl3: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => delay_done,
      Q => delay_done_r3_reg_srl3_n_0
    );
delay_done_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => delay_done_r3_reg_srl3_n_0,
      Q => \^delay_done_r4_reg_0\,
      R => '0'
    );
delay_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => delay_done_i_1_n_0,
      Q => delay_done,
      R => '0'
    );
\gen_byte_sel_div2.byte_sel_cnt[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AEFF"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt[1]_i_4_n_0\,
      I1 => rd_data_offset_cal_done,
      I2 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I3 => \^po_delay_done_r4_reg_0\,
      O => init_dqsfound_done_r_reg
    );
\gen_byte_sel_div2.byte_sel_cnt[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF75"
    )
        port map (
      I0 => \^po_delay_done_r4_reg_0\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I2 => rd_data_offset_cal_done,
      I3 => \gen_byte_sel_div2.byte_sel_cnt[1]_i_4_n_0\,
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]\,
      O => RSTB
    );
\gen_byte_sel_div2.byte_sel_cnt[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^delay_done_r4_reg_0\,
      I1 => pi_dqs_found_done,
      I2 => pi_calib_done,
      I3 => pi_fine_dly_dec_done,
      O => \gen_byte_sel_div2.byte_sel_cnt[1]_i_4_n_0\
    );
\lane_cnt_dqs_c_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEFFFFF00100000"
    )
        port map (
      I0 => \lane_cnt_dqs_c_r[0]_i_2_n_0\,
      I1 => delay_cnt_r_reg(1),
      I2 => delay_cnt_r_reg(0),
      I3 => delay_cnt_r_reg(2),
      I4 => po_en_stg2_c,
      I5 => lane_cnt_dqs_c_r(0),
      O => \lane_cnt_dqs_c_r[0]_i_1_n_0\
    );
\lane_cnt_dqs_c_r[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => delay_cnt_r_reg(4),
      I1 => delay_cnt_r_reg(3),
      I2 => delay_cnt_r_reg(5),
      O => \lane_cnt_dqs_c_r[0]_i_2_n_0\
    );
\lane_cnt_dqs_c_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => lane_cnt_dqs_c_r(0),
      I1 => lane_cnt_dqs_c_r0,
      I2 => lane_cnt_dqs_c_r(1),
      O => \lane_cnt_dqs_c_r[1]_i_1_n_0\
    );
\lane_cnt_dqs_c_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => po_en_stg2_c,
      I1 => delay_cnt_r_reg(2),
      I2 => delay_cnt_r_reg(0),
      I3 => delay_cnt_r_reg(1),
      I4 => \lane_cnt_dqs_c_r[0]_i_2_n_0\,
      O => lane_cnt_dqs_c_r0
    );
\lane_cnt_dqs_c_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \lane_cnt_dqs_c_r[0]_i_1_n_0\,
      Q => lane_cnt_dqs_c_r(0),
      R => \lane_cnt_po_r_reg[0]_0\
    );
\lane_cnt_dqs_c_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \lane_cnt_dqs_c_r[1]_i_1_n_0\,
      Q => lane_cnt_dqs_c_r(1),
      R => \lane_cnt_po_r_reg[0]_0\
    );
\lane_cnt_po_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEFFFFF00100000"
    )
        port map (
      I0 => \lane_cnt_po_r[0]_i_2_n_0\,
      I1 => po_delay_cnt_r_reg(1),
      I2 => po_delay_cnt_r_reg(0),
      I3 => po_delay_cnt_r_reg(2),
      I4 => po_en_stg2_f,
      I5 => lane_cnt_po_r(0),
      O => \lane_cnt_po_r[0]_i_1_n_0\
    );
\lane_cnt_po_r[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => po_delay_cnt_r_reg(4),
      I1 => po_delay_cnt_r_reg(3),
      I2 => po_delay_cnt_r_reg(5),
      O => \lane_cnt_po_r[0]_i_2_n_0\
    );
\lane_cnt_po_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => lane_cnt_po_r(0),
      I1 => lane_cnt_po_r0,
      I2 => lane_cnt_po_r(1),
      O => \lane_cnt_po_r[1]_i_1_n_0\
    );
\lane_cnt_po_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => po_en_stg2_f,
      I1 => po_delay_cnt_r_reg(2),
      I2 => po_delay_cnt_r_reg(0),
      I3 => po_delay_cnt_r_reg(1),
      I4 => \lane_cnt_po_r[0]_i_2_n_0\,
      O => lane_cnt_po_r0
    );
\lane_cnt_po_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \lane_cnt_po_r[0]_i_1_n_0\,
      Q => lane_cnt_po_r(0),
      R => \lane_cnt_po_r_reg[0]_0\
    );
\lane_cnt_po_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \lane_cnt_po_r[1]_i_1_n_0\,
      Q => lane_cnt_po_r(1),
      R => \lane_cnt_po_r_reg[0]_0\
    );
phaser_out_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => po_enstg2_c(2),
      I1 => calib_zero_ctrl,
      I2 => phaser_out,
      I3 => calib_zero_inputs,
      O => po_en_s2_c_reg_0
    );
\phaser_out_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C4"
    )
        port map (
      I0 => phaser_out_0,
      I1 => po_enstg2_c(2),
      I2 => phaser_out,
      I3 => calib_zero_inputs,
      O => \calib_sel_reg[1]_0\
    );
\phaser_out_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => po_enstg2_c(2),
      I1 => phaser_out_0,
      I2 => phaser_out,
      I3 => calib_zero_inputs,
      O => po_en_s2_c_reg_1
    );
phaser_out_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FC54"
    )
        port map (
      I0 => phaser_out_0,
      I1 => \^po_en_s2_f\,
      I2 => ck_po_stg2_f_en,
      I3 => phaser_out,
      I4 => calib_zero_inputs,
      O => \calib_sel_reg[1]\
    );
\phaser_out_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EEE0"
    )
        port map (
      I0 => \^po_en_s2_f\,
      I1 => ck_po_stg2_f_en,
      I2 => phaser_out_0,
      I3 => phaser_out,
      I4 => calib_zero_inputs,
      O => po_en_s2_f_reg_0
    );
pi_fine_dly_dec_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_fine_dly_dec_done,
      Q => pi_fine_dly_dec_done_r,
      R => '0'
    );
\po_delay_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => po_delay_cnt_r_reg(0),
      O => \po_delay_cnt_r0__0\(0)
    );
\po_delay_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => po_delay_cnt_r_reg(1),
      I1 => po_delay_cnt_r_reg(0),
      O => \po_delay_cnt_r0__0\(1)
    );
\po_delay_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => po_delay_cnt_r_reg(2),
      I1 => po_delay_cnt_r_reg(0),
      I2 => po_delay_cnt_r_reg(1),
      O => \po_delay_cnt_r0__0\(2)
    );
\po_delay_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => po_delay_cnt_r_reg(3),
      I1 => po_delay_cnt_r_reg(1),
      I2 => po_delay_cnt_r_reg(0),
      I3 => po_delay_cnt_r_reg(2),
      O => \po_delay_cnt_r0__0\(3)
    );
\po_delay_cnt_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => po_delay_cnt_r_reg(1),
      I1 => po_delay_cnt_r_reg(0),
      I2 => po_delay_cnt_r_reg(2),
      I3 => po_delay_cnt_r_reg(3),
      I4 => po_delay_cnt_r_reg(4),
      O => \po_delay_cnt_r0__0\(4)
    );
\po_delay_cnt_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDDDDDDDDDDDF"
    )
        port map (
      I0 => cmd_delay_start_r6_reg_n_0,
      I1 => delay_done_reg_0,
      I2 => po_delay_cnt_r_reg(4),
      I3 => po_delay_cnt_r_reg(3),
      I4 => po_delay_cnt_r_reg(5),
      I5 => \po_delay_cnt_r[5]_i_4_n_0\,
      O => \po_delay_cnt_r[5]_i_1_n_0\
    );
\po_delay_cnt_r[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => po_en_stg2_f,
      I1 => po_delay_cnt_r_reg(4),
      I2 => po_delay_cnt_r_reg(3),
      I3 => po_delay_cnt_r_reg(5),
      I4 => \po_delay_cnt_r[5]_i_4_n_0\,
      O => po_delay_cnt_r0
    );
\po_delay_cnt_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF00FF00FE01"
    )
        port map (
      I0 => po_delay_cnt_r_reg(2),
      I1 => po_delay_cnt_r_reg(0),
      I2 => po_delay_cnt_r_reg(1),
      I3 => po_delay_cnt_r_reg(5),
      I4 => po_delay_cnt_r_reg(3),
      I5 => po_delay_cnt_r_reg(4),
      O => \po_delay_cnt_r0__0\(5)
    );
\po_delay_cnt_r[5]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => po_delay_cnt_r_reg(1),
      I1 => po_delay_cnt_r_reg(0),
      I2 => po_delay_cnt_r_reg(2),
      O => \po_delay_cnt_r[5]_i_4_n_0\
    );
\po_delay_cnt_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => po_delay_cnt_r0,
      D => \po_delay_cnt_r0__0\(0),
      Q => po_delay_cnt_r_reg(0),
      S => \po_delay_cnt_r[5]_i_1_n_0\
    );
\po_delay_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => po_delay_cnt_r0,
      D => \po_delay_cnt_r0__0\(1),
      Q => po_delay_cnt_r_reg(1),
      R => \po_delay_cnt_r[5]_i_1_n_0\
    );
\po_delay_cnt_r_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => po_delay_cnt_r0,
      D => \po_delay_cnt_r0__0\(2),
      Q => po_delay_cnt_r_reg(2),
      S => \po_delay_cnt_r[5]_i_1_n_0\
    );
\po_delay_cnt_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => po_delay_cnt_r0,
      D => \po_delay_cnt_r0__0\(3),
      Q => po_delay_cnt_r_reg(3),
      S => \po_delay_cnt_r[5]_i_1_n_0\
    );
\po_delay_cnt_r_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => po_delay_cnt_r0,
      D => \po_delay_cnt_r0__0\(4),
      Q => po_delay_cnt_r_reg(4),
      S => \po_delay_cnt_r[5]_i_1_n_0\
    );
\po_delay_cnt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => po_delay_cnt_r0,
      D => \po_delay_cnt_r0__0\(5),
      Q => po_delay_cnt_r_reg(5),
      R => \po_delay_cnt_r[5]_i_1_n_0\
    );
po_delay_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AE00"
    )
        port map (
      I0 => po_delay_done,
      I1 => po_delay_done_i_2_n_0,
      I2 => \lane_cnt_po_r[0]_i_2_n_0\,
      I3 => cmd_delay_start_r6_reg_n_0,
      I4 => delay_done_reg_0,
      O => po_delay_done_i_1_n_0
    );
po_delay_done_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => lane_cnt_po_r(0),
      I1 => po_delay_cnt_r_reg(0),
      I2 => lane_cnt_po_r(1),
      I3 => po_delay_cnt_r_reg(2),
      I4 => po_delay_cnt_r_reg(1),
      O => po_delay_done_i_2_n_0
    );
po_delay_done_r3_reg_srl3: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => po_delay_done,
      Q => po_delay_done_r3_reg_srl3_n_0
    );
po_delay_done_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => po_delay_done_r3_reg_srl3_n_0,
      Q => \^po_delay_done_r4_reg_0\,
      R => '0'
    );
po_delay_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => po_delay_done_i_1_n_0,
      Q => po_delay_done,
      R => '0'
    );
po_en_s2_c_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => po_en_stg2_c,
      Q => po_enstg2_c(2),
      R => '0'
    );
po_en_s2_f_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => po_en_stg2_f,
      Q => \^po_en_s2_f\,
      R => '0'
    );
po_en_stg2_c_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001400"
    )
        port map (
      I0 => delay_done,
      I1 => po_en_stg2_c0,
      I2 => po_en_stg2_c,
      I3 => pi_fine_dly_dec_done_r,
      I4 => delay_done_reg_0,
      O => po_en_stg2_c_i_1_n_0
    );
po_en_stg2_c_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => delay_cnt_r_reg(2),
      I1 => delay_cnt_r_reg(0),
      I2 => delay_cnt_r_reg(1),
      I3 => delay_cnt_r_reg(5),
      I4 => delay_cnt_r_reg(3),
      I5 => delay_cnt_r_reg(4),
      O => po_en_stg2_c0
    );
po_en_stg2_c_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => po_en_stg2_c_i_1_n_0,
      Q => po_en_stg2_c,
      R => '0'
    );
po_en_stg2_f_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001400"
    )
        port map (
      I0 => po_delay_done,
      I1 => po_en_stg2_f0,
      I2 => po_en_stg2_f,
      I3 => cmd_delay_start_r6_reg_n_0,
      I4 => po_en_stg2_f_reg_0,
      O => po_en_stg2_f_i_1_n_0
    );
po_en_stg2_f_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => po_delay_cnt_r_reg(2),
      I1 => po_delay_cnt_r_reg(0),
      I2 => po_delay_cnt_r_reg(1),
      I3 => po_delay_cnt_r_reg(5),
      I4 => po_delay_cnt_r_reg(3),
      I5 => po_delay_cnt_r_reg(4),
      O => po_en_stg2_f0
    );
po_en_stg2_f_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => po_en_stg2_f_i_1_n_0,
      Q => po_en_stg2_f,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_infrastructure is
  port (
    \gen_mmcm.mmcm_i_i_1_0\ : out STD_LOGIC;
    CLK : out STD_LOGIC;
    freq_refclk : out STD_LOGIC;
    mem_refclk : out STD_LOGIC;
    sync_pulse : out STD_LOGIC;
    ui_clk_sync_rst : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    rstdiv0_sync_r1_reg_rep_0 : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__0_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__1_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__2_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__4_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__5_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__6_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__7_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__8_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__9_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__10_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__12_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__13_0\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__14_0\ : out STD_LOGIC;
    RST0 : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__14_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    pll_locked : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11_1\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11_2\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11_3\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11_4\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11_5\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11_6\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__12_1\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__12_2\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__13_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__13_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__13_3\ : out STD_LOGIC;
    SS : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__14_2\ : out STD_LOGIC;
    mmcm_clk : in STD_LOGIC;
    AS : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_tmp : in STD_LOGIC;
    device_temp_sync_r4_neq_r3 : in STD_LOGIC;
    bm_end_r1 : in STD_LOGIC;
    pass_open_bank_r : in STD_LOGIC;
    bm_end_r1_0 : in STD_LOGIC;
    pass_open_bank_r_1 : in STD_LOGIC;
    bm_end_r1_2 : in STD_LOGIC;
    pass_open_bank_r_3 : in STD_LOGIC;
    bm_end_r1_4 : in STD_LOGIC;
    pass_open_bank_r_5 : in STD_LOGIC;
    \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC;
    \cnt_shift_r_reg[0]\ : in STD_LOGIC;
    samp_edge_cnt0_en_r : in STD_LOGIC;
    pi_cnt_dec : in STD_LOGIC;
    prbs_rdlvl_done_pulse : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_infrastructure : entity is "mig_7series_v4_2_infrastructure";
end mig_7series_0_mig_7series_v4_2_infrastructure;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_infrastructure is
  signal \^clk\ : STD_LOGIC;
  signal RST0_0 : STD_LOGIC;
  signal clk_div2_bufg_in : STD_LOGIC;
  signal clk_pll_i : STD_LOGIC;
  signal \^gen_mmcm.mmcm_i_i_1_0\ : STD_LOGIC;
  signal \gen_mmcm.mmcm_i_n_17\ : STD_LOGIC;
  signal \gen_mmcm.u_bufg_clk_div2_n_0\ : STD_LOGIC;
  signal \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\ : STD_LOGIC;
  signal mmcm_ps_clk_bufg_in : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal pll_clk3 : STD_LOGIC;
  signal pll_clk3_out : STD_LOGIC;
  signal pll_clkfbout : STD_LOGIC;
  signal pll_locked_i : STD_LOGIC;
  signal rst_sync_r : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal rst_sync_r1 : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rst_sync_r1 : signal is "10";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rst_sync_r1 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rst_sync_r1 : signal is "10";
  signal rstdiv0_sync_r : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \^rstdiv0_sync_r1_reg_rep__11_0\ : STD_LOGIC;
  signal \^rstdiv0_sync_r1_reg_rep__12_0\ : STD_LOGIC;
  signal \^rstdiv0_sync_r1_reg_rep__13_0\ : STD_LOGIC;
  signal \^rstdiv0_sync_r1_reg_rep__14_0\ : STD_LOGIC;
  signal rstdiv2_sync_r1 : STD_LOGIC;
  attribute MAX_FANOUT of rstdiv2_sync_r1 : signal is "10";
  attribute RTL_MAX_FANOUT of rstdiv2_sync_r1 : signal is "found";
  attribute syn_maxfan of rstdiv2_sync_r1 : signal is "10";
  signal \rstdiv2_sync_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[10]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \rstdiv2_sync_r_reg_n_0_[9]\ : STD_LOGIC;
  signal \^ui_clk_sync_rst\ : STD_LOGIC;
  attribute MAX_FANOUT of ui_clk_sync_rst : signal is "50";
  attribute RTL_MAX_FANOUT of ui_clk_sync_rst : signal is "found";
  attribute syn_maxfan of ui_clk_sync_rst : signal is "50";
  signal \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_plle2_i_CLKOUT4_UNCONNECTED : STD_LOGIC;
  signal NLW_plle2_i_CLKOUT5_UNCONNECTED : STD_LOGIC;
  signal NLW_plle2_i_DRDY_UNCONNECTED : STD_LOGIC;
  signal NLW_plle2_i_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of act_wait_r_lcl_i_3 : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \act_wait_r_lcl_i_3__0\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \act_wait_r_lcl_i_3__1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \act_wait_r_lcl_i_3__2\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \cnt_shift_r[3]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of complex_row0_rd_done_i_2 : label is "soft_lutpair5";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \gen_mmcm.mmcm_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_mmcm.u_bufg_clk_div2\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_mmcm.u_bufg_mmcm_ps_clk\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of phaser_ref_i_i_1 : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of phy_control_i_i_1 : label is "soft_lutpair9";
  attribute BOX_TYPE of plle2_i : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of ras_timer_zero_r_i_3 : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \ras_timer_zero_r_i_3__0\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \ras_timer_zero_r_i_3__1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \ras_timer_zero_r_i_3__2\ : label is "soft_lutpair4";
  attribute RTL_MAX_FANOUT of rst_sync_r1_reg : label is "found";
  attribute syn_maxfan of rst_sync_r1_reg : label is "10";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of rstdiv0_sync_r1_reg : label is "rstdiv0_sync_r1_reg";
  attribute RTL_MAX_FANOUT of rstdiv0_sync_r1_reg : label is "found";
  attribute syn_maxfan of rstdiv0_sync_r1_reg : label is "50";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of rstdiv0_sync_r1_reg_rep : label is 1;
  attribute ORIG_CELL_NAME of rstdiv0_sync_r1_reg_rep : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__0\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__0\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__1\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__1\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__10\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__10\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__11\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__11\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__12\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__12\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__13\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__13\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__14\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__14\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__2\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__2\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__3\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__3\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__4\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__4\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__5\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__5\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__6\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__6\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__7\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__7\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__8\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__8\ : label is "rstdiv0_sync_r1_reg";
  attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__9\ : label is 1;
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__9\ : label is "rstdiv0_sync_r1_reg";
  attribute RTL_MAX_FANOUT of rstdiv2_sync_r1_reg : label is "found";
  attribute syn_maxfan of rstdiv2_sync_r1_reg : label is "10";
  attribute SOFT_HLUTNM of \samp_edge_cnt0_r[0]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \sync_cntr[3]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[5]_i_1\ : label is "soft_lutpair6";
  attribute BOX_TYPE of u_bufg_clkdiv0 : label is "PRIMITIVE";
  attribute BOX_TYPE of u_bufh_pll_clk3 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \wait_cnt_r[3]_i_1\ : label is "soft_lutpair7";
begin
  CLK <= \^clk\;
  SR(0) <= \^ui_clk_sync_rst\;
  \gen_mmcm.mmcm_i_i_1_0\ <= \^gen_mmcm.mmcm_i_i_1_0\;
  \rstdiv0_sync_r1_reg_rep__11_0\ <= \^rstdiv0_sync_r1_reg_rep__11_0\;
  \rstdiv0_sync_r1_reg_rep__12_0\ <= \^rstdiv0_sync_r1_reg_rep__12_0\;
  \rstdiv0_sync_r1_reg_rep__13_0\ <= \^rstdiv0_sync_r1_reg_rep__13_0\;
  \rstdiv0_sync_r1_reg_rep__14_0\ <= \^rstdiv0_sync_r1_reg_rep__14_0\;
  ui_clk_sync_rst <= \^ui_clk_sync_rst\;
act_wait_r_lcl_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      I1 => pass_open_bank_r,
      O => \rstdiv0_sync_r1_reg_rep__11_2\
    );
\act_wait_r_lcl_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      I1 => pass_open_bank_r_1,
      O => \rstdiv0_sync_r1_reg_rep__11_4\
    );
\act_wait_r_lcl_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      I1 => pass_open_bank_r_3,
      O => \rstdiv0_sync_r1_reg_rep__11_6\
    );
\act_wait_r_lcl_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__12_0\,
      I1 => pass_open_bank_r_5,
      O => \rstdiv0_sync_r1_reg_rep__12_2\
    );
\cnt_shift_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__13_0\,
      I1 => \cnt_shift_r_reg[0]\,
      O => \rstdiv0_sync_r1_reg_rep__13_2\(0)
    );
complex_row0_rd_done_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__14_0\,
      I1 => prbs_rdlvl_done_pulse,
      O => \rstdiv0_sync_r1_reg_rep__14_2\
    );
\gen_mmcm.mmcm_i\: unisim.vcomponents.MMCME2_ADV
    generic map(
      BANDWIDTH => "HIGH",
      CLKFBOUT_MULT_F => 15.000000,
      CLKFBOUT_PHASE => 0.000000,
      CLKFBOUT_USE_FINE_PS => false,
      CLKIN1_PERIOD => 13.328000,
      CLKIN2_PERIOD => 0.000000,
      CLKOUT0_DIVIDE_F => 30.000000,
      CLKOUT0_DUTY_CYCLE => 0.500000,
      CLKOUT0_PHASE => 0.000000,
      CLKOUT0_USE_FINE_PS => true,
      CLKOUT1_DIVIDE => 7,
      CLKOUT1_DUTY_CYCLE => 0.500000,
      CLKOUT1_PHASE => 0.000000,
      CLKOUT1_USE_FINE_PS => false,
      CLKOUT2_DIVIDE => 1,
      CLKOUT2_DUTY_CYCLE => 0.500000,
      CLKOUT2_PHASE => 0.000000,
      CLKOUT2_USE_FINE_PS => false,
      CLKOUT3_DIVIDE => 1,
      CLKOUT3_DUTY_CYCLE => 0.500000,
      CLKOUT3_PHASE => 0.000000,
      CLKOUT3_USE_FINE_PS => false,
      CLKOUT4_CASCADE => false,
      CLKOUT4_DIVIDE => 1,
      CLKOUT4_DUTY_CYCLE => 0.500000,
      CLKOUT4_PHASE => 0.000000,
      CLKOUT4_USE_FINE_PS => false,
      CLKOUT5_DIVIDE => 1,
      CLKOUT5_DUTY_CYCLE => 0.500000,
      CLKOUT5_PHASE => 0.000000,
      CLKOUT5_USE_FINE_PS => false,
      CLKOUT6_DIVIDE => 1,
      CLKOUT6_DUTY_CYCLE => 0.500000,
      CLKOUT6_PHASE => 0.000000,
      CLKOUT6_USE_FINE_PS => false,
      COMPENSATION => "BUF_IN",
      DIVCLK_DIVIDE => 1,
      IS_CLKINSEL_INVERTED => '0',
      IS_PSEN_INVERTED => '0',
      IS_PSINCDEC_INVERTED => '0',
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REF_JITTER1 => 0.000000,
      REF_JITTER2 => 0.010000,
      SS_EN => "FALSE",
      SS_MODE => "CENTER_HIGH",
      SS_MOD_PERIOD => 10000,
      STARTUP_WAIT => false
    )
        port map (
      CLKFBIN => \^clk\,
      CLKFBOUT => clk_pll_i,
      CLKFBOUTB => \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED\,
      CLKFBSTOPPED => \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED\,
      CLKIN1 => pll_clk3,
      CLKIN2 => '0',
      CLKINSEL => '1',
      CLKINSTOPPED => \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED\,
      CLKOUT0 => mmcm_ps_clk_bufg_in,
      CLKOUT0B => \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED\,
      CLKOUT1 => clk_div2_bufg_in,
      CLKOUT1B => \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED\,
      CLKOUT2 => \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED\,
      CLKOUT2B => \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED\,
      CLKOUT3 => \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED\,
      CLKOUT3B => \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED\,
      CLKOUT4 => \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED\,
      CLKOUT5 => \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED\,
      CLKOUT6 => \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED\,
      DADDR(6 downto 0) => B"0000000",
      DCLK => '0',
      DEN => '0',
      DI(15 downto 0) => B"0000000000000000",
      DO(15 downto 0) => \NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED\(15 downto 0),
      DRDY => \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED\,
      DWE => '0',
      LOCKED => \^gen_mmcm.mmcm_i_i_1_0\,
      PSCLK => \^clk\,
      PSDONE => \gen_mmcm.mmcm_i_n_17\,
      PSEN => '0',
      PSINCDEC => '0',
      PWRDWN => '0',
      RST => RST0_0
    );
\gen_mmcm.mmcm_i_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pll_locked_i,
      O => RST0_0
    );
\gen_mmcm.u_bufg_clk_div2\: unisim.vcomponents.BUFG
     port map (
      I => clk_div2_bufg_in,
      O => \gen_mmcm.u_bufg_clk_div2_n_0\
    );
\gen_mmcm.u_bufg_mmcm_ps_clk\: unisim.vcomponents.BUFG
     port map (
      I => mmcm_ps_clk_bufg_in,
      O => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\
    );
phaser_ref_i_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^gen_mmcm.mmcm_i_i_1_0\,
      I1 => pll_locked_i,
      O => RST0
    );
phy_control_i_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => pll_locked_i,
      I1 => \^gen_mmcm.mmcm_i_i_1_0\,
      O => pll_locked
    );
plle2_i: unisim.vcomponents.PLLE2_ADV
    generic map(
      BANDWIDTH => "OPTIMIZED",
      CLKFBOUT_MULT => 4,
      CLKFBOUT_PHASE => 0.000000,
      CLKIN1_PERIOD => 3.333000,
      CLKIN2_PERIOD => 0.000000,
      CLKOUT0_DIVIDE => 2,
      CLKOUT0_DUTY_CYCLE => 0.500000,
      CLKOUT0_PHASE => 0.000000,
      CLKOUT1_DIVIDE => 4,
      CLKOUT1_DUTY_CYCLE => 0.500000,
      CLKOUT1_PHASE => 0.000000,
      CLKOUT2_DIVIDE => 64,
      CLKOUT2_DUTY_CYCLE => 0.062500,
      CLKOUT2_PHASE => 9.843750,
      CLKOUT3_DIVIDE => 16,
      CLKOUT3_DUTY_CYCLE => 0.500000,
      CLKOUT3_PHASE => 0.000000,
      CLKOUT4_DIVIDE => 8,
      CLKOUT4_DUTY_CYCLE => 0.500000,
      CLKOUT4_PHASE => 168.750000,
      CLKOUT5_DIVIDE => 1,
      CLKOUT5_DUTY_CYCLE => 0.500000,
      CLKOUT5_PHASE => 0.000000,
      COMPENSATION => "INTERNAL",
      DIVCLK_DIVIDE => 1,
      IS_CLKINSEL_INVERTED => '0',
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REF_JITTER1 => 0.010000,
      REF_JITTER2 => 0.010000,
      STARTUP_WAIT => "FALSE"
    )
        port map (
      CLKFBIN => pll_clkfbout,
      CLKFBOUT => pll_clkfbout,
      CLKIN1 => mmcm_clk,
      CLKIN2 => '0',
      CLKINSEL => '1',
      CLKOUT0 => freq_refclk,
      CLKOUT1 => mem_refclk,
      CLKOUT2 => sync_pulse,
      CLKOUT3 => pll_clk3_out,
      CLKOUT4 => NLW_plle2_i_CLKOUT4_UNCONNECTED,
      CLKOUT5 => NLW_plle2_i_CLKOUT5_UNCONNECTED,
      DADDR(6 downto 0) => B"0000000",
      DCLK => '0',
      DEN => '0',
      DI(15 downto 0) => B"0000000000000000",
      DO(15 downto 0) => NLW_plle2_i_DO_UNCONNECTED(15 downto 0),
      DRDY => NLW_plle2_i_DRDY_UNCONNECTED,
      DWE => '0',
      LOCKED => pll_locked_i,
      PWRDWN => '0',
      RST => AS(0)
    );
ras_timer_zero_r_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      I1 => bm_end_r1,
      O => \rstdiv0_sync_r1_reg_rep__11_1\
    );
\ras_timer_zero_r_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      I1 => bm_end_r1_0,
      O => \rstdiv0_sync_r1_reg_rep__11_3\
    );
\ras_timer_zero_r_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__11_0\,
      I1 => bm_end_r1_2,
      O => \rstdiv0_sync_r1_reg_rep__11_5\
    );
\ras_timer_zero_r_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__12_0\,
      I1 => bm_end_r1_4,
      O => \rstdiv0_sync_r1_reg_rep__12_1\
    );
rst_sync_r1_reg: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(11),
      PRE => rst_tmp,
      Q => rst_sync_r1
    );
\rst_sync_r_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => '0',
      PRE => rst_tmp,
      Q => rst_sync_r(0)
    );
\rst_sync_r_reg[10]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(9),
      PRE => rst_tmp,
      Q => rst_sync_r(10)
    );
\rst_sync_r_reg[11]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(10),
      PRE => rst_tmp,
      Q => rst_sync_r(11)
    );
\rst_sync_r_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(0),
      PRE => rst_tmp,
      Q => rst_sync_r(1)
    );
\rst_sync_r_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(1),
      PRE => rst_tmp,
      Q => rst_sync_r(2)
    );
\rst_sync_r_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(2),
      PRE => rst_tmp,
      Q => rst_sync_r(3)
    );
\rst_sync_r_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(3),
      PRE => rst_tmp,
      Q => rst_sync_r(4)
    );
\rst_sync_r_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(4),
      PRE => rst_tmp,
      Q => rst_sync_r(5)
    );
\rst_sync_r_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(5),
      PRE => rst_tmp,
      Q => rst_sync_r(6)
    );
\rst_sync_r_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(6),
      PRE => rst_tmp,
      Q => rst_sync_r(7)
    );
\rst_sync_r_reg[8]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(7),
      PRE => rst_tmp,
      Q => rst_sync_r(8)
    );
\rst_sync_r_reg[9]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(8),
      PRE => rst_tmp,
      Q => rst_sync_r(9)
    );
rstdiv0_sync_r1_reg: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \^ui_clk_sync_rst\
    );
rstdiv0_sync_r1_reg_rep: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r1_reg_rep_0
    );
\rstdiv0_sync_r1_reg_rep__0\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__0_0\
    );
\rstdiv0_sync_r1_reg_rep__1\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__1_0\(0)
    );
\rstdiv0_sync_r1_reg_rep__10\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__10_0\
    );
\rstdiv0_sync_r1_reg_rep__11\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \^rstdiv0_sync_r1_reg_rep__11_0\
    );
\rstdiv0_sync_r1_reg_rep__12\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \^rstdiv0_sync_r1_reg_rep__12_0\
    );
\rstdiv0_sync_r1_reg_rep__13\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \^rstdiv0_sync_r1_reg_rep__13_0\
    );
\rstdiv0_sync_r1_reg_rep__14\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \^rstdiv0_sync_r1_reg_rep__14_0\
    );
\rstdiv0_sync_r1_reg_rep__2\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__2_0\
    );
\rstdiv0_sync_r1_reg_rep__3\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__4_0\(0)
    );
\rstdiv0_sync_r1_reg_rep__4\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__4_0\(1)
    );
\rstdiv0_sync_r1_reg_rep__5\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__5_0\
    );
\rstdiv0_sync_r1_reg_rep__6\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__6_0\(0)
    );
\rstdiv0_sync_r1_reg_rep__7\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__7_0\(0)
    );
\rstdiv0_sync_r1_reg_rep__8\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__8_0\
    );
\rstdiv0_sync_r1_reg_rep__9\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => rst_tmp,
      Q => \rstdiv0_sync_r1_reg_rep__9_0\
    );
\rstdiv0_sync_r_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => '0',
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(0)
    );
\rstdiv0_sync_r_reg[10]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(9),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(10)
    );
\rstdiv0_sync_r_reg[11]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(10),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(11)
    );
\rstdiv0_sync_r_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(0),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(1)
    );
\rstdiv0_sync_r_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(1),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(2)
    );
\rstdiv0_sync_r_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(2),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(3)
    );
\rstdiv0_sync_r_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(3),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(4)
    );
\rstdiv0_sync_r_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(4),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(5)
    );
\rstdiv0_sync_r_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(5),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(6)
    );
\rstdiv0_sync_r_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(6),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(7)
    );
\rstdiv0_sync_r_reg[8]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(7),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(8)
    );
\rstdiv0_sync_r_reg[9]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(8),
      PRE => rst_tmp,
      Q => rstdiv0_sync_r(9)
    );
rstdiv2_sync_r1_reg: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => p_0_in,
      PRE => rst_tmp,
      Q => rstdiv2_sync_r1
    );
\rstdiv2_sync_r_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => '0',
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[0]\
    );
\rstdiv2_sync_r_reg[10]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[9]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[10]\
    );
\rstdiv2_sync_r_reg[11]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[10]\,
      PRE => rst_tmp,
      Q => p_0_in
    );
\rstdiv2_sync_r_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[0]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[1]\
    );
\rstdiv2_sync_r_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[1]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[2]\
    );
\rstdiv2_sync_r_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[2]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[3]\
    );
\rstdiv2_sync_r_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[3]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[4]\
    );
\rstdiv2_sync_r_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[4]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[5]\
    );
\rstdiv2_sync_r_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[5]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[6]\
    );
\rstdiv2_sync_r_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[6]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[7]\
    );
\rstdiv2_sync_r_reg[8]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[7]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[8]\
    );
\rstdiv2_sync_r_reg[9]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_clk_div2_n_0\,
      CE => '1',
      D => \rstdiv2_sync_r_reg_n_0_[8]\,
      PRE => rst_tmp,
      Q => \rstdiv2_sync_r_reg_n_0_[9]\
    );
\samp_edge_cnt0_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__13_0\,
      I1 => samp_edge_cnt0_en_r,
      O => \rstdiv0_sync_r1_reg_rep__13_3\
    );
\sync_cntr[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__14_0\,
      I1 => device_temp_sync_r4_neq_r3,
      O => \rstdiv0_sync_r1_reg_rep__14_1\(0)
    );
\tap_cnt_cpt_r[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__13_0\,
      I1 => \tap_cnt_cpt_r_reg[5]\,
      O => \rstdiv0_sync_r1_reg_rep__13_1\(0)
    );
u_bufg_clkdiv0: unisim.vcomponents.BUFG
     port map (
      I => clk_pll_i,
      O => \^clk\
    );
u_bufh_pll_clk3: unisim.vcomponents.BUFH
     port map (
      I => pll_clk3_out,
      O => pll_clk3
    );
\wait_cnt_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rstdiv0_sync_r1_reg_rep__13_0\,
      I1 => pi_cnt_dec,
      O => SS(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_iodelay_ctrl is
  port (
    rst_tmp : out STD_LOGIC;
    AS : out STD_LOGIC_VECTOR ( 0 to 0 );
    mmcm_clk : in STD_LOGIC;
    sys_rst : in STD_LOGIC;
    \rstdiv2_sync_r_reg[11]\ : in STD_LOGIC;
    ref_dll_lock : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_iodelay_ctrl : entity is "mig_7series_v4_2_iodelay_ctrl";
end mig_7series_0_mig_7series_v4_2_iodelay_ctrl;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_iodelay_ctrl is
  signal \^as\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal iodelay_ctrl_rdy : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rst_ref : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rst_ref_sync_r_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][10]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][11]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][12]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][13]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][3]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][5]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][6]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][7]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][8]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][9]\ : STD_LOGIC;
  signal sys_rst_i : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of sys_rst_i : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][0]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][10]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][11]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][12]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][13]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][14]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][1]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][2]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][3]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][4]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][5]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][6]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][7]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][8]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][9]\ : label is "10";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_idelayctrl_200 : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of u_idelayctrl_200 : label is "MIG_7SERIES_0_IODELAY_MIG0";
begin
  AS(0) <= \^as\(0);
  sys_rst_i <= sys_rst;
plle2_i_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sys_rst_i,
      O => \^as\(0)
    );
\rst_ref_sync_r_reg[0][0]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => '0',
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][0]\
    );
\rst_ref_sync_r_reg[0][10]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][9]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][10]\
    );
\rst_ref_sync_r_reg[0][11]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][10]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][11]\
    );
\rst_ref_sync_r_reg[0][12]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][11]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][12]\
    );
\rst_ref_sync_r_reg[0][13]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][12]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][13]\
    );
\rst_ref_sync_r_reg[0][14]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][13]\,
      PRE => \^as\(0),
      Q => rst_ref(0)
    );
\rst_ref_sync_r_reg[0][1]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][0]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][1]\
    );
\rst_ref_sync_r_reg[0][2]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][1]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][2]\
    );
\rst_ref_sync_r_reg[0][3]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][2]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][3]\
    );
\rst_ref_sync_r_reg[0][4]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][3]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][4]\
    );
\rst_ref_sync_r_reg[0][5]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][4]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][5]\
    );
\rst_ref_sync_r_reg[0][6]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][5]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][6]\
    );
\rst_ref_sync_r_reg[0][7]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][6]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][7]\
    );
\rst_ref_sync_r_reg[0][8]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][7]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][8]\
    );
\rst_ref_sync_r_reg[0][9]\: unisim.vcomponents.FDPE
     port map (
      C => mmcm_clk,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][8]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][9]\
    );
\rstdiv2_sync_r[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \rstdiv2_sync_r_reg[11]\,
      I1 => iodelay_ctrl_rdy(0),
      I2 => sys_rst_i,
      I3 => ref_dll_lock,
      O => rst_tmp
    );
u_idelayctrl_200: unisim.vcomponents.IDELAYCTRL
    generic map(
      SIM_DEVICE => "7SERIES"
    )
        port map (
      RDY => iodelay_ctrl_rdy(0),
      REFCLK => mmcm_clk,
      RST => rst_ref(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_rank_cntrl is
  port (
    inhbt_act_faw_r : out STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r\ : out STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r\ : out STD_LOGIC;
    \refresh_generation.refresh_bank_r\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__9\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    \wtr_timer.wtr_cnt_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    act_this_rank : in STD_LOGIC;
    CLK : in STD_LOGIC;
    \periodic_rd_generation.read_this_rank\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r_reg_1\ : in STD_LOGIC;
    \refresh_generation.refresh_bank_r_reg[0]_0\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r_reg_0\ : in STD_LOGIC;
    insert_maint_r1 : in STD_LOGIC;
    maint_wip_r : in STD_LOGIC;
    maint_ref_zq_wip : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r_reg_1\ : in STD_LOGIC;
    \inhbt_act_faw.faw_cnt_r_reg[0]_0\ : in STD_LOGIC;
    \inhbt_act_faw.faw_cnt_r_reg[0]_1\ : in STD_LOGIC;
    \rtw_timer.rtw_cnt_r_reg[0]_0\ : in STD_LOGIC;
    \rtw_timer.rtw_cnt_r_reg[1]_0\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]_0\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]_1\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]_2\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]_1\ : in STD_LOGIC;
    maint_prescaler_tick_r : in STD_LOGIC;
    \periodic_read_request.periodic_rd_grant_r\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r_reg_2\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_rank_cntrl : entity is "mig_7series_v4_2_rank_cntrl";
end mig_7series_0_mig_7series_v4_2_rank_cntrl;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_rank_cntrl is
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \inhbt_act_faw.act_delayed\ : STD_LOGIC;
  signal \inhbt_act_faw.faw_cnt_ns\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \inhbt_act_faw.faw_cnt_r\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0\ : STD_LOGIC;
  signal \^periodic_rd_generation.periodic_rd_cntr1_r\ : STD_LOGIC;
  signal \^periodic_rd_generation.periodic_rd_request_r\ : STD_LOGIC;
  signal \periodic_rd_generation.periodic_rd_request_r_i_1_n_0\ : STD_LOGIC;
  signal \periodic_rd_generation.periodic_rd_request_r_i_2_n_0\ : STD_LOGIC;
  signal \periodic_rd_generation.periodic_rd_request_r_i_3_n_0\ : STD_LOGIC;
  signal \periodic_rd_generation.periodic_rd_timer_ns\ : STD_LOGIC;
  signal \periodic_rd_generation.periodic_rd_timer_r\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \periodic_rd_generation.read_this_rank_r\ : STD_LOGIC;
  signal \^refresh_generation.refresh_bank_r\ : STD_LOGIC;
  signal \rtw_timer.rtw_cnt_ns\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rtw_timer.rtw_cnt_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \wtr_timer.wtr_cnt_ns\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wtr_timer.wtr_cnt_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^wtr_timer.wtr_cnt_r_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_inhbt_act_faw.SRLC32E0_Q31_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \inhbt_act_faw.SRLC32E0\ : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \inhbt_act_faw.SRLC32E0\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl ";
  attribute srl_name : string;
  attribute srl_name of \inhbt_act_faw.SRLC32E0\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/inhbt_act_faw.SRLC32E0 ";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \periodic_rd_generation.periodic_rd_request_r_i_2\ : label is "soft_lutpair599";
  attribute SOFT_HLUTNM of \periodic_rd_generation.periodic_rd_timer_r[0]_i_1\ : label is "soft_lutpair599";
  attribute SOFT_HLUTNM of \periodic_rd_generation.periodic_rd_timer_r[1]_i_1\ : label is "soft_lutpair598";
  attribute SOFT_HLUTNM of \periodic_rd_generation.periodic_rd_timer_r[2]_i_1\ : label is "soft_lutpair598";
  attribute SOFT_HLUTNM of \rtw_timer.rtw_cnt_r[0]_i_1\ : label is "soft_lutpair600";
  attribute SOFT_HLUTNM of \rtw_timer.rtw_cnt_r[1]_i_1\ : label is "soft_lutpair600";
begin
  Q(0) <= \^q\(0);
  \periodic_rd_generation.periodic_rd_cntr1_r\ <= \^periodic_rd_generation.periodic_rd_cntr1_r\;
  \periodic_rd_generation.periodic_rd_request_r\ <= \^periodic_rd_generation.periodic_rd_request_r\;
  \refresh_generation.refresh_bank_r\ <= \^refresh_generation.refresh_bank_r\;
  \wtr_timer.wtr_cnt_r_reg[1]_0\(0) <= \^wtr_timer.wtr_cnt_r_reg[1]_0\(0);
\inhbt_act_faw.SRLC32E0\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"00001",
      CE => '1',
      CLK => CLK,
      D => act_this_rank,
      Q => \inhbt_act_faw.act_delayed\,
      Q31 => \NLW_inhbt_act_faw.SRLC32E0_Q31_UNCONNECTED\
    );
\inhbt_act_faw.faw_cnt_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0069"
    )
        port map (
      I0 => \inhbt_act_faw.act_delayed\,
      I1 => \inhbt_act_faw.faw_cnt_r_reg[0]_0\,
      I2 => \inhbt_act_faw.faw_cnt_r\(0),
      I3 => \inhbt_act_faw.faw_cnt_r_reg[0]_1\,
      O => \inhbt_act_faw.faw_cnt_ns\(0)
    );
\inhbt_act_faw.faw_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000E178"
    )
        port map (
      I0 => \inhbt_act_faw.faw_cnt_r_reg[0]_0\,
      I1 => \inhbt_act_faw.act_delayed\,
      I2 => \inhbt_act_faw.faw_cnt_r\(1),
      I3 => \inhbt_act_faw.faw_cnt_r\(0),
      I4 => \wtr_timer.wtr_cnt_r_reg[0]_0\,
      O => \inhbt_act_faw.faw_cnt_ns\(1)
    );
\inhbt_act_faw.faw_cnt_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EFF71008"
    )
        port map (
      I0 => \inhbt_act_faw.act_delayed\,
      I1 => \inhbt_act_faw.faw_cnt_r_reg[0]_0\,
      I2 => \inhbt_act_faw.faw_cnt_r\(0),
      I3 => \inhbt_act_faw.faw_cnt_r\(1),
      I4 => \inhbt_act_faw.faw_cnt_r\(2),
      I5 => \wtr_timer.wtr_cnt_r_reg[0]_0\,
      O => \inhbt_act_faw.faw_cnt_ns\(2)
    );
\inhbt_act_faw.faw_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \inhbt_act_faw.faw_cnt_ns\(0),
      Q => \inhbt_act_faw.faw_cnt_r\(0),
      R => '0'
    );
\inhbt_act_faw.faw_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \inhbt_act_faw.faw_cnt_ns\(1),
      Q => \inhbt_act_faw.faw_cnt_r\(1),
      R => '0'
    );
\inhbt_act_faw.faw_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \inhbt_act_faw.faw_cnt_ns\(2),
      Q => \inhbt_act_faw.faw_cnt_r\(2),
      R => '0'
    );
\inhbt_act_faw.inhbt_act_faw_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400000400041000"
    )
        port map (
      I0 => \wtr_timer.wtr_cnt_r_reg[0]_0\,
      I1 => \inhbt_act_faw.faw_cnt_r\(2),
      I2 => \inhbt_act_faw.faw_cnt_r\(1),
      I3 => \inhbt_act_faw.faw_cnt_r\(0),
      I4 => \inhbt_act_faw.faw_cnt_r_reg[0]_0\,
      I5 => \inhbt_act_faw.act_delayed\,
      O => \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0\
    );
\inhbt_act_faw.inhbt_act_faw_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0\,
      Q => inhbt_act_faw_r,
      R => '0'
    );
maint_ref_zq_wip_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF202020"
    )
        port map (
      I0 => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      I1 => \^refresh_generation.refresh_bank_r\,
      I2 => insert_maint_r1,
      I3 => maint_wip_r,
      I4 => maint_ref_zq_wip,
      O => \init_calib_complete_reg_rep__9\
    );
\periodic_rd_generation.periodic_rd_cntr1_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_cntr1_r_reg_1\,
      Q => \^periodic_rd_generation.periodic_rd_cntr1_r\,
      R => \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\
    );
\periodic_rd_generation.periodic_rd_request_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F7F7F733"
    )
        port map (
      I0 => \periodic_rd_generation.read_this_rank_r\,
      I1 => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      I2 => \periodic_rd_generation.periodic_rd_request_r_reg_1\,
      I3 => \^periodic_rd_generation.periodic_rd_request_r\,
      I4 => \periodic_rd_generation.periodic_rd_request_r_i_2_n_0\,
      I5 => \periodic_rd_generation.periodic_rd_request_r_i_3_n_0\,
      O => \periodic_rd_generation.periodic_rd_request_r_i_1_n_0\
    );
\periodic_rd_generation.periodic_rd_request_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \periodic_rd_generation.periodic_rd_timer_r\(1),
      I1 => \periodic_rd_generation.periodic_rd_timer_r\(0),
      I2 => \periodic_rd_generation.periodic_rd_timer_r\(2),
      I3 => maint_prescaler_tick_r,
      O => \periodic_rd_generation.periodic_rd_request_r_i_2_n_0\
    );
\periodic_rd_generation.periodic_rd_request_r_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^periodic_rd_generation.periodic_rd_cntr1_r\,
      I1 => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      I2 => \periodic_read_request.periodic_rd_grant_r\,
      I3 => \periodic_rd_generation.periodic_rd_request_r_reg_2\,
      O => \periodic_rd_generation.periodic_rd_request_r_i_3_n_0\
    );
\periodic_rd_generation.periodic_rd_request_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_request_r_i_1_n_0\,
      Q => \^periodic_rd_generation.periodic_rd_request_r\,
      R => \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\
    );
\periodic_rd_generation.periodic_rd_timer_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF54AA"
    )
        port map (
      I0 => \periodic_rd_generation.periodic_rd_timer_r\(0),
      I1 => \periodic_rd_generation.periodic_rd_timer_r\(1),
      I2 => \periodic_rd_generation.periodic_rd_timer_r\(2),
      I3 => maint_prescaler_tick_r,
      I4 => \periodic_rd_generation.periodic_rd_timer_ns\,
      O => \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0\
    );
\periodic_rd_generation.periodic_rd_timer_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F508"
    )
        port map (
      I0 => maint_prescaler_tick_r,
      I1 => \periodic_rd_generation.periodic_rd_timer_r\(2),
      I2 => \periodic_rd_generation.periodic_rd_timer_r\(0),
      I3 => \periodic_rd_generation.periodic_rd_timer_r\(1),
      I4 => \periodic_rd_generation.periodic_rd_timer_ns\,
      O => \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0\
    );
\periodic_rd_generation.periodic_rd_timer_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFCCC4"
    )
        port map (
      I0 => maint_prescaler_tick_r,
      I1 => \periodic_rd_generation.periodic_rd_timer_r\(2),
      I2 => \periodic_rd_generation.periodic_rd_timer_r\(0),
      I3 => \periodic_rd_generation.periodic_rd_timer_r\(1),
      I4 => \periodic_rd_generation.periodic_rd_timer_ns\,
      O => \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0\
    );
\periodic_rd_generation.periodic_rd_timer_r[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFDD"
    )
        port map (
      I0 => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      I1 => \periodic_rd_generation.periodic_rd_request_r_i_2_n_0\,
      I2 => \periodic_rd_generation.periodic_rd_request_r_reg_1\,
      I3 => \periodic_rd_generation.read_this_rank_r\,
      O => \periodic_rd_generation.periodic_rd_timer_ns\
    );
\periodic_rd_generation.periodic_rd_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0\,
      Q => \periodic_rd_generation.periodic_rd_timer_r\(0),
      R => '0'
    );
\periodic_rd_generation.periodic_rd_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0\,
      Q => \periodic_rd_generation.periodic_rd_timer_r\(1),
      R => '0'
    );
\periodic_rd_generation.periodic_rd_timer_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0\,
      Q => \periodic_rd_generation.periodic_rd_timer_r\(2),
      R => '0'
    );
\periodic_rd_generation.read_this_rank_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_rd_generation.read_this_rank\,
      Q => \periodic_rd_generation.read_this_rank_r\,
      R => '0'
    );
\refresh_generation.refresh_bank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \refresh_generation.refresh_bank_r_reg[0]_0\,
      Q => \^refresh_generation.refresh_bank_r\,
      R => '0'
    );
\rtw_timer.rtw_cnt_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \rtw_timer.rtw_cnt_r\(0),
      I1 => \^q\(0),
      I2 => \rtw_timer.rtw_cnt_r_reg[0]_0\,
      I3 => \rtw_timer.rtw_cnt_r_reg[1]_0\,
      O => \rtw_timer.rtw_cnt_ns\(0)
    );
\rtw_timer.rtw_cnt_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \rtw_timer.rtw_cnt_r\(0),
      I2 => \rtw_timer.rtw_cnt_r_reg[1]_0\,
      I3 => \rtw_timer.rtw_cnt_r_reg[0]_0\,
      O => \rtw_timer.rtw_cnt_ns\(1)
    );
\rtw_timer.rtw_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtw_timer.rtw_cnt_ns\(0),
      Q => \rtw_timer.rtw_cnt_r\(0),
      R => '0'
    );
\rtw_timer.rtw_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtw_timer.rtw_cnt_ns\(1),
      Q => \^q\(0),
      R => '0'
    );
\wtr_timer.wtr_cnt_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00040000"
    )
        port map (
      I0 => \wtr_timer.wtr_cnt_r\(0),
      I1 => \^wtr_timer.wtr_cnt_r_reg[1]_0\(0),
      I2 => \wtr_timer.wtr_cnt_r_reg[0]_0\,
      I3 => \wtr_timer.wtr_cnt_r_reg[0]_1\,
      I4 => \wtr_timer.wtr_cnt_r_reg[0]_2\,
      O => \wtr_timer.wtr_cnt_ns\(0)
    );
\wtr_timer.wtr_cnt_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D5"
    )
        port map (
      I0 => \wtr_timer.wtr_cnt_r_reg[1]_1\,
      I1 => \^wtr_timer.wtr_cnt_r_reg[1]_0\(0),
      I2 => \wtr_timer.wtr_cnt_r\(0),
      I3 => \wtr_timer.wtr_cnt_r_reg[0]_0\,
      O => \wtr_timer.wtr_cnt_ns\(1)
    );
\wtr_timer.wtr_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wtr_timer.wtr_cnt_ns\(0),
      Q => \wtr_timer.wtr_cnt_r\(0),
      R => '0'
    );
\wtr_timer.wtr_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wtr_timer.wtr_cnt_ns\(1),
      Q => \^wtr_timer.wtr_cnt_r_reg[1]_0\(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_round_robin_arb is
  port (
    \maintenance_request.maint_rank_r_lcl_reg[0]\ : out STD_LOGIC;
    \maintenance_request.maint_sre_ns\ : out STD_LOGIC;
    \maintenance_request.maint_srx_ns\ : out STD_LOGIC;
    \maintenance_request.maint_rank_r_lcl_reg[0]_0\ : in STD_LOGIC;
    \last_master_r_reg[2]_0\ : in STD_LOGIC;
    \maintenance_request.maint_rank_r_lcl_reg[0]_1\ : in STD_LOGIC;
    \maintenance_request.maint_srx_r_lcl_reg\ : in STD_LOGIC;
    \maintenance_request.maint_srx_r_lcl_reg_0\ : in STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg\ : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    \sr_cntrl.ckesr_timer.ckesr_timer_r\ : in STD_LOGIC;
    \sr_cntrl.sre_request_logic.sre_request_r\ : in STD_LOGIC;
    \grant_r_reg[0]_0\ : in STD_LOGIC;
    \refresh_generation.refresh_bank_r\ : in STD_LOGIC;
    \maintenance_request.new_maint_rank_r\ : in STD_LOGIC;
    \maintenance_request.upd_last_master_r\ : in STD_LOGIC;
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_round_robin_arb : entity is "mig_7series_v4_2_round_robin_arb";
end mig_7series_0_mig_7series_v4_2_round_robin_arb;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_round_robin_arb is
  signal \grant_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \grant_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_3_n_0\ : STD_LOGIC;
  signal last_master_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \last_master_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \last_master_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \last_master_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \maintenance_request.maint_grant_r\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \maintenance_request.maint_rank_r_lcl[0]_i_2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \grant_r[0]_i_2\ : label is "soft_lutpair601";
  attribute SOFT_HLUTNM of \grant_r[2]_i_2\ : label is "soft_lutpair602";
  attribute SOFT_HLUTNM of \last_master_r[0]_i_1\ : label is "soft_lutpair601";
  attribute SOFT_HLUTNM of \last_master_r[2]_i_1\ : label is "soft_lutpair602";
begin
\grant_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000015FF0000"
    )
        port map (
      I0 => \last_master_r[0]_i_1_n_0\,
      I1 => last_master_r(1),
      I2 => \grant_r[0]_i_2_n_0\,
      I3 => \sr_cntrl.sre_request_logic.sre_request_r\,
      I4 => \grant_r_reg[0]_0\,
      I5 => \refresh_generation.refresh_bank_r\,
      O => \grant_r[0]_i_1_n_0\
    );
\grant_r[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => \maintenance_request.new_maint_rank_r\,
      I2 => \maintenance_request.upd_last_master_r\,
      O => \grant_r[0]_i_2_n_0\
    );
\grant_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF015100000000"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => last_master_r(2),
      I2 => \grant_r[2]_i_2_n_0\,
      I3 => \maintenance_request.maint_grant_r\(2),
      I4 => \refresh_generation.refresh_bank_r\,
      I5 => \grant_r[2]_i_3_n_0\,
      O => \grant_r[2]_i_1_n_0\
    );
\grant_r[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \maintenance_request.upd_last_master_r\,
      I1 => \maintenance_request.new_maint_rank_r\,
      O => \grant_r[2]_i_2_n_0\
    );
\grant_r[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sr_cntrl.sre_request_logic.sre_request_r\,
      I1 => \grant_r_reg[0]_0\,
      O => \grant_r[2]_i_3_n_0\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[0]_i_1_n_0\,
      Q => \maintenance_request.maint_grant_r\(0),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[2]_i_1_n_0\,
      Q => \maintenance_request.maint_grant_r\(2),
      R => '0'
    );
\last_master_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0C0A0C0C"
    )
        port map (
      I0 => \maintenance_request.maint_grant_r\(0),
      I1 => last_master_r(0),
      I2 => \last_master_r_reg[2]_0\,
      I3 => \maintenance_request.new_maint_rank_r\,
      I4 => \maintenance_request.upd_last_master_r\,
      O => \last_master_r[0]_i_1_n_0\
    );
\last_master_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0D00"
    )
        port map (
      I0 => \maintenance_request.upd_last_master_r\,
      I1 => \maintenance_request.new_maint_rank_r\,
      I2 => \last_master_r_reg[2]_0\,
      I3 => last_master_r(1),
      O => \last_master_r[1]_i_1_n_0\
    );
\last_master_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEFEEEAE"
    )
        port map (
      I0 => \last_master_r_reg[2]_0\,
      I1 => last_master_r(2),
      I2 => \maintenance_request.upd_last_master_r\,
      I3 => \maintenance_request.new_maint_rank_r\,
      I4 => \maintenance_request.maint_grant_r\(2),
      O => \last_master_r[2]_i_1_n_0\
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[0]_i_1_n_0\,
      Q => last_master_r(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[1]_i_1_n_0\,
      Q => last_master_r(1),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[2]_i_1_n_0\,
      Q => last_master_r(2),
      R => '0'
    );
\maintenance_request.maint_rank_r_lcl[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000202020002"
    )
        port map (
      I0 => \maintenance_request.maint_rank_r_lcl_reg[0]_0\,
      I1 => \maintenance_request.maint_rank_r_lcl[0]_i_2_n_0\,
      I2 => \last_master_r_reg[2]_0\,
      I3 => \maintenance_request.maint_rank_r_lcl_reg[0]_1\,
      I4 => \grant_r[2]_i_2_n_0\,
      I5 => \maintenance_request.maint_grant_r\(0),
      O => \maintenance_request.maint_rank_r_lcl_reg[0]\
    );
\maintenance_request.maint_rank_r_lcl[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFA0000C0FA"
    )
        port map (
      I0 => \maintenance_request.maint_srx_r_lcl_reg\,
      I1 => \maintenance_request.maint_srx_r_lcl_reg_0\,
      I2 => \maintenance_request.maint_sre_r_lcl_reg\,
      I3 => \grant_r[2]_i_2_n_0\,
      I4 => \last_master_r_reg[2]_0\,
      I5 => \maintenance_request.maint_grant_r\(2),
      O => \maintenance_request.maint_rank_r_lcl[0]_i_2_n_0\
    );
\maintenance_request.maint_sre_r_lcl_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2320232023202020"
    )
        port map (
      I0 => \maintenance_request.maint_grant_r\(2),
      I1 => \last_master_r_reg[2]_0\,
      I2 => \grant_r[2]_i_2_n_0\,
      I3 => \maintenance_request.maint_sre_r_lcl_reg\,
      I4 => app_sr_req,
      I5 => \sr_cntrl.ckesr_timer.ckesr_timer_r\,
      O => \maintenance_request.maint_sre_ns\
    );
\maintenance_request.maint_srx_r_lcl_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AA00AA00F30000"
    )
        port map (
      I0 => \maintenance_request.maint_srx_r_lcl_reg_0\,
      I1 => \grant_r[2]_i_2_n_0\,
      I2 => \maintenance_request.maint_grant_r\(2),
      I3 => \last_master_r_reg[2]_0\,
      I4 => \maintenance_request.maint_srx_r_lcl_reg\,
      I5 => \maintenance_request.maint_sre_r_lcl_reg\,
      O => \maintenance_request.maint_srx_ns\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    col_wait_r_reg : out STD_LOGIC;
    rd_wr_r_lcl_reg : out STD_LOGIC;
    granted_col_r_reg : out STD_LOGIC;
    granted_col_r_reg_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_odt_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \periodic_rd_generation.read_this_rank\ : out STD_LOGIC;
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    granted_col_r_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    rd_wr_r_lcl_reg_1 : out STD_LOGIC;
    rd_wr_r_lcl_reg_2 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_aux_out0_1 : out STD_LOGIC;
    col_rd_wr : out STD_LOGIC;
    DIC : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    col_wr_data_buf_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \genblk3[2].rnk_config_strobe_r_reg[2]\ : out STD_LOGIC;
    \grant_r_reg[3]_1\ : out STD_LOGIC;
    \wr_this_rank_r_reg[0]\ : out STD_LOGIC;
    \grant_r_reg[0]_0\ : out STD_LOGIC;
    \grant_r_reg[1]_0\ : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    \grant_r_reg[2]_0\ : out STD_LOGIC;
    \grant_r_reg[1]_1\ : out STD_LOGIC;
    \grant_r_reg[3]_2\ : out STD_LOGIC;
    \grant_r_reg[0]_1\ : out STD_LOGIC;
    rd_wr_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \col_mux.col_periodic_rd_r\ : in STD_LOGIC;
    \col_mux.col_periodic_rd_r_reg\ : in STD_LOGIC;
    granted_col_r_reg_2 : in STD_LOGIC;
    col_wait_r : in STD_LOGIC;
    \grant_r_reg[0]_2\ : in STD_LOGIC;
    \grant_r_reg[0]_3\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_odt_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_odt_reg[0]_0\ : in STD_LOGIC;
    rd_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \grant_r_reg[1]_2\ : in STD_LOGIC;
    \grant_r_reg[2]_1\ : in STD_LOGIC;
    \grant_r_reg[1]_3\ : in STD_LOGIC;
    col_wait_r_0 : in STD_LOGIC;
    \grant_r[1]_i_3\ : in STD_LOGIC;
    \grant_r[1]_i_3_0\ : in STD_LOGIC;
    \grant_r[3]_i_2\ : in STD_LOGIC;
    \grant_r[3]_i_2_0\ : in STD_LOGIC;
    granted_col_r_reg_3 : in STD_LOGIC;
    granted_col_r_reg_4 : in STD_LOGIC;
    granted_col_r_reg_5 : in STD_LOGIC;
    granted_col_r_reg_6 : in STD_LOGIC;
    granted_col_r_reg_7 : in STD_LOGIC;
    granted_col_r_reg_8 : in STD_LOGIC;
    granted_col_r_reg_9 : in STD_LOGIC;
    \grant_r[3]_i_5_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr_r : in STD_LOGIC;
    req_periodic_rd_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_address_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[9]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    auto_pre_r : in STD_LOGIC;
    auto_pre_r_1 : in STD_LOGIC;
    auto_pre_r_2 : in STD_LOGIC;
    auto_pre_r_3 : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    req_data_buf_addr_r : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rnk_config_strobe_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rnk_config_strobe : in STD_LOGIC;
    wr_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \last_master_r_reg[0]_0\ : in STD_LOGIC;
    demand_priority_r : in STD_LOGIC;
    override_demand_r : in STD_LOGIC;
    demand_priority_r_7 : in STD_LOGIC;
    demanded_prior_r : in STD_LOGIC;
    demanded_prior_r_8 : in STD_LOGIC;
    demanded_prior_r_9 : in STD_LOGIC;
    demand_priority_r_10 : in STD_LOGIC;
    demanded_prior_r_11 : in STD_LOGIC;
    demand_priority_r_12 : in STD_LOGIC;
    ofs_rdy_r : in STD_LOGIC;
    ofs_rdy_r_13 : in STD_LOGIC;
    ofs_rdy_r_14 : in STD_LOGIC;
    ofs_rdy_r_15 : in STD_LOGIC;
    \grant_r[3]_i_5_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r[3]_i_8_0\ : in STD_LOGIC;
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1\ : entity is "mig_7series_v4_2_round_robin_arb";
end \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \cmd_pipe_plus.mc_address[0]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[10]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[10]_i_3_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[1]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[2]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[3]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[4]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[5]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[6]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[7]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[8]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[9]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[0]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[1]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[2]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_odt[0]_i_2_n_0\ : STD_LOGIC;
  signal \col_mux.col_periodic_rd_r_i_2_n_0\ : STD_LOGIC;
  signal \col_mux.col_periodic_rd_r_i_3_n_0\ : STD_LOGIC;
  signal \col_mux.col_rd_wr_r_i_3_n_0\ : STD_LOGIC;
  signal \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \grant_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \grant_r[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_3__2_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_11__0_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_15__0_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_17_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_18_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_4__2_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \^grant_r_reg[0]_0\ : STD_LOGIC;
  signal \^grant_r_reg[1]_0\ : STD_LOGIC;
  signal \^grant_r_reg[3]_0\ : STD_LOGIC;
  signal granted_col_r_i_6_n_0 : STD_LOGIC;
  signal granted_col_r_i_8_n_0 : STD_LOGIC;
  signal last_master_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \last_master_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \last_master_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \last_master_r[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \last_master_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \periodic_rd_generation.read_this_rank_r_i_3_n_0\ : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \^rd_wr_r_lcl_reg_1\ : STD_LOGIC;
  signal \^wr_this_rank_r_reg[0]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[10]_i_2\ : label is "soft_lutpair526";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_aux_out0[1]_i_1\ : label is "soft_lutpair538";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_cmd[1]_i_1\ : label is "soft_lutpair534";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset[1]_i_1\ : label is "soft_lutpair537";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset[2]_i_1\ : label is "soft_lutpair537";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset[5]_i_1\ : label is "soft_lutpair536";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_odt[0]_i_1\ : label is "soft_lutpair538";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_ras_n[0]_i_1\ : label is "soft_lutpair526";
  attribute SOFT_HLUTNM of \col_mux.col_rd_wr_r_i_2\ : label is "soft_lutpair528";
  attribute SOFT_HLUTNM of \grant_r[2]_i_3__2\ : label is "soft_lutpair531";
  attribute SOFT_HLUTNM of \grant_r[2]_i_5__0\ : label is "soft_lutpair535";
  attribute SOFT_HLUTNM of \grant_r[3]_i_11__0\ : label is "soft_lutpair525";
  attribute SOFT_HLUTNM of \grant_r[3]_i_18\ : label is "soft_lutpair528";
  attribute SOFT_HLUTNM of \grant_r[3]_i_19\ : label is "soft_lutpair530";
  attribute SOFT_HLUTNM of \grant_r[3]_i_23\ : label is "soft_lutpair535";
  attribute SOFT_HLUTNM of \grant_r[3]_i_24\ : label is "soft_lutpair532";
  attribute SOFT_HLUTNM of \grant_r[3]_i_9\ : label is "soft_lutpair527";
  attribute SOFT_HLUTNM of granted_col_r_i_11 : label is "soft_lutpair533";
  attribute SOFT_HLUTNM of granted_col_r_i_6 : label is "soft_lutpair525";
  attribute SOFT_HLUTNM of granted_col_r_i_8 : label is "soft_lutpair527";
  attribute SOFT_HLUTNM of \last_master_r[0]_i_1__0\ : label is "soft_lutpair532";
  attribute SOFT_HLUTNM of \last_master_r[1]_i_1__0\ : label is "soft_lutpair534";
  attribute SOFT_HLUTNM of \last_master_r[2]_i_1__0\ : label is "soft_lutpair536";
  attribute SOFT_HLUTNM of \last_master_r[3]_i_1\ : label is "soft_lutpair531";
  attribute SOFT_HLUTNM of \periodic_rd_generation.read_this_rank_r_i_3\ : label is "soft_lutpair530";
  attribute SOFT_HLUTNM of \wtr_timer.wtr_cnt_r[0]_i_2\ : label is "soft_lutpair533";
  attribute SOFT_HLUTNM of \wtr_timer.wtr_cnt_r[0]_i_3\ : label is "soft_lutpair529";
  attribute SOFT_HLUTNM of \wtr_timer.wtr_cnt_r[1]_i_2\ : label is "soft_lutpair529";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  \grant_r_reg[0]_0\ <= \^grant_r_reg[0]_0\;
  \grant_r_reg[1]_0\ <= \^grant_r_reg[1]_0\;
  \grant_r_reg[3]_0\ <= \^grant_r_reg[3]_0\;
  rd_wr_r_lcl_reg <= \^rd_wr_r_lcl_reg\;
  rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\;
  rd_wr_r_lcl_reg_1 <= \^rd_wr_r_lcl_reg_1\;
  \wr_this_rank_r_reg[0]\ <= \^wr_this_rank_r_reg[0]\;
\cmd_pipe_plus.mc_address[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[9]\(0),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[9]_0\(0),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_address[0]_i_2_n_0\,
      O => auto_pre_r_lcl_reg(0)
    );
\cmd_pipe_plus.mc_address[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[9]_1\(0),
      I1 => \cmd_pipe_plus.mc_address_reg[9]_2\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_address[0]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => auto_pre_r,
      I2 => \^q\(3),
      I3 => auto_pre_r_1,
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_address[10]_i_3_n_0\,
      O => auto_pre_r_lcl_reg(10)
    );
\cmd_pipe_plus.mc_address[10]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[10]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[10]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => auto_pre_r_2,
      I1 => auto_pre_r_3,
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_address[10]_i_3_n_0\
    );
\cmd_pipe_plus.mc_address[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[9]\(1),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[9]_0\(1),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_address[1]_i_2_n_0\,
      O => auto_pre_r_lcl_reg(1)
    );
\cmd_pipe_plus.mc_address[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[9]_1\(1),
      I1 => \cmd_pipe_plus.mc_address_reg[9]_2\(1),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_address[1]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[9]\(2),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[9]_0\(2),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_address[2]_i_2_n_0\,
      O => auto_pre_r_lcl_reg(2)
    );
\cmd_pipe_plus.mc_address[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[9]_1\(2),
      I1 => \cmd_pipe_plus.mc_address_reg[9]_2\(2),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_address[2]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[9]\(3),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[9]_0\(3),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_address[3]_i_2_n_0\,
      O => auto_pre_r_lcl_reg(3)
    );
\cmd_pipe_plus.mc_address[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[9]_1\(3),
      I1 => \cmd_pipe_plus.mc_address_reg[9]_2\(3),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_address[3]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[9]\(4),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[9]_0\(4),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_address[4]_i_2_n_0\,
      O => auto_pre_r_lcl_reg(4)
    );
\cmd_pipe_plus.mc_address[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[9]_1\(4),
      I1 => \cmd_pipe_plus.mc_address_reg[9]_2\(4),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_address[4]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[9]\(5),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[9]_0\(5),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_address[5]_i_2_n_0\,
      O => auto_pre_r_lcl_reg(5)
    );
\cmd_pipe_plus.mc_address[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[9]_1\(5),
      I1 => \cmd_pipe_plus.mc_address_reg[9]_2\(5),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_address[5]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[9]\(6),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[9]_0\(6),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_address[6]_i_2_n_0\,
      O => auto_pre_r_lcl_reg(6)
    );
\cmd_pipe_plus.mc_address[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[9]_1\(6),
      I1 => \cmd_pipe_plus.mc_address_reg[9]_2\(6),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_address[6]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[9]\(7),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[9]_0\(7),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_address[7]_i_2_n_0\,
      O => auto_pre_r_lcl_reg(7)
    );
\cmd_pipe_plus.mc_address[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[9]_1\(7),
      I1 => \cmd_pipe_plus.mc_address_reg[9]_2\(7),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_address[7]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[9]\(8),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[9]_0\(8),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_address[8]_i_2_n_0\,
      O => auto_pre_r_lcl_reg(8)
    );
\cmd_pipe_plus.mc_address[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[9]_1\(8),
      I1 => \cmd_pipe_plus.mc_address_reg[9]_2\(8),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_address[8]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address_reg[9]\(9),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address_reg[9]_0\(9),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_address[9]_i_2_n_0\,
      O => auto_pre_r_lcl_reg(9)
    );
\cmd_pipe_plus.mc_address[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[9]_1\(9),
      I1 => \cmd_pipe_plus.mc_address_reg[9]_2\(9),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_address[9]_i_2_n_0\
    );
\cmd_pipe_plus.mc_aux_out0[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I1 => \cmd_pipe_plus.mc_odt[0]_i_2_n_0\,
      O => mc_aux_out0_1
    );
\cmd_pipe_plus.mc_bank[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_bank_reg[2]\(0),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_bank_reg[2]_0\(0),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_bank[0]_i_2_n_0\,
      O => \req_bank_r_lcl_reg[2]\(0)
    );
\cmd_pipe_plus.mc_bank[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[2]_1\(0),
      I1 => \cmd_pipe_plus.mc_bank_reg[2]_2\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_bank[0]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_bank_reg[2]\(1),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_bank_reg[2]_0\(1),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_bank[1]_i_2_n_0\,
      O => \req_bank_r_lcl_reg[2]\(1)
    );
\cmd_pipe_plus.mc_bank[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[2]_1\(1),
      I1 => \cmd_pipe_plus.mc_bank_reg[2]_2\(1),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_bank[1]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_bank_reg[2]\(2),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_bank_reg[2]_0\(2),
      I4 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I5 => \cmd_pipe_plus.mc_bank[2]_i_2_n_0\,
      O => \req_bank_r_lcl_reg[2]\(2)
    );
\cmd_pipe_plus.mc_bank[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00AA00C0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[2]_1\(2),
      I1 => \cmd_pipe_plus.mc_bank_reg[2]_2\(2),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \cmd_pipe_plus.mc_bank[2]_i_2_n_0\
    );
\cmd_pipe_plus.mc_cmd[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I1 => \cmd_pipe_plus.mc_odt[0]_i_2_n_0\,
      O => E(0)
    );
\cmd_pipe_plus.mc_data_offset[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I1 => \cmd_pipe_plus.mc_odt[0]_i_2_n_0\,
      I2 => \cmd_pipe_plus.mc_data_offset_reg[2]\(0),
      O => granted_col_r_reg_0(0)
    );
\cmd_pipe_plus.mc_data_offset[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I1 => \cmd_pipe_plus.mc_odt[0]_i_2_n_0\,
      I2 => \cmd_pipe_plus.mc_data_offset_reg[2]\(1),
      O => granted_col_r_reg_0(1)
    );
\cmd_pipe_plus.mc_data_offset[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I1 => \cmd_pipe_plus.mc_odt[0]_i_2_n_0\,
      O => granted_col_r_reg
    );
\cmd_pipe_plus.mc_odt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I1 => \cmd_pipe_plus.mc_odt[0]_i_2_n_0\,
      I2 => \cmd_pipe_plus.mc_odt_reg[0]_0\,
      O => mc_odt_ns(0)
    );
\cmd_pipe_plus.mc_odt[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFFEF"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => col_rd_wr_r,
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \^rd_wr_r_lcl_reg_0\,
      O => \cmd_pipe_plus.mc_odt[0]_i_2_n_0\
    );
\cmd_pipe_plus.mc_ras_n[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I1 => \^q\(2),
      I2 => \^q\(3),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => mc_ras_n_ns(0)
    );
\cmd_pipe_plus.mc_we_n[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      I1 => \cmd_pipe_plus.mc_odt_reg[0]\,
      O => granted_col_r_reg_1(0)
    );
\col_mux.col_periodic_rd_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEEEEFAAA"
    )
        port map (
      I0 => \col_mux.col_periodic_rd_r_i_2_n_0\,
      I1 => req_periodic_rd_r(3),
      I2 => req_periodic_rd_r(2),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => \col_mux.col_periodic_rd_r_i_3_n_0\,
      O => DIC(0)
    );
\col_mux.col_periodic_rd_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \col_mux.col_periodic_rd_r\,
      I3 => \col_mux.col_periodic_rd_r_reg\,
      I4 => \^q\(3),
      I5 => \^q\(2),
      O => \col_mux.col_periodic_rd_r_i_2_n_0\
    );
\col_mux.col_periodic_rd_r_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0202020203000000"
    )
        port map (
      I0 => req_periodic_rd_r(1),
      I1 => \^q\(2),
      I2 => \^q\(3),
      I3 => req_periodic_rd_r(0),
      I4 => \^q\(0),
      I5 => \^q\(1),
      O => \col_mux.col_periodic_rd_r_i_3_n_0\
    );
\col_mux.col_rd_wr_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAABAA"
    )
        port map (
      I0 => \^rd_wr_r_lcl_reg_0\,
      I1 => \^q\(2),
      I2 => \^q\(3),
      I3 => col_rd_wr_r,
      I4 => \^q\(1),
      I5 => \^q\(0),
      O => col_rd_wr
    );
\col_mux.col_rd_wr_r_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEC20"
    )
        port map (
      I0 => rd_wr_r(2),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => rd_wr_r(3),
      I4 => \col_mux.col_rd_wr_r_i_3_n_0\,
      O => \^rd_wr_r_lcl_reg_0\
    );
\col_mux.col_rd_wr_r_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000B888"
    )
        port map (
      I0 => rd_wr_r(1),
      I1 => \^q\(1),
      I2 => rd_wr_r(0),
      I3 => \^q\(0),
      I4 => \^q\(3),
      I5 => \^q\(2),
      O => \col_mux.col_rd_wr_r_i_3_n_0\
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE200E2"
    )
        port map (
      I0 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2_n_0\,
      I1 => \^q\(2),
      I2 => req_data_buf_addr_r(8),
      I3 => \^q\(3),
      I4 => req_data_buf_addr_r(12),
      O => col_wr_data_buf_addr(0)
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE200E2"
    )
        port map (
      I0 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(0),
      I1 => \^q\(0),
      I2 => req_data_buf_addr_r(0),
      I3 => \^q\(1),
      I4 => req_data_buf_addr_r(4),
      O => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2_n_0\
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE200E2"
    )
        port map (
      I0 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2_n_0\,
      I1 => \^q\(2),
      I2 => req_data_buf_addr_r(9),
      I3 => \^q\(3),
      I4 => req_data_buf_addr_r(13),
      O => col_wr_data_buf_addr(1)
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE200E2"
    )
        port map (
      I0 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(1),
      I1 => \^q\(0),
      I2 => req_data_buf_addr_r(1),
      I3 => \^q\(1),
      I4 => req_data_buf_addr_r(5),
      O => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2_n_0\
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE200E2"
    )
        port map (
      I0 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2_n_0\,
      I1 => \^q\(2),
      I2 => req_data_buf_addr_r(10),
      I3 => \^q\(3),
      I4 => req_data_buf_addr_r(14),
      O => col_wr_data_buf_addr(2)
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE200E2"
    )
        port map (
      I0 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(2),
      I1 => \^q\(0),
      I2 => req_data_buf_addr_r(2),
      I3 => \^q\(1),
      I4 => req_data_buf_addr_r(6),
      O => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2_n_0\
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE200E2"
    )
        port map (
      I0 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2_n_0\,
      I1 => \^q\(2),
      I2 => req_data_buf_addr_r(11),
      I3 => \^q\(3),
      I4 => req_data_buf_addr_r(15),
      O => col_wr_data_buf_addr(3)
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE200E2"
    )
        port map (
      I0 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3),
      I1 => \^q\(0),
      I2 => req_data_buf_addr_r(3),
      I3 => \^q\(1),
      I4 => req_data_buf_addr_r(7),
      O => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2_n_0\
    );
\demanded_prior_r_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFEF00EFEFEFEF"
    )
        port map (
      I0 => \^q\(1),
      I1 => demanded_prior_r_9,
      I2 => demand_priority_r_10,
      I3 => \^q\(2),
      I4 => demanded_prior_r_11,
      I5 => demand_priority_r_12,
      O => \^grant_r_reg[1]_0\
    );
\grant_r[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20002000A0A0A000"
    )
        port map (
      I0 => \grant_r_reg[0]_3\,
      I1 => \last_master_r[2]_i_1__0_n_0\,
      I2 => \grant_r[2]_i_2__0_n_0\,
      I3 => \grant_r[0]_i_2__0_n_0\,
      I4 => \grant_r[3]_i_5_n_0\,
      I5 => \grant_r_reg[0]_2\,
      O => \grant_r[0]_i_1__0_n_0\
    );
\grant_r[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0F0F5F3F0F3F5"
    )
        port map (
      I0 => last_master_r(0),
      I1 => \^q\(0),
      I2 => \last_master_r_reg[0]_0\,
      I3 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I4 => last_master_r(1),
      I5 => \^q\(1),
      O => \grant_r[0]_i_2__0_n_0\
    );
\grant_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000800088888"
    )
        port map (
      I0 => \grant_r_reg[1]_2\,
      I1 => \grant_r[1]_i_2_n_0\,
      I2 => \last_master_r[1]_i_1__0_n_0\,
      I3 => \last_master_r[2]_i_1__0_n_0\,
      I4 => \grant_r_reg[0]_3\,
      I5 => \grant_r_reg[0]_2\,
      O => \grant_r[1]_i_1_n_0\
    );
\grant_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDD0D0DDDDD0DD"
    )
        port map (
      I0 => \last_master_r[1]_i_1__0_n_0\,
      I1 => \grant_r[3]_i_5_n_0\,
      I2 => \grant_r[2]_i_3__2_n_0\,
      I3 => \grant_r_reg[1]_3\,
      I4 => \^rd_wr_r_lcl_reg_1\,
      I5 => col_wait_r_0,
      O => \grant_r[1]_i_2_n_0\
    );
\grant_r[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010505000005000"
    )
        port map (
      I0 => \grant_r[3]_i_5_n_0\,
      I1 => \grant_r_reg[0]_2\,
      I2 => \grant_r[2]_i_2__0_n_0\,
      I3 => \grant_r[2]_i_3__2_n_0\,
      I4 => \last_master_r[2]_i_1__0_n_0\,
      I5 => \grant_r_reg[2]_1\,
      O => \grant_r[2]_i_1__0_n_0\
    );
\grant_r[2]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F5F7"
    )
        port map (
      I0 => \last_master_r[0]_i_1__0_n_0\,
      I1 => granted_col_r_reg_2,
      I2 => \^rd_wr_r_lcl_reg\,
      I3 => col_wait_r,
      O => \grant_r[2]_i_2__0_n_0\
    );
\grant_r[2]_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0053"
    )
        port map (
      I0 => \^q\(3),
      I1 => last_master_r(3),
      I2 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I3 => \last_master_r_reg[0]_0\,
      O => \grant_r[2]_i_3__2_n_0\
    );
\grant_r[2]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA8A"
    )
        port map (
      I0 => \^grant_r_reg[1]_0\,
      I1 => demanded_prior_r_8,
      I2 => demand_priority_r,
      I3 => \^q\(3),
      O => demanded_prior_r_reg_0
    );
\grant_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0002000A0A02000"
    )
        port map (
      I0 => \grant_r_reg[0]_2\,
      I1 => \last_master_r[1]_i_1__0_n_0\,
      I2 => \grant_r[3]_i_3_n_0\,
      I3 => \grant_r[3]_i_4__2_n_0\,
      I4 => \grant_r[3]_i_5_n_0\,
      I5 => \grant_r_reg[1]_2\,
      O => \grant_r[3]_i_1_n_0\
    );
\grant_r[3]_i_11__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0A080A0A"
    )
        port map (
      I0 => rd_wr_r(2),
      I1 => \grant_r[3]_i_5_1\(0),
      I2 => \grant_r[3]_i_8_0\,
      I3 => \^wr_this_rank_r_reg[0]\,
      I4 => \^grant_r_reg[0]_0\,
      O => \grant_r[3]_i_11__0_n_0\
    );
\grant_r[3]_i_15__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010011111111"
    )
        port map (
      I0 => demand_priority_r,
      I1 => override_demand_r,
      I2 => \^q\(0),
      I3 => demand_priority_r_7,
      I4 => demanded_prior_r,
      I5 => \^grant_r_reg[1]_0\,
      O => \grant_r[3]_i_15__0_n_0\
    );
\grant_r[3]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010011111111"
    )
        port map (
      I0 => demand_priority_r_7,
      I1 => override_demand_r,
      I2 => \^q\(3),
      I3 => demand_priority_r,
      I4 => demanded_prior_r_8,
      I5 => \^grant_r_reg[1]_0\,
      O => \grant_r[3]_i_17_n_0\
    );
\grant_r[3]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ACA0"
    )
        port map (
      I0 => rd_wr_r(3),
      I1 => \^q\(2),
      I2 => \^q\(3),
      I3 => rd_wr_r(2),
      O => \grant_r[3]_i_18_n_0\
    );
\grant_r[3]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(2),
      I1 => ofs_rdy_r,
      O => \grant_r_reg[2]_0\
    );
\grant_r[3]_i_23\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(3),
      I1 => ofs_rdy_r_14,
      O => \grant_r_reg[3]_2\
    );
\grant_r[3]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(0),
      I1 => ofs_rdy_r_15,
      O => \grant_r_reg[0]_1\
    );
\grant_r[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FAFB"
    )
        port map (
      I0 => \grant_r[2]_i_3__2_n_0\,
      I1 => \grant_r_reg[1]_3\,
      I2 => \^rd_wr_r_lcl_reg_1\,
      I3 => col_wait_r_0,
      O => \grant_r[3]_i_3_n_0\
    );
\grant_r[3]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000503000305"
    )
        port map (
      I0 => last_master_r(3),
      I1 => \^q\(3),
      I2 => \last_master_r_reg[0]_0\,
      I3 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I4 => last_master_r(0),
      I5 => \^q\(0),
      O => \grant_r[3]_i_4__2_n_0\
    );
\grant_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \grant_r[3]_i_9_n_0\,
      I1 => granted_col_r_reg_6,
      I2 => granted_col_r_reg_7,
      I3 => \grant_r[3]_i_11__0_n_0\,
      I4 => granted_col_r_reg_8,
      I5 => granted_col_r_reg_9,
      O => \grant_r[3]_i_5_n_0\
    );
\grant_r[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFBFFFBFFFAFFFF"
    )
        port map (
      I0 => \grant_r[3]_i_2\,
      I1 => granted_col_r_i_6_n_0,
      I2 => \grant_r[3]_i_15__0_n_0\,
      I3 => \grant_r[3]_i_2_0\,
      I4 => granted_col_r_i_8_n_0,
      I5 => rd_wr_r(3),
      O => rd_wr_r_lcl_reg_2
    );
\grant_r[3]_i_7__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA8A"
    )
        port map (
      I0 => \^grant_r_reg[1]_0\,
      I1 => demanded_prior_r,
      I2 => demand_priority_r_7,
      I3 => \^q\(0),
      O => demanded_prior_r_reg
    );
\grant_r[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFBFFFBFFFAFFFF"
    )
        port map (
      I0 => \grant_r[1]_i_3\,
      I1 => granted_col_r_i_6_n_0,
      I2 => \grant_r[3]_i_17_n_0\,
      I3 => \grant_r[1]_i_3_0\,
      I4 => granted_col_r_i_8_n_0,
      I5 => rd_wr_r(0),
      O => \^rd_wr_r_lcl_reg_1\
    );
\grant_r[3]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003332"
    )
        port map (
      I0 => \grant_r[3]_i_5_0\(0),
      I1 => \col_mux.col_periodic_rd_r_reg\,
      I2 => \col_mux.col_rd_wr_r_i_3_n_0\,
      I3 => \grant_r[3]_i_18_n_0\,
      I4 => rd_wr_r(2),
      O => \grant_r[3]_i_9_n_0\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[0]_i_1__0_n_0\,
      Q => \^q\(0),
      R => '0'
    );
\grant_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[1]_i_1_n_0\,
      Q => \^q\(1),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[2]_i_1__0_n_0\,
      Q => \^q\(2),
      R => '0'
    );
\grant_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[3]_i_1_n_0\,
      Q => \^q\(3),
      R => '0'
    );
granted_col_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF5F5D"
    )
        port map (
      I0 => \grant_r[3]_i_5_n_0\,
      I1 => granted_col_r_reg_2,
      I2 => \^rd_wr_r_lcl_reg\,
      I3 => col_wait_r,
      I4 => \grant_r_reg[0]_2\,
      I5 => \grant_r_reg[0]_3\,
      O => col_wait_r_reg
    );
granted_col_r_i_11: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(1),
      I1 => ofs_rdy_r_13,
      O => \grant_r_reg[1]_1\
    );
granted_col_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFBFFFBFFFAFFFF"
    )
        port map (
      I0 => granted_col_r_reg_3,
      I1 => granted_col_r_i_6_n_0,
      I2 => granted_col_r_reg_4,
      I3 => granted_col_r_reg_5,
      I4 => granted_col_r_i_8_n_0,
      I5 => rd_wr_r(1),
      O => \^rd_wr_r_lcl_reg\
    );
granted_col_r_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F0F2"
    )
        port map (
      I0 => \^grant_r_reg[0]_0\,
      I1 => \^wr_this_rank_r_reg[0]\,
      I2 => \grant_r[3]_i_8_0\,
      I3 => \grant_r[3]_i_5_1\(0),
      O => granted_col_r_i_6_n_0
    );
granted_col_r_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F0F1"
    )
        port map (
      I0 => \grant_r[3]_i_18_n_0\,
      I1 => \col_mux.col_rd_wr_r_i_3_n_0\,
      I2 => \col_mux.col_periodic_rd_r_reg\,
      I3 => \grant_r[3]_i_5_0\(0),
      O => granted_col_r_i_8_n_0
    );
\last_master_r[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => \^q\(0),
      I1 => last_master_r(0),
      I2 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I3 => \last_master_r_reg[0]_0\,
      O => \last_master_r[0]_i_1__0_n_0\
    );
\last_master_r[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => \^q\(1),
      I1 => last_master_r(1),
      I2 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I3 => \last_master_r_reg[0]_0\,
      O => \last_master_r[1]_i_1__0_n_0\
    );
\last_master_r[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => \^q\(2),
      I1 => last_master_r(2),
      I2 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I3 => \last_master_r_reg[0]_0\,
      O => \last_master_r[2]_i_1__0_n_0\
    );
\last_master_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEBA"
    )
        port map (
      I0 => \last_master_r_reg[0]_0\,
      I1 => \cmd_pipe_plus.mc_odt_reg[0]\,
      I2 => last_master_r(3),
      I3 => \^q\(3),
      O => \last_master_r[3]_i_1_n_0\
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[0]_i_1__0_n_0\,
      Q => last_master_r(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[1]_i_1__0_n_0\,
      Q => last_master_r(1),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[2]_i_1__0_n_0\,
      Q => last_master_r(2),
      R => '0'
    );
\last_master_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[3]_i_1_n_0\,
      Q => last_master_r(3),
      R => '0'
    );
override_demand_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => rnk_config_strobe_0(1),
      I1 => rnk_config_strobe,
      I2 => rnk_config_strobe_0(0),
      O => \genblk3[2].rnk_config_strobe_r_reg[2]\
    );
\periodic_rd_generation.read_this_rank_r_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^grant_r_reg[3]_0\,
      O => \periodic_rd_generation.read_this_rank\
    );
\periodic_rd_generation.read_this_rank_r_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000777"
    )
        port map (
      I0 => \^q\(3),
      I1 => rd_this_rank_r(3),
      I2 => \^q\(0),
      I3 => rd_this_rank_r(0),
      I4 => \periodic_rd_generation.read_this_rank_r_i_3_n_0\,
      O => \^grant_r_reg[3]_0\
    );
\periodic_rd_generation.read_this_rank_r_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => rd_this_rank_r(2),
      I1 => \^q\(2),
      I2 => rd_this_rank_r(1),
      I3 => \^q\(1),
      O => \periodic_rd_generation.read_this_rank_r_i_3_n_0\
    );
\wtr_timer.wtr_cnt_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => wr_this_rank_r(2),
      I1 => \^q\(2),
      I2 => wr_this_rank_r(1),
      I3 => \^q\(1),
      O => \^wr_this_rank_r_reg[0]\
    );
\wtr_timer.wtr_cnt_r[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \^q\(0),
      I1 => wr_this_rank_r(0),
      I2 => wr_this_rank_r(3),
      I3 => \^q\(3),
      O => \^grant_r_reg[0]_0\
    );
\wtr_timer.wtr_cnt_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000777"
    )
        port map (
      I0 => \^q\(3),
      I1 => wr_this_rank_r(3),
      I2 => wr_this_rank_r(0),
      I3 => \^q\(0),
      I4 => \^wr_this_rank_r_reg[0]\,
      O => \grant_r_reg[3]_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_3\ is
  port (
    \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_0\ : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_1\ : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_2\ : out STD_LOGIC;
    p_0_in : out STD_LOGIC;
    \genblk3[1].rnk_config_strobe_r_reg[1]\ : out STD_LOGIC;
    \grant_r_reg[0]_0\ : in STD_LOGIC;
    \grant_r_reg[0]_1\ : in STD_LOGIC;
    \grant_r_reg[2]_0\ : in STD_LOGIC;
    \grant_r_reg[0]_2\ : in STD_LOGIC;
    \grant_r[3]_i_8\ : in STD_LOGIC;
    \grant_r[3]_i_5\ : in STD_LOGIC;
    rnk_config_strobe : in STD_LOGIC;
    \grant_r[2]_i_4__0\ : in STD_LOGIC;
    \grant_r[3]_i_7\ : in STD_LOGIC;
    granted_col_r_i_3 : in STD_LOGIC;
    \grant_r[3]_i_5_0\ : in STD_LOGIC;
    rnk_config_r : in STD_LOGIC;
    \rnk_config_r_reg[0]\ : in STD_LOGIC;
    \last_master_r_reg[3]_0\ : in STD_LOGIC;
    rnk_config_strobe_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_3\ : entity is "mig_7series_v4_2_round_robin_arb";
end \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_3\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_3\ is
  signal grant_config_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \grant_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_3__3_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_20_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_5__0_n_0\ : STD_LOGIC;
  signal last_master_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \last_master_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \last_master_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \last_master_r[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \last_master_r[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \rnk_config_r[0]_i_2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \grant_r[2]_i_3__3\ : label is "soft_lutpair540";
  attribute SOFT_HLUTNM of \grant_r[3]_i_20\ : label is "soft_lutpair539";
  attribute SOFT_HLUTNM of \rnk_config_r[0]_i_1\ : label is "soft_lutpair539";
  attribute SOFT_HLUTNM of \rnk_config_r[0]_i_2\ : label is "soft_lutpair540";
begin
\grant_r[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000888880008"
    )
        port map (
      I0 => \grant_r_reg[0]_1\,
      I1 => \grant_r[2]_i_2__1_n_0\,
      I2 => \last_master_r[1]_i_1__1_n_0\,
      I3 => \last_master_r[0]_i_1__1_n_0\,
      I4 => \grant_r_reg[0]_2\,
      I5 => \grant_r_reg[0]_0\,
      O => \grant_r[0]_i_1__1_n_0\
    );
\grant_r[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"100010001000F000"
    )
        port map (
      I0 => \grant_r_reg[0]_0\,
      I1 => \grant_r_reg[0]_1\,
      I2 => \grant_r_reg[2]_0\,
      I3 => \grant_r[3]_i_5__0_n_0\,
      I4 => \last_master_r[1]_i_1__1_n_0\,
      I5 => \last_master_r[2]_i_1__1_n_0\,
      O => \grant_r[1]_i_1__1_n_0\
    );
\grant_r[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000400044444"
    )
        port map (
      I0 => \grant_r_reg[0]_2\,
      I1 => \grant_r[2]_i_2__1_n_0\,
      I2 => \grant_r[2]_i_3__3_n_0\,
      I3 => \last_master_r[3]_i_1__0_n_0\,
      I4 => \grant_r_reg[2]_0\,
      I5 => \grant_r_reg[0]_1\,
      O => \grant_r[2]_i_1__1_n_0\
    );
\grant_r[2]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \last_master_r[2]_i_1__1_n_0\,
      I1 => \grant_r_reg[0]_0\,
      I2 => \last_master_r[0]_i_1__1_n_0\,
      I3 => \grant_r_reg[2]_0\,
      O => \grant_r[2]_i_2__1_n_0\
    );
\grant_r[2]_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => grant_config_r(2),
      I1 => rnk_config_strobe,
      I2 => last_master_r(2),
      O => \grant_r[2]_i_3__3_n_0\
    );
\grant_r[3]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFEEEFFFFFFFFF"
    )
        port map (
      I0 => \grant_r[3]_i_5_0\,
      I1 => \grant_r[3]_i_5\,
      I2 => \rnk_config_r[0]_i_2_n_0\,
      I3 => rnk_config_strobe,
      I4 => \grant_r[3]_i_20_n_0\,
      I5 => \grant_r[2]_i_4__0\,
      O => \rnk_config_strobe_r_reg[0]_2\
    );
\grant_r[3]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFEEEFFFFFFFFF"
    )
        port map (
      I0 => \grant_r[3]_i_7\,
      I1 => \grant_r[3]_i_5\,
      I2 => \rnk_config_r[0]_i_2_n_0\,
      I3 => rnk_config_strobe,
      I4 => \grant_r[3]_i_20_n_0\,
      I5 => \grant_r[2]_i_4__0\,
      O => \rnk_config_strobe_r_reg[0]_0\
    );
\grant_r[3]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFEEEFFFFFFFFF"
    )
        port map (
      I0 => \grant_r[3]_i_8\,
      I1 => \grant_r[3]_i_5\,
      I2 => \rnk_config_r[0]_i_2_n_0\,
      I3 => rnk_config_strobe,
      I4 => \grant_r[3]_i_20_n_0\,
      I5 => \grant_r[2]_i_4__0\,
      O => \rnk_config_strobe_r_reg[0]\
    );
\grant_r[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"400040004000F000"
    )
        port map (
      I0 => \grant_r_reg[2]_0\,
      I1 => \grant_r_reg[0]_2\,
      I2 => \grant_r_reg[0]_0\,
      I3 => \grant_r[3]_i_5__0_n_0\,
      I4 => \last_master_r[0]_i_1__1_n_0\,
      I5 => \last_master_r[3]_i_1__0_n_0\,
      O => \grant_r[3]_i_1__1_n_0\
    );
\grant_r[3]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => grant_config_r(3),
      I1 => grant_config_r(1),
      I2 => grant_config_r(0),
      O => \grant_r[3]_i_20_n_0\
    );
\grant_r[3]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7077"
    )
        port map (
      I0 => \last_master_r[3]_i_1__0_n_0\,
      I1 => \grant_r_reg[0]_1\,
      I2 => \grant_r_reg[0]_2\,
      I3 => \last_master_r[1]_i_1__1_n_0\,
      O => \grant_r[3]_i_5__0_n_0\
    );
\grant_r[3]_i_6__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFEE"
    )
        port map (
      I0 => rnk_config_strobe_0(0),
      I1 => rnk_config_strobe_0(1),
      I2 => \grant_r[2]_i_4__0\,
      I3 => rnk_config_strobe,
      I4 => \rnk_config_r[0]_i_2_n_0\,
      O => \genblk3[1].rnk_config_strobe_r_reg[1]\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[0]_i_1__1_n_0\,
      Q => grant_config_r(0),
      R => '0'
    );
\grant_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[1]_i_1__1_n_0\,
      Q => grant_config_r(1),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[2]_i_1__1_n_0\,
      Q => grant_config_r(2),
      R => '0'
    );
\grant_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[3]_i_1__1_n_0\,
      Q => grant_config_r(3),
      R => '0'
    );
granted_col_r_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFEEEFFFFFFFFF"
    )
        port map (
      I0 => granted_col_r_i_3,
      I1 => \grant_r[3]_i_5\,
      I2 => \rnk_config_r[0]_i_2_n_0\,
      I3 => rnk_config_strobe,
      I4 => \grant_r[3]_i_20_n_0\,
      I5 => \grant_r[2]_i_4__0\,
      O => \rnk_config_strobe_r_reg[0]_1\
    );
\last_master_r[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00B8"
    )
        port map (
      I0 => grant_config_r(0),
      I1 => rnk_config_strobe,
      I2 => last_master_r(0),
      I3 => \last_master_r_reg[3]_0\,
      O => \last_master_r[0]_i_1__1_n_0\
    );
\last_master_r[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00B8"
    )
        port map (
      I0 => grant_config_r(1),
      I1 => rnk_config_strobe,
      I2 => last_master_r(1),
      I3 => \last_master_r_reg[3]_0\,
      O => \last_master_r[1]_i_1__1_n_0\
    );
\last_master_r[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(2),
      I1 => rnk_config_strobe,
      I2 => grant_config_r(2),
      I3 => \last_master_r_reg[3]_0\,
      O => \last_master_r[2]_i_1__1_n_0\
    );
\last_master_r[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAE"
    )
        port map (
      I0 => \last_master_r_reg[3]_0\,
      I1 => last_master_r(3),
      I2 => rnk_config_strobe,
      I3 => grant_config_r(3),
      O => \last_master_r[3]_i_1__0_n_0\
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[0]_i_1__1_n_0\,
      Q => last_master_r(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[1]_i_1__1_n_0\,
      Q => last_master_r(1),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[2]_i_1__1_n_0\,
      Q => last_master_r(2),
      R => '0'
    );
\last_master_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[3]_i_1__0_n_0\,
      Q => last_master_r(3),
      R => '0'
    );
\rnk_config_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000001FF"
    )
        port map (
      I0 => grant_config_r(3),
      I1 => grant_config_r(1),
      I2 => grant_config_r(0),
      I3 => rnk_config_strobe,
      I4 => \rnk_config_r[0]_i_2_n_0\,
      O => p_0_in
    );
\rnk_config_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FDDD"
    )
        port map (
      I0 => rnk_config_r,
      I1 => \rnk_config_r_reg[0]\,
      I2 => grant_config_r(2),
      I3 => rnk_config_strobe,
      O => \rnk_config_r[0]_i_2_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_4\ is
  port (
    \grant_r_reg[2]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rstdiv0_sync_r1_reg_rep__11\ : out STD_LOGIC;
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[3]_1\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \grant_r_reg[3]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    act_wait_r_lcl_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[0]_0\ : in STD_LOGIC;
    \grant_r_reg[0]_1\ : in STD_LOGIC;
    \grant_r_reg[0]_2\ : in STD_LOGIC;
    \grant_r_reg[2]_1\ : in STD_LOGIC;
    \grant_r_reg[3]_3\ : in STD_LOGIC;
    cs_en2 : in STD_LOGIC;
    \grant_r_reg[2]_2\ : in STD_LOGIC;
    \last_master_r_reg[0]_0\ : in STD_LOGIC;
    req_row_r : in STD_LOGIC_VECTOR ( 38 downto 0 );
    \cmd_pipe_plus.mc_address_reg[38]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    row_cmd_wr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    CLK : in STD_LOGIC;
    \grant_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_4\ : entity is "mig_7series_v4_2_round_robin_arb";
end \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_4\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_4\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \cmd_pipe_plus.mc_address[26]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[27]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[28]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[29]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[30]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[31]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[32]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[33]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[34]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[35]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[36]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[36]_i_3_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[36]_i_4_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[37]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[38]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[6]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[7]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[8]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_we_n[2]_i_3_n_0\ : STD_LOGIC;
  signal \grant_r[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_3__1_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_4__1_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \^grant_r_reg[2]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^grant_r_reg[3]_0\ : STD_LOGIC;
  signal last_master_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \last_master_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \last_master_r[3]_i_1__1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[36]_i_4\ : label is "soft_lutpair542";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_cas_n[2]_i_1\ : label is "soft_lutpair541";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_we_n[2]_i_2\ : label is "soft_lutpair541";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_we_n[2]_i_3\ : label is "soft_lutpair542";
  attribute SOFT_HLUTNM of \grant_r[3]_i_6__1\ : label is "soft_lutpair543";
  attribute SOFT_HLUTNM of \last_master_r[3]_i_1__1\ : label is "soft_lutpair543";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  \grant_r_reg[2]_0\(1 downto 0) <= \^grant_r_reg[2]_0\(1 downto 0);
  \grant_r_reg[3]_0\ <= \^grant_r_reg[3]_0\;
\cmd_pipe_plus.mc_address[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => req_row_r(15),
      I3 => req_row_r(27),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_address[26]_i_2_n_0\,
      O => \grant_r_reg[3]_1\(0)
    );
\cmd_pipe_plus.mc_address[26]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[38]\(0),
      I1 => \^q\(0),
      I2 => req_row_r(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[26]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => req_row_r(16),
      I3 => req_row_r(28),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_address[27]_i_2_n_0\,
      O => \grant_r_reg[3]_1\(1)
    );
\cmd_pipe_plus.mc_address[27]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[38]\(1),
      I1 => \^q\(0),
      I2 => req_row_r(4),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[27]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => req_row_r(17),
      I3 => req_row_r(29),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_address[28]_i_2_n_0\,
      O => \grant_r_reg[3]_1\(2)
    );
\cmd_pipe_plus.mc_address[28]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[38]\(2),
      I1 => \^q\(0),
      I2 => req_row_r(5),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[28]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => req_row_r(18),
      I3 => req_row_r(30),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_address[29]_i_2_n_0\,
      O => \grant_r_reg[3]_1\(3)
    );
\cmd_pipe_plus.mc_address[29]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[38]\(3),
      I1 => \^q\(0),
      I2 => req_row_r(6),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[29]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => req_row_r(19),
      I3 => req_row_r(31),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_address[30]_i_2_n_0\,
      O => \grant_r_reg[3]_1\(4)
    );
\cmd_pipe_plus.mc_address[30]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[38]\(4),
      I1 => \^q\(0),
      I2 => req_row_r(7),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[30]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => req_row_r(20),
      I3 => req_row_r(32),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_address[31]_i_2_n_0\,
      O => \grant_r_reg[3]_1\(5)
    );
\cmd_pipe_plus.mc_address[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[38]\(5),
      I1 => \^q\(0),
      I2 => req_row_r(8),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[31]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[32]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => req_row_r(21),
      I3 => req_row_r(33),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_address[32]_i_2_n_0\,
      O => \grant_r_reg[3]_1\(6)
    );
\cmd_pipe_plus.mc_address[32]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[38]\(6),
      I1 => \^q\(0),
      I2 => req_row_r(9),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[32]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => req_row_r(22),
      I3 => req_row_r(34),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_address[33]_i_2_n_0\,
      O => \grant_r_reg[3]_1\(7)
    );
\cmd_pipe_plus.mc_address[33]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[38]\(7),
      I1 => \^q\(0),
      I2 => req_row_r(10),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[33]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[34]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => req_row_r(23),
      I3 => req_row_r(35),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_address[34]_i_2_n_0\,
      O => \grant_r_reg[3]_1\(8)
    );
\cmd_pipe_plus.mc_address[34]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[38]\(8),
      I1 => \^q\(0),
      I2 => req_row_r(11),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[34]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[35]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => req_row_r(24),
      I3 => req_row_r(36),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_address[35]_i_2_n_0\,
      O => \grant_r_reg[3]_1\(9)
    );
\cmd_pipe_plus.mc_address[35]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => req_row_r(0),
      I1 => \^q\(0),
      I2 => req_row_r(12),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[35]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[36]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF80"
    )
        port map (
      I0 => req_row_r(37),
      I1 => row_cmd_wr(3),
      I2 => \^q\(3),
      I3 => \cmd_pipe_plus.mc_address[36]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_address[36]_i_3_n_0\,
      O => \grant_r_reg[3]_1\(10)
    );
\cmd_pipe_plus.mc_address[36]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2000FFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => row_cmd_wr(2),
      I3 => req_row_r(25),
      I4 => cs_en2,
      O => \cmd_pipe_plus.mc_address[36]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[36]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80808080FF808080"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\,
      I1 => req_row_r(1),
      I2 => row_cmd_wr(0),
      I3 => \cmd_pipe_plus.mc_address[36]_i_4_n_0\,
      I4 => req_row_r(13),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[36]_i_3_n_0\
    );
\cmd_pipe_plus.mc_address[36]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => row_cmd_wr(1),
      O => \cmd_pipe_plus.mc_address[36]_i_4_n_0\
    );
\cmd_pipe_plus.mc_address[37]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => req_row_r(26),
      I3 => req_row_r(38),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_address[37]_i_2_n_0\,
      O => \grant_r_reg[3]_1\(11)
    );
\cmd_pipe_plus.mc_address[37]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => req_row_r(2),
      I1 => \^q\(0),
      I2 => req_row_r(14),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[37]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[38]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \cmd_pipe_plus.mc_address_reg[38]\(11),
      I3 => \cmd_pipe_plus.mc_address_reg[38]\(12),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_address[38]_i_2_n_0\,
      O => \grant_r_reg[3]_1\(12)
    );
\cmd_pipe_plus.mc_address[38]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[38]\(9),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_address_reg[38]\(10),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_address[38]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \cmd_pipe_plus.mc_bank_reg[8]\(0),
      I3 => \cmd_pipe_plus.mc_bank_reg[8]_0\(0),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_bank[6]_i_2_n_0\,
      O => \grant_r_reg[3]_2\(0)
    );
\cmd_pipe_plus.mc_bank[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[8]_1\(0),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_bank_reg[8]_2\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_bank[6]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \cmd_pipe_plus.mc_bank_reg[8]\(1),
      I3 => \cmd_pipe_plus.mc_bank_reg[8]_0\(1),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_bank[7]_i_2_n_0\,
      O => \grant_r_reg[3]_2\(1)
    );
\cmd_pipe_plus.mc_bank[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[8]_1\(1),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_bank_reg[8]_2\(1),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_bank[7]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEA40FFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \cmd_pipe_plus.mc_bank_reg[8]\(2),
      I3 => \cmd_pipe_plus.mc_bank_reg[8]_0\(2),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_bank[8]_i_2_n_0\,
      O => \grant_r_reg[3]_2\(2)
    );
\cmd_pipe_plus.mc_bank[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F088"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[8]_1\(2),
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_bank_reg[8]_2\(2),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_bank[8]_i_2_n_0\
    );
\cmd_pipe_plus.mc_cas_n[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => cs_en2,
      I4 => \^q\(1),
      O => mc_cas_n_ns(0)
    );
\cmd_pipe_plus.mc_we_n[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\,
      I1 => row_cmd_wr(0),
      I2 => row_cmd_wr(3),
      I3 => \^q\(3),
      I4 => cs_en2,
      I5 => \cmd_pipe_plus.mc_we_n[2]_i_3_n_0\,
      O => act_wait_r_lcl_reg(0)
    );
\cmd_pipe_plus.mc_we_n[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\
    );
\cmd_pipe_plus.mc_we_n[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"23202020"
    )
        port map (
      I0 => row_cmd_wr(2),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => row_cmd_wr(1),
      O => \cmd_pipe_plus.mc_we_n[2]_i_3_n_0\
    );
\grant_r[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000800088888"
    )
        port map (
      I0 => \grant_r_reg[0]_0\,
      I1 => \grant_r[2]_i_3__1_n_0\,
      I2 => \^grant_r_reg[2]_0\(0),
      I3 => \last_master_r[0]_i_1__2_n_0\,
      I4 => \grant_r_reg[0]_1\,
      I5 => \grant_r_reg[0]_2\,
      O => \grant_r[0]_i_1__3_n_0\
    );
\grant_r[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02AA020200000000"
    )
        port map (
      I0 => \grant_r_reg[0]_1\,
      I1 => \grant_r_reg[0]_0\,
      I2 => \grant_r_reg[2]_1\,
      I3 => \^grant_r_reg[2]_0\(1),
      I4 => \^grant_r_reg[3]_0\,
      I5 => \grant_r[2]_i_3__1_n_0\,
      O => \grant_r[2]_i_1__3_n_0\
    );
\grant_r[2]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF53FFFF00000000"
    )
        port map (
      I0 => \^q\(2),
      I1 => last_master_r(2),
      I2 => cs_en2,
      I3 => \grant_r_reg[2]_2\,
      I4 => \grant_r_reg[0]_2\,
      I5 => \grant_r[2]_i_4__1_n_0\,
      O => \grant_r[2]_i_3__1_n_0\
    );
\grant_r[2]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABEFFFFF"
    )
        port map (
      I0 => \grant_r_reg[2]_2\,
      I1 => cs_en2,
      I2 => last_master_r(0),
      I3 => \^q\(0),
      I4 => \grant_r_reg[2]_1\,
      O => \grant_r[2]_i_4__1_n_0\
    );
\grant_r[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000888880008"
    )
        port map (
      I0 => \grant_r_reg[0]_2\,
      I1 => \grant_r_reg[3]_3\,
      I2 => \grant_r_reg[0]_1\,
      I3 => \grant_r_reg[2]_1\,
      I4 => \^grant_r_reg[3]_0\,
      I5 => \last_master_r[0]_i_1__2_n_0\,
      O => \grant_r[3]_i_1__0_n_0\
    );
\grant_r[3]_i_6__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0053"
    )
        port map (
      I0 => \^q\(3),
      I1 => last_master_r(3),
      I2 => cs_en2,
      I3 => \last_master_r_reg[0]_0\,
      O => \^grant_r_reg[3]_0\
    );
\grant_r[3]_i_7__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"54100000"
    )
        port map (
      I0 => \grant_r_reg[2]_2\,
      I1 => cs_en2,
      I2 => last_master_r(1),
      I3 => \^q\(1),
      I4 => \grant_r_reg[0]_1\,
      O => \rstdiv0_sync_r1_reg_rep__11\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[0]_i_1__3_n_0\,
      Q => \^q\(0),
      R => '0'
    );
\grant_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r_reg[1]_0\(0),
      Q => \^q\(1),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[2]_i_1__3_n_0\,
      Q => \^q\(2),
      R => '0'
    );
\grant_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[3]_i_1__0_n_0\,
      Q => \^q\(3),
      R => '0'
    );
\last_master_r[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => \^q\(0),
      I1 => last_master_r(0),
      I2 => cs_en2,
      I3 => \last_master_r_reg[0]_0\,
      O => \last_master_r[0]_i_1__2_n_0\
    );
\last_master_r[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => \^q\(1),
      I1 => last_master_r(1),
      I2 => cs_en2,
      I3 => \last_master_r_reg[0]_0\,
      O => \^grant_r_reg[2]_0\(0)
    );
\last_master_r[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => \^q\(2),
      I1 => last_master_r(2),
      I2 => cs_en2,
      I3 => \last_master_r_reg[0]_0\,
      O => \^grant_r_reg[2]_0\(1)
    );
\last_master_r[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEBA"
    )
        port map (
      I0 => \last_master_r_reg[0]_0\,
      I1 => cs_en2,
      I2 => last_master_r(3),
      I3 => \^q\(3),
      O => \last_master_r[3]_i_1__1_n_0\
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[0]_i_1__2_n_0\,
      Q => last_master_r(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^grant_r_reg[2]_0\(0),
      Q => last_master_r(1),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^grant_r_reg[2]_0\(1),
      Q => last_master_r(2),
      R => '0'
    );
\last_master_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[3]_i_1__1_n_0\,
      Q => last_master_r(3),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_5\ is
  port (
    granted_row_ns : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \req_row_r_lcl_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    granted_row_r_reg : out STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cs_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    act_this_rank : out STD_LOGIC;
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    \grant_r_reg[3]_1\ : out STD_LOGIC;
    \grant_r_reg[2]_0\ : in STD_LOGIC;
    row_cmd_wr : in STD_LOGIC_VECTOR ( 2 downto 0 );
    sent_row : in STD_LOGIC;
    \cmd_pipe_plus.mc_cs_n_reg[1]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[1]\ : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[25]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
    req_row_r : in STD_LOGIC_VECTOR ( 37 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_cas_n_reg[1]\ : in STD_LOGIC;
    maint_rank_r : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[1]_0\ : in STD_LOGIC;
    demand_act_priority_r : in STD_LOGIC;
    granted_row_r_reg_0 : in STD_LOGIC;
    granted_row_r_reg_1 : in STD_LOGIC;
    \grant_r_reg[3]_2\ : in STD_LOGIC;
    demand_act_priority_r_4 : in STD_LOGIC;
    demand_act_priority_r_5 : in STD_LOGIC;
    \grant_r_reg[3]_3\ : in STD_LOGIC;
    inhbt_act_faw_r : in STD_LOGIC;
    \grant_r[3]_i_4__0_0\ : in STD_LOGIC;
    \last_master_r_reg[3]_0\ : in STD_LOGIC;
    act_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    demand_act_priority_r_6 : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[5]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[5]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[5]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_5\ : entity is "mig_7series_v4_2_round_robin_arb";
end \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_5\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_5\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \cmd_pipe_plus.mc_address[13]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[14]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[15]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[16]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[17]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[18]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[19]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[20]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[21]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[22]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[23]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[24]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[25]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[3]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[4]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[5]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_cs_n[1]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_ras_n[1]_i_3_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_we_n[1]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_we_n[1]_i_3_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_we_n[1]_i_4_n_0\ : STD_LOGIC;
  signal \grant_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_2__3_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_4__2_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_10__0_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_13_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_14__0_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_15_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_3__2_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_5__1_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_9__0_n_0\ : STD_LOGIC;
  signal \^grant_r_reg[3]_0\ : STD_LOGIC;
  signal \^granted_row_r_reg\ : STD_LOGIC;
  signal \inhbt_act_faw.SRLC32E0_i_3_n_0\ : STD_LOGIC;
  signal last_master_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \last_master_r[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \last_master_r[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \last_master_r[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \last_master_r[3]_i_1__2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[24]_i_2\ : label is "soft_lutpair544";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_cas_n[1]_i_2\ : label is "soft_lutpair545";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_cs_n[1]_i_2\ : label is "soft_lutpair546";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_ras_n[1]_i_2\ : label is "soft_lutpair545";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_we_n[1]_i_4\ : label is "soft_lutpair544";
  attribute SOFT_HLUTNM of \inhbt_act_faw.SRLC32E0_i_3\ : label is "soft_lutpair546";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  \grant_r_reg[3]_0\ <= \^grant_r_reg[3]_0\;
  granted_row_r_reg <= \^granted_row_r_reg\;
\cmd_pipe_plus.mc_address[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDD000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address[13]_i_2_n_0\,
      I2 => \^q\(0),
      I3 => \cmd_pipe_plus.mc_address_reg[25]\(0),
      I4 => \^granted_row_r_reg\,
      O => \req_row_r_lcl_reg[12]\(0)
    );
\cmd_pipe_plus.mc_address[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => req_row_r(2),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => req_row_r(14),
      I4 => \^q\(3),
      I5 => req_row_r(26),
      O => \cmd_pipe_plus.mc_address[13]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F2F2F2F2F2000000"
    )
        port map (
      I0 => req_row_r(3),
      I1 => \cmd_pipe_plus.mc_we_n[1]_i_3_n_0\,
      I2 => \cmd_pipe_plus.mc_address[14]_i_2_n_0\,
      I3 => \^q\(0),
      I4 => \cmd_pipe_plus.mc_address_reg[25]\(1),
      I5 => \^granted_row_r_reg\,
      O => \req_row_r_lcl_reg[12]\(1)
    );
\cmd_pipe_plus.mc_address[14]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFD5D5D5"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => req_row_r(27),
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => req_row_r(15),
      O => \cmd_pipe_plus.mc_address[14]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDD000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address[15]_i_2_n_0\,
      I2 => \^q\(0),
      I3 => \cmd_pipe_plus.mc_address_reg[25]\(2),
      I4 => \^granted_row_r_reg\,
      O => \req_row_r_lcl_reg[12]\(2)
    );
\cmd_pipe_plus.mc_address[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => req_row_r(4),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => req_row_r(16),
      I4 => \^q\(3),
      I5 => req_row_r(28),
      O => \cmd_pipe_plus.mc_address[15]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDD000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address[16]_i_2_n_0\,
      I2 => \^q\(0),
      I3 => \cmd_pipe_plus.mc_address_reg[25]\(3),
      I4 => \^granted_row_r_reg\,
      O => \req_row_r_lcl_reg[12]\(3)
    );
\cmd_pipe_plus.mc_address[16]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => req_row_r(5),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => req_row_r(17),
      I4 => \^q\(3),
      I5 => req_row_r(29),
      O => \cmd_pipe_plus.mc_address[16]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDD000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address[17]_i_2_n_0\,
      I2 => \^q\(0),
      I3 => \cmd_pipe_plus.mc_address_reg[25]\(4),
      I4 => \^granted_row_r_reg\,
      O => \req_row_r_lcl_reg[12]\(4)
    );
\cmd_pipe_plus.mc_address[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => req_row_r(6),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => req_row_r(18),
      I4 => \^q\(3),
      I5 => req_row_r(30),
      O => \cmd_pipe_plus.mc_address[17]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F2F2F2F2F2000000"
    )
        port map (
      I0 => req_row_r(7),
      I1 => \cmd_pipe_plus.mc_we_n[1]_i_3_n_0\,
      I2 => \cmd_pipe_plus.mc_address[18]_i_2_n_0\,
      I3 => \^q\(0),
      I4 => \cmd_pipe_plus.mc_address_reg[25]\(5),
      I5 => \^granted_row_r_reg\,
      O => \req_row_r_lcl_reg[12]\(5)
    );
\cmd_pipe_plus.mc_address[18]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFD5D5D5"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => req_row_r(31),
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => req_row_r(19),
      O => \cmd_pipe_plus.mc_address[18]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDD000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address[19]_i_2_n_0\,
      I2 => \^q\(0),
      I3 => \cmd_pipe_plus.mc_address_reg[25]\(6),
      I4 => \^granted_row_r_reg\,
      O => \req_row_r_lcl_reg[12]\(6)
    );
\cmd_pipe_plus.mc_address[19]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => req_row_r(8),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => req_row_r(20),
      I4 => \^q\(3),
      I5 => req_row_r(32),
      O => \cmd_pipe_plus.mc_address[19]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDD000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address[20]_i_2_n_0\,
      I2 => \^q\(0),
      I3 => \cmd_pipe_plus.mc_address_reg[25]\(7),
      I4 => \^granted_row_r_reg\,
      O => \req_row_r_lcl_reg[12]\(7)
    );
\cmd_pipe_plus.mc_address[20]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => req_row_r(9),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => req_row_r(21),
      I4 => \^q\(3),
      I5 => req_row_r(33),
      O => \cmd_pipe_plus.mc_address[20]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F2F2F2F2F2000000"
    )
        port map (
      I0 => req_row_r(10),
      I1 => \cmd_pipe_plus.mc_we_n[1]_i_3_n_0\,
      I2 => \cmd_pipe_plus.mc_address[21]_i_2_n_0\,
      I3 => \^q\(0),
      I4 => \cmd_pipe_plus.mc_address_reg[25]\(8),
      I5 => \^granted_row_r_reg\,
      O => \req_row_r_lcl_reg[12]\(8)
    );
\cmd_pipe_plus.mc_address[21]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFD5D5D5"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => req_row_r(34),
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => req_row_r(22),
      O => \cmd_pipe_plus.mc_address[21]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDD000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address[22]_i_2_n_0\,
      I2 => \^q\(0),
      I3 => req_row_r(0),
      I4 => \^granted_row_r_reg\,
      O => \req_row_r_lcl_reg[12]\(9)
    );
\cmd_pipe_plus.mc_address[22]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => req_row_r(11),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => req_row_r(23),
      I4 => \^q\(3),
      I5 => req_row_r(35),
      O => \cmd_pipe_plus.mc_address[22]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDDDDDD00000000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address[23]_i_2_n_0\,
      I2 => \cmd_pipe_plus.mc_we_n[1]_i_3_n_0\,
      I3 => row_cmd_wr(0),
      I4 => req_row_r(12),
      I5 => \cmd_pipe_plus.mc_address_reg[23]\,
      O => \req_row_r_lcl_reg[12]\(10)
    );
\cmd_pipe_plus.mc_address[23]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00808000008080"
    )
        port map (
      I0 => \^q\(2),
      I1 => row_cmd_wr(1),
      I2 => req_row_r(24),
      I3 => row_cmd_wr(2),
      I4 => \^q\(3),
      I5 => req_row_r(36),
      O => \cmd_pipe_plus.mc_address[23]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F2F2F2F2F2000000"
    )
        port map (
      I0 => req_row_r(13),
      I1 => \cmd_pipe_plus.mc_we_n[1]_i_3_n_0\,
      I2 => \cmd_pipe_plus.mc_address[24]_i_2_n_0\,
      I3 => \^q\(0),
      I4 => req_row_r(1),
      I5 => \^granted_row_r_reg\,
      O => \req_row_r_lcl_reg[12]\(11)
    );
\cmd_pipe_plus.mc_address[24]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFD5D5D5"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => req_row_r(37),
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => req_row_r(25),
      O => \cmd_pipe_plus.mc_address[24]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDD000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_address[25]_i_2_n_0\,
      I2 => \cmd_pipe_plus.mc_address_reg[25]\(9),
      I3 => \^q\(0),
      I4 => \^granted_row_r_reg\,
      O => \req_row_r_lcl_reg[12]\(12)
    );
\cmd_pipe_plus.mc_address[25]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address_reg[25]\(10),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \cmd_pipe_plus.mc_address_reg[25]\(11),
      I4 => \^q\(3),
      I5 => \cmd_pipe_plus.mc_address_reg[25]\(12),
      O => \cmd_pipe_plus.mc_address[25]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDD000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_bank[3]_i_2_n_0\,
      I2 => \cmd_pipe_plus.mc_bank_reg[5]\(0),
      I3 => \^q\(0),
      I4 => \^granted_row_r_reg\,
      O => \req_bank_r_lcl_reg[2]\(0)
    );
\cmd_pipe_plus.mc_bank[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[5]_0\(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \cmd_pipe_plus.mc_bank_reg[5]_1\(0),
      I4 => \^q\(3),
      I5 => \cmd_pipe_plus.mc_bank_reg[5]_2\(0),
      O => \cmd_pipe_plus.mc_bank[3]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDD000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_bank[4]_i_2_n_0\,
      I2 => \cmd_pipe_plus.mc_bank_reg[5]\(1),
      I3 => \^q\(0),
      I4 => \^granted_row_r_reg\,
      O => \req_bank_r_lcl_reg[2]\(1)
    );
\cmd_pipe_plus.mc_bank[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[5]_0\(1),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \cmd_pipe_plus.mc_bank_reg[5]_1\(1),
      I4 => \^q\(3),
      I5 => \cmd_pipe_plus.mc_bank_reg[5]_2\(1),
      O => \cmd_pipe_plus.mc_bank[4]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDD000"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_bank[5]_i_2_n_0\,
      I2 => \cmd_pipe_plus.mc_bank_reg[5]\(2),
      I3 => \^q\(0),
      I4 => \^granted_row_r_reg\,
      O => \req_bank_r_lcl_reg[2]\(2)
    );
\cmd_pipe_plus.mc_bank[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC200000EC20"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank_reg[5]_0\(2),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \cmd_pipe_plus.mc_bank_reg[5]_1\(2),
      I4 => \^q\(3),
      I5 => \cmd_pipe_plus.mc_bank_reg[5]_2\(2),
      O => \cmd_pipe_plus.mc_bank[5]_i_2_n_0\
    );
\cmd_pipe_plus.mc_cas_n[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF0EFF00"
    )
        port map (
      I0 => maint_srx_r,
      I1 => maint_zq_r,
      I2 => \cmd_pipe_plus.mc_cas_n_reg[1]\,
      I3 => \^q\(0),
      I4 => \cmd_pipe_plus.mc_cs_n_reg[1]\,
      I5 => \^granted_row_r_reg\,
      O => mc_cas_n_ns(0)
    );
\cmd_pipe_plus.mc_cas_n[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF1"
    )
        port map (
      I0 => sent_row,
      I1 => \cmd_pipe_plus.mc_cs_n_reg[1]\,
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(3),
      O => \^granted_row_r_reg\
    );
\cmd_pipe_plus.mc_cs_n[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"020002000000FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_cs_n[1]_i_2_n_0\,
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_cas_n_reg[1]\,
      I3 => maint_rank_r,
      I4 => sent_row,
      I5 => \cmd_pipe_plus.mc_cs_n_reg[1]\,
      O => mc_cs_n_ns(0)
    );
\cmd_pipe_plus.mc_cs_n[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(1),
      O => \cmd_pipe_plus.mc_cs_n[1]_i_2_n_0\
    );
\cmd_pipe_plus.mc_ras_n[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F0F0101010101"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_cs_n_reg[1]\,
      I1 => sent_row,
      I2 => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\,
      I3 => maint_srx_r,
      I4 => maint_zq_r,
      I5 => \cmd_pipe_plus.mc_ras_n[1]_i_3_n_0\,
      O => mc_ras_n_ns(0)
    );
\cmd_pipe_plus.mc_ras_n[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFEFE00"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(3),
      I3 => sent_row,
      I4 => \cmd_pipe_plus.mc_cs_n_reg[1]\,
      O => \cmd_pipe_plus.mc_ras_n[1]_i_2_n_0\
    );
\cmd_pipe_plus.mc_ras_n[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_cas_n_reg[1]\,
      I1 => \^q\(0),
      I2 => \cmd_pipe_plus.mc_cs_n_reg[1]\,
      O => \cmd_pipe_plus.mc_ras_n[1]_i_3_n_0\
    );
\cmd_pipe_plus.mc_we_n[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAEAEFFFFFFFFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n[1]_i_2_n_0\,
      I1 => row_cmd_wr(0),
      I2 => \cmd_pipe_plus.mc_we_n[1]_i_3_n_0\,
      I3 => sent_row,
      I4 => \cmd_pipe_plus.mc_cs_n_reg[1]\,
      I5 => \cmd_pipe_plus.mc_we_n_reg[1]\,
      O => act_wait_r_lcl_reg(0)
    );
\cmd_pipe_plus.mc_we_n[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D0C5D0CFF0C5D0C"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n_reg[1]_0\,
      I1 => row_cmd_wr(1),
      I2 => \cmd_pipe_plus.mc_we_n[1]_i_4_n_0\,
      I3 => \cmd_pipe_plus.mc_cs_n[1]_i_2_n_0\,
      I4 => \cmd_pipe_plus.mc_ras_n[1]_i_3_n_0\,
      I5 => maint_zq_r,
      O => \cmd_pipe_plus.mc_we_n[1]_i_2_n_0\
    );
\cmd_pipe_plus.mc_we_n[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(3),
      O => \cmd_pipe_plus.mc_we_n[1]_i_3_n_0\
    );
\cmd_pipe_plus.mc_we_n[1]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      O => \cmd_pipe_plus.mc_we_n[1]_i_4_n_0\
    );
\grant_r[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000444440004"
    )
        port map (
      I0 => \grant_r[2]_i_3__0_n_0\,
      I1 => \grant_r[2]_i_2__3_n_0\,
      I2 => \last_master_r[0]_i_1__3_n_0\,
      I3 => \last_master_r[1]_i_1__3_n_0\,
      I4 => \grant_r[3]_i_3__2_n_0\,
      I5 => \grant_r[3]_i_4__0_n_0\,
      O => \grant_r[0]_i_1__2_n_0\
    );
\grant_r[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"400040004000F000"
    )
        port map (
      I0 => \grant_r[3]_i_4__0_n_0\,
      I1 => \grant_r[2]_i_3__0_n_0\,
      I2 => \grant_r_reg[2]_0\,
      I3 => \grant_r[3]_i_5__1_n_0\,
      I4 => \last_master_r[1]_i_1__3_n_0\,
      I5 => \last_master_r[2]_i_1__3_n_0\,
      O => \grant_r[1]_i_1__2_n_0\
    );
\grant_r[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000444440004"
    )
        port map (
      I0 => \grant_r[3]_i_3__2_n_0\,
      I1 => \grant_r[2]_i_2__3_n_0\,
      I2 => \last_master_r[2]_i_1__3_n_0\,
      I3 => \last_master_r[3]_i_1__2_n_0\,
      I4 => \grant_r[2]_i_3__0_n_0\,
      I5 => \grant_r_reg[2]_0\,
      O => \grant_r[2]_i_1__2_n_0\
    );
\grant_r[2]_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \last_master_r[2]_i_1__3_n_0\,
      I1 => \grant_r[3]_i_4__0_n_0\,
      I2 => \last_master_r[0]_i_1__3_n_0\,
      I3 => \grant_r_reg[2]_0\,
      O => \grant_r[2]_i_2__3_n_0\
    );
\grant_r[2]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF2FF"
    )
        port map (
      I0 => \grant_r[2]_i_4__2_n_0\,
      I1 => demand_act_priority_r,
      I2 => \^q\(0),
      I3 => granted_row_r_reg_0,
      I4 => \grant_r[3]_i_10__0_n_0\,
      I5 => granted_row_r_reg_1,
      O => \grant_r[2]_i_3__0_n_0\
    );
\grant_r[2]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22F2FFFF22F222F2"
    )
        port map (
      I0 => demand_act_priority_r_5,
      I1 => \^q\(2),
      I2 => demand_act_priority_r_6,
      I3 => \^q\(1),
      I4 => \^q\(3),
      I5 => demand_act_priority_r_4,
      O => \grant_r[2]_i_4__2_n_0\
    );
\grant_r[3]_i_10__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF8FFF8FFF8"
    )
        port map (
      I0 => row_cmd_wr(2),
      I1 => \^q\(3),
      I2 => \grant_r[3]_i_4__0_0\,
      I3 => inhbt_act_faw_r,
      I4 => \^q\(1),
      I5 => row_cmd_wr(0),
      O => \grant_r[3]_i_10__0_n_0\
    );
\grant_r[3]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD0D0000DD0DDD0D"
    )
        port map (
      I0 => demand_act_priority_r,
      I1 => \^q\(0),
      I2 => demand_act_priority_r_6,
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => demand_act_priority_r_5,
      O => \grant_r[3]_i_13_n_0\
    );
\grant_r[3]_i_14__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000777"
    )
        port map (
      I0 => row_cmd_wr(0),
      I1 => \^q\(1),
      I2 => row_cmd_wr(1),
      I3 => \^q\(2),
      I4 => inhbt_act_faw_r,
      I5 => \grant_r[3]_i_4__0_0\,
      O => \grant_r[3]_i_14__0_n_0\
    );
\grant_r[3]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FFB8"
    )
        port map (
      I0 => \^q\(3),
      I1 => sent_row,
      I2 => last_master_r(3),
      I3 => \cmd_pipe_plus.mc_cas_n_reg[1]\,
      I4 => \grant_r[2]_i_3__0_n_0\,
      O => \grant_r[3]_i_15_n_0\
    );
\grant_r[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"400040004000F000"
    )
        port map (
      I0 => \grant_r_reg[2]_0\,
      I1 => \grant_r[3]_i_3__2_n_0\,
      I2 => \grant_r[3]_i_4__0_n_0\,
      I3 => \grant_r[3]_i_5__1_n_0\,
      I4 => \last_master_r[0]_i_1__3_n_0\,
      I5 => \last_master_r[3]_i_1__2_n_0\,
      O => \grant_r[3]_i_1__2_n_0\
    );
\grant_r[3]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF1FF"
    )
        port map (
      I0 => demand_act_priority_r_5,
      I1 => \grant_r[3]_i_9__0_n_0\,
      I2 => \^q\(2),
      I3 => \cmd_pipe_plus.mc_we_n_reg[1]_0\,
      I4 => \grant_r[3]_i_10__0_n_0\,
      I5 => \grant_r_reg[3]_3\,
      O => \grant_r[3]_i_3__2_n_0\
    );
\grant_r[3]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000540000000000"
    )
        port map (
      I0 => \grant_r_reg[3]_2\,
      I1 => demand_act_priority_r_4,
      I2 => \grant_r[3]_i_13_n_0\,
      I3 => \cmd_pipe_plus.mc_we_n_reg[1]_0\,
      I4 => \^q\(3),
      I5 => \grant_r[3]_i_14__0_n_0\,
      O => \grant_r[3]_i_4__0_n_0\
    );
\grant_r[3]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF0000FF47"
    )
        port map (
      I0 => \^q\(1),
      I1 => sent_row,
      I2 => last_master_r(1),
      I3 => \cmd_pipe_plus.mc_cas_n_reg[1]\,
      I4 => \grant_r[3]_i_15_n_0\,
      I5 => \grant_r[3]_i_3__2_n_0\,
      O => \grant_r[3]_i_5__1_n_0\
    );
\grant_r[3]_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B0BB"
    )
        port map (
      I0 => \^q\(3),
      I1 => demand_act_priority_r_4,
      I2 => \^q\(0),
      I3 => demand_act_priority_r,
      O => \grant_r_reg[3]_1\
    );
\grant_r[3]_i_9__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD0D0000DD0DDD0D"
    )
        port map (
      I0 => demand_act_priority_r,
      I1 => \^q\(0),
      I2 => demand_act_priority_r_4,
      I3 => \^q\(3),
      I4 => \^q\(1),
      I5 => demand_act_priority_r_6,
      O => \grant_r[3]_i_9__0_n_0\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[0]_i_1__2_n_0\,
      Q => \^q\(0),
      R => '0'
    );
\grant_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[1]_i_1__2_n_0\,
      Q => \^q\(1),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[2]_i_1__2_n_0\,
      Q => \^q\(2),
      R => '0'
    );
\grant_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[3]_i_1__2_n_0\,
      Q => \^q\(3),
      R => '0'
    );
granted_row_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \grant_r_reg[2]_0\,
      I1 => \grant_r[3]_i_3__2_n_0\,
      I2 => \grant_r[3]_i_4__0_n_0\,
      I3 => \grant_r[2]_i_3__0_n_0\,
      O => granted_row_ns
    );
\inhbt_act_faw.SRLC32E0_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^grant_r_reg[3]_0\,
      O => act_this_rank
    );
\inhbt_act_faw.SRLC32E0_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000777"
    )
        port map (
      I0 => \^q\(3),
      I1 => act_this_rank_r(3),
      I2 => \^q\(0),
      I3 => act_this_rank_r(0),
      I4 => \inhbt_act_faw.SRLC32E0_i_3_n_0\,
      O => \^grant_r_reg[3]_0\
    );
\inhbt_act_faw.SRLC32E0_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => act_this_rank_r(2),
      I1 => \^q\(2),
      I2 => act_this_rank_r(1),
      I3 => \^q\(1),
      O => \inhbt_act_faw.SRLC32E0_i_3_n_0\
    );
\last_master_r[0]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00B8"
    )
        port map (
      I0 => \^q\(0),
      I1 => sent_row,
      I2 => last_master_r(0),
      I3 => \last_master_r_reg[3]_0\,
      O => \last_master_r[0]_i_1__3_n_0\
    );
\last_master_r[1]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00B8"
    )
        port map (
      I0 => \^q\(1),
      I1 => sent_row,
      I2 => last_master_r(1),
      I3 => \last_master_r_reg[3]_0\,
      O => \last_master_r[1]_i_1__3_n_0\
    );
\last_master_r[2]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00B8"
    )
        port map (
      I0 => \^q\(2),
      I1 => sent_row,
      I2 => last_master_r(2),
      I3 => \last_master_r_reg[3]_0\,
      O => \last_master_r[2]_i_1__3_n_0\
    );
\last_master_r[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAE"
    )
        port map (
      I0 => \last_master_r_reg[3]_0\,
      I1 => last_master_r(3),
      I2 => sent_row,
      I3 => \^q\(3),
      O => \last_master_r[3]_i_1__2_n_0\
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[0]_i_1__3_n_0\,
      Q => last_master_r(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[1]_i_1__3_n_0\,
      Q => last_master_r(1),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[2]_i_1__3_n_0\,
      Q => last_master_r(2),
      R => '0'
    );
\last_master_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[3]_i_1__2_n_0\,
      Q => last_master_r(3),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_tempmon is
  port (
    device_temp_sync_r4_neq_r3 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 11 downto 0 );
    device_temp_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
    \device_temp_sync_r5_reg[11]_0\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_tempmon : entity is "mig_7series_v4_2_tempmon";
end mig_7series_0_mig_7series_v4_2_tempmon;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_tempmon is
  signal \device_temp_101[11]_i_2_n_0\ : STD_LOGIC;
  signal \device_temp_101[11]_i_4_n_0\ : STD_LOGIC;
  signal \device_temp_101[11]_i_5_n_0\ : STD_LOGIC;
  signal device_temp_lcl : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal device_temp_r : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg : string;
  attribute async_reg of device_temp_r : signal is "true";
  signal \device_temp_r[11]_i_1_n_0\ : STD_LOGIC;
  signal device_temp_sync_r1 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r1 : signal is "true";
  signal device_temp_sync_r2 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r2 : signal is "true";
  signal device_temp_sync_r3 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r3 : signal is "true";
  attribute syn_srlstyle : string;
  attribute syn_srlstyle of device_temp_sync_r3 : signal is "registers";
  signal device_temp_sync_r4 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r4 : signal is "true";
  signal device_temp_sync_r4_neq_r3_i_2_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_i_3_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_i_4_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_i_5_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_reg_i_1_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_reg_i_1_n_1 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_reg_i_1_n_2 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_reg_i_1_n_3 : STD_LOGIC;
  signal device_temp_sync_r5 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r5 : signal is "true";
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \sync_cntr[2]_i_1_n_0\ : STD_LOGIC;
  signal \sync_cntr[3]_i_2_n_0\ : STD_LOGIC;
  signal sync_cntr_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\ : STD_LOGIC;
  signal NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \device_temp_r_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \device_temp_r_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[0]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[0]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[10]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[10]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[11]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[11]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[1]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[1]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[2]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[2]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[3]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[3]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[4]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[4]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[5]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[5]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[6]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[6]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[7]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[7]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[8]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[8]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[9]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[9]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \sync_cntr[0]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \sync_cntr[1]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \sync_cntr[2]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \sync_cntr[3]_i_3\ : label is "soft_lutpair0";
begin
  device_temp_lcl(11 downto 0) <= device_temp_i(11 downto 0);
\device_temp_101[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(0),
      O => D(0)
    );
\device_temp_101[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      O => D(10)
    );
\device_temp_101[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(11),
      O => D(11)
    );
\device_temp_101[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA88888"
    )
        port map (
      I0 => device_temp_r(11),
      I1 => device_temp_r(9),
      I2 => device_temp_r(6),
      I3 => \device_temp_101[11]_i_4_n_0\,
      I4 => device_temp_r(7),
      I5 => device_temp_r(8),
      O => \device_temp_101[11]_i_2_n_0\
    );
\device_temp_101[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0100FFFF"
    )
        port map (
      I0 => device_temp_r(8),
      I1 => device_temp_r(10),
      I2 => device_temp_r(9),
      I3 => \device_temp_101[11]_i_5_n_0\,
      I4 => device_temp_r(11),
      O => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\
    );
\device_temp_101[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA88888"
    )
        port map (
      I0 => device_temp_r(5),
      I1 => device_temp_r(4),
      I2 => device_temp_r(1),
      I3 => device_temp_r(0),
      I4 => device_temp_r(2),
      I5 => device_temp_r(3),
      O => \device_temp_101[11]_i_4_n_0\
    );
\device_temp_101[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00155555FFFFFFFF"
    )
        port map (
      I0 => device_temp_r(6),
      I1 => device_temp_r(2),
      I2 => device_temp_r(3),
      I3 => device_temp_r(4),
      I4 => device_temp_r(5),
      I5 => device_temp_r(7),
      O => \device_temp_101[11]_i_5_n_0\
    );
\device_temp_101[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(1),
      O => D(1)
    );
\device_temp_101[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(2),
      O => D(2)
    );
\device_temp_101[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7F0"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(3),
      O => D(3)
    );
\device_temp_101[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(4),
      O => D(4)
    );
\device_temp_101[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(5),
      O => D(5)
    );
\device_temp_101[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(6),
      O => D(6)
    );
\device_temp_101[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(7),
      O => D(7)
    );
\device_temp_101[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(8),
      O => D(8)
    );
\device_temp_101[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => device_temp_r(10),
      I1 => \device_temp_101[11]_i_2_n_0\,
      I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I3 => device_temp_r(9),
      O => D(9)
    );
\device_temp_r[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => sync_cntr_reg(1),
      I1 => sync_cntr_reg(0),
      I2 => sync_cntr_reg(3),
      I3 => sync_cntr_reg(2),
      O => \device_temp_r[11]_i_1_n_0\
    );
\device_temp_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(0),
      Q => device_temp_r(0),
      R => '0'
    );
\device_temp_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(10),
      Q => device_temp_r(10),
      R => '0'
    );
\device_temp_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(11),
      Q => device_temp_r(11),
      R => '0'
    );
\device_temp_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(1),
      Q => device_temp_r(1),
      R => '0'
    );
\device_temp_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(2),
      Q => device_temp_r(2),
      R => '0'
    );
\device_temp_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(3),
      Q => device_temp_r(3),
      R => '0'
    );
\device_temp_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(4),
      Q => device_temp_r(4),
      R => '0'
    );
\device_temp_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(5),
      Q => device_temp_r(5),
      R => '0'
    );
\device_temp_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(6),
      Q => device_temp_r(6),
      R => '0'
    );
\device_temp_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(7),
      Q => device_temp_r(7),
      R => '0'
    );
\device_temp_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(8),
      Q => device_temp_r(8),
      R => '0'
    );
\device_temp_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(9),
      Q => device_temp_r(9),
      R => '0'
    );
\device_temp_sync_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_lcl(0),
      Q => device_temp_sync_r1(0),
      R => '0'
    );
\device_temp_sync_r1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_lcl(10),
      Q => device_temp_sync_r1(10),
      R => '0'
    );
\device_temp_sync_r1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_lcl(11),
      Q => device_temp_sync_r1(11),
      R => '0'
    );
\device_temp_sync_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_lcl(1),
      Q => device_temp_sync_r1(1),
      R => '0'
    );
\device_temp_sync_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_lcl(2),
      Q => device_temp_sync_r1(2),
      R => '0'
    );
\device_temp_sync_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_lcl(3),
      Q => device_temp_sync_r1(3),
      R => '0'
    );
\device_temp_sync_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_lcl(4),
      Q => device_temp_sync_r1(4),
      R => '0'
    );
\device_temp_sync_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_lcl(5),
      Q => device_temp_sync_r1(5),
      R => '0'
    );
\device_temp_sync_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_lcl(6),
      Q => device_temp_sync_r1(6),
      R => '0'
    );
\device_temp_sync_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_lcl(7),
      Q => device_temp_sync_r1(7),
      R => '0'
    );
\device_temp_sync_r1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_lcl(8),
      Q => device_temp_sync_r1(8),
      R => '0'
    );
\device_temp_sync_r1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_lcl(9),
      Q => device_temp_sync_r1(9),
      R => '0'
    );
\device_temp_sync_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r1(0),
      Q => device_temp_sync_r2(0),
      R => '0'
    );
\device_temp_sync_r2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r1(10),
      Q => device_temp_sync_r2(10),
      R => '0'
    );
\device_temp_sync_r2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r1(11),
      Q => device_temp_sync_r2(11),
      R => '0'
    );
\device_temp_sync_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r1(1),
      Q => device_temp_sync_r2(1),
      R => '0'
    );
\device_temp_sync_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r1(2),
      Q => device_temp_sync_r2(2),
      R => '0'
    );
\device_temp_sync_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r1(3),
      Q => device_temp_sync_r2(3),
      R => '0'
    );
\device_temp_sync_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r1(4),
      Q => device_temp_sync_r2(4),
      R => '0'
    );
\device_temp_sync_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r1(5),
      Q => device_temp_sync_r2(5),
      R => '0'
    );
\device_temp_sync_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r1(6),
      Q => device_temp_sync_r2(6),
      R => '0'
    );
\device_temp_sync_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r1(7),
      Q => device_temp_sync_r2(7),
      R => '0'
    );
\device_temp_sync_r2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r1(8),
      Q => device_temp_sync_r2(8),
      R => '0'
    );
\device_temp_sync_r2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r1(9),
      Q => device_temp_sync_r2(9),
      R => '0'
    );
\device_temp_sync_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r2(0),
      Q => device_temp_sync_r3(0),
      R => '0'
    );
\device_temp_sync_r3_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r2(10),
      Q => device_temp_sync_r3(10),
      R => '0'
    );
\device_temp_sync_r3_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r2(11),
      Q => device_temp_sync_r3(11),
      R => '0'
    );
\device_temp_sync_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r2(1),
      Q => device_temp_sync_r3(1),
      R => '0'
    );
\device_temp_sync_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r2(2),
      Q => device_temp_sync_r3(2),
      R => '0'
    );
\device_temp_sync_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r2(3),
      Q => device_temp_sync_r3(3),
      R => '0'
    );
\device_temp_sync_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r2(4),
      Q => device_temp_sync_r3(4),
      R => '0'
    );
\device_temp_sync_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r2(5),
      Q => device_temp_sync_r3(5),
      R => '0'
    );
\device_temp_sync_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r2(6),
      Q => device_temp_sync_r3(6),
      R => '0'
    );
\device_temp_sync_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r2(7),
      Q => device_temp_sync_r3(7),
      R => '0'
    );
\device_temp_sync_r3_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r2(8),
      Q => device_temp_sync_r3(8),
      R => '0'
    );
\device_temp_sync_r3_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r2(9),
      Q => device_temp_sync_r3(9),
      R => '0'
    );
device_temp_sync_r4_neq_r3_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => device_temp_sync_r4(9),
      I1 => device_temp_sync_r3(9),
      I2 => device_temp_sync_r3(11),
      I3 => device_temp_sync_r4(11),
      I4 => device_temp_sync_r3(10),
      I5 => device_temp_sync_r4(10),
      O => device_temp_sync_r4_neq_r3_i_2_n_0
    );
device_temp_sync_r4_neq_r3_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => device_temp_sync_r4(6),
      I1 => device_temp_sync_r3(6),
      I2 => device_temp_sync_r3(8),
      I3 => device_temp_sync_r4(8),
      I4 => device_temp_sync_r3(7),
      I5 => device_temp_sync_r4(7),
      O => device_temp_sync_r4_neq_r3_i_3_n_0
    );
device_temp_sync_r4_neq_r3_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => device_temp_sync_r4(3),
      I1 => device_temp_sync_r3(3),
      I2 => device_temp_sync_r3(5),
      I3 => device_temp_sync_r4(5),
      I4 => device_temp_sync_r3(4),
      I5 => device_temp_sync_r4(4),
      O => device_temp_sync_r4_neq_r3_i_4_n_0
    );
device_temp_sync_r4_neq_r3_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => device_temp_sync_r4(0),
      I1 => device_temp_sync_r3(0),
      I2 => device_temp_sync_r3(2),
      I3 => device_temp_sync_r4(2),
      I4 => device_temp_sync_r3(1),
      I5 => device_temp_sync_r4(1),
      O => device_temp_sync_r4_neq_r3_i_5_n_0
    );
device_temp_sync_r4_neq_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4_neq_r3_reg_i_1_n_0,
      Q => device_temp_sync_r4_neq_r3,
      R => '0'
    );
device_temp_sync_r4_neq_r3_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => device_temp_sync_r4_neq_r3_reg_i_1_n_0,
      CO(2) => device_temp_sync_r4_neq_r3_reg_i_1_n_1,
      CO(1) => device_temp_sync_r4_neq_r3_reg_i_1_n_2,
      CO(0) => device_temp_sync_r4_neq_r3_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3 downto 0) => NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3) => device_temp_sync_r4_neq_r3_i_2_n_0,
      S(2) => device_temp_sync_r4_neq_r3_i_3_n_0,
      S(1) => device_temp_sync_r4_neq_r3_i_4_n_0,
      S(0) => device_temp_sync_r4_neq_r3_i_5_n_0
    );
\device_temp_sync_r4_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r3(0),
      Q => device_temp_sync_r4(0),
      R => '0'
    );
\device_temp_sync_r4_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r3(10),
      Q => device_temp_sync_r4(10),
      R => '0'
    );
\device_temp_sync_r4_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r3(11),
      Q => device_temp_sync_r4(11),
      R => '0'
    );
\device_temp_sync_r4_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r3(1),
      Q => device_temp_sync_r4(1),
      R => '0'
    );
\device_temp_sync_r4_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r3(2),
      Q => device_temp_sync_r4(2),
      R => '0'
    );
\device_temp_sync_r4_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r3(3),
      Q => device_temp_sync_r4(3),
      R => '0'
    );
\device_temp_sync_r4_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r3(4),
      Q => device_temp_sync_r4(4),
      R => '0'
    );
\device_temp_sync_r4_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r3(5),
      Q => device_temp_sync_r4(5),
      R => '0'
    );
\device_temp_sync_r4_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r3(6),
      Q => device_temp_sync_r4(6),
      R => '0'
    );
\device_temp_sync_r4_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r3(7),
      Q => device_temp_sync_r4(7),
      R => '0'
    );
\device_temp_sync_r4_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r3(8),
      Q => device_temp_sync_r4(8),
      R => '0'
    );
\device_temp_sync_r4_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r3(9),
      Q => device_temp_sync_r4(9),
      R => '0'
    );
\device_temp_sync_r5_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4(0),
      Q => device_temp_sync_r5(0),
      R => '0'
    );
\device_temp_sync_r5_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4(10),
      Q => device_temp_sync_r5(10),
      R => '0'
    );
\device_temp_sync_r5_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4(11),
      Q => device_temp_sync_r5(11),
      R => '0'
    );
\device_temp_sync_r5_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4(1),
      Q => device_temp_sync_r5(1),
      R => '0'
    );
\device_temp_sync_r5_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4(2),
      Q => device_temp_sync_r5(2),
      R => '0'
    );
\device_temp_sync_r5_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4(3),
      Q => device_temp_sync_r5(3),
      R => '0'
    );
\device_temp_sync_r5_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4(4),
      Q => device_temp_sync_r5(4),
      R => '0'
    );
\device_temp_sync_r5_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4(5),
      Q => device_temp_sync_r5(5),
      R => '0'
    );
\device_temp_sync_r5_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4(6),
      Q => device_temp_sync_r5(6),
      R => '0'
    );
\device_temp_sync_r5_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4(7),
      Q => device_temp_sync_r5(7),
      R => '0'
    );
\device_temp_sync_r5_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4(8),
      Q => device_temp_sync_r5(8),
      R => '0'
    );
\device_temp_sync_r5_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => '1',
      D => device_temp_sync_r4(9),
      Q => device_temp_sync_r5(9),
      R => '0'
    );
\sync_cntr[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sync_cntr_reg(0),
      O => \p_0_in__0\(0)
    );
\sync_cntr[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => sync_cntr_reg(0),
      I1 => sync_cntr_reg(1),
      O => \p_0_in__0\(1)
    );
\sync_cntr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => sync_cntr_reg(1),
      I1 => sync_cntr_reg(0),
      I2 => sync_cntr_reg(2),
      O => \sync_cntr[2]_i_1_n_0\
    );
\sync_cntr[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => sync_cntr_reg(2),
      I1 => sync_cntr_reg(3),
      I2 => sync_cntr_reg(0),
      I3 => sync_cntr_reg(1),
      O => \sync_cntr[3]_i_2_n_0\
    );
\sync_cntr[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => sync_cntr_reg(0),
      I1 => sync_cntr_reg(1),
      I2 => sync_cntr_reg(2),
      I3 => sync_cntr_reg(3),
      O => \p_0_in__0\(3)
    );
\sync_cntr_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \sync_cntr[3]_i_2_n_0\,
      D => \p_0_in__0\(0),
      Q => sync_cntr_reg(0),
      R => SR(0)
    );
\sync_cntr_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \sync_cntr[3]_i_2_n_0\,
      D => \p_0_in__0\(1),
      Q => sync_cntr_reg(1),
      R => SR(0)
    );
\sync_cntr_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \sync_cntr[3]_i_2_n_0\,
      D => \sync_cntr[2]_i_1_n_0\,
      Q => sync_cntr_reg(2),
      R => SR(0)
    );
\sync_cntr_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \device_temp_sync_r5_reg[11]_0\,
      CE => \sync_cntr[3]_i_2_n_0\,
      D => \p_0_in__0\(3),
      Q => sync_cntr_reg(3),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ui_cmd is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    app_en_r2_reg_0 : out STD_LOGIC;
    \app_addr_r2_reg[22]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r2_reg[22]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r2_reg[22]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r2_reg[22]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_145_out : out STD_LOGIC;
    p_28_out : out STD_LOGIC;
    p_67_out : out STD_LOGIC;
    p_106_out : out STD_LOGIC;
    app_cmd_r2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \app_cmd_r2_reg[0]_0\ : out STD_LOGIC;
    was_wr0 : out STD_LOGIC;
    S : out STD_LOGIC_VECTOR ( 2 downto 0 );
    row : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \app_addr_r1_reg[23]_0\ : out STD_LOGIC;
    \app_addr_r1_reg[25]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    req_wr_r_lcl0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    use_addr : out STD_LOGIC;
    app_en_r2_reg_1 : out STD_LOGIC;
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0]\ : out STD_LOGIC;
    \strict_mode.rd_data_buf_addr_r_lcl_reg[1]\ : out STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[0]\ : out STD_LOGIC;
    \read_data_indx.rd_data_upd_indx_r_reg\ : out STD_LOGIC;
    wr_accepted : out STD_LOGIC;
    \app_addr_r1_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    app_rdy_ns : in STD_LOGIC;
    CLK : in STD_LOGIC;
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
    rb_hit_busy_r_reg : in STD_LOGIC;
    req_bank_r : in STD_LOGIC_VECTOR ( 11 downto 0 );
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r_reg_2 : in STD_LOGIC;
    periodic_rd_r : in STD_LOGIC;
    periodic_rd_cntr_r : in STD_LOGIC;
    periodic_rd_ack_r : in STD_LOGIC;
    app_en : in STD_LOGIC;
    \app_addr_r1_reg[0]_0\ : in STD_LOGIC;
    wr_data_buf_addr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \strict_mode.rd_data_buf_addr_r_lcl\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \wr_req_counter.wr_req_cnt_r\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    app_addr : in STD_LOGIC_VECTOR ( 25 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ui_cmd : entity is "mig_7series_v4_2_ui_cmd";
end mig_7series_0_mig_7series_v4_2_ui_cmd;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ui_cmd is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal app_addr_r10 : STD_LOGIC;
  signal \^app_addr_r1_reg[23]_0\ : STD_LOGIC;
  signal \^app_addr_r1_reg[25]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \app_addr_r1_reg_n_0_[0]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[10]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[11]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[12]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[13]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[14]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[15]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[16]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[17]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[18]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[19]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[1]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[20]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[21]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[22]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[2]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[3]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[4]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[5]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[6]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[7]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[8]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[9]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[0]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[10]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[11]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[12]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[13]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[14]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[15]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[16]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[17]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[18]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[19]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[1]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[20]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[21]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[22]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[2]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[3]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[4]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[5]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[6]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[7]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[8]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[9]\ : STD_LOGIC;
  signal app_cmd_r1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^app_cmd_r2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^app_cmd_r2_reg[0]_0\ : STD_LOGIC;
  signal app_en_ns1 : STD_LOGIC;
  signal app_en_ns2 : STD_LOGIC;
  signal app_en_r1 : STD_LOGIC;
  signal \^app_en_r2_reg_0\ : STD_LOGIC;
  signal p_0_in_0 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal p_1_in : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rb_hit_busy_r_i_2__0_n_0\ : STD_LOGIC;
  signal \rb_hit_busy_r_i_2__1_n_0\ : STD_LOGIC;
  signal \rb_hit_busy_r_i_2__2_n_0\ : STD_LOGIC;
  signal rb_hit_busy_r_i_2_n_0 : STD_LOGIC;
  signal req_wr_r_lcl_i_2_n_0 : STD_LOGIC;
  signal \^row\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \^strict_mode.rd_data_buf_addr_r_lcl_reg[0]\ : STD_LOGIC;
  signal \^strict_mode.rd_data_buf_addr_r_lcl_reg[1]\ : STD_LOGIC;
  signal \^use_addr\ : STD_LOGIC;
  signal \write__0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of app_en_r1_i_1 : label is "soft_lutpair616";
  attribute SOFT_HLUTNM of app_en_r2_i_1 : label is "soft_lutpair616";
  attribute syn_maxfan : string;
  attribute syn_maxfan of app_rdy_r_reg : label is "10";
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1\ : label is "soft_lutpair614";
  attribute SOFT_HLUTNM of \req_bank_r_lcl[0]_i_1\ : label is "soft_lutpair623";
  attribute SOFT_HLUTNM of \req_bank_r_lcl[1]_i_1\ : label is "soft_lutpair624";
  attribute SOFT_HLUTNM of \req_bank_r_lcl[2]_i_1\ : label is "soft_lutpair620";
  attribute SOFT_HLUTNM of \req_col_r[0]_i_1\ : label is "soft_lutpair626";
  attribute SOFT_HLUTNM of \req_col_r[1]_i_1\ : label is "soft_lutpair629";
  attribute SOFT_HLUTNM of \req_col_r[2]_i_1\ : label is "soft_lutpair629";
  attribute SOFT_HLUTNM of \req_col_r[3]_i_1\ : label is "soft_lutpair628";
  attribute SOFT_HLUTNM of \req_col_r[4]_i_1\ : label is "soft_lutpair628";
  attribute SOFT_HLUTNM of \req_col_r[5]_i_1\ : label is "soft_lutpair627";
  attribute SOFT_HLUTNM of \req_col_r[6]_i_1\ : label is "soft_lutpair625";
  attribute SOFT_HLUTNM of \req_col_r[7]_i_1\ : label is "soft_lutpair624";
  attribute SOFT_HLUTNM of \req_col_r[8]_i_1\ : label is "soft_lutpair627";
  attribute SOFT_HLUTNM of \req_col_r[9]_i_1\ : label is "soft_lutpair626";
  attribute SOFT_HLUTNM of \req_data_buf_addr_r[0]_i_2\ : label is "soft_lutpair615";
  attribute SOFT_HLUTNM of \req_data_buf_addr_r[1]_i_1\ : label is "soft_lutpair613";
  attribute SOFT_HLUTNM of \req_data_buf_addr_r[3]_i_2\ : label is "soft_lutpair613";
  attribute SOFT_HLUTNM of \req_row_r_lcl[0]_i_1\ : label is "soft_lutpair619";
  attribute SOFT_HLUTNM of \req_row_r_lcl[10]_i_1\ : label is "soft_lutpair623";
  attribute SOFT_HLUTNM of \req_row_r_lcl[11]_i_1\ : label is "soft_lutpair622";
  attribute SOFT_HLUTNM of \req_row_r_lcl[12]_i_1\ : label is "soft_lutpair625";
  attribute SOFT_HLUTNM of \req_row_r_lcl[1]_i_1\ : label is "soft_lutpair621";
  attribute SOFT_HLUTNM of \req_row_r_lcl[2]_i_1\ : label is "soft_lutpair620";
  attribute SOFT_HLUTNM of \req_row_r_lcl[3]_i_1\ : label is "soft_lutpair619";
  attribute SOFT_HLUTNM of \req_row_r_lcl[4]_i_1\ : label is "soft_lutpair618";
  attribute SOFT_HLUTNM of \req_row_r_lcl[5]_i_1\ : label is "soft_lutpair617";
  attribute SOFT_HLUTNM of \req_row_r_lcl[6]_i_1\ : label is "soft_lutpair621";
  attribute SOFT_HLUTNM of \req_row_r_lcl[7]_i_1\ : label is "soft_lutpair617";
  attribute SOFT_HLUTNM of \req_row_r_lcl[8]_i_1\ : label is "soft_lutpair618";
  attribute SOFT_HLUTNM of \req_row_r_lcl[9]_i_1\ : label is "soft_lutpair622";
  attribute SOFT_HLUTNM of \strict_mode.rd_data_buf_addr_r_lcl[0]_i_1\ : label is "soft_lutpair614";
  attribute SOFT_HLUTNM of \wr_req_counter.wr_req_cnt_r[4]_i_3\ : label is "soft_lutpair615";
begin
  E(0) <= \^e\(0);
  \app_addr_r1_reg[23]_0\ <= \^app_addr_r1_reg[23]_0\;
  \app_addr_r1_reg[25]_0\(1 downto 0) <= \^app_addr_r1_reg[25]_0\(1 downto 0);
  app_cmd_r2(1 downto 0) <= \^app_cmd_r2\(1 downto 0);
  \app_cmd_r2_reg[0]_0\ <= \^app_cmd_r2_reg[0]_0\;
  app_en_r2_reg_0 <= \^app_en_r2_reg_0\;
  row(12 downto 0) <= \^row\(12 downto 0);
  \strict_mode.rd_data_buf_addr_r_lcl_reg[0]\ <= \^strict_mode.rd_data_buf_addr_r_lcl_reg[0]\;
  \strict_mode.rd_data_buf_addr_r_lcl_reg[1]\ <= \^strict_mode.rd_data_buf_addr_r_lcl_reg[1]\;
  use_addr <= \^use_addr\;
\app_addr_r1[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^e\(0),
      I1 => app_en,
      O => app_addr_r10
    );
\app_addr_r1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(0),
      Q => \app_addr_r1_reg_n_0_[0]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(10),
      Q => \app_addr_r1_reg_n_0_[10]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(11),
      Q => \app_addr_r1_reg_n_0_[11]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(12),
      Q => \app_addr_r1_reg_n_0_[12]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(13),
      Q => \app_addr_r1_reg_n_0_[13]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(14),
      Q => \app_addr_r1_reg_n_0_[14]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(15),
      Q => \app_addr_r1_reg_n_0_[15]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(16),
      Q => \app_addr_r1_reg_n_0_[16]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(17),
      Q => \app_addr_r1_reg_n_0_[17]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(18),
      Q => \app_addr_r1_reg_n_0_[18]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(19),
      Q => \app_addr_r1_reg_n_0_[19]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(1),
      Q => \app_addr_r1_reg_n_0_[1]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(20),
      Q => \app_addr_r1_reg_n_0_[20]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(21),
      Q => \app_addr_r1_reg_n_0_[21]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(22),
      Q => \app_addr_r1_reg_n_0_[22]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(23),
      Q => p_1_in(0),
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(24),
      Q => p_1_in(1),
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(25),
      Q => p_1_in(2),
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(2),
      Q => \app_addr_r1_reg_n_0_[2]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(3),
      Q => \app_addr_r1_reg_n_0_[3]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(4),
      Q => \app_addr_r1_reg_n_0_[4]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(5),
      Q => \app_addr_r1_reg_n_0_[5]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(6),
      Q => \app_addr_r1_reg_n_0_[6]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(7),
      Q => \app_addr_r1_reg_n_0_[7]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(8),
      Q => \app_addr_r1_reg_n_0_[8]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r1_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(9),
      Q => \app_addr_r1_reg_n_0_[9]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[0]\,
      Q => \app_addr_r2_reg_n_0_[0]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[10]\,
      Q => \app_addr_r2_reg_n_0_[10]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[11]\,
      Q => \app_addr_r2_reg_n_0_[11]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[12]\,
      Q => \app_addr_r2_reg_n_0_[12]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[13]\,
      Q => \app_addr_r2_reg_n_0_[13]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[14]\,
      Q => \app_addr_r2_reg_n_0_[14]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[15]\,
      Q => \app_addr_r2_reg_n_0_[15]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[16]\,
      Q => \app_addr_r2_reg_n_0_[16]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[17]\,
      Q => \app_addr_r2_reg_n_0_[17]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[18]\,
      Q => \app_addr_r2_reg_n_0_[18]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[19]\,
      Q => \app_addr_r2_reg_n_0_[19]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[1]\,
      Q => \app_addr_r2_reg_n_0_[1]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[20]\,
      Q => \app_addr_r2_reg_n_0_[20]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[21]\,
      Q => \app_addr_r2_reg_n_0_[21]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[22]\,
      Q => \app_addr_r2_reg_n_0_[22]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => p_1_in(0),
      Q => p_0_in_0(0),
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => p_1_in(1),
      Q => p_0_in_0(1),
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => p_1_in(2),
      Q => p_0_in_0(2),
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[2]\,
      Q => \app_addr_r2_reg_n_0_[2]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[3]\,
      Q => \app_addr_r2_reg_n_0_[3]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[4]\,
      Q => \app_addr_r2_reg_n_0_[4]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[5]\,
      Q => \app_addr_r2_reg_n_0_[5]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[6]\,
      Q => \app_addr_r2_reg_n_0_[6]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[7]\,
      Q => \app_addr_r2_reg_n_0_[7]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[8]\,
      Q => \app_addr_r2_reg_n_0_[8]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_addr_r2_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[9]\,
      Q => \app_addr_r2_reg_n_0_[9]\,
      R => \app_addr_r1_reg[0]_0\
    );
\app_cmd_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => app_cmd(0),
      Q => app_cmd_r1(0),
      R => '0'
    );
\app_cmd_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => app_cmd(1),
      Q => app_cmd_r1(1),
      R => '0'
    );
\app_cmd_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => app_cmd_r1(0),
      Q => \^app_cmd_r2\(0),
      R => '0'
    );
\app_cmd_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => app_cmd_r1(1),
      Q => \^app_cmd_r2\(1),
      R => '0'
    );
app_en_r1_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2230"
    )
        port map (
      I0 => app_en,
      I1 => \app_addr_r1_reg[0]_0\,
      I2 => app_en_r1,
      I3 => \^e\(0),
      O => app_en_ns1
    );
app_en_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => app_en_ns1,
      Q => app_en_r1,
      R => '0'
    );
app_en_r2_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2230"
    )
        port map (
      I0 => app_en_r1,
      I1 => \app_addr_r1_reg[0]_0\,
      I2 => \^app_en_r2_reg_0\,
      I3 => \^e\(0),
      O => app_en_ns2
    );
app_en_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => app_en_ns2,
      Q => \^app_en_r2_reg_0\,
      R => '0'
    );
app_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => app_rdy_ns,
      Q => \^e\(0),
      R => '0'
    );
\data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8008"
    )
        port map (
      I0 => \^e\(0),
      I1 => \^app_en_r2_reg_0\,
      I2 => \^app_cmd_r2\(0),
      I3 => \^app_cmd_r2\(1),
      O => wr_accepted
    );
rb_hit_busy_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000088822282"
    )
        port map (
      I0 => rb_hit_busy_r_reg,
      I1 => req_bank_r(1),
      I2 => p_0_in_0(1),
      I3 => \^e\(0),
      I4 => p_1_in(1),
      I5 => \rb_hit_busy_r_i_2__1_n_0\,
      O => p_145_out
    );
\rb_hit_busy_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000088822282"
    )
        port map (
      I0 => rb_hit_busy_r_reg_0,
      I1 => req_bank_r(10),
      I2 => p_0_in_0(1),
      I3 => \^e\(0),
      I4 => p_1_in(1),
      I5 => \rb_hit_busy_r_i_2__2_n_0\,
      O => p_28_out
    );
\rb_hit_busy_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000088822282"
    )
        port map (
      I0 => rb_hit_busy_r_reg_1,
      I1 => req_bank_r(7),
      I2 => p_0_in_0(1),
      I3 => \^e\(0),
      I4 => p_1_in(1),
      I5 => rb_hit_busy_r_i_2_n_0,
      O => p_67_out
    );
\rb_hit_busy_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000088822282"
    )
        port map (
      I0 => rb_hit_busy_r_reg_2,
      I1 => req_bank_r(4),
      I2 => p_0_in_0(1),
      I3 => \^e\(0),
      I4 => p_1_in(1),
      I5 => \rb_hit_busy_r_i_2__0_n_0\,
      O => p_106_out
    );
rb_hit_busy_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47B8FFFFFFFF47B8"
    )
        port map (
      I0 => p_1_in(2),
      I1 => \^e\(0),
      I2 => p_0_in_0(2),
      I3 => req_bank_r(8),
      I4 => \^app_addr_r1_reg[23]_0\,
      I5 => req_bank_r(6),
      O => rb_hit_busy_r_i_2_n_0
    );
\rb_hit_busy_r_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47B8FFFFFFFF47B8"
    )
        port map (
      I0 => p_1_in(0),
      I1 => \^e\(0),
      I2 => p_0_in_0(0),
      I3 => req_bank_r(3),
      I4 => \^app_addr_r1_reg[25]_0\(1),
      I5 => req_bank_r(5),
      O => \rb_hit_busy_r_i_2__0_n_0\
    );
\rb_hit_busy_r_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47B8FFFFFFFF47B8"
    )
        port map (
      I0 => p_1_in(2),
      I1 => \^e\(0),
      I2 => p_0_in_0(2),
      I3 => req_bank_r(2),
      I4 => \^app_addr_r1_reg[23]_0\,
      I5 => req_bank_r(0),
      O => \rb_hit_busy_r_i_2__1_n_0\
    );
\rb_hit_busy_r_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47B8FFFFFFFF47B8"
    )
        port map (
      I0 => p_1_in(2),
      I1 => \^e\(0),
      I2 => p_0_in_0(2),
      I3 => req_bank_r(11),
      I4 => \^app_addr_r1_reg[23]_0\,
      I5 => req_bank_r(9),
      O => \rb_hit_busy_r_i_2__2_n_0\
    );
rd_wr_r_lcl_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E2E2FFE2FFE2FFE2"
    )
        port map (
      I0 => \^app_cmd_r2\(0),
      I1 => \^e\(0),
      I2 => app_cmd_r1(0),
      I3 => periodic_rd_r,
      I4 => periodic_rd_cntr_r,
      I5 => periodic_rd_ack_r,
      O => \^app_cmd_r2_reg[0]_0\
    );
\req_bank_r_lcl[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_1_in(0),
      I1 => \^e\(0),
      I2 => p_0_in_0(0),
      O => \^app_addr_r1_reg[23]_0\
    );
\req_bank_r_lcl[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_1_in(1),
      I1 => \^e\(0),
      I2 => p_0_in_0(1),
      O => \^app_addr_r1_reg[25]_0\(0)
    );
\req_bank_r_lcl[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_1_in(2),
      I1 => \^e\(0),
      I2 => p_0_in_0(2),
      O => \^app_addr_r1_reg[25]_0\(1)
    );
\req_col_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[0]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[0]\,
      O => \app_addr_r1_reg[9]_0\(0)
    );
\req_col_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[1]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[1]\,
      O => \app_addr_r1_reg[9]_0\(1)
    );
\req_col_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[2]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[2]\,
      O => \app_addr_r1_reg[9]_0\(2)
    );
\req_col_r[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[3]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[3]\,
      O => \app_addr_r1_reg[9]_0\(3)
    );
\req_col_r[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[4]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[4]\,
      O => \app_addr_r1_reg[9]_0\(4)
    );
\req_col_r[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[5]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[5]\,
      O => \app_addr_r1_reg[9]_0\(5)
    );
\req_col_r[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[6]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[6]\,
      O => \app_addr_r1_reg[9]_0\(6)
    );
\req_col_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[7]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[7]\,
      O => \app_addr_r1_reg[9]_0\(7)
    );
\req_col_r[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[8]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[8]\,
      O => \app_addr_r1_reg[9]_0\(8)
    );
\req_col_r[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[9]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[9]\,
      O => \app_addr_r1_reg[9]_0\(9)
    );
\req_data_buf_addr_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"82B282BE828E8282"
    )
        port map (
      I0 => wr_data_buf_addr(0),
      I1 => \^app_cmd_r2\(0),
      I2 => \^app_cmd_r2\(1),
      I3 => \app_addr_r1_reg[0]_0\,
      I4 => \^use_addr\,
      I5 => \strict_mode.rd_data_buf_addr_r_lcl\(0),
      O => D(0)
    );
\req_data_buf_addr_r[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^app_en_r2_reg_0\,
      I1 => \^e\(0),
      O => \^use_addr\
    );
\req_data_buf_addr_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82BE8282"
    )
        port map (
      I0 => wr_data_buf_addr(1),
      I1 => \^app_cmd_r2\(0),
      I2 => \^app_cmd_r2\(1),
      I3 => \app_addr_r1_reg[0]_0\,
      I4 => \^strict_mode.rd_data_buf_addr_r_lcl_reg[0]\,
      O => D(1)
    );
\req_data_buf_addr_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"828282BE82BE8282"
    )
        port map (
      I0 => wr_data_buf_addr(2),
      I1 => \^app_cmd_r2\(0),
      I2 => \^app_cmd_r2\(1),
      I3 => \app_addr_r1_reg[0]_0\,
      I4 => \strict_mode.rd_data_buf_addr_r_lcl\(2),
      I5 => \^strict_mode.rd_data_buf_addr_r_lcl_reg[1]\,
      O => D(2)
    );
\req_data_buf_addr_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"888B8B8B8B888888"
    )
        port map (
      I0 => wr_data_buf_addr(3),
      I1 => \write__0\,
      I2 => \app_addr_r1_reg[0]_0\,
      I3 => \^strict_mode.rd_data_buf_addr_r_lcl_reg[1]\,
      I4 => \strict_mode.rd_data_buf_addr_r_lcl\(2),
      I5 => \strict_mode.rd_data_buf_addr_r_lcl\(3),
      O => D(3)
    );
\req_data_buf_addr_r[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^app_cmd_r2\(1),
      I1 => \^app_cmd_r2\(0),
      O => \write__0\
    );
\req_data_buf_addr_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800000000000000"
    )
        port map (
      I0 => \strict_mode.rd_data_buf_addr_r_lcl\(1),
      I1 => \strict_mode.rd_data_buf_addr_r_lcl\(0),
      I2 => \^app_cmd_r2\(1),
      I3 => \^app_cmd_r2\(0),
      I4 => \^e\(0),
      I5 => \^app_en_r2_reg_0\,
      O => \^strict_mode.rd_data_buf_addr_r_lcl_reg[1]\
    );
\req_row_r_lcl[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[10]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[10]\,
      O => \^row\(0)
    );
\req_row_r_lcl[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[20]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[20]\,
      O => \^row\(10)
    );
\req_row_r_lcl[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[21]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[21]\,
      O => \^row\(11)
    );
\req_row_r_lcl[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[22]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[22]\,
      O => \^row\(12)
    );
\req_row_r_lcl[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[11]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[11]\,
      O => \^row\(1)
    );
\req_row_r_lcl[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[12]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[12]\,
      O => \^row\(2)
    );
\req_row_r_lcl[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[13]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[13]\,
      O => \^row\(3)
    );
\req_row_r_lcl[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[14]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[14]\,
      O => \^row\(4)
    );
\req_row_r_lcl[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[15]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[15]\,
      O => \^row\(5)
    );
\req_row_r_lcl[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[16]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[16]\,
      O => \^row\(6)
    );
\req_row_r_lcl[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[17]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[17]\,
      O => \^row\(7)
    );
\req_row_r_lcl[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[18]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[18]\,
      O => \^row\(8)
    );
\req_row_r_lcl[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[19]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[19]\,
      O => \^row\(9)
    );
req_wr_r_lcl_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => req_wr_r_lcl_i_2_n_0,
      I1 => \^app_cmd_r2_reg[0]_0\,
      O => req_wr_r_lcl0
    );
req_wr_r_lcl_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E2E200E200E200E2"
    )
        port map (
      I0 => \^app_cmd_r2\(1),
      I1 => \^e\(0),
      I2 => app_cmd_r1(1),
      I3 => periodic_rd_r,
      I4 => periodic_rd_cntr_r,
      I5 => periodic_rd_ack_r,
      O => req_wr_r_lcl_i_2_n_0
    );
\row_hit_ns_carry__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E21D"
    )
        port map (
      I0 => \app_addr_r2_reg_n_0_[22]\,
      I1 => \^e\(0),
      I2 => \app_addr_r1_reg_n_0_[22]\,
      I3 => row_hit_r_reg(12),
      O => \app_addr_r2_reg[22]_0\(0)
    );
\row_hit_ns_carry__0_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E21D"
    )
        port map (
      I0 => \app_addr_r2_reg_n_0_[22]\,
      I1 => \^e\(0),
      I2 => \app_addr_r1_reg_n_0_[22]\,
      I3 => row_hit_r_reg(11),
      O => \app_addr_r2_reg[22]_1\(0)
    );
\row_hit_ns_carry__0_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E21D"
    )
        port map (
      I0 => \app_addr_r2_reg_n_0_[22]\,
      I1 => \^e\(0),
      I2 => \app_addr_r1_reg_n_0_[22]\,
      I3 => row_hit_r_reg(9),
      O => \app_addr_r2_reg[22]_2\(0)
    );
\row_hit_ns_carry__0_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E21D"
    )
        port map (
      I0 => \app_addr_r2_reg_n_0_[22]\,
      I1 => \^e\(0),
      I2 => \app_addr_r1_reg_n_0_[22]\,
      I3 => row_hit_r_reg(10),
      O => \app_addr_r2_reg[22]_3\(0)
    );
row_hit_ns_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^row\(8),
      I1 => row_hit_r_reg(8),
      I2 => \^row\(7),
      I3 => row_hit_r_reg(7),
      I4 => \^row\(6),
      I5 => row_hit_r_reg(6),
      O => S(2)
    );
row_hit_ns_carry_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^row\(5),
      I1 => row_hit_r_reg(5),
      I2 => \^row\(4),
      I3 => row_hit_r_reg(4),
      I4 => \^row\(3),
      I5 => row_hit_r_reg(3),
      O => S(1)
    );
row_hit_ns_carry_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^row\(2),
      I1 => row_hit_r_reg(2),
      I2 => \^row\(0),
      I3 => row_hit_r_reg(0),
      I4 => \^row\(1),
      I5 => row_hit_r_reg(1),
      O => S(0)
    );
\strict_mode.rd_data_buf_addr_r_lcl[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF7F0080"
    )
        port map (
      I0 => \^app_en_r2_reg_0\,
      I1 => \^e\(0),
      I2 => \^app_cmd_r2\(0),
      I3 => \^app_cmd_r2\(1),
      I4 => \strict_mode.rd_data_buf_addr_r_lcl\(0),
      O => app_en_r2_reg_1
    );
\strict_mode.rd_data_buf_addr_r_lcl[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFFFFF20000000"
    )
        port map (
      I0 => \strict_mode.rd_data_buf_addr_r_lcl\(0),
      I1 => \^app_cmd_r2\(1),
      I2 => \^app_cmd_r2\(0),
      I3 => \^e\(0),
      I4 => \^app_en_r2_reg_0\,
      I5 => \strict_mode.rd_data_buf_addr_r_lcl\(1),
      O => \^strict_mode.rd_data_buf_addr_r_lcl_reg[0]\
    );
was_wr_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E200E2E2"
    )
        port map (
      I0 => \^app_cmd_r2\(0),
      I1 => \^e\(0),
      I2 => app_cmd_r1(0),
      I3 => periodic_rd_ack_r,
      I4 => periodic_rd_r,
      O => was_wr0
    );
\wr_req_counter.wr_req_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"955555956AAAAA6A"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r\(0),
      I1 => \^e\(0),
      I2 => \^app_en_r2_reg_0\,
      I3 => \^app_cmd_r2\(0),
      I4 => \^app_cmd_r2\(1),
      I5 => p_0_in(0),
      O => \wr_req_counter.wr_req_cnt_r_reg[0]\
    );
\wr_req_counter.wr_req_cnt_r[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69AAAAAA"
    )
        port map (
      I0 => p_0_in(0),
      I1 => \^app_cmd_r2\(1),
      I2 => \^app_cmd_r2\(0),
      I3 => \^app_en_r2_reg_0\,
      I4 => \^e\(0),
      O => \read_data_indx.rd_data_upd_indx_r_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ui_rd_data is
  port (
    \rd_buf_indx.ram_init_done_r_lcl_reg_0\ : out STD_LOGIC;
    \strict_mode.rd_data_buf_addr_r_lcl\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ADDRD : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \pointer_ram.pointer_wr_data\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    CLK : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    app_cmd_r2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0\ : in STD_LOGIC;
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \pointer_ram.rams[1].RAM32M0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0\ : in STD_LOGIC;
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ui_rd_data : entity is "mig_7series_v4_2_ui_rd_data";
end mig_7series_0_mig_7series_v4_2_ui_rd_data;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ui_rd_data is
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal ram_init_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_buf_indx.ram_init_done_ns\ : STD_LOGIC;
  signal \rd_buf_indx.ram_init_done_r_lcl_i_2_n_0\ : STD_LOGIC;
  signal \^rd_buf_indx.ram_init_done_r_lcl_reg_0\ : STD_LOGIC;
  signal \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \rd_buf_indx.rd_buf_indx_r_reg\ : STD_LOGIC_VECTOR ( 4 to 4 );
  signal \^strict_mode.rd_data_buf_addr_r_lcl\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \strict_mode.rd_data_buf_addr_r_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \strict_mode.rd_data_buf_addr_r_lcl[3]_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rd_buf_indx.ram_init_done_r_lcl_i_2\ : label is "soft_lutpair630";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \rd_buf_indx.ram_init_done_r_lcl_reg\ : label is "10";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[0]_i_1\ : label is "soft_lutpair632";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[1]_i_1\ : label is "soft_lutpair632";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[2]_i_1\ : label is "soft_lutpair631";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[3]_i_1\ : label is "soft_lutpair631";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[4]_i_2\ : label is "soft_lutpair630";
begin
  \rd_buf_indx.ram_init_done_r_lcl_reg_0\ <= \^rd_buf_indx.ram_init_done_r_lcl_reg_0\;
  \strict_mode.rd_data_buf_addr_r_lcl\(3 downto 0) <= \^strict_mode.rd_data_buf_addr_r_lcl\(3 downto 0);
\pointer_ram.rams[0].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pointer_ram.rams[1].RAM32M0\(1),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(1),
      O => \pointer_ram.pointer_wr_data\(1)
    );
\pointer_ram.rams[0].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pointer_ram.rams[1].RAM32M0\(0),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(0),
      O => \pointer_ram.pointer_wr_data\(0)
    );
\pointer_ram.rams[0].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(3),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(3),
      O => ADDRD(3)
    );
\pointer_ram.rams[0].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(2),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(2),
      O => ADDRD(2)
    );
\pointer_ram.rams[0].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(1),
      O => ADDRD(1)
    );
\pointer_ram.rams[0].RAM32M0_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(0),
      O => ADDRD(0)
    );
\pointer_ram.rams[1].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pointer_ram.rams[1].RAM32M0\(3),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(3),
      O => \pointer_ram.pointer_wr_data\(3)
    );
\pointer_ram.rams[1].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pointer_ram.rams[1].RAM32M0\(2),
      I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      I2 => ram_init_addr(2),
      O => \pointer_ram.pointer_wr_data\(2)
    );
\rd_buf_indx.ram_init_done_r_lcl_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F04"
    )
        port map (
      I0 => \rd_buf_indx.ram_init_done_r_lcl_i_2_n_0\,
      I1 => \rd_buf_indx.rd_buf_indx_r_reg\(4),
      I2 => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\,
      I3 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      O => \rd_buf_indx.ram_init_done_ns\
    );
\rd_buf_indx.ram_init_done_r_lcl_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => ram_init_addr(2),
      I1 => ram_init_addr(1),
      I2 => ram_init_addr(0),
      I3 => ram_init_addr(3),
      O => \rd_buf_indx.ram_init_done_r_lcl_i_2_n_0\
    );
\rd_buf_indx.ram_init_done_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.ram_init_done_ns\,
      Q => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      R => '0'
    );
\rd_buf_indx.rd_buf_indx_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ram_init_addr(0),
      O => \p_0_in__2\(0)
    );
\rd_buf_indx.rd_buf_indx_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ram_init_addr(0),
      I1 => ram_init_addr(1),
      O => \p_0_in__2\(1)
    );
\rd_buf_indx.rd_buf_indx_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => ram_init_addr(0),
      I1 => ram_init_addr(1),
      I2 => ram_init_addr(2),
      O => \p_0_in__2\(2)
    );
\rd_buf_indx.rd_buf_indx_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => ram_init_addr(2),
      I1 => ram_init_addr(1),
      I2 => ram_init_addr(0),
      I3 => ram_init_addr(3),
      O => \p_0_in__2\(3)
    );
\rd_buf_indx.rd_buf_indx_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\,
      O => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\
    );
\rd_buf_indx.rd_buf_indx_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => ram_init_addr(3),
      I1 => ram_init_addr(0),
      I2 => ram_init_addr(1),
      I3 => ram_init_addr(2),
      I4 => \rd_buf_indx.rd_buf_indx_r_reg\(4),
      O => \p_0_in__2\(4)
    );
\rd_buf_indx.rd_buf_indx_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\,
      D => \p_0_in__2\(0),
      Q => ram_init_addr(0),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\
    );
\rd_buf_indx.rd_buf_indx_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\,
      D => \p_0_in__2\(1),
      Q => ram_init_addr(1),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\
    );
\rd_buf_indx.rd_buf_indx_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\,
      D => \p_0_in__2\(2),
      Q => ram_init_addr(2),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\
    );
\rd_buf_indx.rd_buf_indx_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\,
      D => \p_0_in__2\(3),
      Q => ram_init_addr(3),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\
    );
\rd_buf_indx.rd_buf_indx_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\,
      D => \p_0_in__2\(4),
      Q => \rd_buf_indx.rd_buf_indx_r_reg\(4),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\
    );
\strict_mode.rd_data_buf_addr_r_lcl[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA6AAAAAAAAAAAAA"
    )
        port map (
      I0 => \^strict_mode.rd_data_buf_addr_r_lcl\(2),
      I1 => use_addr,
      I2 => app_cmd_r2(0),
      I3 => app_cmd_r2(1),
      I4 => \^strict_mode.rd_data_buf_addr_r_lcl\(0),
      I5 => \^strict_mode.rd_data_buf_addr_r_lcl\(1),
      O => \strict_mode.rd_data_buf_addr_r_lcl[2]_i_1_n_0\
    );
\strict_mode.rd_data_buf_addr_r_lcl[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0\,
      I1 => \^strict_mode.rd_data_buf_addr_r_lcl\(2),
      I2 => \^strict_mode.rd_data_buf_addr_r_lcl\(3),
      O => \strict_mode.rd_data_buf_addr_r_lcl[3]_i_1_n_0\
    );
\strict_mode.rd_data_buf_addr_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\,
      Q => \^strict_mode.rd_data_buf_addr_r_lcl\(0),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\
    );
\strict_mode.rd_data_buf_addr_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0\,
      Q => \^strict_mode.rd_data_buf_addr_r_lcl\(1),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\
    );
\strict_mode.rd_data_buf_addr_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \strict_mode.rd_data_buf_addr_r_lcl[2]_i_1_n_0\,
      Q => \^strict_mode.rd_data_buf_addr_r_lcl\(2),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\
    );
\strict_mode.rd_data_buf_addr_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \strict_mode.rd_data_buf_addr_r_lcl[3]_i_1_n_0\,
      Q => \^strict_mode.rd_data_buf_addr_r_lcl\(3),
      R => \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ui_wr_data is
  port (
    wr_data_buf_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    app_wdf_rdy : out STD_LOGIC;
    app_rdy_ns : out STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \write_buffer.wr_buf_out_data_reg[37]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \write_buffer.wr_buf_out_data_reg[143]_0\ : out STD_LOGIC_VECTOR ( 143 downto 0 );
    \write_buffer.wr_buf_out_data_reg[78]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
    CLK : in STD_LOGIC;
    \pointer_ram.pointer_we\ : in STD_LOGIC;
    \pointer_ram.pointer_wr_data\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    ADDRD : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \write_buffer.wr_buf_out_data_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    accept_ns : in STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[0]_1\ : in STD_LOGIC;
    wr_accepted : in STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[4]_0\ : in STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[0]_2\ : in STD_LOGIC;
    app_wdf_wren : in STD_LOGIC;
    app_wdf_end : in STD_LOGIC;
    ram_init_done_r : in STD_LOGIC;
    app_wdf_mask : in STD_LOGIC_VECTOR ( 15 downto 0 );
    app_wdf_data : in STD_LOGIC_VECTOR ( 127 downto 0 );
    \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : in STD_LOGIC;
    \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : in STD_LOGIC;
    \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ui_wr_data : entity is "mig_7series_v4_2_ui_wr_data";
end mig_7series_0_mig_7series_v4_2_ui_wr_data;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ui_wr_data is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal app_rdy_r_i_2_n_0 : STD_LOGIC;
  signal app_wdf_data_r1 : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal app_wdf_end_ns1 : STD_LOGIC;
  signal app_wdf_end_r1 : STD_LOGIC;
  signal app_wdf_mask_r1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal app_wdf_rdy_r_copy1 : STD_LOGIC;
  signal app_wdf_rdy_r_copy2 : STD_LOGIC;
  signal app_wdf_rdy_r_copy3 : STD_LOGIC;
  signal app_wdf_wren_ns1 : STD_LOGIC;
  signal app_wdf_wren_r1 : STD_LOGIC;
  signal \data_buf_address_counter.data_buf_addr_cnt_r_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \occupied_counter.occ_cnt[15]_i_1_n_0\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__0_0\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_1_in_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal p_4_in : STD_LOGIC;
  signal wb_wr_data_addr_w : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal wdf_rdy_ns : STD_LOGIC;
  signal wr_buf_out_data_w : STD_LOGIC_VECTOR ( 143 downto 0 );
  signal wr_data_pntr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_req_counter.wr_req_cnt_r\ : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \^wr_req_counter.wr_req_cnt_r_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \write_buffer.wr_buf_in_data\ : STD_LOGIC_VECTOR ( 143 downto 0 );
  signal \^write_buffer.wr_buf_out_data_reg[143]_0\ : STD_LOGIC_VECTOR ( 143 downto 0 );
  signal \write_data_control.wb_wr_data_addr0_ns\ : STD_LOGIC;
  signal \write_data_control.wb_wr_data_addr0_r\ : STD_LOGIC;
  signal \write_data_control.wb_wr_data_addr_r\ : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \write_data_control.wr_data_addr_le\ : STD_LOGIC;
  signal \write_data_control.wr_data_indx_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \write_data_control.wr_data_indx_r_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of app_wdf_rdy_r_copy1_reg : label is "no";
  attribute equivalent_register_removal of app_wdf_rdy_r_copy2_reg : label is "no";
  attribute equivalent_register_removal of app_wdf_rdy_r_copy3_reg : label is "no";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1\ : label is "soft_lutpair640";
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1\ : label is "soft_lutpair640";
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1\ : label is "soft_lutpair639";
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2\ : label is "soft_lutpair639";
  attribute SOFT_HLUTNM of \occupied_counter.app_wdf_rdy_r_i_2\ : label is "soft_lutpair634";
  attribute equivalent_register_removal of \occupied_counter.app_wdf_rdy_r_reg\ : label is "no";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[0]_i_1\ : label is "soft_lutpair636";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[13]_i_1\ : label is "soft_lutpair635";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[15]_i_2\ : label is "soft_lutpair635";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[2]_i_1\ : label is "soft_lutpair636";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[8]_i_1\ : label is "soft_lutpair634";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \pointer_ram.rams[0].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \pointer_ram.rams[1].RAM32M0\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[0]_i_1\ : label is "soft_lutpair641";
  attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[1]_i_1\ : label is "soft_lutpair641";
  attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[2]_i_1\ : label is "soft_lutpair638";
  attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[3]_i_1\ : label is "soft_lutpair638";
  attribute SOFT_HLUTNM of \wr_req_counter.wr_req_cnt_r[1]_i_1\ : label is "soft_lutpair633";
  attribute SOFT_HLUTNM of \wr_req_counter.wr_req_cnt_r[2]_i_1\ : label is "soft_lutpair633";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[0].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[10].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[11].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[12].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[13].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[14].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[15].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[16].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[17].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[18].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[19].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[1].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[20].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[21].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[22].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[23].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[2].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[3].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[4].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[5].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[6].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[7].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[8].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[9].RAM32M0\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \write_data_control.wr_data_indx_r[2]_i_1\ : label is "soft_lutpair637";
  attribute SOFT_HLUTNM of \write_data_control.wr_data_indx_r[3]_i_2\ : label is "soft_lutpair637";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  p_0_in(0) <= \^p_0_in\(0);
  \wr_req_counter.wr_req_cnt_r_reg[0]_0\(0) <= \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0);
  \write_buffer.wr_buf_out_data_reg[143]_0\(143 downto 0) <= \^write_buffer.wr_buf_out_data_reg[143]_0\(143 downto 0);
app_rdy_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000FFFE0000"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\,
      I1 => \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\,
      I2 => app_rdy_r_i_2_n_0,
      I3 => \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\,
      I4 => accept_ns,
      I5 => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      O => app_rdy_ns
    );
app_rdy_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAEBFFFFFFB"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r_reg[0]_2\,
      I1 => \wr_req_counter.wr_req_cnt_r_reg[4]_0\,
      I2 => \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0\,
      I3 => \wr_req_counter.wr_req_cnt_r\(2),
      I4 => \wr_req_counter.wr_req_cnt_r\(3),
      I5 => \wr_req_counter.wr_req_cnt_r\(4),
      O => app_rdy_r_i_2_n_0
    );
\app_wdf_data_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(0),
      Q => app_wdf_data_r1(0),
      R => '0'
    );
\app_wdf_data_r1_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(100),
      Q => app_wdf_data_r1(100),
      R => '0'
    );
\app_wdf_data_r1_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(101),
      Q => app_wdf_data_r1(101),
      R => '0'
    );
\app_wdf_data_r1_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(102),
      Q => app_wdf_data_r1(102),
      R => '0'
    );
\app_wdf_data_r1_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(103),
      Q => app_wdf_data_r1(103),
      R => '0'
    );
\app_wdf_data_r1_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(104),
      Q => app_wdf_data_r1(104),
      R => '0'
    );
\app_wdf_data_r1_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(105),
      Q => app_wdf_data_r1(105),
      R => '0'
    );
\app_wdf_data_r1_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(106),
      Q => app_wdf_data_r1(106),
      R => '0'
    );
\app_wdf_data_r1_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(107),
      Q => app_wdf_data_r1(107),
      R => '0'
    );
\app_wdf_data_r1_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(108),
      Q => app_wdf_data_r1(108),
      R => '0'
    );
\app_wdf_data_r1_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(109),
      Q => app_wdf_data_r1(109),
      R => '0'
    );
\app_wdf_data_r1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(10),
      Q => app_wdf_data_r1(10),
      R => '0'
    );
\app_wdf_data_r1_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(110),
      Q => app_wdf_data_r1(110),
      R => '0'
    );
\app_wdf_data_r1_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(111),
      Q => app_wdf_data_r1(111),
      R => '0'
    );
\app_wdf_data_r1_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(112),
      Q => app_wdf_data_r1(112),
      R => '0'
    );
\app_wdf_data_r1_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(113),
      Q => app_wdf_data_r1(113),
      R => '0'
    );
\app_wdf_data_r1_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(114),
      Q => app_wdf_data_r1(114),
      R => '0'
    );
\app_wdf_data_r1_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(115),
      Q => app_wdf_data_r1(115),
      R => '0'
    );
\app_wdf_data_r1_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(116),
      Q => app_wdf_data_r1(116),
      R => '0'
    );
\app_wdf_data_r1_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(117),
      Q => app_wdf_data_r1(117),
      R => '0'
    );
\app_wdf_data_r1_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(118),
      Q => app_wdf_data_r1(118),
      R => '0'
    );
\app_wdf_data_r1_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(119),
      Q => app_wdf_data_r1(119),
      R => '0'
    );
\app_wdf_data_r1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(11),
      Q => app_wdf_data_r1(11),
      R => '0'
    );
\app_wdf_data_r1_reg[120]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(120),
      Q => app_wdf_data_r1(120),
      R => '0'
    );
\app_wdf_data_r1_reg[121]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(121),
      Q => app_wdf_data_r1(121),
      R => '0'
    );
\app_wdf_data_r1_reg[122]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(122),
      Q => app_wdf_data_r1(122),
      R => '0'
    );
\app_wdf_data_r1_reg[123]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(123),
      Q => app_wdf_data_r1(123),
      R => '0'
    );
\app_wdf_data_r1_reg[124]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(124),
      Q => app_wdf_data_r1(124),
      R => '0'
    );
\app_wdf_data_r1_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(125),
      Q => app_wdf_data_r1(125),
      R => '0'
    );
\app_wdf_data_r1_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(126),
      Q => app_wdf_data_r1(126),
      R => '0'
    );
\app_wdf_data_r1_reg[127]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(127),
      Q => app_wdf_data_r1(127),
      R => '0'
    );
\app_wdf_data_r1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(12),
      Q => app_wdf_data_r1(12),
      R => '0'
    );
\app_wdf_data_r1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(13),
      Q => app_wdf_data_r1(13),
      R => '0'
    );
\app_wdf_data_r1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(14),
      Q => app_wdf_data_r1(14),
      R => '0'
    );
\app_wdf_data_r1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(15),
      Q => app_wdf_data_r1(15),
      R => '0'
    );
\app_wdf_data_r1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(16),
      Q => app_wdf_data_r1(16),
      R => '0'
    );
\app_wdf_data_r1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(17),
      Q => app_wdf_data_r1(17),
      R => '0'
    );
\app_wdf_data_r1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(18),
      Q => app_wdf_data_r1(18),
      R => '0'
    );
\app_wdf_data_r1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(19),
      Q => app_wdf_data_r1(19),
      R => '0'
    );
\app_wdf_data_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(1),
      Q => app_wdf_data_r1(1),
      R => '0'
    );
\app_wdf_data_r1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(20),
      Q => app_wdf_data_r1(20),
      R => '0'
    );
\app_wdf_data_r1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(21),
      Q => app_wdf_data_r1(21),
      R => '0'
    );
\app_wdf_data_r1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(22),
      Q => app_wdf_data_r1(22),
      R => '0'
    );
\app_wdf_data_r1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(23),
      Q => app_wdf_data_r1(23),
      R => '0'
    );
\app_wdf_data_r1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(24),
      Q => app_wdf_data_r1(24),
      R => '0'
    );
\app_wdf_data_r1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(25),
      Q => app_wdf_data_r1(25),
      R => '0'
    );
\app_wdf_data_r1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(26),
      Q => app_wdf_data_r1(26),
      R => '0'
    );
\app_wdf_data_r1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(27),
      Q => app_wdf_data_r1(27),
      R => '0'
    );
\app_wdf_data_r1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(28),
      Q => app_wdf_data_r1(28),
      R => '0'
    );
\app_wdf_data_r1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(29),
      Q => app_wdf_data_r1(29),
      R => '0'
    );
\app_wdf_data_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(2),
      Q => app_wdf_data_r1(2),
      R => '0'
    );
\app_wdf_data_r1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(30),
      Q => app_wdf_data_r1(30),
      R => '0'
    );
\app_wdf_data_r1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(31),
      Q => app_wdf_data_r1(31),
      R => '0'
    );
\app_wdf_data_r1_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(32),
      Q => app_wdf_data_r1(32),
      R => '0'
    );
\app_wdf_data_r1_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(33),
      Q => app_wdf_data_r1(33),
      R => '0'
    );
\app_wdf_data_r1_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(34),
      Q => app_wdf_data_r1(34),
      R => '0'
    );
\app_wdf_data_r1_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(35),
      Q => app_wdf_data_r1(35),
      R => '0'
    );
\app_wdf_data_r1_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(36),
      Q => app_wdf_data_r1(36),
      R => '0'
    );
\app_wdf_data_r1_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(37),
      Q => app_wdf_data_r1(37),
      R => '0'
    );
\app_wdf_data_r1_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(38),
      Q => app_wdf_data_r1(38),
      R => '0'
    );
\app_wdf_data_r1_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(39),
      Q => app_wdf_data_r1(39),
      R => '0'
    );
\app_wdf_data_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(3),
      Q => app_wdf_data_r1(3),
      R => '0'
    );
\app_wdf_data_r1_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(40),
      Q => app_wdf_data_r1(40),
      R => '0'
    );
\app_wdf_data_r1_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(41),
      Q => app_wdf_data_r1(41),
      R => '0'
    );
\app_wdf_data_r1_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(42),
      Q => app_wdf_data_r1(42),
      R => '0'
    );
\app_wdf_data_r1_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(43),
      Q => app_wdf_data_r1(43),
      R => '0'
    );
\app_wdf_data_r1_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(44),
      Q => app_wdf_data_r1(44),
      R => '0'
    );
\app_wdf_data_r1_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(45),
      Q => app_wdf_data_r1(45),
      R => '0'
    );
\app_wdf_data_r1_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(46),
      Q => app_wdf_data_r1(46),
      R => '0'
    );
\app_wdf_data_r1_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(47),
      Q => app_wdf_data_r1(47),
      R => '0'
    );
\app_wdf_data_r1_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(48),
      Q => app_wdf_data_r1(48),
      R => '0'
    );
\app_wdf_data_r1_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(49),
      Q => app_wdf_data_r1(49),
      R => '0'
    );
\app_wdf_data_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(4),
      Q => app_wdf_data_r1(4),
      R => '0'
    );
\app_wdf_data_r1_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(50),
      Q => app_wdf_data_r1(50),
      R => '0'
    );
\app_wdf_data_r1_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(51),
      Q => app_wdf_data_r1(51),
      R => '0'
    );
\app_wdf_data_r1_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(52),
      Q => app_wdf_data_r1(52),
      R => '0'
    );
\app_wdf_data_r1_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(53),
      Q => app_wdf_data_r1(53),
      R => '0'
    );
\app_wdf_data_r1_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(54),
      Q => app_wdf_data_r1(54),
      R => '0'
    );
\app_wdf_data_r1_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(55),
      Q => app_wdf_data_r1(55),
      R => '0'
    );
\app_wdf_data_r1_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(56),
      Q => app_wdf_data_r1(56),
      R => '0'
    );
\app_wdf_data_r1_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(57),
      Q => app_wdf_data_r1(57),
      R => '0'
    );
\app_wdf_data_r1_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(58),
      Q => app_wdf_data_r1(58),
      R => '0'
    );
\app_wdf_data_r1_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(59),
      Q => app_wdf_data_r1(59),
      R => '0'
    );
\app_wdf_data_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(5),
      Q => app_wdf_data_r1(5),
      R => '0'
    );
\app_wdf_data_r1_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(60),
      Q => app_wdf_data_r1(60),
      R => '0'
    );
\app_wdf_data_r1_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(61),
      Q => app_wdf_data_r1(61),
      R => '0'
    );
\app_wdf_data_r1_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(62),
      Q => app_wdf_data_r1(62),
      R => '0'
    );
\app_wdf_data_r1_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(63),
      Q => app_wdf_data_r1(63),
      R => '0'
    );
\app_wdf_data_r1_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(64),
      Q => app_wdf_data_r1(64),
      R => '0'
    );
\app_wdf_data_r1_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(65),
      Q => app_wdf_data_r1(65),
      R => '0'
    );
\app_wdf_data_r1_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(66),
      Q => app_wdf_data_r1(66),
      R => '0'
    );
\app_wdf_data_r1_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(67),
      Q => app_wdf_data_r1(67),
      R => '0'
    );
\app_wdf_data_r1_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(68),
      Q => app_wdf_data_r1(68),
      R => '0'
    );
\app_wdf_data_r1_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(69),
      Q => app_wdf_data_r1(69),
      R => '0'
    );
\app_wdf_data_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(6),
      Q => app_wdf_data_r1(6),
      R => '0'
    );
\app_wdf_data_r1_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(70),
      Q => app_wdf_data_r1(70),
      R => '0'
    );
\app_wdf_data_r1_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(71),
      Q => app_wdf_data_r1(71),
      R => '0'
    );
\app_wdf_data_r1_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(72),
      Q => app_wdf_data_r1(72),
      R => '0'
    );
\app_wdf_data_r1_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(73),
      Q => app_wdf_data_r1(73),
      R => '0'
    );
\app_wdf_data_r1_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(74),
      Q => app_wdf_data_r1(74),
      R => '0'
    );
\app_wdf_data_r1_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(75),
      Q => app_wdf_data_r1(75),
      R => '0'
    );
\app_wdf_data_r1_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(76),
      Q => app_wdf_data_r1(76),
      R => '0'
    );
\app_wdf_data_r1_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(77),
      Q => app_wdf_data_r1(77),
      R => '0'
    );
\app_wdf_data_r1_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(78),
      Q => app_wdf_data_r1(78),
      R => '0'
    );
\app_wdf_data_r1_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(79),
      Q => app_wdf_data_r1(79),
      R => '0'
    );
\app_wdf_data_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(7),
      Q => app_wdf_data_r1(7),
      R => '0'
    );
\app_wdf_data_r1_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(80),
      Q => app_wdf_data_r1(80),
      R => '0'
    );
\app_wdf_data_r1_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(81),
      Q => app_wdf_data_r1(81),
      R => '0'
    );
\app_wdf_data_r1_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(82),
      Q => app_wdf_data_r1(82),
      R => '0'
    );
\app_wdf_data_r1_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(83),
      Q => app_wdf_data_r1(83),
      R => '0'
    );
\app_wdf_data_r1_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(84),
      Q => app_wdf_data_r1(84),
      R => '0'
    );
\app_wdf_data_r1_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(85),
      Q => app_wdf_data_r1(85),
      R => '0'
    );
\app_wdf_data_r1_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(86),
      Q => app_wdf_data_r1(86),
      R => '0'
    );
\app_wdf_data_r1_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(87),
      Q => app_wdf_data_r1(87),
      R => '0'
    );
\app_wdf_data_r1_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(88),
      Q => app_wdf_data_r1(88),
      R => '0'
    );
\app_wdf_data_r1_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(89),
      Q => app_wdf_data_r1(89),
      R => '0'
    );
\app_wdf_data_r1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(8),
      Q => app_wdf_data_r1(8),
      R => '0'
    );
\app_wdf_data_r1_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(90),
      Q => app_wdf_data_r1(90),
      R => '0'
    );
\app_wdf_data_r1_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(91),
      Q => app_wdf_data_r1(91),
      R => '0'
    );
\app_wdf_data_r1_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(92),
      Q => app_wdf_data_r1(92),
      R => '0'
    );
\app_wdf_data_r1_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(93),
      Q => app_wdf_data_r1(93),
      R => '0'
    );
\app_wdf_data_r1_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(94),
      Q => app_wdf_data_r1(94),
      R => '0'
    );
\app_wdf_data_r1_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(95),
      Q => app_wdf_data_r1(95),
      R => '0'
    );
\app_wdf_data_r1_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(96),
      Q => app_wdf_data_r1(96),
      R => '0'
    );
\app_wdf_data_r1_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(97),
      Q => app_wdf_data_r1(97),
      R => '0'
    );
\app_wdf_data_r1_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(98),
      Q => app_wdf_data_r1(98),
      R => '0'
    );
\app_wdf_data_r1_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(99),
      Q => app_wdf_data_r1(99),
      R => '0'
    );
\app_wdf_data_r1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(9),
      Q => app_wdf_data_r1(9),
      R => '0'
    );
app_wdf_end_r1_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2230"
    )
        port map (
      I0 => app_wdf_end,
      I1 => \wr_req_counter.wr_req_cnt_r_reg[0]_2\,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy2,
      O => app_wdf_end_ns1
    );
app_wdf_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => app_wdf_end_ns1,
      Q => app_wdf_end_r1,
      R => '0'
    );
\app_wdf_mask_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(0),
      Q => app_wdf_mask_r1(0),
      R => '0'
    );
\app_wdf_mask_r1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(10),
      Q => app_wdf_mask_r1(10),
      R => '0'
    );
\app_wdf_mask_r1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(11),
      Q => app_wdf_mask_r1(11),
      R => '0'
    );
\app_wdf_mask_r1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(12),
      Q => app_wdf_mask_r1(12),
      R => '0'
    );
\app_wdf_mask_r1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(13),
      Q => app_wdf_mask_r1(13),
      R => '0'
    );
\app_wdf_mask_r1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(14),
      Q => app_wdf_mask_r1(14),
      R => '0'
    );
\app_wdf_mask_r1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(15),
      Q => app_wdf_mask_r1(15),
      R => '0'
    );
\app_wdf_mask_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(1),
      Q => app_wdf_mask_r1(1),
      R => '0'
    );
\app_wdf_mask_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(2),
      Q => app_wdf_mask_r1(2),
      R => '0'
    );
\app_wdf_mask_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(3),
      Q => app_wdf_mask_r1(3),
      R => '0'
    );
\app_wdf_mask_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(4),
      Q => app_wdf_mask_r1(4),
      R => '0'
    );
\app_wdf_mask_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(5),
      Q => app_wdf_mask_r1(5),
      R => '0'
    );
\app_wdf_mask_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(6),
      Q => app_wdf_mask_r1(6),
      R => '0'
    );
\app_wdf_mask_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(7),
      Q => app_wdf_mask_r1(7),
      R => '0'
    );
\app_wdf_mask_r1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(8),
      Q => app_wdf_mask_r1(8),
      R => '0'
    );
\app_wdf_mask_r1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(9),
      Q => app_wdf_mask_r1(9),
      R => '0'
    );
app_wdf_rdy_r_copy1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wdf_rdy_ns,
      Q => app_wdf_rdy_r_copy1,
      R => '0'
    );
app_wdf_rdy_r_copy2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wdf_rdy_ns,
      Q => app_wdf_rdy_r_copy2,
      R => '0'
    );
app_wdf_rdy_r_copy3_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wdf_rdy_ns,
      Q => app_wdf_rdy_r_copy3,
      R => '0'
    );
app_wdf_wren_r1_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2230"
    )
        port map (
      I0 => app_wdf_wren,
      I1 => \wr_req_counter.wr_req_cnt_r_reg[0]_2\,
      I2 => app_wdf_wren_r1,
      I3 => app_wdf_rdy_r_copy2,
      O => app_wdf_wren_ns1
    );
app_wdf_wren_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => app_wdf_wren_ns1,
      Q => app_wdf_wren_r1,
      R => '0'
    );
\data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0),
      O => \p_0_in__0\(0)
    );
\data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0),
      I1 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(1),
      O => \p_0_in__0\(1)
    );
\data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0),
      I1 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(1),
      I2 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(2),
      O => \p_0_in__0\(2)
    );
\data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(2),
      I1 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(1),
      I2 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0),
      I3 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(3),
      O => \p_0_in__0\(3)
    );
\data_buf_address_counter.data_buf_addr_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_accepted,
      D => \p_0_in__0\(0),
      Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\data_buf_address_counter.data_buf_addr_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_accepted,
      D => \p_0_in__0\(1),
      Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(1),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\data_buf_address_counter.data_buf_addr_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_accepted,
      D => \p_0_in__0\(2),
      Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(2),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\data_buf_address_counter.data_buf_addr_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_accepted,
      D => \p_0_in__0\(3),
      Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(3),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
mem_reg_0_15_0_5_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(45),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[78]_0\(0)
    );
\mem_reg_0_15_12_17_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(66),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\,
      O => \write_buffer.wr_buf_out_data_reg[37]_0\(1)
    );
mem_reg_0_15_12_17_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(15),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\,
      O => \write_buffer.wr_buf_out_data_reg[78]_0\(2)
    );
mem_reg_0_15_18_23_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(95),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\,
      O => \write_buffer.wr_buf_out_data_reg[78]_0\(3)
    );
\mem_reg_0_15_24_29_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(0),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\,
      O => \write_buffer.wr_buf_out_data_reg[37]_0\(2)
    );
\mem_reg_0_15_30_35_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(12),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\,
      O => \write_buffer.wr_buf_out_data_reg[78]_0\(4)
    );
mem_reg_0_15_30_35_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(54),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[37]_0\(3)
    );
\mem_reg_0_15_36_41_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(70),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\,
      O => \write_buffer.wr_buf_out_data_reg[37]_0\(4)
    );
mem_reg_0_15_36_41_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(3),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\,
      O => \write_buffer.wr_buf_out_data_reg[37]_0\(5)
    );
\mem_reg_0_15_42_47_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(58),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[78]_0\(5)
    );
\mem_reg_0_15_42_47_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(83),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\,
      O => \write_buffer.wr_buf_out_data_reg[37]_0\(6)
    );
\mem_reg_0_15_42_47_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(74),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\,
      O => \write_buffer.wr_buf_out_data_reg[78]_0\(6)
    );
\mem_reg_0_15_48_53_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(33),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[37]_0\(7)
    );
\mem_reg_0_15_48_53_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(41),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[78]_0\(7)
    );
\mem_reg_0_15_54_59_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(4),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\,
      O => \write_buffer.wr_buf_out_data_reg[37]_0\(8)
    );
\mem_reg_0_15_54_59_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(11),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\,
      O => \write_buffer.wr_buf_out_data_reg[78]_0\(8)
    );
\mem_reg_0_15_60_65_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(91),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\,
      O => \write_buffer.wr_buf_out_data_reg[78]_0\(9)
    );
mem_reg_0_15_60_65_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(7),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\,
      O => \write_buffer.wr_buf_out_data_reg[37]_0\(9)
    );
\mem_reg_0_15_66_71_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(62),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[78]_0\(10)
    );
mem_reg_0_15_66_71_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(87),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\,
      O => \write_buffer.wr_buf_out_data_reg[37]_0\(10)
    );
\mem_reg_0_15_66_71_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(78),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\,
      O => \write_buffer.wr_buf_out_data_reg[78]_0\(11)
    );
\mem_reg_0_15_6_11_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(50),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[37]_0\(0)
    );
\mem_reg_0_15_6_11_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(8),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\,
      O => \write_buffer.wr_buf_out_data_reg[78]_0\(1)
    );
\mem_reg_0_15_72_77_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(37),
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      O => \write_buffer.wr_buf_out_data_reg[37]_0\(11)
    );
\occupied_counter.app_wdf_rdy_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5000501050105010"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r_reg[0]_2\,
      I1 => \occupied_counter.occ_cnt_reg_n_0_[15]\,
      I2 => ram_init_done_r,
      I3 => \^p_0_in\(0),
      I4 => p_4_in,
      I5 => \p_0_in__0_0\(1),
      O => wdf_rdy_ns
    );
\occupied_counter.app_wdf_rdy_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => app_wdf_wren_r1,
      I1 => app_wdf_end_r1,
      I2 => app_wdf_rdy_r_copy1,
      O => \p_0_in__0_0\(1)
    );
\occupied_counter.app_wdf_rdy_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wdf_rdy_ns,
      Q => app_wdf_rdy,
      R => '0'
    );
\occupied_counter.occ_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => app_wdf_rdy_r_copy1,
      I1 => app_wdf_end_r1,
      I2 => app_wdf_wren_r1,
      I3 => \occupied_counter.occ_cnt_reg_n_0_[1]\,
      O => p_1_in_0(0)
    );
\occupied_counter.occ_cnt[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[9]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[11]\,
      O => p_1_in_0(10)
    );
\occupied_counter.occ_cnt[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[10]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[12]\,
      O => p_1_in_0(11)
    );
\occupied_counter.occ_cnt[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[11]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[13]\,
      O => p_1_in_0(12)
    );
\occupied_counter.occ_cnt[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[12]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => p_4_in,
      O => p_1_in_0(13)
    );
\occupied_counter.occ_cnt[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[13]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[15]\,
      O => p_1_in_0(14)
    );
\occupied_counter.occ_cnt[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \^p_0_in\(0),
      I1 => app_wdf_rdy_r_copy1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_wren_r1,
      O => \occupied_counter.occ_cnt[15]_i_1_n_0\
    );
\occupied_counter.occ_cnt[15]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => app_wdf_rdy_r_copy1,
      I1 => app_wdf_end_r1,
      I2 => app_wdf_wren_r1,
      I3 => p_4_in,
      O => p_1_in_0(15)
    );
\occupied_counter.occ_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[0]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[2]\,
      O => p_1_in_0(1)
    );
\occupied_counter.occ_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[1]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[3]\,
      O => p_1_in_0(2)
    );
\occupied_counter.occ_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[2]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[4]\,
      O => p_1_in_0(3)
    );
\occupied_counter.occ_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[3]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[5]\,
      O => p_1_in_0(4)
    );
\occupied_counter.occ_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[4]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[6]\,
      O => p_1_in_0(5)
    );
\occupied_counter.occ_cnt[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[5]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[7]\,
      O => p_1_in_0(6)
    );
\occupied_counter.occ_cnt[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[6]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[8]\,
      O => p_1_in_0(7)
    );
\occupied_counter.occ_cnt[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[7]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[9]\,
      O => p_1_in_0(8)
    );
\occupied_counter.occ_cnt[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[8]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[10]\,
      O => p_1_in_0(9)
    );
\occupied_counter.occ_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(0),
      Q => \occupied_counter.occ_cnt_reg_n_0_[0]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(10),
      Q => \occupied_counter.occ_cnt_reg_n_0_[10]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(11),
      Q => \occupied_counter.occ_cnt_reg_n_0_[11]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(12),
      Q => \occupied_counter.occ_cnt_reg_n_0_[12]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(13),
      Q => \occupied_counter.occ_cnt_reg_n_0_[13]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(14),
      Q => p_4_in,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(15),
      Q => \occupied_counter.occ_cnt_reg_n_0_[15]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(1),
      Q => \occupied_counter.occ_cnt_reg_n_0_[1]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(2),
      Q => \occupied_counter.occ_cnt_reg_n_0_[2]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(3),
      Q => \occupied_counter.occ_cnt_reg_n_0_[3]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(4),
      Q => \occupied_counter.occ_cnt_reg_n_0_[4]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(5),
      Q => \occupied_counter.occ_cnt_reg_n_0_[5]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(6),
      Q => \occupied_counter.occ_cnt_reg_n_0_[6]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(7),
      Q => \occupied_counter.occ_cnt_reg_n_0_[7]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(8),
      Q => \occupied_counter.occ_cnt_reg_n_0_[8]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\occupied_counter.occ_cnt_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in_0(9),
      Q => \occupied_counter.occ_cnt_reg_n_0_[9]\,
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\pointer_ram.rams[0].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => B"00000",
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \write_data_control.wr_data_indx_r_reg\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => ADDRD(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \pointer_ram.pointer_wr_data\(1 downto 0),
      DIC(1 downto 0) => \pointer_ram.pointer_wr_data\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED\(1 downto 0),
      DOB(1 downto 0) => wr_data_buf_addr(1 downto 0),
      DOC(1 downto 0) => wr_data_pntr(1 downto 0),
      DOD(1 downto 0) => \NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \pointer_ram.pointer_we\
    );
\pointer_ram.rams[1].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => B"00000",
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \write_data_control.wr_data_indx_r_reg\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => ADDRD(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 2),
      DIC(1 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED\(1 downto 0),
      DOB(1 downto 0) => wr_data_buf_addr(3 downto 2),
      DOC(1 downto 0) => wr_data_pntr(3 downto 2),
      DOD(1 downto 0) => \NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \pointer_ram.pointer_we\
    );
\read_data_indx.rd_data_indx_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \p_0_in__1\(0)
    );
\read_data_indx.rd_data_indx_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \p_0_in__1\(1)
    );
\read_data_indx.rd_data_indx_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \p_0_in__1\(2)
    );
\read_data_indx.rd_data_indx_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(3),
      O => \p_0_in__1\(3)
    );
\read_data_indx.rd_data_indx_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__1\(0),
      Q => \^q\(0),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\read_data_indx.rd_data_indx_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__1\(1),
      Q => \^q\(1),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\read_data_indx.rd_data_indx_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__1\(2),
      Q => \^q\(2),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\read_data_indx.rd_data_indx_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__1\(3),
      Q => \^q\(3),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\read_data_indx.rd_data_upd_indx_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => E(0),
      Q => \^p_0_in\(0),
      R => '0'
    );
\wr_req_counter.wr_req_cnt_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DB24"
    )
        port map (
      I0 => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0),
      I1 => \^p_0_in\(0),
      I2 => wr_accepted,
      I3 => \wr_req_counter.wr_req_cnt_r\(1),
      O => \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\
    );
\wr_req_counter.wr_req_cnt_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7EF0810"
    )
        port map (
      I0 => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0),
      I1 => \wr_req_counter.wr_req_cnt_r\(1),
      I2 => \^p_0_in\(0),
      I3 => wr_accepted,
      I4 => \wr_req_counter.wr_req_cnt_r\(2),
      O => \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\
    );
\wr_req_counter.wr_req_cnt_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7FFEFF00800100"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r\(2),
      I1 => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0),
      I2 => \wr_req_counter.wr_req_cnt_r\(1),
      I3 => \^p_0_in\(0),
      I4 => wr_accepted,
      I5 => \wr_req_counter.wr_req_cnt_r\(3),
      O => \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\
    );
\wr_req_counter.wr_req_cnt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000006AA9AAAA"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r\(4),
      I1 => \wr_req_counter.wr_req_cnt_r\(3),
      I2 => \wr_req_counter.wr_req_cnt_r\(2),
      I3 => \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0\,
      I4 => \wr_req_counter.wr_req_cnt_r_reg[4]_0\,
      I5 => \wr_req_counter.wr_req_cnt_r_reg[0]_2\,
      O => \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\
    );
\wr_req_counter.wr_req_cnt_r[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80FE"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r\(1),
      I1 => wr_accepted,
      I2 => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0),
      I3 => \wr_req_counter.wr_req_cnt_r\(2),
      O => \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0\
    );
\wr_req_counter.wr_req_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r_reg[0]_1\,
      Q => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\wr_req_counter.wr_req_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\,
      Q => \wr_req_counter.wr_req_cnt_r\(1),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\wr_req_counter.wr_req_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\,
      Q => \wr_req_counter.wr_req_cnt_r\(2),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\wr_req_counter.wr_req_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\,
      Q => \wr_req_counter.wr_req_cnt_r\(3),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\wr_req_counter.wr_req_cnt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\,
      Q => \wr_req_counter.wr_req_cnt_r\(4),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(0),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(0),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(100),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(100),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(101),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(101),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(102),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(102),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(103),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(103),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(104),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(104),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(105),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(105),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(106),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(106),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(107),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(107),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(108),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(108),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(109),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(109),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(10),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(10),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(110),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(110),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(111),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(111),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(112),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(112),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(113),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(113),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(114),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(114),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(115),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(115),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(116),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(116),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(117),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(117),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(118),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(118),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(119),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(119),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(11),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(11),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[120]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(120),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(120),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[121]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(121),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(121),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[122]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(122),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(122),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[123]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(123),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(123),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[124]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(124),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(124),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(125),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(125),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(126),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(126),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[127]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(127),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(127),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[128]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(128),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(128),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[129]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(129),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(129),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(12),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(12),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[130]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(130),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(130),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[131]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(131),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(131),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[132]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(132),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(132),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[133]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(133),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(133),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[134]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(134),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(134),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[135]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(135),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(135),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[136]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(136),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(136),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[137]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(137),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(137),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[138]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(138),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(138),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[139]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(139),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(139),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(13),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(13),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[140]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(140),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(140),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[141]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(141),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(141),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[142]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(142),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(142),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[143]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(143),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(143),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(14),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(14),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(15),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(15),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(16),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(16),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(17),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(17),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(18),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(18),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(19),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(19),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(1),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(1),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(20),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(20),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(21),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(21),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(22),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(22),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(23),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(23),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(24),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(24),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(25),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(25),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(26),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(26),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(27),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(27),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(28),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(28),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(29),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(29),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(2),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(2),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(30),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(30),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(31),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(31),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(32),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(32),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(33),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(33),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(34),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(34),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(35),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(35),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(36),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(36),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(37),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(37),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(38),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(38),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(39),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(39),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(3),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(3),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(40),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(40),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(41),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(41),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(42),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(42),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(43),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(43),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(44),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(44),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(45),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(45),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(46),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(46),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(47),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(47),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(48),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(48),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(49),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(49),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(4),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(4),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(50),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(50),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(51),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(51),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(52),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(52),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(53),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(53),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(54),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(54),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(55),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(55),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(56),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(56),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(57),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(57),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(58),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(58),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(59),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(59),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(5),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(5),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(60),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(60),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(61),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(61),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(62),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(62),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(63),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(63),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(64),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(64),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(65),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(65),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(66),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(66),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(67),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(67),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(68),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(68),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(69),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(69),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(6),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(6),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(70),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(70),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(71),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(71),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(72),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(72),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(73),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(73),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(74),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(74),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(75),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(75),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(76),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(76),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(77),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(77),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(78),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(78),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(79),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(79),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(7),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(7),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(80),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(80),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(81),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(81),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(82),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(82),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(83),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(83),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(84),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(84),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(85),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(85),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(86),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(86),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(87),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(87),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(88),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(88),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(89),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(89),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(8),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(8),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(90),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(90),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(91),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(91),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(92),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(92),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(93),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(93),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(94),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(94),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(95),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(95),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(96),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(96),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(97),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(97),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(98),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(98),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(99),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(99),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(9),
      Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(9),
      R => '0'
    );
\write_buffer.wr_buffer_ram[0].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(5 downto 4),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(3 downto 2),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(5 downto 4),
      DOB(1 downto 0) => wr_buf_out_data_w(3 downto 2),
      DOC(1 downto 0) => wr_buf_out_data_w(1 downto 0),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(5),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(5),
      O => \write_buffer.wr_buf_in_data\(5)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => wr_data_pntr(0),
      I1 => \write_data_control.wb_wr_data_addr_r\(1),
      I2 => \write_data_control.wr_data_addr_le\,
      I3 => \wr_req_counter.wr_req_cnt_r_reg[0]_2\,
      O => wb_wr_data_addr_w(1)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02020F00"
    )
        port map (
      I0 => app_wdf_rdy_r_copy3,
      I1 => app_wdf_end_r1,
      I2 => \wr_req_counter.wr_req_cnt_r_reg[0]_2\,
      I3 => \write_data_control.wb_wr_data_addr0_r\,
      I4 => app_wdf_wren_r1,
      O => \write_data_control.wb_wr_data_addr0_ns\
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(4),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(4),
      O => \write_buffer.wr_buf_in_data\(4)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(3),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(3),
      O => \write_buffer.wr_buf_in_data\(3)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(2),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(2),
      O => \write_buffer.wr_buf_in_data\(2)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(1),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(1),
      O => \write_buffer.wr_buf_in_data\(1)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(0),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(0),
      O => \write_buffer.wr_buf_in_data\(0)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => wr_data_pntr(3),
      I1 => \write_data_control.wb_wr_data_addr_r\(4),
      I2 => \write_data_control.wr_data_addr_le\,
      I3 => \wr_req_counter.wr_req_cnt_r_reg[0]_2\,
      O => wb_wr_data_addr_w(4)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => wr_data_pntr(2),
      I1 => \write_data_control.wb_wr_data_addr_r\(3),
      I2 => \write_data_control.wr_data_addr_le\,
      I3 => \wr_req_counter.wr_req_cnt_r_reg[0]_2\,
      O => wb_wr_data_addr_w(3)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => wr_data_pntr(1),
      I1 => \write_data_control.wb_wr_data_addr_r\(2),
      I2 => \write_data_control.wr_data_addr_le\,
      I3 => \wr_req_counter.wr_req_cnt_r_reg[0]_2\,
      O => wb_wr_data_addr_w(2)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(65 downto 64),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(63 downto 62),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(61 downto 60),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(65 downto 64),
      DOB(1 downto 0) => wr_buf_out_data_w(63 downto 62),
      DOC(1 downto 0) => wr_buf_out_data_w(61 downto 60),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(65),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(65),
      O => \write_buffer.wr_buf_in_data\(65)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(64),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(64),
      O => \write_buffer.wr_buf_in_data\(64)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(63),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(63),
      O => \write_buffer.wr_buf_in_data\(63)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(62),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(62),
      O => \write_buffer.wr_buf_in_data\(62)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(61),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(61),
      O => \write_buffer.wr_buf_in_data\(61)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(60),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(60),
      O => \write_buffer.wr_buf_in_data\(60)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(71 downto 70),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(69 downto 68),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(67 downto 66),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(71 downto 70),
      DOB(1 downto 0) => wr_buf_out_data_w(69 downto 68),
      DOC(1 downto 0) => wr_buf_out_data_w(67 downto 66),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(71),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(71),
      O => \write_buffer.wr_buf_in_data\(71)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(70),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(70),
      O => \write_buffer.wr_buf_in_data\(70)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(69),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(69),
      O => \write_buffer.wr_buf_in_data\(69)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(68),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(68),
      O => \write_buffer.wr_buf_in_data\(68)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(67),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(67),
      O => \write_buffer.wr_buf_in_data\(67)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(66),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(66),
      O => \write_buffer.wr_buf_in_data\(66)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(77 downto 76),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(75 downto 74),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(73 downto 72),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(77 downto 76),
      DOB(1 downto 0) => wr_buf_out_data_w(75 downto 74),
      DOC(1 downto 0) => wr_buf_out_data_w(73 downto 72),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(77),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(77),
      O => \write_buffer.wr_buf_in_data\(77)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(76),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(76),
      O => \write_buffer.wr_buf_in_data\(76)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(75),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(75),
      O => \write_buffer.wr_buf_in_data\(75)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(74),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(74),
      O => \write_buffer.wr_buf_in_data\(74)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(73),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(73),
      O => \write_buffer.wr_buf_in_data\(73)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(72),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(72),
      O => \write_buffer.wr_buf_in_data\(72)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(83 downto 82),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(81 downto 80),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(79 downto 78),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(83 downto 82),
      DOB(1 downto 0) => wr_buf_out_data_w(81 downto 80),
      DOC(1 downto 0) => wr_buf_out_data_w(79 downto 78),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(83),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(83),
      O => \write_buffer.wr_buf_in_data\(83)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(82),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(82),
      O => \write_buffer.wr_buf_in_data\(82)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(81),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(81),
      O => \write_buffer.wr_buf_in_data\(81)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(80),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(80),
      O => \write_buffer.wr_buf_in_data\(80)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(79),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(79),
      O => \write_buffer.wr_buf_in_data\(79)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(78),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(78),
      O => \write_buffer.wr_buf_in_data\(78)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(89 downto 88),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(87 downto 86),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(85 downto 84),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(89 downto 88),
      DOB(1 downto 0) => wr_buf_out_data_w(87 downto 86),
      DOC(1 downto 0) => wr_buf_out_data_w(85 downto 84),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(89),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(89),
      O => \write_buffer.wr_buf_in_data\(89)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(88),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(88),
      O => \write_buffer.wr_buf_in_data\(88)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(87),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(87),
      O => \write_buffer.wr_buf_in_data\(87)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(86),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(86),
      O => \write_buffer.wr_buf_in_data\(86)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(85),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(85),
      O => \write_buffer.wr_buf_in_data\(85)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(84),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(84),
      O => \write_buffer.wr_buf_in_data\(84)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(95 downto 94),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(93 downto 92),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(91 downto 90),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(95 downto 94),
      DOB(1 downto 0) => wr_buf_out_data_w(93 downto 92),
      DOC(1 downto 0) => wr_buf_out_data_w(91 downto 90),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(95),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(95),
      O => \write_buffer.wr_buf_in_data\(95)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(94),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(94),
      O => \write_buffer.wr_buf_in_data\(94)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(93),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(93),
      O => \write_buffer.wr_buf_in_data\(93)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(92),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(92),
      O => \write_buffer.wr_buf_in_data\(92)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(91),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(91),
      O => \write_buffer.wr_buf_in_data\(91)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(90),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(90),
      O => \write_buffer.wr_buf_in_data\(90)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(101 downto 100),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(99 downto 98),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(97 downto 96),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(101 downto 100),
      DOB(1 downto 0) => wr_buf_out_data_w(99 downto 98),
      DOC(1 downto 0) => wr_buf_out_data_w(97 downto 96),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(101),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(101),
      O => \write_buffer.wr_buf_in_data\(101)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(100),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(100),
      O => \write_buffer.wr_buf_in_data\(100)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(99),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(99),
      O => \write_buffer.wr_buf_in_data\(99)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(98),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(98),
      O => \write_buffer.wr_buf_in_data\(98)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(97),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(97),
      O => \write_buffer.wr_buf_in_data\(97)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(96),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(96),
      O => \write_buffer.wr_buf_in_data\(96)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(107 downto 106),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(105 downto 104),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(103 downto 102),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(107 downto 106),
      DOB(1 downto 0) => wr_buf_out_data_w(105 downto 104),
      DOC(1 downto 0) => wr_buf_out_data_w(103 downto 102),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(107),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(107),
      O => \write_buffer.wr_buf_in_data\(107)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(106),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(106),
      O => \write_buffer.wr_buf_in_data\(106)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(105),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(105),
      O => \write_buffer.wr_buf_in_data\(105)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(104),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(104),
      O => \write_buffer.wr_buf_in_data\(104)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(103),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(103),
      O => \write_buffer.wr_buf_in_data\(103)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(102),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(102),
      O => \write_buffer.wr_buf_in_data\(102)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(113 downto 112),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(111 downto 110),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(109 downto 108),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(113 downto 112),
      DOB(1 downto 0) => wr_buf_out_data_w(111 downto 110),
      DOC(1 downto 0) => wr_buf_out_data_w(109 downto 108),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(113),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(113),
      O => \write_buffer.wr_buf_in_data\(113)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(112),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(112),
      O => \write_buffer.wr_buf_in_data\(112)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(111),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(111),
      O => \write_buffer.wr_buf_in_data\(111)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(110),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(110),
      O => \write_buffer.wr_buf_in_data\(110)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(109),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(109),
      O => \write_buffer.wr_buf_in_data\(109)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(108),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(108),
      O => \write_buffer.wr_buf_in_data\(108)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(119 downto 118),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(117 downto 116),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(115 downto 114),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(119 downto 118),
      DOB(1 downto 0) => wr_buf_out_data_w(117 downto 116),
      DOC(1 downto 0) => wr_buf_out_data_w(115 downto 114),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(119),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(119),
      O => \write_buffer.wr_buf_in_data\(119)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(118),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(118),
      O => \write_buffer.wr_buf_in_data\(118)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(117),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(117),
      O => \write_buffer.wr_buf_in_data\(117)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(116),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(116),
      O => \write_buffer.wr_buf_in_data\(116)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(115),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(115),
      O => \write_buffer.wr_buf_in_data\(115)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(114),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(114),
      O => \write_buffer.wr_buf_in_data\(114)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(11 downto 10),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(9 downto 8),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(7 downto 6),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(11 downto 10),
      DOB(1 downto 0) => wr_buf_out_data_w(9 downto 8),
      DOC(1 downto 0) => wr_buf_out_data_w(7 downto 6),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(11),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(11),
      O => \write_buffer.wr_buf_in_data\(11)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(10),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(10),
      O => \write_buffer.wr_buf_in_data\(10)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(9),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(9),
      O => \write_buffer.wr_buf_in_data\(9)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(8),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(8),
      O => \write_buffer.wr_buf_in_data\(8)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(7),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(7),
      O => \write_buffer.wr_buf_in_data\(7)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(6),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(6),
      O => \write_buffer.wr_buf_in_data\(6)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(125 downto 124),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(123 downto 122),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(121 downto 120),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(125 downto 124),
      DOB(1 downto 0) => wr_buf_out_data_w(123 downto 122),
      DOC(1 downto 0) => wr_buf_out_data_w(121 downto 120),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(125),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(125),
      O => \write_buffer.wr_buf_in_data\(125)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(124),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(124),
      O => \write_buffer.wr_buf_in_data\(124)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(123),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(123),
      O => \write_buffer.wr_buf_in_data\(123)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(122),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(122),
      O => \write_buffer.wr_buf_in_data\(122)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(121),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(121),
      O => \write_buffer.wr_buf_in_data\(121)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(120),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(120),
      O => \write_buffer.wr_buf_in_data\(120)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(131 downto 130),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(129 downto 128),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(127 downto 126),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(131 downto 130),
      DOB(1 downto 0) => wr_buf_out_data_w(129 downto 128),
      DOC(1 downto 0) => wr_buf_out_data_w(127 downto 126),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(3),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(3),
      O => \write_buffer.wr_buf_in_data\(131)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(2),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(2),
      O => \write_buffer.wr_buf_in_data\(130)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(1),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(1),
      O => \write_buffer.wr_buf_in_data\(129)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(0),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(0),
      O => \write_buffer.wr_buf_in_data\(128)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(127),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(127),
      O => \write_buffer.wr_buf_in_data\(127)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(126),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(126),
      O => \write_buffer.wr_buf_in_data\(126)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(137 downto 136),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(135 downto 134),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(133 downto 132),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(137 downto 136),
      DOB(1 downto 0) => wr_buf_out_data_w(135 downto 134),
      DOC(1 downto 0) => wr_buf_out_data_w(133 downto 132),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(9),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(9),
      O => \write_buffer.wr_buf_in_data\(137)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(8),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(8),
      O => \write_buffer.wr_buf_in_data\(136)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(7),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(7),
      O => \write_buffer.wr_buf_in_data\(135)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(6),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(6),
      O => \write_buffer.wr_buf_in_data\(134)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(5),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(5),
      O => \write_buffer.wr_buf_in_data\(133)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(4),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(4),
      O => \write_buffer.wr_buf_in_data\(132)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(143 downto 142),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(141 downto 140),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(139 downto 138),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(143 downto 142),
      DOB(1 downto 0) => wr_buf_out_data_w(141 downto 140),
      DOC(1 downto 0) => wr_buf_out_data_w(139 downto 138),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(15),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(15),
      O => \write_buffer.wr_buf_in_data\(143)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(14),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(14),
      O => \write_buffer.wr_buf_in_data\(142)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(13),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(13),
      O => \write_buffer.wr_buf_in_data\(141)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(12),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(12),
      O => \write_buffer.wr_buf_in_data\(140)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(11),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(11),
      O => \write_buffer.wr_buf_in_data\(139)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(10),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(10),
      O => \write_buffer.wr_buf_in_data\(138)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(17 downto 16),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(15 downto 14),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(13 downto 12),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(17 downto 16),
      DOB(1 downto 0) => wr_buf_out_data_w(15 downto 14),
      DOC(1 downto 0) => wr_buf_out_data_w(13 downto 12),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(17),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(17),
      O => \write_buffer.wr_buf_in_data\(17)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(16),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(16),
      O => \write_buffer.wr_buf_in_data\(16)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(15),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(15),
      O => \write_buffer.wr_buf_in_data\(15)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(14),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(14),
      O => \write_buffer.wr_buf_in_data\(14)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(13),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(13),
      O => \write_buffer.wr_buf_in_data\(13)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(12),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(12),
      O => \write_buffer.wr_buf_in_data\(12)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(23 downto 22),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(21 downto 20),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(19 downto 18),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(23 downto 22),
      DOB(1 downto 0) => wr_buf_out_data_w(21 downto 20),
      DOC(1 downto 0) => wr_buf_out_data_w(19 downto 18),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(23),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(23),
      O => \write_buffer.wr_buf_in_data\(23)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(22),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(22),
      O => \write_buffer.wr_buf_in_data\(22)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(21),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(21),
      O => \write_buffer.wr_buf_in_data\(21)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(20),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(20),
      O => \write_buffer.wr_buf_in_data\(20)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(19),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(19),
      O => \write_buffer.wr_buf_in_data\(19)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(18),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(18),
      O => \write_buffer.wr_buf_in_data\(18)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(29 downto 28),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(27 downto 26),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(25 downto 24),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(29 downto 28),
      DOB(1 downto 0) => wr_buf_out_data_w(27 downto 26),
      DOC(1 downto 0) => wr_buf_out_data_w(25 downto 24),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(29),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(29),
      O => \write_buffer.wr_buf_in_data\(29)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(28),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(28),
      O => \write_buffer.wr_buf_in_data\(28)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(27),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(27),
      O => \write_buffer.wr_buf_in_data\(27)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(26),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(26),
      O => \write_buffer.wr_buf_in_data\(26)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(25),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(25),
      O => \write_buffer.wr_buf_in_data\(25)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(24),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(24),
      O => \write_buffer.wr_buf_in_data\(24)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(35 downto 34),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(33 downto 32),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(31 downto 30),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(35 downto 34),
      DOB(1 downto 0) => wr_buf_out_data_w(33 downto 32),
      DOC(1 downto 0) => wr_buf_out_data_w(31 downto 30),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(35),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(35),
      O => \write_buffer.wr_buf_in_data\(35)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(34),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(34),
      O => \write_buffer.wr_buf_in_data\(34)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(33),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(33),
      O => \write_buffer.wr_buf_in_data\(33)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(32),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(32),
      O => \write_buffer.wr_buf_in_data\(32)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(31),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(31),
      O => \write_buffer.wr_buf_in_data\(31)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(30),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(30),
      O => \write_buffer.wr_buf_in_data\(30)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(41 downto 40),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(39 downto 38),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(37 downto 36),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(41 downto 40),
      DOB(1 downto 0) => wr_buf_out_data_w(39 downto 38),
      DOC(1 downto 0) => wr_buf_out_data_w(37 downto 36),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(41),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(41),
      O => \write_buffer.wr_buf_in_data\(41)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(40),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(40),
      O => \write_buffer.wr_buf_in_data\(40)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(39),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(39),
      O => \write_buffer.wr_buf_in_data\(39)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(38),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(38),
      O => \write_buffer.wr_buf_in_data\(38)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(37),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(37),
      O => \write_buffer.wr_buf_in_data\(37)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(36),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(36),
      O => \write_buffer.wr_buf_in_data\(36)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(47 downto 46),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(45 downto 44),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(43 downto 42),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(47 downto 46),
      DOB(1 downto 0) => wr_buf_out_data_w(45 downto 44),
      DOC(1 downto 0) => wr_buf_out_data_w(43 downto 42),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(47),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(47),
      O => \write_buffer.wr_buf_in_data\(47)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(46),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(46),
      O => \write_buffer.wr_buf_in_data\(46)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(45),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(45),
      O => \write_buffer.wr_buf_in_data\(45)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(44),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(44),
      O => \write_buffer.wr_buf_in_data\(44)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(43),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(43),
      O => \write_buffer.wr_buf_in_data\(43)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(42),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(42),
      O => \write_buffer.wr_buf_in_data\(42)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(53 downto 52),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(51 downto 50),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(49 downto 48),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(53 downto 52),
      DOB(1 downto 0) => wr_buf_out_data_w(51 downto 50),
      DOC(1 downto 0) => wr_buf_out_data_w(49 downto 48),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(53),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(53),
      O => \write_buffer.wr_buf_in_data\(53)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(52),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(52),
      O => \write_buffer.wr_buf_in_data\(52)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(51),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(51),
      O => \write_buffer.wr_buf_in_data\(51)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(50),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(50),
      O => \write_buffer.wr_buf_in_data\(50)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(49),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(49),
      O => \write_buffer.wr_buf_in_data\(49)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(48),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(48),
      O => \write_buffer.wr_buf_in_data\(48)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(59 downto 58),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(57 downto 56),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(55 downto 54),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(59 downto 58),
      DOB(1 downto 0) => wr_buf_out_data_w(57 downto 56),
      DOC(1 downto 0) => wr_buf_out_data_w(55 downto 54),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(59),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(59),
      O => \write_buffer.wr_buf_in_data\(59)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(58),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(58),
      O => \write_buffer.wr_buf_in_data\(58)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(57),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(57),
      O => \write_buffer.wr_buf_in_data\(57)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(56),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(56),
      O => \write_buffer.wr_buf_in_data\(56)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(55),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(55),
      O => \write_buffer.wr_buf_in_data\(55)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(54),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(54),
      O => \write_buffer.wr_buf_in_data\(54)
    );
\write_data_control.wb_wr_data_addr0_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \write_data_control.wb_wr_data_addr0_ns\,
      Q => \write_data_control.wb_wr_data_addr0_r\,
      R => '0'
    );
\write_data_control.wb_wr_data_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wb_wr_data_addr_w(1),
      Q => \write_data_control.wb_wr_data_addr_r\(1),
      R => '0'
    );
\write_data_control.wb_wr_data_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wb_wr_data_addr_w(2),
      Q => \write_data_control.wb_wr_data_addr_r\(2),
      R => '0'
    );
\write_data_control.wb_wr_data_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wb_wr_data_addr_w(3),
      Q => \write_data_control.wb_wr_data_addr_r\(3),
      R => '0'
    );
\write_data_control.wb_wr_data_addr_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wb_wr_data_addr_w(4),
      Q => \write_data_control.wb_wr_data_addr_r\(4),
      R => '0'
    );
\write_data_control.wr_data_indx_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r_reg\(0),
      O => \p_0_in__0__0\(0)
    );
\write_data_control.wr_data_indx_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r_reg\(0),
      I1 => \write_data_control.wr_data_indx_r_reg\(1),
      O => \p_0_in__0__0\(1)
    );
\write_data_control.wr_data_indx_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r_reg\(0),
      I1 => \write_data_control.wr_data_indx_r_reg\(1),
      I2 => \write_data_control.wr_data_indx_r_reg\(2),
      O => \p_0_in__0__0\(2)
    );
\write_data_control.wr_data_indx_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1100FFFF01000100"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r[3]_i_3_n_0\,
      I1 => \wr_req_counter.wr_req_cnt_r_reg[0]_2\,
      I2 => \occupied_counter.occ_cnt_reg_n_0_[15]\,
      I3 => \p_0_in__0_0\(1),
      I4 => app_wdf_rdy_r_copy1,
      I5 => \^p_0_in\(0),
      O => \write_data_control.wr_data_addr_le\
    );
\write_data_control.wr_data_indx_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r_reg\(2),
      I1 => \write_data_control.wr_data_indx_r_reg\(1),
      I2 => \write_data_control.wr_data_indx_r_reg\(0),
      I3 => \write_data_control.wr_data_indx_r_reg\(3),
      O => \p_0_in__0__0\(3)
    );
\write_data_control.wr_data_indx_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008000FFFFFFFF"
    )
        port map (
      I0 => app_wdf_wren_r1,
      I1 => app_wdf_end_r1,
      I2 => app_wdf_rdy_r_copy1,
      I3 => p_4_in,
      I4 => \^p_0_in\(0),
      I5 => ram_init_done_r,
      O => \write_data_control.wr_data_indx_r[3]_i_3_n_0\
    );
\write_data_control.wr_data_indx_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \write_data_control.wr_data_addr_le\,
      D => \p_0_in__0__0\(0),
      Q => \write_data_control.wr_data_indx_r_reg\(0),
      S => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\write_data_control.wr_data_indx_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \write_data_control.wr_data_addr_le\,
      D => \p_0_in__0__0\(1),
      Q => \write_data_control.wr_data_indx_r_reg\(1),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\write_data_control.wr_data_indx_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \write_data_control.wr_data_addr_le\,
      D => \p_0_in__0__0\(2),
      Q => \write_data_control.wr_data_indx_r_reg\(2),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
\write_data_control.wr_data_indx_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \write_data_control.wr_data_addr_le\,
      D => \p_0_in__0__0\(3),
      Q => \write_data_control.wr_data_indx_r_reg\(3),
      R => \wr_req_counter.wr_req_cnt_r_reg[0]_2\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_arb_row_col is
  port (
    rnk_config_valid_r_lcl_reg_0 : out STD_LOGIC;
    granted_col_r_reg_0 : out STD_LOGIC;
    insert_maint_r1_lcl_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    rd_wr_r_lcl_reg : out STD_LOGIC;
    granted_col_r_reg_1 : out STD_LOGIC;
    granted_col_r_reg_2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_odt_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \periodic_rd_generation.read_this_rank\ : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    rd_wr_r_lcl_reg_1 : out STD_LOGIC;
    rd_wr_r_lcl_reg_2 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_aux_out0_1 : out STD_LOGIC;
    col_rd_wr : out STD_LOGIC;
    DIC : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \grant_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
    \grant_r_reg[3]_1\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    col_wr_data_buf_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \grant_r_reg[3]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    granted_row_r_reg_0 : out STD_LOGIC;
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_cs_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \genblk3[2].rnk_config_strobe_r_reg[2]_0\ : out STD_LOGIC;
    p_0_in : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[3]_3\ : out STD_LOGIC;
    \grant_r_reg[3]_4\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rstdiv0_sync_r1_reg_rep__11\ : out STD_LOGIC;
    \grant_r_reg[3]_5\ : out STD_LOGIC;
    \wr_this_rank_r_reg[0]\ : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    act_this_rank : out STD_LOGIC;
    \grant_r_reg[3]_6\ : out STD_LOGIC;
    \grant_r_reg[3]_7\ : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    \genblk3[1].rnk_config_strobe_r_reg[1]_0\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    rnk_config_strobe_ns : in STD_LOGIC;
    rnk_config_valid_ns : in STD_LOGIC;
    insert_maint_r1_lcl_reg_1 : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg_0\ : in STD_LOGIC;
    rd_wr_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \col_mux.col_periodic_rd_r\ : in STD_LOGIC;
    \col_mux.col_periodic_rd_r_reg\ : in STD_LOGIC;
    granted_col_r_reg_3 : in STD_LOGIC;
    col_wait_r : in STD_LOGIC;
    \grant_r_reg[0]_0\ : in STD_LOGIC;
    \grant_r_reg[0]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_odt_reg[0]\ : in STD_LOGIC;
    \grant_r_reg[0]_2\ : in STD_LOGIC;
    \grant_r_reg[0]_3\ : in STD_LOGIC;
    \grant_r_reg[2]_0\ : in STD_LOGIC;
    \grant_r_reg[0]_4\ : in STD_LOGIC;
    \grant_r_reg[2]_1\ : in STD_LOGIC;
    rd_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \grant_r_reg[1]_0\ : in STD_LOGIC;
    \grant_r_reg[2]_2\ : in STD_LOGIC;
    \grant_r_reg[1]_1\ : in STD_LOGIC;
    col_wait_r_0 : in STD_LOGIC;
    \grant_r[1]_i_3\ : in STD_LOGIC;
    \grant_r[3]_i_2\ : in STD_LOGIC;
    granted_col_r_reg_4 : in STD_LOGIC;
    granted_col_r_reg_5 : in STD_LOGIC;
    granted_col_r_reg_6 : in STD_LOGIC;
    granted_col_r_reg_7 : in STD_LOGIC;
    granted_col_r_reg_8 : in STD_LOGIC;
    \grant_r[3]_i_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr_r : in STD_LOGIC;
    req_periodic_rd_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_address_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[9]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    auto_pre_r : in STD_LOGIC;
    auto_pre_r_1 : in STD_LOGIC;
    auto_pre_r_2 : in STD_LOGIC;
    auto_pre_r_3 : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[5]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    req_data_buf_addr_r : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    row_cmd_wr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[1]\ : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[38]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
    req_row_r : in STD_LOGIC_VECTOR ( 38 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_cas_n_reg[1]\ : in STD_LOGIC;
    maint_rank_r : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[1]_0\ : in STD_LOGIC;
    rnk_config_r : in STD_LOGIC;
    demand_act_priority_r : in STD_LOGIC;
    granted_row_r_reg_1 : in STD_LOGIC;
    granted_row_r_reg_2 : in STD_LOGIC;
    \grant_r_reg[0]_5\ : in STD_LOGIC;
    \grant_r_reg[0]_6\ : in STD_LOGIC;
    \grant_r_reg[0]_7\ : in STD_LOGIC;
    \grant_r_reg[2]_3\ : in STD_LOGIC;
    \grant_r_reg[3]_8\ : in STD_LOGIC;
    \grant_r_reg[3]_9\ : in STD_LOGIC;
    demand_act_priority_r_4 : in STD_LOGIC;
    demand_act_priority_r_5 : in STD_LOGIC;
    \grant_r_reg[3]_10\ : in STD_LOGIC;
    inhbt_act_faw_r : in STD_LOGIC;
    wr_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \last_master_r_reg[3]\ : in STD_LOGIC;
    act_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    demand_act_priority_r_6 : in STD_LOGIC;
    demand_priority_r : in STD_LOGIC;
    override_demand_r : in STD_LOGIC;
    demand_priority_r_7 : in STD_LOGIC;
    demanded_prior_r : in STD_LOGIC;
    demanded_prior_r_8 : in STD_LOGIC;
    demanded_prior_r_9 : in STD_LOGIC;
    demand_priority_r_10 : in STD_LOGIC;
    demanded_prior_r_11 : in STD_LOGIC;
    demand_priority_r_12 : in STD_LOGIC;
    ofs_rdy_r : in STD_LOGIC;
    ofs_rdy_r_13 : in STD_LOGIC;
    ofs_rdy_r_14 : in STD_LOGIC;
    ofs_rdy_r_15 : in STD_LOGIC;
    \grant_r[3]_i_5_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r[3]_i_8\ : in STD_LOGIC;
    \grant_r_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_arb_row_col : entity is "mig_7series_v4_2_arb_row_col";
end mig_7series_0_mig_7series_v4_2_arb_row_col;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_arb_row_col is
  signal col_arb0_n_4 : STD_LOGIC;
  signal col_arb0_n_46 : STD_LOGIC;
  signal col_arb0_n_47 : STD_LOGIC;
  signal col_arb0_n_48 : STD_LOGIC;
  signal col_arb0_n_49 : STD_LOGIC;
  signal config_arb0_n_0 : STD_LOGIC;
  signal config_arb0_n_1 : STD_LOGIC;
  signal config_arb0_n_2 : STD_LOGIC;
  signal config_arb0_n_3 : STD_LOGIC;
  signal cs_en2 : STD_LOGIC;
  signal \^genblk3[2].rnk_config_strobe_r_reg[2]_0\ : STD_LOGIC;
  signal \^granted_col_r_reg_0\ : STD_LOGIC;
  signal granted_row_ns : STD_LOGIC;
  signal \^insert_maint_r1_lcl_reg_0\ : STD_LOGIC;
  signal rnk_config_strobe : STD_LOGIC;
  signal rnk_config_strobe_0 : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal \^rnk_config_valid_r_lcl_reg_0\ : STD_LOGIC;
  signal sent_row : STD_LOGIC;
begin
  \genblk3[2].rnk_config_strobe_r_reg[2]_0\ <= \^genblk3[2].rnk_config_strobe_r_reg[2]_0\;
  granted_col_r_reg_0 <= \^granted_col_r_reg_0\;
  insert_maint_r1_lcl_reg_0 <= \^insert_maint_r1_lcl_reg_0\;
  rnk_config_valid_r_lcl_reg_0 <= \^rnk_config_valid_r_lcl_reg_0\;
\cmd_pipe_plus.mc_cas_n[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^granted_col_r_reg_0\,
      O => mc_cas_n_ns(0)
    );
\cmd_pipe_plus.mc_ras_n[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cs_en2,
      O => mc_ras_n_ns(2)
    );
col_arb0: entity work.\mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1\
     port map (
      CLK => CLK,
      DIC(0) => DIC(0),
      E(0) => E(0),
      Q(3 downto 0) => Q(3 downto 0),
      auto_pre_r => auto_pre_r,
      auto_pre_r_1 => auto_pre_r_1,
      auto_pre_r_2 => auto_pre_r_2,
      auto_pre_r_3 => auto_pre_r_3,
      auto_pre_r_lcl_reg(10 downto 0) => \grant_r_reg[3]_0\(10 downto 0),
      \cmd_pipe_plus.mc_address_reg[9]\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[9]\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[9]_0\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[9]_0\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[9]_1\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[9]_1\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[9]_2\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[9]_2\(9 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[5]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_2\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[5]_0\(2 downto 0),
      \cmd_pipe_plus.mc_data_offset_reg[2]\(1 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[2]\(1 downto 0),
      \cmd_pipe_plus.mc_odt_reg[0]\ => \^granted_col_r_reg_0\,
      \cmd_pipe_plus.mc_odt_reg[0]_0\ => \cmd_pipe_plus.mc_odt_reg[0]\,
      \col_mux.col_periodic_rd_r\ => \col_mux.col_periodic_rd_r\,
      \col_mux.col_periodic_rd_r_reg\ => \col_mux.col_periodic_rd_r_reg\,
      col_rd_wr => col_rd_wr,
      col_rd_wr_r => col_rd_wr_r,
      col_wait_r => col_wait_r,
      col_wait_r_0 => col_wait_r_0,
      col_wait_r_reg => col_arb0_n_4,
      col_wr_data_buf_addr(3 downto 0) => col_wr_data_buf_addr(3 downto 0),
      \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0),
      demand_priority_r => demand_priority_r,
      demand_priority_r_10 => demand_priority_r_10,
      demand_priority_r_12 => demand_priority_r_12,
      demand_priority_r_7 => demand_priority_r_7,
      demanded_prior_r => demanded_prior_r,
      demanded_prior_r_11 => demanded_prior_r_11,
      demanded_prior_r_8 => demanded_prior_r_8,
      demanded_prior_r_9 => demanded_prior_r_9,
      demanded_prior_r_reg => demanded_prior_r_reg,
      demanded_prior_r_reg_0 => demanded_prior_r_reg_0,
      \genblk3[2].rnk_config_strobe_r_reg[2]\ => \^genblk3[2].rnk_config_strobe_r_reg[2]_0\,
      \grant_r[1]_i_3\ => config_arb0_n_0,
      \grant_r[1]_i_3_0\ => \grant_r[1]_i_3\,
      \grant_r[3]_i_2\ => config_arb0_n_1,
      \grant_r[3]_i_2_0\ => \grant_r[3]_i_2\,
      \grant_r[3]_i_5_0\(0) => \grant_r[3]_i_5\(0),
      \grant_r[3]_i_5_1\(0) => \grant_r[3]_i_5_0\(0),
      \grant_r[3]_i_8_0\ => \grant_r[3]_i_8\,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]\,
      \grant_r_reg[0]_1\ => col_arb0_n_49,
      \grant_r_reg[0]_2\ => \grant_r_reg[0]_0\,
      \grant_r_reg[0]_3\ => \grant_r_reg[0]_1\,
      \grant_r_reg[1]_0\ => \grant_r_reg[1]\,
      \grant_r_reg[1]_1\ => col_arb0_n_47,
      \grant_r_reg[1]_2\ => \grant_r_reg[1]_0\,
      \grant_r_reg[1]_3\ => \grant_r_reg[1]_1\,
      \grant_r_reg[2]_0\ => col_arb0_n_46,
      \grant_r_reg[2]_1\ => \grant_r_reg[2]_2\,
      \grant_r_reg[3]_0\ => \grant_r_reg[3]\,
      \grant_r_reg[3]_1\ => \grant_r_reg[3]_5\,
      \grant_r_reg[3]_2\ => col_arb0_n_48,
      granted_col_r_reg => granted_col_r_reg_1,
      granted_col_r_reg_0(1 downto 0) => granted_col_r_reg_2(1 downto 0),
      granted_col_r_reg_1(0) => act_wait_r_lcl_reg(0),
      granted_col_r_reg_2 => granted_col_r_reg_3,
      granted_col_r_reg_3 => config_arb0_n_2,
      granted_col_r_reg_4 => granted_col_r_reg_4,
      granted_col_r_reg_5 => granted_col_r_reg_5,
      granted_col_r_reg_6 => granted_col_r_reg_6,
      granted_col_r_reg_7 => config_arb0_n_3,
      granted_col_r_reg_8 => granted_col_r_reg_7,
      granted_col_r_reg_9 => granted_col_r_reg_8,
      \last_master_r_reg[0]_0\ => \last_master_r_reg[3]\,
      mc_aux_out0_1 => mc_aux_out0_1,
      mc_odt_ns(0) => mc_odt_ns(0),
      mc_ras_n_ns(0) => mc_ras_n_ns(0),
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r_13 => ofs_rdy_r_13,
      ofs_rdy_r_14 => ofs_rdy_r_14,
      ofs_rdy_r_15 => ofs_rdy_r_15,
      override_demand_r => override_demand_r,
      \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\,
      rd_this_rank_r(3 downto 0) => rd_this_rank_r(3 downto 0),
      rd_wr_r(3 downto 0) => rd_wr_r(3 downto 0),
      rd_wr_r_lcl_reg => rd_wr_r_lcl_reg,
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg_0,
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_1,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_2,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \grant_r_reg[3]_1\(2 downto 0),
      req_data_buf_addr_r(15 downto 0) => req_data_buf_addr_r(15 downto 0),
      req_periodic_rd_r(3 downto 0) => req_periodic_rd_r(3 downto 0),
      rnk_config_strobe => rnk_config_strobe,
      rnk_config_strobe_0(1 downto 0) => rnk_config_strobe_0(2 downto 1),
      wr_this_rank_r(3 downto 0) => wr_this_rank_r(3 downto 0),
      \wr_this_rank_r_reg[0]\ => \wr_this_rank_r_reg[0]\
    );
config_arb0: entity work.\mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_3\
     port map (
      CLK => CLK,
      \genblk3[1].rnk_config_strobe_r_reg[1]\ => \genblk3[1].rnk_config_strobe_r_reg[1]_0\,
      \grant_r[2]_i_4__0\ => \^rnk_config_valid_r_lcl_reg_0\,
      \grant_r[3]_i_5\ => \^genblk3[2].rnk_config_strobe_r_reg[2]_0\,
      \grant_r[3]_i_5_0\ => col_arb0_n_46,
      \grant_r[3]_i_7\ => col_arb0_n_48,
      \grant_r[3]_i_8\ => col_arb0_n_49,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]_2\,
      \grant_r_reg[0]_1\ => \grant_r_reg[0]_3\,
      \grant_r_reg[0]_2\ => \grant_r_reg[0]_4\,
      \grant_r_reg[2]_0\ => \grant_r_reg[2]_0\,
      granted_col_r_i_3 => col_arb0_n_47,
      \last_master_r_reg[3]_0\ => \last_master_r_reg[3]\,
      p_0_in => p_0_in,
      rnk_config_r => rnk_config_r,
      \rnk_config_r_reg[0]\ => \cmd_pipe_plus.mc_cas_n_reg[1]\,
      rnk_config_strobe => rnk_config_strobe,
      rnk_config_strobe_0(1 downto 0) => rnk_config_strobe_0(2 downto 1),
      \rnk_config_strobe_r_reg[0]\ => config_arb0_n_0,
      \rnk_config_strobe_r_reg[0]_0\ => config_arb0_n_1,
      \rnk_config_strobe_r_reg[0]_1\ => config_arb0_n_2,
      \rnk_config_strobe_r_reg[0]_2\ => config_arb0_n_3
    );
\genblk3[1].rnk_config_strobe_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rnk_config_strobe,
      Q => rnk_config_strobe_0(1),
      R => '0'
    );
\genblk3[2].rnk_config_strobe_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rnk_config_strobe_0(1),
      Q => rnk_config_strobe_0(2),
      R => '0'
    );
granted_col_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => col_arb0_n_4,
      Q => \^granted_col_r_reg_0\,
      R => '0'
    );
granted_row_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => granted_row_ns,
      Q => sent_row,
      R => '0'
    );
insert_maint_r1_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => insert_maint_r1_lcl_reg_1,
      Q => \^insert_maint_r1_lcl_reg_0\,
      R => '0'
    );
\pre_4_1_1T_arb.granted_pre_r_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \pre_4_1_1T_arb.granted_pre_r_reg_0\,
      Q => cs_en2,
      R => '0'
    );
\pre_4_1_1T_arb.pre_arb0\: entity work.\mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_4\
     port map (
      CLK => CLK,
      Q(3 downto 0) => \grant_r_reg[3]_4\(3 downto 0),
      act_wait_r_lcl_reg(0) => act_wait_r_lcl_reg(2),
      \cmd_pipe_plus.mc_address_reg[38]\(12 downto 0) => \cmd_pipe_plus.mc_address_reg[38]\(12 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]_1\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[5]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]_2\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[5]_0\(2 downto 0),
      cs_en2 => cs_en2,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]_5\,
      \grant_r_reg[0]_1\ => \grant_r_reg[0]_6\,
      \grant_r_reg[0]_2\ => \grant_r_reg[0]_7\,
      \grant_r_reg[1]_0\(0) => \grant_r_reg[1]_2\(0),
      \grant_r_reg[2]_0\(1 downto 0) => \grant_r_reg[2]\(1 downto 0),
      \grant_r_reg[2]_1\ => \grant_r_reg[2]_3\,
      \grant_r_reg[2]_2\ => \cmd_pipe_plus.mc_cas_n_reg[1]\,
      \grant_r_reg[3]_0\ => \grant_r_reg[3]_3\,
      \grant_r_reg[3]_1\(12 downto 0) => \grant_r_reg[3]_0\(36 downto 24),
      \grant_r_reg[3]_2\(2 downto 0) => \grant_r_reg[3]_1\(8 downto 6),
      \grant_r_reg[3]_3\ => \grant_r_reg[3]_8\,
      \last_master_r_reg[0]_0\ => \last_master_r_reg[3]\,
      mc_cas_n_ns(0) => mc_cas_n_ns(2),
      req_row_r(38 downto 0) => req_row_r(38 downto 0),
      row_cmd_wr(3 downto 0) => row_cmd_wr(3 downto 0),
      \rstdiv0_sync_r1_reg_rep__11\ => \rstdiv0_sync_r1_reg_rep__11\
    );
\rnk_config_strobe_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rnk_config_strobe_ns,
      Q => rnk_config_strobe,
      R => '0'
    );
rnk_config_valid_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rnk_config_valid_ns,
      Q => \^rnk_config_valid_r_lcl_reg_0\,
      R => '0'
    );
row_arb0: entity work.\mig_7series_0_mig_7series_v4_2_round_robin_arb__parameterized1_5\
     port map (
      CLK => CLK,
      Q(3 downto 0) => \grant_r_reg[3]_2\(3 downto 0),
      act_this_rank => act_this_rank,
      act_this_rank_r(3 downto 0) => act_this_rank_r(3 downto 0),
      act_wait_r_lcl_reg(0) => act_wait_r_lcl_reg(1),
      \cmd_pipe_plus.mc_address_reg[23]\ => \cmd_pipe_plus.mc_address_reg[23]\,
      \cmd_pipe_plus.mc_address_reg[25]\(12 downto 0) => \cmd_pipe_plus.mc_address_reg[38]\(12 downto 0),
      \cmd_pipe_plus.mc_bank_reg[5]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[5]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[5]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[5]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[5]_1\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[5]_2\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0),
      \cmd_pipe_plus.mc_cas_n_reg[1]\ => \cmd_pipe_plus.mc_cas_n_reg[1]\,
      \cmd_pipe_plus.mc_cs_n_reg[1]\ => \^insert_maint_r1_lcl_reg_0\,
      \cmd_pipe_plus.mc_we_n_reg[1]\ => \cmd_pipe_plus.mc_we_n_reg[1]\,
      \cmd_pipe_plus.mc_we_n_reg[1]_0\ => \cmd_pipe_plus.mc_we_n_reg[1]_0\,
      demand_act_priority_r => demand_act_priority_r,
      demand_act_priority_r_4 => demand_act_priority_r_4,
      demand_act_priority_r_5 => demand_act_priority_r_5,
      demand_act_priority_r_6 => demand_act_priority_r_6,
      \grant_r[3]_i_4__0_0\ => insert_maint_r1_lcl_reg_1,
      \grant_r_reg[2]_0\ => \grant_r_reg[2]_1\,
      \grant_r_reg[3]_0\ => \grant_r_reg[3]_6\,
      \grant_r_reg[3]_1\ => \grant_r_reg[3]_7\,
      \grant_r_reg[3]_2\ => \grant_r_reg[3]_9\,
      \grant_r_reg[3]_3\ => \grant_r_reg[3]_10\,
      granted_row_ns => granted_row_ns,
      granted_row_r_reg => granted_row_r_reg_0,
      granted_row_r_reg_0 => granted_row_r_reg_1,
      granted_row_r_reg_1 => granted_row_r_reg_2,
      inhbt_act_faw_r => inhbt_act_faw_r,
      \last_master_r_reg[3]_0\ => \last_master_r_reg[3]\,
      maint_rank_r => maint_rank_r,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      mc_cas_n_ns(0) => mc_cas_n_ns(1),
      mc_cs_n_ns(0) => mc_cs_n_ns(0),
      mc_ras_n_ns(0) => mc_ras_n_ns(1),
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \grant_r_reg[3]_1\(5 downto 3),
      req_row_r(37 downto 1) => req_row_r(38 downto 2),
      req_row_r(0) => req_row_r(0),
      \req_row_r_lcl_reg[12]\(12 downto 0) => \grant_r_reg[3]_0\(23 downto 11),
      row_cmd_wr(2 downto 0) => row_cmd_wr(3 downto 1),
      sent_row => sent_row
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_bank_cntrl is
  port (
    idle_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1 : out STD_LOGIC;
    p_130_out : out STD_LOGIC;
    row_cmd_wr : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_act_priority_r : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r : out STD_LOGIC;
    demanded_prior_r : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    col_wait_r : out STD_LOGIC;
    auto_pre_r : out STD_LOGIC;
    ordered_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg : out STD_LOGIC;
    col_wait_r_reg : out STD_LOGIC;
    \q_entry_r_reg[0]\ : out STD_LOGIC;
    \ras_timer_r_reg[1]\ : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    \order_q_r_reg[0]\ : out STD_LOGIC;
    idle_r_lcl_reg_0 : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    req_wr_r_lcl_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_9_in : out STD_LOGIC;
    pre_bm_end_r_reg : out STD_LOGIC;
    rb_hit_busy_r_reg : out STD_LOGIC;
    q_entry_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    pre_bm_end_r_reg_1 : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    idle_r_lcl_reg_2 : out STD_LOGIC;
    idle_r_lcl_reg_3 : out STD_LOGIC;
    idle_r_lcl_reg_4 : out STD_LOGIC;
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    \req_row_r_lcl_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    head_r_lcl_reg : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    ras_timer_zero_r_reg_1 : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    \grant_r_reg[0]_0\ : out STD_LOGIC;
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    \req_data_buf_addr_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    CLK : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    p_145_out : in STD_LOGIC;
    ofs_rdy_r_reg : in STD_LOGIC;
    ofs_rdy_r0 : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 2 downto 0 );
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg_0 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : in STD_LOGIC;
    \grant_r_reg[0]_1\ : in STD_LOGIC;
    ras_timer_zero_r_reg_2 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pre_wait_r_reg : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    demand_priority_r_reg_1 : in STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    \grant_r[3]_i_12\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    q_has_priority_r_reg : in STD_LOGIC;
    was_priority : in STD_LOGIC;
    was_wr : in STD_LOGIC;
    q_has_rd_r_reg : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    col_wait_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg : in STD_LOGIC;
    pre_bm_end_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \maint_controller.maint_hit_busies_r_reg[0]\ : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    p_106_out : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ : in STD_LOGIC;
    p_67_out : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : in STD_LOGIC;
    p_28_out : in STD_LOGIC;
    p_13_out : in STD_LOGIC;
    rd_wr_r_lcl_reg : in STD_LOGIC;
    accept_internal_r_reg : in STD_LOGIC;
    accept_internal_r_reg_0 : in STD_LOGIC;
    accept_internal_r_reg_1 : in STD_LOGIC;
    accept_internal_r_reg_2 : in STD_LOGIC;
    head_r_lcl_reg_0 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \q_entry_r_reg[1]_0\ : in STD_LOGIC;
    \q_entry_r_reg[1]_1\ : in STD_LOGIC;
    maint_sre_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    maint_rank_r : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    accept_internal_r : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    app_en_r2 : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    \act_wait_r_lcl_i_4__1\ : in STD_LOGIC;
    \act_wait_r_lcl_i_4__1_0\ : in STD_LOGIC;
    \act_wait_r_lcl_i_4__1_1\ : in STD_LOGIC;
    \q_entry_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : in STD_LOGIC;
    \grant_r_reg[1]\ : in STD_LOGIC;
    \grant_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[1]_1\ : in STD_LOGIC;
    \grant_r_reg[1]_2\ : in STD_LOGIC;
    \grant_r_reg[1]_3\ : in STD_LOGIC;
    row : in STD_LOGIC_VECTOR ( 12 downto 0 );
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    demand_priority_r_0 : in STD_LOGIC;
    demanded_prior_r_1 : in STD_LOGIC;
    demanded_prior_r_reg : in STD_LOGIC;
    demand_priority_r_2 : in STD_LOGIC;
    override_demand_r : in STD_LOGIC;
    granted_col_r_i_3 : in STD_LOGIC;
    demand_priority_r_reg_4 : in STD_LOGIC;
    \q_entry_r_reg[1]_2\ : in STD_LOGIC;
    \q_entry_r_reg[1]_3\ : in STD_LOGIC;
    \q_entry_r_reg[1]_4\ : in STD_LOGIC;
    q_entry_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_data_buf_addr_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \order_q_r_reg[1]\ : in STD_LOGIC;
    \order_q_r_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_bank_cntrl : entity is "mig_7series_v4_2_bank_cntrl";
end mig_7series_0_mig_7series_v4_2_bank_cntrl;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_bank_cntrl is
  signal \^auto_pre_r\ : STD_LOGIC;
  signal bank_queue0_n_22 : STD_LOGIC;
  signal bank_state0_n_21 : STD_LOGIC;
  signal bank_state0_n_27 : STD_LOGIC;
  signal col_wait_ns : STD_LOGIC;
  signal \^col_wait_r\ : STD_LOGIC;
  signal demand_priority_ns : STD_LOGIC;
  signal \^grant_r_reg[0]\ : STD_LOGIC;
  signal head_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal idle_ns : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^idle_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^idle_r_lcl_reg_0\ : STD_LOGIC;
  signal \^order_q_r_reg[0]\ : STD_LOGIC;
  signal \^p_130_out\ : STD_LOGIC;
  signal pass_open_bank_ns : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg\ : STD_LOGIC;
  signal pre_bm_end_ns : STD_LOGIC;
  signal pre_passing_open_bank_ns : STD_LOGIC;
  signal pre_wait_r : STD_LOGIC;
  signal \^q_entry_r_reg[0]\ : STD_LOGIC;
  signal q_has_rd : STD_LOGIC;
  signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ras_timer_r_reg[1]\ : STD_LOGIC;
  signal ras_timer_zero_r : STD_LOGIC;
  signal \^rb_hit_busy_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg_0\ : STD_LOGIC;
  signal \^rd_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal req_bank_rdy_ns : STD_LOGIC;
  signal req_priority_r : STD_LOGIC;
  signal \^req_row_r_lcl_reg[12]\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal req_wr_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^req_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^row_cmd_wr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal row_hit_r : STD_LOGIC;
  signal start_wtp_timer0 : STD_LOGIC;
  signal tail_r : STD_LOGIC;
  signal wait_for_maint_r : STD_LOGIC;
begin
  auto_pre_r <= \^auto_pre_r\;
  col_wait_r <= \^col_wait_r\;
  \grant_r_reg[0]\ <= \^grant_r_reg[0]\;
  idle_r(0) <= \^idle_r\(0);
  idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\;
  \order_q_r_reg[0]\ <= \^order_q_r_reg[0]\;
  p_130_out <= \^p_130_out\;
  pass_open_bank_r_lcl_reg <= \^pass_open_bank_r_lcl_reg\;
  \q_entry_r_reg[0]\ <= \^q_entry_r_reg[0]\;
  \ras_timer_r_reg[1]\ <= \^ras_timer_r_reg[1]\;
  rb_hit_busy_r(0) <= \^rb_hit_busy_r\(0);
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  rb_hit_busy_r_reg_0 <= \^rb_hit_busy_r_reg_0\;
  rd_wr_r(0) <= \^rd_wr_r\(0);
  \req_row_r_lcl_reg[12]\(12 downto 0) <= \^req_row_r_lcl_reg[12]\(12 downto 0);
  req_wr_r_lcl_reg <= \^req_wr_r_lcl_reg\;
  row_cmd_wr(0) <= \^row_cmd_wr\(0);
bank_compare0: entity work.mig_7series_0_mig_7series_v4_2_bank_compare_2
     port map (
      CLK => CLK,
      E(0) => idle_ns(0),
      Q(0) => Q(0),
      S(2 downto 0) => S(2 downto 0),
      \head_r_lcl_i_2__1\(2 downto 0) => \q_entry_r_reg[0]_0\(2 downto 0),
      hi_priority => hi_priority,
      p_145_out => p_145_out,
      periodic_rd_insert => periodic_rd_insert,
      rb_hit_busy_r_reg_0 => \^rb_hit_busy_r\(0),
      rb_hit_busy_r_reg_1 => \^rb_hit_busy_r_reg\,
      rb_hit_busy_r_reg_2 => \^rb_hit_busy_r_reg_0\,
      rd_wr_r_lcl_reg_0 => \^rd_wr_r\(0),
      rd_wr_r_lcl_reg_1 => \^idle_r_lcl_reg_0\,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg,
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_col_r_reg[9]_1\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0),
      \req_data_buf_addr_r_reg[0]_0\(0) => \^idle_r\(0),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      \req_data_buf_addr_r_reg[3]_1\(3 downto 0) => \req_data_buf_addr_r_reg[3]_0\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      req_priority_r => req_priority_r,
      \req_row_r_lcl_reg[12]_0\(12 downto 0) => \^req_row_r_lcl_reg[12]\(12 downto 0),
      req_wr_r(0) => req_wr_r(0),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg_0 => \^req_wr_r_lcl_reg\,
      row(12 downto 0) => row(12 downto 0),
      row_hit_r => row_hit_r,
      row_hit_r_reg_0(0) => row_hit_r_reg(0),
      start_wtp_timer0 => start_wtp_timer0
    );
bank_queue0: entity work.mig_7series_0_mig_7series_v4_2_bank_queue
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      E(0) => idle_ns(0),
      Q(0) => Q(0),
      accept_internal_r => accept_internal_r,
      accept_internal_r_reg => accept_internal_r_reg,
      accept_internal_r_reg_0 => accept_internal_r_reg_0,
      accept_internal_r_reg_1 => accept_internal_r_reg_1,
      accept_internal_r_reg_2 => accept_internal_r_reg_2,
      \act_wait_r_lcl_i_4__1_0\ => \act_wait_r_lcl_i_4__1\,
      \act_wait_r_lcl_i_4__1_1\ => \act_wait_r_lcl_i_4__1_0\,
      \act_wait_r_lcl_i_4__1_2\ => \act_wait_r_lcl_i_4__1_1\,
      app_en_r2 => app_en_r2,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r\,
      auto_pre_r_lcl_reg_1 => bank_state0_n_21,
      auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg,
      bm_end_r1_reg => \^rd_wr_r\(0),
      col_wait_ns => col_wait_ns,
      \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg\,
      demand_priority_ns => demand_priority_ns,
      demand_priority_r_reg => bank_state0_n_27,
      demand_priority_r_reg_0 => \^req_wr_r_lcl_reg\,
      demand_priority_r_reg_1 => demand_priority_r_reg_1,
      demand_priority_r_reg_2 => demand_priority_r_reg_2,
      demand_priority_r_reg_3 => demand_priority_r_reg_3,
      \grant_r[2]_i_3__0\ => \^row_cmd_wr\(0),
      \grant_r[3]_i_12\(0) => \grant_r[3]_i_12\(0),
      head_r(0) => head_r(0),
      head_r_lcl_reg_0 => head_r_lcl_reg,
      head_r_lcl_reg_1 => \^rb_hit_busy_r_reg\,
      head_r_lcl_reg_2(2 downto 0) => head_r_lcl_reg_0(2 downto 0),
      idle_r_lcl_reg_0(0) => \^idle_r\(0),
      idle_r_lcl_reg_1 => idle_r_lcl_reg,
      idle_r_lcl_reg_2 => \^idle_r_lcl_reg_0\,
      idle_r_lcl_reg_3 => idle_r_lcl_reg_1,
      idle_r_lcl_reg_4 => idle_r_lcl_reg_2,
      idle_r_lcl_reg_5 => idle_r_lcl_reg_3,
      idle_r_lcl_reg_6 => idle_r_lcl_reg_4,
      \maint_controller.maint_hit_busies_r_reg[0]\ => \maint_controller.maint_hit_busies_r_reg[0]\,
      \maint_controller.maint_hit_busies_r_reg[0]_0\(0) => \maint_controller.maint_hit_busies_r_reg[0]_0\(0),
      maint_rank_r => maint_rank_r,
      maint_sre_r => maint_sre_r,
      maint_zq_r => maint_zq_r,
      \order_q_r_reg[0]_0\ => \^order_q_r_reg[0]\,
      \order_q_r_reg[0]_1\ => \order_q_r_reg[0]_0\,
      \order_q_r_reg[1]_0\ => \order_q_r_reg[1]\,
      ordered_r(0) => ordered_r(0),
      p_106_out => p_106_out,
      p_13_out => p_13_out,
      p_28_out => p_28_out,
      p_67_out => p_67_out,
      p_9_in => p_9_in,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r_lcl_reg_0 => \^pass_open_bank_r_lcl_reg\,
      pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg_0,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg_0 => \^p_130_out\,
      pre_bm_end_r_reg_1 => pre_bm_end_r_reg,
      pre_bm_end_r_reg_2 => pre_bm_end_r_reg_0,
      pre_bm_end_r_reg_3 => pre_bm_end_r_reg_1,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg,
      pre_wait_r => pre_wait_r,
      q_entry_ns(0) => q_entry_ns(0),
      q_entry_r(0) => q_entry_r(0),
      \q_entry_r[1]_i_2__0_0\ => \^rb_hit_busy_r_reg_0\,
      \q_entry_r_reg[0]_0\ => \^q_entry_r_reg[0]\,
      \q_entry_r_reg[0]_1\ => ofs_rdy_r_reg,
      \q_entry_r_reg[0]_2\(2 downto 0) => \q_entry_r_reg[0]_0\(2 downto 0),
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_2\,
      \q_entry_r_reg[1]_2\ => \q_entry_r_reg[1]_3\,
      \q_entry_r_reg[1]_3\ => \q_entry_r_reg[1]_4\,
      \q_entry_r_reg[1]_4\ => \q_entry_r_reg[1]_0\,
      \q_entry_r_reg[1]_5\ => \q_entry_r_reg[1]_1\,
      q_has_priority_r_reg_0 => \^rb_hit_busy_r\(0),
      q_has_priority_r_reg_1 => q_has_priority_r_reg,
      q_has_rd => q_has_rd,
      q_has_rd_r_reg_0 => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \^ras_timer_r_reg[1]\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_1\ => \ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\,
      \ras_timer_r_reg[1]\ => \^grant_r_reg[0]\,
      \ras_timer_r_reg[1]_0\ => \ras_timer_r_reg[1]_0\,
      \ras_timer_r_reg[1]_1\ => \ras_timer_r_reg[1]_1\,
      \ras_timer_r_reg[1]_2\ => \ras_timer_r_reg[1]_2\,
      ras_timer_zero_r => ras_timer_zero_r,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => pre_wait_r_reg,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      req_bank_rdy_ns => req_bank_rdy_ns,
      req_bank_rdy_r_reg => \^col_wait_r\,
      req_bank_rdy_r_reg_0 => req_bank_rdy_r_reg,
      req_priority_r => req_priority_r,
      req_wr_r(0) => req_wr_r(0),
      row_hit_r => row_hit_r,
      \rstdiv0_sync_r1_reg_rep__10\ => bank_queue0_n_22,
      \rstdiv0_sync_r1_reg_rep__10_0\(0) => D(0),
      tail_r => tail_r,
      wait_for_maint_r => wait_for_maint_r,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0,
      wait_for_maint_r_lcl_reg_2 => wait_for_maint_r_lcl_reg_1,
      was_priority => was_priority,
      was_wr => was_wr
    );
bank_state0: entity work.mig_7series_0_mig_7series_v4_2_bank_state
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      Q(1 downto 0) => Q(1 downto 0),
      act_this_rank_r(0) => act_this_rank_r(0),
      act_wait_r_lcl_reg_0 => \^row_cmd_wr\(0),
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg,
      act_wait_r_lcl_reg_2 => act_wait_r_lcl_reg_0,
      act_wait_r_lcl_reg_3 => bank_queue0_n_22,
      act_wait_r_lcl_reg_4 => act_wait_r_lcl_reg_1,
      auto_pre_r_lcl_reg => q_has_priority_r_reg,
      bm_end_r1 => bm_end_r1,
      \cmd_pipe_plus.mc_address_reg[23]\(0) => \^req_row_r_lcl_reg[12]\(10),
      \cmd_pipe_plus.mc_address_reg[23]_0\ => \cmd_pipe_plus.mc_address_reg[23]\,
      col_wait_ns => col_wait_ns,
      col_wait_r_reg_0 => \^col_wait_r\,
      col_wait_r_reg_1 => col_wait_r_reg,
      col_wait_r_reg_2 => col_wait_r_reg_0,
      col_wait_r_reg_3 => \^q_entry_r_reg[0]\,
      col_wait_r_reg_4(0) => col_wait_r_reg_1(0),
      \compute_tail.tail_r_lcl_reg\ => bank_state0_n_21,
      demand_act_priority_r => demand_act_priority_r,
      demand_priority_ns => demand_priority_ns,
      demand_priority_r_0 => demand_priority_r_0,
      demand_priority_r_2 => demand_priority_r_2,
      demand_priority_r_reg_0 => demand_priority_r,
      demand_priority_r_reg_1 => demand_priority_r_reg,
      demand_priority_r_reg_2 => demand_priority_r_reg_0,
      demand_priority_r_reg_3 => demand_priority_r_reg_4,
      demanded_prior_r_1 => demanded_prior_r_1,
      demanded_prior_r_reg_0 => demanded_prior_r,
      demanded_prior_r_reg_1 => demanded_prior_r_reg,
      \grant_r_reg[0]\ => \^grant_r_reg[0]\,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]_0\,
      \grant_r_reg[0]_1\ => bank_state0_n_27,
      \grant_r_reg[0]_2\ => \grant_r_reg[0]_1\,
      \grant_r_reg[1]\ => \grant_r_reg[1]\,
      \grant_r_reg[1]_0\(1 downto 0) => \grant_r_reg[1]_0\(1 downto 0),
      \grant_r_reg[1]_1\ => \grant_r_reg[1]_1\,
      \grant_r_reg[1]_2\ => \grant_r_reg[1]_2\,
      \grant_r_reg[1]_3\ => \grant_r_reg[1]_3\,
      granted_col_r_i_3 => granted_col_r_i_3,
      head_r(0) => head_r(0),
      idle_r(0) => \^idle_r\(0),
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r0 => ofs_rdy_r0,
      ofs_rdy_r_reg_0 => ofs_rdy_r_reg,
      override_demand_r => override_demand_r,
      p_130_out => \^p_130_out\,
      pass_open_bank_ns => pass_open_bank_ns,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg(0) => pre_bm_end_r_reg_2(0),
      pre_bm_end_r_reg_0 => \^auto_pre_r\,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_wait_r => pre_wait_r,
      pre_wait_r_reg_0 => pre_wait_r_reg,
      q_has_rd => q_has_rd,
      \ras_timer_r_reg[1]_0\ => \^ras_timer_r_reg[1]\,
      ras_timer_zero_r => ras_timer_zero_r,
      ras_timer_zero_r_reg_0(0) => ras_timer_zero_r_reg(0),
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_0,
      ras_timer_zero_r_reg_2 => ras_timer_zero_r_reg_1,
      ras_timer_zero_r_reg_3 => ras_timer_zero_r_reg_2,
      rb_hit_busy_r(0) => \^rb_hit_busy_r\(0),
      rd_this_rank_r(0) => rd_this_rank_r(0),
      \rd_this_rank_r_reg[0]_0\ => \^rd_wr_r\(0),
      req_bank_rdy_ns => req_bank_rdy_ns,
      req_wr_r(0) => req_wr_r(0),
      \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\,
      \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]_0\,
      \rnk_config_strobe_r_reg[0]_1\ => \^order_q_r_reg[0]\,
      \rtp_timer_r_reg[0]_0\ => \^pass_open_bank_r_lcl_reg\,
      \rtp_timer_r_reg[0]_1\ => \rtp_timer_r_reg[0]\,
      start_wtp_timer0 => start_wtp_timer0,
      tail_r => tail_r,
      wait_for_maint_r => wait_for_maint_r,
      wr_this_rank_r(0) => wr_this_rank_r(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized0\ is
  port (
    idle_r_lcl_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_0 : out STD_LOGIC;
    row_cmd_wr : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_act_priority_r : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r : out STD_LOGIC;
    demanded_prior_r : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    col_wait_r : out STD_LOGIC;
    auto_pre_r : out STD_LOGIC;
    ordered_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg : out STD_LOGIC;
    rnk_config_valid_ns : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    rnk_config_strobe_ns : out STD_LOGIC;
    col_wait_r_reg : out STD_LOGIC;
    \q_entry_r_reg[0]\ : out STD_LOGIC;
    col_wait_r_reg_0 : out STD_LOGIC;
    \ras_timer_r_reg[1]\ : out STD_LOGIC;
    rd_wr_r_lcl_reg : out STD_LOGIC;
    \order_q_r_reg[0]\ : out STD_LOGIC;
    idle_r_lcl_reg_0 : out STD_LOGIC;
    req_wr_r_lcl_reg : out STD_LOGIC;
    periodic_rd_ack_ns : out STD_LOGIC;
    accept_ns : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg : out STD_LOGIC;
    pre_bm_end_r_reg_1 : out STD_LOGIC;
    demand_act_priority_r_reg : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    \req_row_r_lcl_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    demand_priority_r_reg_0 : out STD_LOGIC;
    \req_data_buf_addr_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    CLK : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    p_106_out : in STD_LOGIC;
    ofs_rdy_r_reg : in STD_LOGIC;
    ofs_rdy_r0 : in STD_LOGIC;
    col_wait_r_reg_1 : in STD_LOGIC;
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg_1 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_1\ : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    rnk_config_valid_r : in STD_LOGIC;
    \grant_r_reg[1]\ : in STD_LOGIC;
    \grant_r_reg[2]\ : in STD_LOGIC;
    \grant_r_reg[2]_0\ : in STD_LOGIC;
    col_wait_r_0 : in STD_LOGIC;
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    demanded_prior_r_reg : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_2\ : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    demand_priority_r_reg_1 : in STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    \grant_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : in STD_LOGIC;
    act_wait_r_lcl_reg : in STD_LOGIC;
    granted_col_r_i_2 : in STD_LOGIC;
    granted_col_r_i_2_0 : in STD_LOGIC;
    granted_col_r_i_2_1 : in STD_LOGIC;
    p_145_out : in STD_LOGIC;
    p_130_out : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_1 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_2 : in STD_LOGIC;
    idle_r : in STD_LOGIC_VECTOR ( 2 downto 0 );
    p_13_out : in STD_LOGIC;
    head_r_lcl_reg : in STD_LOGIC;
    head_r_lcl_reg_0 : in STD_LOGIC;
    \q_entry_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[0]_0\ : in STD_LOGIC;
    q_has_priority_r_reg : in STD_LOGIC;
    rb_hit_busy_r : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \q_entry_r[1]_i_2__1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : in STD_LOGIC;
    p_28_out : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    p_67_out : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[1]\ : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    maint_sre_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    maint_rank_r : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    accept_internal_r : in STD_LOGIC;
    ordered_r_lcl_reg : in STD_LOGIC;
    ordered_r_lcl_reg_0 : in STD_LOGIC;
    app_en_r2 : in STD_LOGIC;
    \grant_r[3]_i_12\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    was_priority : in STD_LOGIC;
    q_has_rd_r_reg : in STD_LOGIC;
    was_wr : in STD_LOGIC;
    auto_pre_r_lcl_reg : in STD_LOGIC;
    pre_bm_end_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[2]_2\ : in STD_LOGIC;
    \grant_r_reg[2]_3\ : in STD_LOGIC;
    demand_act_priority_r_1 : in STD_LOGIC;
    row : in STD_LOGIC_VECTOR ( 12 downto 0 );
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    demanded_prior_r_reg_0 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    demand_priority_r_reg_4 : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \order_q_r_reg[1]\ : in STD_LOGIC;
    \order_q_r_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized0\ : entity is "mig_7series_v4_2_bank_cntrl";
end \mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized0\ is
  signal \^auto_pre_r\ : STD_LOGIC;
  signal bank_queue0_n_30 : STD_LOGIC;
  signal bank_state0_n_19 : STD_LOGIC;
  signal bank_state0_n_24 : STD_LOGIC;
  signal col_wait_ns : STD_LOGIC;
  signal \^col_wait_r\ : STD_LOGIC;
  signal \^demand_act_priority_r\ : STD_LOGIC;
  signal demand_priority_ns : STD_LOGIC;
  signal head_r : STD_LOGIC_VECTOR ( 1 to 1 );
  signal idle_ns : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^idle_r_lcl_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^idle_r_lcl_reg_0\ : STD_LOGIC;
  signal \^order_q_r_reg[0]\ : STD_LOGIC;
  signal p_91_out : STD_LOGIC;
  signal pass_open_bank_ns : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg\ : STD_LOGIC;
  signal pre_bm_end_ns : STD_LOGIC;
  signal pre_passing_open_bank_ns : STD_LOGIC;
  signal pre_wait_r : STD_LOGIC;
  signal \^q_entry_r_reg[0]\ : STD_LOGIC;
  signal q_has_rd : STD_LOGIC;
  signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ras_timer_r_reg[1]\ : STD_LOGIC;
  signal ras_timer_zero_r : STD_LOGIC;
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rd_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rd_wr_r_lcl_reg\ : STD_LOGIC;
  signal req_bank_rdy_ns : STD_LOGIC;
  signal req_priority_r : STD_LOGIC;
  signal req_wr_r : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^req_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^row_cmd_wr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal row_hit_r : STD_LOGIC;
  signal start_wtp_timer0 : STD_LOGIC;
  signal tail_r : STD_LOGIC;
  signal wait_for_maint_r : STD_LOGIC;
begin
  auto_pre_r <= \^auto_pre_r\;
  col_wait_r <= \^col_wait_r\;
  demand_act_priority_r <= \^demand_act_priority_r\;
  idle_r_lcl_reg(0) <= \^idle_r_lcl_reg\(0);
  idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\;
  \order_q_r_reg[0]\ <= \^order_q_r_reg[0]\;
  pass_open_bank_r_lcl_reg <= \^pass_open_bank_r_lcl_reg\;
  \q_entry_r_reg[0]\ <= \^q_entry_r_reg[0]\;
  \ras_timer_r_reg[1]\ <= \^ras_timer_r_reg[1]\;
  rb_hit_busy_r_reg(0) <= \^rb_hit_busy_r_reg\(0);
  rd_wr_r(0) <= \^rd_wr_r\(0);
  rd_wr_r_lcl_reg <= \^rd_wr_r_lcl_reg\;
  req_wr_r_lcl_reg <= \^req_wr_r_lcl_reg\;
  row_cmd_wr(0) <= \^row_cmd_wr\(0);
bank_compare0: entity work.mig_7series_0_mig_7series_v4_2_bank_compare_1
     port map (
      CLK => CLK,
      E(0) => idle_ns(1),
      Q(0) => Q(0),
      hi_priority => hi_priority,
      p_106_out => p_106_out,
      periodic_rd_insert => periodic_rd_insert,
      rb_hit_busy_r_reg_0 => \^rb_hit_busy_r_reg\(0),
      rd_wr_r_lcl_reg_0 => \^rd_wr_r\(0),
      rd_wr_r_lcl_reg_1 => \^idle_r_lcl_reg_0\,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_0,
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_col_r_reg[9]_1\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0),
      \req_data_buf_addr_r_reg[0]_0\(0) => \^idle_r_lcl_reg\(0),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      \req_data_buf_addr_r_reg[3]_1\(3 downto 0) => \req_data_buf_addr_r_reg[3]_0\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      req_priority_r => req_priority_r,
      \req_row_r_lcl_reg[12]_0\(12 downto 0) => \req_row_r_lcl_reg[12]\(12 downto 0),
      req_wr_r(0) => req_wr_r(1),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg_0 => \^req_wr_r_lcl_reg\,
      row(12 downto 0) => row(12 downto 0),
      row_hit_r => row_hit_r,
      row_hit_r_reg_0(0) => row_hit_r_reg(0),
      start_wtp_timer0 => start_wtp_timer0
    );
bank_queue0: entity work.\mig_7series_0_mig_7series_v4_2_bank_queue__parameterized0\
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      E(0) => idle_ns(1),
      Q(0) => Q(0),
      accept_internal_r => accept_internal_r,
      accept_ns => accept_ns,
      app_en_r2 => app_en_r2,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r\,
      auto_pre_r_lcl_reg_1 => bank_state0_n_19,
      auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg,
      bm_end_r1_reg => \^rd_wr_r\(0),
      col_wait_ns => col_wait_ns,
      col_wait_r_0 => col_wait_r_0,
      col_wait_r_reg => col_wait_r_reg,
      \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg\,
      demand_act_priority_r => \^demand_act_priority_r\,
      demand_act_priority_r_1 => demand_act_priority_r_1,
      demand_act_priority_r_reg => demand_act_priority_r_reg,
      demand_priority_ns => demand_priority_ns,
      demand_priority_r_reg => bank_state0_n_24,
      demand_priority_r_reg_0 => demand_priority_r_reg_1,
      demand_priority_r_reg_1 => demand_priority_r_reg_2,
      demand_priority_r_reg_2 => \^req_wr_r_lcl_reg\,
      demand_priority_r_reg_3 => demand_priority_r_reg_3,
      \grant_r[3]_i_12\(0) => \grant_r[3]_i_12\(0),
      \grant_r[3]_i_2__1_0\ => \^row_cmd_wr\(0),
      \grant_r_reg[2]\ => \grant_r_reg[1]\,
      \grant_r_reg[2]_0\ => \grant_r_reg[2]\,
      \grant_r_reg[2]_1\ => \grant_r_reg[2]_0\,
      \grant_r_reg[2]_2\ => \grant_r_reg[2]_2\,
      \grant_r_reg[2]_3\ => \grant_r_reg[2]_3\,
      \grant_r_reg[2]_4\(0) => \grant_r_reg[2]_1\(1),
      granted_col_r_i_2_0 => granted_col_r_i_2,
      granted_col_r_i_2_1 => granted_col_r_i_2_0,
      granted_col_r_i_2_2 => granted_col_r_i_2_1,
      head_r(0) => head_r(1),
      head_r_lcl_reg_0 => head_r_lcl_reg,
      head_r_lcl_reg_1 => head_r_lcl_reg_0,
      idle_r(2 downto 0) => idle_r(2 downto 0),
      idle_r_lcl_reg_0(0) => \^idle_r_lcl_reg\(0),
      idle_r_lcl_reg_1 => \^idle_r_lcl_reg_0\,
      idle_r_lcl_reg_2 => idle_r_lcl_reg_1,
      \maint_controller.maint_hit_busies_r_reg[1]\ => \maint_controller.maint_hit_busies_r_reg[1]\,
      \maint_controller.maint_hit_busies_r_reg[1]_0\(0) => \maint_controller.maint_hit_busies_r_reg[1]_0\(0),
      maint_rank_r => maint_rank_r,
      maint_sre_r => maint_sre_r,
      maint_zq_r => maint_zq_r,
      \order_q_r_reg[0]_0\ => \^order_q_r_reg[0]\,
      \order_q_r_reg[0]_1\ => \order_q_r_reg[0]_0\,
      \order_q_r_reg[1]_0\ => \order_q_r_reg[1]\,
      ordered_r(0) => ordered_r(0),
      ordered_r_lcl_reg_0 => ordered_r_lcl_reg,
      ordered_r_lcl_reg_1 => ordered_r_lcl_reg_0,
      p_130_out => p_130_out,
      p_13_out => p_13_out,
      p_145_out => p_145_out,
      p_28_out => p_28_out,
      p_67_out => p_67_out,
      p_91_out => p_91_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r_lcl_reg_0 => \^pass_open_bank_r_lcl_reg\,
      pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg_0,
      pass_open_bank_r_lcl_reg_2 => pass_open_bank_r_lcl_reg_1,
      periodic_rd_ack_ns => periodic_rd_ack_ns,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg,
      periodic_rd_ack_r_lcl_reg_0 => periodic_rd_ack_r_lcl_reg_0,
      periodic_rd_ack_r_lcl_reg_1 => periodic_rd_ack_r_lcl_reg_1,
      periodic_rd_ack_r_lcl_reg_2 => periodic_rd_ack_r_lcl_reg_2,
      periodic_rd_insert => periodic_rd_insert,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg_0 => pre_bm_end_r_reg,
      pre_bm_end_r_reg_1 => pre_bm_end_r_reg_0,
      pre_bm_end_r_reg_2 => pre_bm_end_r_reg_1,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg,
      pre_wait_r => pre_wait_r,
      \q_entry_r[1]_i_2__1\ => \q_entry_r[1]_i_2__1\,
      \q_entry_r_reg[0]_0\ => \^q_entry_r_reg[0]\,
      \q_entry_r_reg[0]_1\ => ofs_rdy_r_reg,
      \q_entry_r_reg[0]_2\ => \q_entry_r_reg[0]_0\,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_1\(0) => \q_entry_r_reg[1]_0\(0),
      q_has_priority_r_reg_0 => q_has_priority_r_reg,
      q_has_priority_r_reg_1 => \^rb_hit_busy_r_reg\(0),
      q_has_priority_r_reg_2 => \rtp_timer_r_reg[0]\,
      q_has_rd => q_has_rd,
      q_has_rd_r_reg_0 => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \^ras_timer_r_reg[1]\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_1\ => \ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\,
      \ras_timer_r_reg[1]\ => \^rd_wr_r_lcl_reg\,
      \ras_timer_r_reg[1]_0\ => \ras_timer_r_reg[1]_0\,
      \ras_timer_r_reg[1]_1\ => \ras_timer_r_reg[1]_1\,
      \ras_timer_r_reg[1]_2\ => \ras_timer_r_reg[1]_2\,
      ras_timer_zero_r => ras_timer_zero_r,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      rb_hit_busy_r(2 downto 0) => rb_hit_busy_r(2 downto 0),
      req_bank_rdy_ns => req_bank_rdy_ns,
      req_bank_rdy_r_reg => \^col_wait_r\,
      req_bank_rdy_r_reg_0 => req_bank_rdy_r_reg,
      req_priority_r => req_priority_r,
      req_wr_r(0) => req_wr_r(1),
      row_hit_r => row_hit_r,
      \rstdiv0_sync_r1_reg_rep__11\(0) => D(0),
      \rstdiv0_sync_r1_reg_rep__11_0\ => bank_queue0_n_30,
      tail_r => tail_r,
      wait_for_maint_r => wait_for_maint_r,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      was_priority => was_priority,
      was_wr => was_wr
    );
bank_state0: entity work.\mig_7series_0_mig_7series_v4_2_bank_state__parameterized0\
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      Q(0) => Q(0),
      act_this_rank_r(0) => act_this_rank_r(0),
      act_wait_r_lcl_reg_0 => \^row_cmd_wr\(0),
      act_wait_r_lcl_reg_1 => \^q_entry_r_reg[0]\,
      act_wait_r_lcl_reg_2(0) => \grant_r_reg[2]_1\(0),
      act_wait_r_lcl_reg_3 => bank_queue0_n_30,
      act_wait_r_lcl_reg_4 => act_wait_r_lcl_reg,
      auto_pre_r_lcl_reg(0) => \^rb_hit_busy_r_reg\(0),
      auto_pre_r_lcl_reg_0 => q_has_priority_r_reg,
      bm_end_r1_0 => bm_end_r1_0,
      col_wait_ns => col_wait_ns,
      col_wait_r_reg_0 => \^col_wait_r\,
      col_wait_r_reg_1 => col_wait_r_reg_0,
      col_wait_r_reg_2 => col_wait_r_reg_1,
      \compute_tail.tail_r_lcl_reg\ => bank_state0_n_19,
      demand_act_priority_r => \^demand_act_priority_r\,
      demand_act_priority_r_reg_0(0) => \^idle_r_lcl_reg\(0),
      demand_priority_ns => demand_priority_ns,
      demand_priority_r_reg_0 => demand_priority_r,
      demand_priority_r_reg_1 => demand_priority_r_reg,
      demand_priority_r_reg_2 => demand_priority_r_reg_0,
      demand_priority_r_reg_3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      demand_priority_r_reg_4 => demand_priority_r_reg_4,
      demanded_prior_r => demanded_prior_r,
      demanded_prior_r_reg_0 => demanded_prior_r_reg,
      demanded_prior_r_reg_1 => demanded_prior_r_reg_0,
      demanded_prior_r_reg_2 => demanded_prior_r_reg_1,
      \grant_r_reg[1]\ => bank_state0_n_24,
      \grant_r_reg[1]_0\ => \grant_r_reg[1]\,
      head_r(0) => head_r(1),
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r0 => ofs_rdy_r0,
      ofs_rdy_r_reg_0 => ofs_rdy_r_reg,
      p_91_out => p_91_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg(0) => pre_bm_end_r_reg_2(0),
      pre_bm_end_r_reg_0 => \^auto_pre_r\,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_wait_r => pre_wait_r,
      q_has_rd => q_has_rd,
      \ras_timer_r_reg[1]_0\ => \^ras_timer_r_reg[1]\,
      ras_timer_zero_r => ras_timer_zero_r,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_0,
      rd_this_rank_r(0) => rd_this_rank_r(0),
      \rd_this_rank_r_reg[0]_0\ => \^rd_wr_r\(0),
      rd_wr_r_lcl_reg => \^rd_wr_r_lcl_reg\,
      req_bank_rdy_ns => req_bank_rdy_ns,
      req_wr_r(0) => req_wr_r(1),
      rnk_config_strobe_ns => rnk_config_strobe_ns,
      \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\,
      \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]_0\,
      \rnk_config_strobe_r_reg[0]_1\ => \rnk_config_strobe_r_reg[0]_1\,
      \rnk_config_strobe_r_reg[0]_2\ => \rnk_config_strobe_r_reg[0]_2\,
      \rnk_config_strobe_r_reg[0]_3\ => \^order_q_r_reg[0]\,
      rnk_config_valid_ns => rnk_config_valid_ns,
      rnk_config_valid_r => rnk_config_valid_r,
      rnk_config_valid_r_lcl_reg => rnk_config_valid_r_lcl_reg,
      \rtp_timer_r_reg[0]_0\ => \^pass_open_bank_r_lcl_reg\,
      \rtp_timer_r_reg[0]_1\ => \rtp_timer_r_reg[0]\,
      start_wtp_timer0 => start_wtp_timer0,
      tail_r => tail_r,
      wait_for_maint_r => wait_for_maint_r,
      wr_this_rank_r(0) => wr_this_rank_r(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized1\ is
  port (
    idle_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_2 : out STD_LOGIC;
    row_cmd_wr : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_act_priority_r : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r : out STD_LOGIC;
    demanded_prior_r : out STD_LOGIC;
    override_demand_r : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    auto_pre_r : out STD_LOGIC;
    ordered_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    ofs_rdy_r0 : out STD_LOGIC;
    ofs_rdy_r0_0 : out STD_LOGIC;
    ofs_rdy_r0_1 : out STD_LOGIC;
    \ras_timer_r_reg[1]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rd_wr_r_lcl_reg : out STD_LOGIC;
    \order_q_r_reg[0]\ : out STD_LOGIC;
    idle_r_lcl_reg : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    req_wr_r_lcl_reg : out STD_LOGIC;
    idle_r_lcl_reg_0 : out STD_LOGIC;
    pre_bm_end_r_reg_0 : out STD_LOGIC;
    \q_entry_r_reg[0]\ : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    pre_passing_open_bank_r_reg : out STD_LOGIC;
    head_r_lcl_reg : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    \req_row_r_lcl_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    act_wait_r_lcl_reg : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    demand_priority_r_reg_1 : out STD_LOGIC;
    \req_data_buf_addr_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    CLK : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    p_67_out : in STD_LOGIC;
    override_demand_ns : in STD_LOGIC;
    phy_mc_ctl_full_r_reg : in STD_LOGIC;
    phy_mc_cmd_full : in STD_LOGIC;
    phy_mc_ctl_full : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[1]_0\ : in STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pre_4_1_1T_arb.granted_pre_r_reg_1\ : in STD_LOGIC;
    phy_mc_data_full : in STD_LOGIC;
    ofs_rdy_r_reg : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    demanded_prior_r_reg : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    demand_priority_r_reg_4 : in STD_LOGIC;
    act_wait_r_lcl_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    ras_timer_zero_r_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    \grant_r[3]_i_5\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_3\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_4\ : in STD_LOGIC;
    p_145_out : in STD_LOGIC;
    p_130_out : in STD_LOGIC;
    head_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : in STD_LOGIC;
    \q_entry_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \q_entry_r[1]_i_2__2\ : in STD_LOGIC;
    q_has_priority_r_reg : in STD_LOGIC;
    p_13_out : in STD_LOGIC;
    p_28_out : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    p_106_out : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[2]\ : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    maint_sre_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    maint_rank_r : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    accept_internal_r : in STD_LOGIC;
    ordered_r_lcl_reg : in STD_LOGIC;
    ordered_r_lcl_reg_0 : in STD_LOGIC;
    app_en_r2 : in STD_LOGIC;
    was_priority : in STD_LOGIC;
    q_has_rd_r_reg : in STD_LOGIC;
    was_wr : in STD_LOGIC;
    auto_pre_r_lcl_reg : in STD_LOGIC;
    row : in STD_LOGIC_VECTOR ( 12 downto 0 );
    ras_timer_zero_r_reg_2 : in STD_LOGIC;
    demanded_prior_r_reg_0 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    demand_priority_r_2 : in STD_LOGIC;
    demanded_prior_r_3 : in STD_LOGIC;
    \grant_r[3]_i_5_0\ : in STD_LOGIC;
    \starve_limit_cntr_r_reg[0]\ : in STD_LOGIC;
    \q_entry_r_reg[0]_1\ : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \order_q_r_reg[1]\ : in STD_LOGIC;
    \order_q_r_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized1\ : entity is "mig_7series_v4_2_bank_cntrl";
end \mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized1\ is
  signal \^auto_pre_r\ : STD_LOGIC;
  signal bank_compare0_n_6 : STD_LOGIC;
  signal bank_queue0_n_13 : STD_LOGIC;
  signal bank_queue0_n_24 : STD_LOGIC;
  signal bank_queue0_n_29 : STD_LOGIC;
  signal bank_queue0_n_31 : STD_LOGIC;
  signal bank_state0_n_22 : STD_LOGIC;
  signal bank_state0_n_29 : STD_LOGIC;
  signal col_wait_ns : STD_LOGIC;
  signal col_wait_r : STD_LOGIC;
  signal demand_priority_ns : STD_LOGIC;
  signal head_r : STD_LOGIC_VECTOR ( 2 to 2 );
  signal idle_ns : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \^idle_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^idle_r_lcl_reg\ : STD_LOGIC;
  signal \^order_q_r_reg[0]\ : STD_LOGIC;
  signal p_52_out : STD_LOGIC;
  signal pass_open_bank_ns : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg\ : STD_LOGIC;
  signal pre_bm_end_ns : STD_LOGIC;
  signal pre_passing_open_bank_ns : STD_LOGIC;
  signal pre_wait_r : STD_LOGIC;
  signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ras_timer_r_reg[1]\ : STD_LOGIC;
  signal ras_timer_zero_r : STD_LOGIC;
  signal \^rb_hit_busy_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rd_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rd_wr_r_lcl_reg\ : STD_LOGIC;
  signal req_bank_rdy_ns : STD_LOGIC;
  signal req_bank_rdy_r : STD_LOGIC;
  signal req_priority_r : STD_LOGIC;
  signal req_wr_r : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \^req_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^row_cmd_wr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal row_hit_r : STD_LOGIC;
  signal start_wtp_timer0 : STD_LOGIC;
  signal tail_r : STD_LOGIC;
  signal wait_for_maint_r : STD_LOGIC;
begin
  auto_pre_r <= \^auto_pre_r\;
  idle_r(0) <= \^idle_r\(0);
  idle_r_lcl_reg <= \^idle_r_lcl_reg\;
  \order_q_r_reg[0]\ <= \^order_q_r_reg[0]\;
  pass_open_bank_r_lcl_reg <= \^pass_open_bank_r_lcl_reg\;
  \ras_timer_r_reg[1]\ <= \^ras_timer_r_reg[1]\;
  rb_hit_busy_r(0) <= \^rb_hit_busy_r\(0);
  rd_wr_r(0) <= \^rd_wr_r\(0);
  rd_wr_r_lcl_reg <= \^rd_wr_r_lcl_reg\;
  req_wr_r_lcl_reg <= \^req_wr_r_lcl_reg\;
  row_cmd_wr(0) <= \^row_cmd_wr\(0);
bank_compare0: entity work.mig_7series_0_mig_7series_v4_2_bank_compare_0
     port map (
      CLK => CLK,
      E(0) => idle_ns(2),
      hi_priority => hi_priority,
      p_67_out => p_67_out,
      periodic_rd_insert => periodic_rd_insert,
      \q_entry_r_reg[0]\(2 downto 0) => \q_entry_r_reg[0]_0\(2 downto 0),
      \q_entry_r_reg[0]_0\ => bank_queue0_n_24,
      rb_hit_busy_r_reg_0 => \^rb_hit_busy_r\(0),
      rb_hit_busy_r_reg_1 => bank_compare0_n_6,
      rd_wr_r_lcl_reg_0 => \^rd_wr_r\(0),
      rd_wr_r_lcl_reg_1(0) => ras_timer_zero_r_reg_1(1),
      rd_wr_r_lcl_reg_2 => \^idle_r_lcl_reg\,
      rd_wr_r_lcl_reg_3 => rd_wr_r_lcl_reg_0,
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_col_r_reg[9]_1\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0),
      \req_data_buf_addr_r_reg[0]_0\(0) => \^idle_r\(0),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      \req_data_buf_addr_r_reg[3]_1\(3 downto 0) => \req_data_buf_addr_r_reg[3]_0\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      req_priority_r => req_priority_r,
      \req_row_r_lcl_reg[12]_0\(12 downto 0) => \req_row_r_lcl_reg[12]\(12 downto 0),
      req_wr_r(0) => req_wr_r(2),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg_0 => \^req_wr_r_lcl_reg\,
      row(12 downto 0) => row(12 downto 0),
      row_hit_r => row_hit_r,
      row_hit_r_reg_0(0) => row_hit_r_reg(0),
      start_wtp_timer0 => start_wtp_timer0
    );
bank_queue0: entity work.\mig_7series_0_mig_7series_v4_2_bank_queue__parameterized1\
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      E(0) => idle_ns(2),
      Q(2 downto 0) => Q(2 downto 0),
      accept_internal_r => accept_internal_r,
      app_en_r2 => app_en_r2,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r\,
      auto_pre_r_lcl_reg_1 => bank_state0_n_22,
      auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg,
      bm_end_r1_reg(0) => ras_timer_zero_r_reg_1(1),
      bm_end_r1_reg_0 => \^rd_wr_r\(0),
      col_wait_ns => col_wait_ns,
      col_wait_r => col_wait_r,
      \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg\,
      demand_priority_ns => demand_priority_ns,
      \demand_priority_r_i_4__1\ => \starve_limit_cntr_r_reg[0]\,
      demand_priority_r_reg => bank_state0_n_29,
      demand_priority_r_reg_0 => demand_priority_r_reg_2,
      demand_priority_r_reg_1 => demand_priority_r_reg_3,
      demand_priority_r_reg_2 => demand_priority_r_reg_4,
      demand_priority_r_reg_3 => \^req_wr_r_lcl_reg\,
      \grant_r[3]_i_3__2\ => \^row_cmd_wr\(0),
      \grant_r[3]_i_5\ => \grant_r[3]_i_5\,
      head_r(0) => head_r(2),
      head_r_lcl_reg_0 => head_r_lcl_reg,
      head_r_lcl_reg_1 => head_r_lcl_reg_0,
      head_r_lcl_reg_2 => head_r_lcl_reg_1,
      head_r_lcl_reg_3 => head_r_lcl_reg_2,
      idle_r_lcl_reg_0(0) => \^idle_r\(0),
      idle_r_lcl_reg_1 => bank_queue0_n_13,
      idle_r_lcl_reg_2 => \^idle_r_lcl_reg\,
      idle_r_lcl_reg_3 => idle_r_lcl_reg_0,
      idle_r_lcl_reg_4 => idle_r_lcl_reg_1,
      \maint_controller.maint_hit_busies_r_reg[2]\ => \maint_controller.maint_hit_busies_r_reg[2]\,
      \maint_controller.maint_hit_busies_r_reg[2]_0\(0) => \maint_controller.maint_hit_busies_r_reg[2]_0\(0),
      maint_rank_r => maint_rank_r,
      maint_sre_r => maint_sre_r,
      maint_zq_r => maint_zq_r,
      \order_q_r_reg[0]_0\ => \^order_q_r_reg[0]\,
      \order_q_r_reg[0]_1\ => \order_q_r_reg[0]_0\,
      \order_q_r_reg[1]_0\ => \order_q_r_reg[1]\,
      ordered_r(0) => ordered_r(0),
      ordered_r_lcl_reg_0 => ordered_r_lcl_reg,
      ordered_r_lcl_reg_1 => ordered_r_lcl_reg_0,
      p_106_out => p_106_out,
      p_130_out => p_130_out,
      p_13_out => p_13_out,
      p_145_out => p_145_out,
      p_28_out => p_28_out,
      p_52_out => p_52_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r_lcl_reg_0 => \^pass_open_bank_r_lcl_reg\,
      pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg_0,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg_0 => pre_bm_end_r_reg,
      pre_bm_end_r_reg_1 => pre_bm_end_r_reg_0,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg,
      pre_wait_r => pre_wait_r,
      \q_entry_r[1]_i_2__2\ => \q_entry_r[1]_i_2__2\,
      \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]\,
      \q_entry_r_reg[0]_1\ => phy_mc_ctl_full_r_reg,
      \q_entry_r_reg[0]_2\ => bank_compare0_n_6,
      \q_entry_r_reg[0]_3\ => \q_entry_r_reg[0]_1\,
      \q_entry_r_reg[1]_0\(0) => \q_entry_r_reg[1]\(0),
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_0\,
      q_has_priority_r_reg_0 => q_has_priority_r_reg,
      q_has_priority_r_reg_1 => \rtp_timer_r_reg[0]\,
      q_has_rd_r_reg_0 => bank_queue0_n_31,
      q_has_rd_r_reg_1 => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \^ras_timer_r_reg[1]\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_1\ => \ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\,
      \ras_timer_r_reg[0]_3\ => \ras_timer_r_reg[0]_2\,
      \ras_timer_r_reg[0]_4\ => \ras_timer_r_reg[0]_3\,
      \ras_timer_r_reg[0]_5\ => \ras_timer_r_reg[0]_4\,
      \ras_timer_r_reg[1]\ => \^rd_wr_r_lcl_reg\,
      \ras_timer_r_reg[1]_0\ => \ras_timer_r_reg[1]_0\,
      \ras_timer_r_reg[1]_1\ => \ras_timer_r_reg[1]_1\,
      \ras_timer_r_reg[1]_2\ => \ras_timer_r_reg[1]_2\,
      ras_timer_zero_r => ras_timer_zero_r,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => bank_queue0_n_24,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      rb_hit_busy_r(0) => \^rb_hit_busy_r\(0),
      req_bank_rdy_ns => req_bank_rdy_ns,
      req_bank_rdy_r => req_bank_rdy_r,
      req_bank_rdy_r_reg => req_bank_rdy_r_reg,
      req_priority_r => req_priority_r,
      req_wr_r(0) => req_wr_r(2),
      row_hit_r => row_hit_r,
      \rstdiv0_sync_r1_reg_rep__11\(0) => D(0),
      \rstdiv0_sync_r1_reg_rep__11_0\ => bank_queue0_n_29,
      tail_r => tail_r,
      wait_for_maint_r => wait_for_maint_r,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      was_priority => was_priority,
      was_wr => was_wr
    );
bank_state0: entity work.\mig_7series_0_mig_7series_v4_2_bank_state__parameterized1\
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      act_this_rank_r(0) => act_this_rank_r(0),
      act_wait_r_lcl_reg_0 => \^row_cmd_wr\(0),
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg,
      act_wait_r_lcl_reg_2(0) => act_wait_r_lcl_reg_0(0),
      act_wait_r_lcl_reg_3 => bank_queue0_n_29,
      act_wait_r_lcl_reg_4 => act_wait_r_lcl_reg_1,
      auto_pre_r_lcl_reg => q_has_priority_r_reg,
      bm_end_r1_2 => bm_end_r1_2,
      col_wait_ns => col_wait_ns,
      col_wait_r => col_wait_r,
      col_wait_r_reg_0 => col_wait_r_reg,
      col_wait_r_reg_1 => bank_queue0_n_13,
      \compute_tail.tail_r_lcl_reg\ => bank_state0_n_22,
      demand_act_priority_r => demand_act_priority_r,
      demand_priority_ns => demand_priority_ns,
      demand_priority_r_2 => demand_priority_r_2,
      demand_priority_r_reg_0 => demand_priority_r,
      demand_priority_r_reg_1 => demand_priority_r_reg,
      demand_priority_r_reg_2 => demand_priority_r_reg_0,
      demand_priority_r_reg_3 => demand_priority_r_reg_1,
      demand_priority_r_reg_4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      demand_priority_r_reg_5 => bank_queue0_n_31,
      demanded_prior_r => demanded_prior_r,
      demanded_prior_r_3 => demanded_prior_r_3,
      demanded_prior_r_reg_0 => demanded_prior_r_reg,
      demanded_prior_r_reg_1 => demanded_prior_r_reg_0,
      demanded_prior_r_reg_2 => demanded_prior_r_reg_1,
      \grant_r[3]_i_5\ => \grant_r[3]_i_5_0\,
      head_r(0) => head_r(2),
      idle_r(0) => \^idle_r\(0),
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r0 => ofs_rdy_r0,
      ofs_rdy_r0_0 => ofs_rdy_r0_0,
      ofs_rdy_r0_1 => ofs_rdy_r0_1,
      ofs_rdy_r_reg_0(2 downto 0) => ofs_rdy_r_reg(2 downto 0),
      override_demand_ns => override_demand_ns,
      override_demand_r => override_demand_r,
      p_52_out => p_52_out,
      pass_open_bank_ns => pass_open_bank_ns,
      phy_mc_cmd_full => phy_mc_cmd_full,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_ctl_full_r_reg_0 => phy_mc_ctl_full_r_reg,
      phy_mc_data_full => phy_mc_data_full,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \pre_4_1_1T_arb.granted_pre_r_reg\,
      \pre_4_1_1T_arb.granted_pre_r_reg_0\ => \^auto_pre_r\,
      \pre_4_1_1T_arb.granted_pre_r_reg_1\(0) => \pre_4_1_1T_arb.granted_pre_r_reg_0\(0),
      \pre_4_1_1T_arb.granted_pre_r_reg_2\ => \pre_4_1_1T_arb.granted_pre_r_reg_1\,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_wait_r => pre_wait_r,
      \ras_timer_r_reg[1]_0\ => \^ras_timer_r_reg[1]\,
      ras_timer_zero_r => ras_timer_zero_r,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_0,
      ras_timer_zero_r_reg_2(1 downto 0) => ras_timer_zero_r_reg_1(1 downto 0),
      ras_timer_zero_r_reg_3 => ras_timer_zero_r_reg_2,
      rb_hit_busy_r(0) => \^rb_hit_busy_r\(0),
      rd_this_rank_r(0) => rd_this_rank_r(0),
      \rd_this_rank_r_reg[0]_0\ => \^rd_wr_r\(0),
      rd_wr_r_lcl_reg => \^rd_wr_r_lcl_reg\,
      req_bank_rdy_ns => req_bank_rdy_ns,
      req_bank_rdy_r => req_bank_rdy_r,
      \rnk_config_strobe_r_reg[0]\ => \^order_q_r_reg[0]\,
      \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]\,
      \rtp_timer_r_reg[0]_0\ => \^pass_open_bank_r_lcl_reg\,
      \rtp_timer_r_reg[0]_1\ => \rtp_timer_r_reg[0]\,
      start_wtp_timer0 => start_wtp_timer0,
      \starve_limit_cntr_r_reg[0]_0\ => \starve_limit_cntr_r_reg[0]\,
      \starve_limit_cntr_r_reg[2]_0\ => bank_state0_n_29,
      tail_r => tail_r,
      wait_for_maint_r => wait_for_maint_r,
      wr_this_rank_r(0) => wr_this_rank_r(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized2\ is
  port (
    idle_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_4 : out STD_LOGIC;
    p_13_out : out STD_LOGIC;
    row_cmd_wr : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_act_priority_r : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r : out STD_LOGIC;
    demanded_prior_r : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    auto_pre_r : out STD_LOGIC;
    col_wait_r_reg : out STD_LOGIC;
    \ras_timer_r_reg[1]\ : out STD_LOGIC;
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    req_wr_r_lcl_reg : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC;
    \order_q_r_reg[0]\ : out STD_LOGIC;
    idle_r_lcl_reg : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    req_wr_r_lcl_reg_0 : out STD_LOGIC;
    pre_bm_end_r_reg : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : out STD_LOGIC;
    pre_passing_open_bank_r_reg : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    head_r_lcl_reg : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    \req_row_r_lcl_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    act_wait_r_lcl_reg : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    \req_data_buf_addr_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    CLK : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    p_28_out : in STD_LOGIC;
    ofs_rdy_r_reg : in STD_LOGIC;
    ofs_rdy_r0 : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    \order_q_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    \grant_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_1\ : in STD_LOGIC;
    \ras_timer_r_reg[1]_2\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC;
    demand_priority_r_reg_0 : in STD_LOGIC;
    demand_priority_r_reg_1 : in STD_LOGIC;
    demand_priority_r_reg_2 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    act_wait_r_lcl_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_i_4 : in STD_LOGIC;
    act_wait_r_lcl_i_4_0 : in STD_LOGIC;
    act_wait_r_lcl_i_4_1 : in STD_LOGIC;
    p_145_out : in STD_LOGIC;
    p_130_out : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ : in STD_LOGIC;
    \q_entry_r_reg[1]\ : in STD_LOGIC;
    \q_entry_r_reg[1]_0\ : in STD_LOGIC;
    q_has_priority_r_reg : in STD_LOGIC;
    \q_entry_r_reg[0]\ : in STD_LOGIC;
    head_r_lcl_reg_2 : in STD_LOGIC;
    rb_hit_busy_r : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : in STD_LOGIC;
    p_106_out : in STD_LOGIC;
    p_67_out : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]\ : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    maint_sre_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    maint_rank_r : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    accept_internal_r : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    ordered_r_lcl_reg_2 : in STD_LOGIC;
    app_en_r2 : in STD_LOGIC;
    \grant_r[3]_i_12\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    was_priority : in STD_LOGIC;
    q_has_rd_r_reg : in STD_LOGIC;
    was_wr : in STD_LOGIC;
    auto_pre_r_lcl_reg : in STD_LOGIC;
    pre_bm_end_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC;
    row : in STD_LOGIC_VECTOR ( 12 downto 0 );
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : in STD_LOGIC;
    demand_priority_r_0 : in STD_LOGIC;
    demanded_prior_r_1 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    demanded_prior_r_2 : in STD_LOGIC;
    demand_priority_r_3 : in STD_LOGIC;
    demanded_prior_r_4 : in STD_LOGIC;
    demand_priority_r_5 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \q_entry_r_reg[1]_1\ : in STD_LOGIC;
    \q_entry_r_reg[1]_2\ : in STD_LOGIC;
    \q_entry_r_reg[1]_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized2\ : entity is "mig_7series_v4_2_bank_cntrl";
end \mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized2\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized2\ is
  signal \^auto_pre_r\ : STD_LOGIC;
  signal bank_queue0_n_13 : STD_LOGIC;
  signal bank_queue0_n_23 : STD_LOGIC;
  signal bank_state0_n_17 : STD_LOGIC;
  signal bank_state0_n_26 : STD_LOGIC;
  signal col_wait_ns : STD_LOGIC;
  signal col_wait_r : STD_LOGIC;
  signal demand_priority_ns : STD_LOGIC;
  signal head_r : STD_LOGIC_VECTOR ( 3 to 3 );
  signal idle_ns : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \^idle_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^idle_r_lcl_reg\ : STD_LOGIC;
  signal \^order_q_r_reg[0]\ : STD_LOGIC;
  signal ordered_r : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \^ordered_r_lcl_reg_0\ : STD_LOGIC;
  signal \^p_13_out\ : STD_LOGIC;
  signal pass_open_bank_ns : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg\ : STD_LOGIC;
  signal pre_bm_end_ns : STD_LOGIC;
  signal pre_passing_open_bank_ns : STD_LOGIC;
  signal pre_wait_r : STD_LOGIC;
  signal q_has_rd : STD_LOGIC;
  signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ras_timer_r_reg[1]\ : STD_LOGIC;
  signal ras_timer_zero_r : STD_LOGIC;
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rd_wr_r_lcl_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal req_bank_rdy_ns : STD_LOGIC;
  signal req_priority_r : STD_LOGIC;
  signal req_wr_r : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \^req_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^req_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \^row_cmd_wr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal row_hit_r : STD_LOGIC;
  signal start_wtp_timer0 : STD_LOGIC;
  signal tail_r : STD_LOGIC;
  signal wait_for_maint_r : STD_LOGIC;
begin
  auto_pre_r <= \^auto_pre_r\;
  idle_r(0) <= \^idle_r\(0);
  idle_r_lcl_reg <= \^idle_r_lcl_reg\;
  \order_q_r_reg[0]\ <= \^order_q_r_reg[0]\;
  ordered_r_lcl_reg_0 <= \^ordered_r_lcl_reg_0\;
  p_13_out <= \^p_13_out\;
  pass_open_bank_r_lcl_reg <= \^pass_open_bank_r_lcl_reg\;
  \ras_timer_r_reg[1]\ <= \^ras_timer_r_reg[1]\;
  rb_hit_busy_r_reg(0) <= \^rb_hit_busy_r_reg\(0);
  rd_wr_r_lcl_reg(0) <= \^rd_wr_r_lcl_reg\(0);
  rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\;
  req_wr_r_lcl_reg <= \^req_wr_r_lcl_reg\;
  req_wr_r_lcl_reg_0 <= \^req_wr_r_lcl_reg_0\;
  row_cmd_wr(0) <= \^row_cmd_wr\(0);
bank_compare0: entity work.mig_7series_0_mig_7series_v4_2_bank_compare
     port map (
      CLK => CLK,
      E(0) => idle_ns(3),
      Q(0) => Q(3),
      hi_priority => hi_priority,
      \order_q_r_reg[1]\(2 downto 0) => \order_q_r_reg[0]_0\(2 downto 0),
      ordered_r(0) => ordered_r(3),
      ordered_r_lcl_reg => \^ordered_r_lcl_reg_0\,
      p_28_out => p_28_out,
      periodic_rd_insert => periodic_rd_insert,
      rb_hit_busy_r_reg_0 => \^rb_hit_busy_r_reg\(0),
      rd_wr_r_lcl_reg_0 => \^rd_wr_r_lcl_reg\(0),
      rd_wr_r_lcl_reg_1 => \^idle_r_lcl_reg\,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_1,
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      req_bank_rdy_r_reg => demand_priority_r_reg_0,
      req_bank_rdy_r_reg_0 => demand_priority_r_reg_1,
      req_bank_rdy_r_reg_1 => demand_priority_r_reg_2,
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_col_r_reg[9]_1\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0),
      \req_data_buf_addr_r_reg[0]_0\(0) => \^idle_r\(0),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      \req_data_buf_addr_r_reg[3]_1\(3 downto 0) => \req_data_buf_addr_r_reg[3]_0\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      req_priority_r => req_priority_r,
      \req_row_r_lcl_reg[12]_0\(12 downto 0) => \req_row_r_lcl_reg[12]\(12 downto 0),
      req_wr_r(0) => req_wr_r(3),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg_0 => \^req_wr_r_lcl_reg\,
      req_wr_r_lcl_reg_1 => \^req_wr_r_lcl_reg_0\,
      row(12 downto 0) => row(12 downto 0),
      row_hit_r => row_hit_r,
      row_hit_r_reg_0(0) => row_hit_r_reg(0),
      start_wtp_timer0 => start_wtp_timer0
    );
bank_queue0: entity work.\mig_7series_0_mig_7series_v4_2_bank_queue__parameterized2\
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      E(0) => idle_ns(3),
      Q(0) => Q(3),
      accept_internal_r => accept_internal_r,
      act_wait_r_lcl_i_4_0 => act_wait_r_lcl_i_4,
      act_wait_r_lcl_i_4_1 => act_wait_r_lcl_i_4_0,
      act_wait_r_lcl_i_4_2 => act_wait_r_lcl_i_4_1,
      app_en_r2 => app_en_r2,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r\,
      auto_pre_r_lcl_reg_1 => bank_state0_n_17,
      auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg,
      bm_end_r1_reg => \^rd_wr_r_lcl_reg\(0),
      col_wait_ns => col_wait_ns,
      col_wait_r => col_wait_r,
      demand_priority_ns => demand_priority_ns,
      demand_priority_r_reg => bank_state0_n_26,
      demand_priority_r_reg_0 => demand_priority_r_reg_0,
      demand_priority_r_reg_1 => \^req_wr_r_lcl_reg_0\,
      demand_priority_r_reg_2 => demand_priority_r_reg_1,
      demand_priority_r_reg_3 => demand_priority_r_reg_2,
      \grant_r[3]_i_12\(0) => \grant_r[3]_i_12\(0),
      \grant_r[3]_i_4__0\ => \^row_cmd_wr\(0),
      head_r(0) => head_r(3),
      head_r_lcl_reg_0 => head_r_lcl_reg,
      head_r_lcl_reg_1 => head_r_lcl_reg_0,
      head_r_lcl_reg_2 => head_r_lcl_reg_1,
      head_r_lcl_reg_3 => head_r_lcl_reg_2,
      idle_r_lcl_reg_0(0) => \^idle_r\(0),
      idle_r_lcl_reg_1 => \^idle_r_lcl_reg\,
      \maint_controller.maint_hit_busies_r_reg[3]\ => \maint_controller.maint_hit_busies_r_reg[3]\,
      \maint_controller.maint_hit_busies_r_reg[3]_0\(0) => \maint_controller.maint_hit_busies_r_reg[3]_0\(0),
      maint_rank_r => maint_rank_r,
      maint_sre_r => maint_sre_r,
      maint_zq_r => maint_zq_r,
      \order_q_r_reg[0]_0\ => \^order_q_r_reg[0]\,
      \order_q_r_reg[0]_1\(2 downto 0) => \order_q_r_reg[0]_0\(2 downto 0),
      \order_q_r_reg[1]_0\ => \^ordered_r_lcl_reg_0\,
      ordered_r(0) => ordered_r(3),
      ordered_r_lcl_reg_0 => ordered_r_lcl_reg,
      ordered_r_lcl_reg_1 => ordered_r_lcl_reg_1,
      ordered_r_lcl_reg_2 => ordered_r_lcl_reg_2,
      p_106_out => p_106_out,
      p_130_out => p_130_out,
      p_145_out => p_145_out,
      p_67_out => p_67_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r_lcl_reg_0 => \^pass_open_bank_r_lcl_reg\,
      pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg_0,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg_0 => \^p_13_out\,
      pre_bm_end_r_reg_1 => pre_bm_end_r_reg,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg,
      pre_wait_r => pre_wait_r,
      \q_entry_r_reg[0]_0\ => bank_queue0_n_13,
      \q_entry_r_reg[0]_1\ => ofs_rdy_r_reg,
      \q_entry_r_reg[0]_2\ => \q_entry_r_reg[0]\,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_0\,
      \q_entry_r_reg[1]_2\ => \q_entry_r_reg[1]_1\,
      \q_entry_r_reg[1]_3\ => \q_entry_r_reg[1]_2\,
      \q_entry_r_reg[1]_4\ => \q_entry_r_reg[1]_3\,
      q_has_priority_r_reg_0 => q_has_priority_r_reg,
      q_has_priority_r_reg_1 => \^rb_hit_busy_r_reg\(0),
      q_has_priority_r_reg_2 => \rtp_timer_r_reg[0]\,
      q_has_rd => q_has_rd,
      q_has_rd_r_reg_0 => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \^ras_timer_r_reg[1]\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_1\ => \ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\,
      \ras_timer_r_reg[1]\ => \^rd_wr_r_lcl_reg_0\,
      \ras_timer_r_reg[1]_0\ => \ras_timer_r_reg[1]_0\,
      \ras_timer_r_reg[1]_1\ => \ras_timer_r_reg[1]_1\,
      \ras_timer_r_reg[1]_2\ => \ras_timer_r_reg[1]_2\,
      ras_timer_zero_r => ras_timer_zero_r,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      rb_hit_busy_r(2 downto 0) => rb_hit_busy_r(2 downto 0),
      req_bank_rdy_ns => req_bank_rdy_ns,
      req_bank_rdy_r_reg => \^req_wr_r_lcl_reg\,
      req_priority_r => req_priority_r,
      req_wr_r(0) => req_wr_r(3),
      row_hit_r => row_hit_r,
      \rstdiv0_sync_r1_reg_rep__11\(0) => D(0),
      \rstdiv0_sync_r1_reg_rep__11_0\ => bank_queue0_n_23,
      tail_r => tail_r,
      wait_for_maint_r => wait_for_maint_r,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      was_priority => was_priority,
      was_wr => was_wr
    );
bank_state0: entity work.\mig_7series_0_mig_7series_v4_2_bank_state__parameterized2\
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      Q(3 downto 0) => Q(3 downto 0),
      act_this_rank_r(0) => act_this_rank_r(0),
      act_wait_r_lcl_reg_0 => \^row_cmd_wr\(0),
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg,
      act_wait_r_lcl_reg_2(0) => act_wait_r_lcl_reg_0(0),
      act_wait_r_lcl_reg_3 => bank_queue0_n_23,
      act_wait_r_lcl_reg_4 => act_wait_r_lcl_reg_1,
      auto_pre_r_lcl_reg => q_has_priority_r_reg,
      auto_pre_r_lcl_reg_0(0) => \^rb_hit_busy_r_reg\(0),
      bm_end_r1_4 => bm_end_r1_4,
      col_wait_ns => col_wait_ns,
      col_wait_r => col_wait_r,
      col_wait_r_reg_0 => col_wait_r_reg,
      col_wait_r_reg_1 => col_wait_r_reg_0,
      col_wait_r_reg_2 => bank_queue0_n_13,
      \compute_tail.tail_r_lcl_reg\ => bank_state0_n_17,
      demand_act_priority_r => demand_act_priority_r,
      demand_priority_ns => demand_priority_ns,
      demand_priority_r_0 => demand_priority_r_0,
      demand_priority_r_3 => demand_priority_r_3,
      demand_priority_r_5 => demand_priority_r_5,
      demand_priority_r_reg_0 => demand_priority_r,
      demand_priority_r_reg_1 => demand_priority_r_reg,
      demand_priority_r_reg_2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\,
      demand_priority_r_reg_3 => demand_priority_r_reg_3,
      demanded_prior_r_1 => demanded_prior_r_1,
      demanded_prior_r_2 => demanded_prior_r_2,
      demanded_prior_r_4 => demanded_prior_r_4,
      demanded_prior_r_reg_0 => demanded_prior_r,
      demanded_prior_r_reg_1 => demanded_prior_r_reg,
      demanded_prior_r_reg_2 => demanded_prior_r_reg_0,
      demanded_prior_r_reg_3 => demanded_prior_r_reg_1,
      \grant_r_reg[0]\ => \grant_r_reg[0]\,
      \grant_r_reg[3]\ => \grant_r_reg[3]\,
      \grant_r_reg[3]_0\ => \grant_r_reg[3]_0\,
      \grant_r_reg[3]_1\ => bank_state0_n_26,
      head_r(0) => head_r(3),
      idle_r(0) => \^idle_r\(0),
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r0 => ofs_rdy_r0,
      ofs_rdy_r_reg_0 => ofs_rdy_r_reg,
      p_13_out => \^p_13_out\,
      pass_open_bank_ns => pass_open_bank_ns,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \pre_4_1_1T_arb.granted_pre_r_reg\,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg(0) => pre_bm_end_r_reg_0(0),
      pre_bm_end_r_reg_0 => \^auto_pre_r\,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_wait_r => pre_wait_r,
      q_has_rd => q_has_rd,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]_2\,
      \ras_timer_r_reg[1]_0\ => \^ras_timer_r_reg[1]\,
      ras_timer_zero_r => ras_timer_zero_r,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_0,
      rd_this_rank_r(0) => rd_this_rank_r(0),
      \rd_this_rank_r_reg[0]_0\ => \^rd_wr_r_lcl_reg\(0),
      rd_wr_r_lcl_reg => \^rd_wr_r_lcl_reg_0\,
      req_bank_rdy_ns => req_bank_rdy_ns,
      req_wr_r(0) => req_wr_r(3),
      \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\,
      \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]_0\,
      \rnk_config_strobe_r_reg[0]_1\ => \^order_q_r_reg[0]\,
      \rtp_timer_r_reg[0]_0\ => \^pass_open_bank_r_lcl_reg\,
      \rtp_timer_r_reg[0]_1\ => \rtp_timer_r_reg[0]\,
      start_wtp_timer0 => start_wtp_timer0,
      tail_r => tail_r,
      wait_for_maint_r => wait_for_maint_r,
      wr_this_rank_r(0) => wr_this_rank_r(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_byte_lane is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mem_dqs_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    mem_dqs_ts : out STD_LOGIC_VECTOR ( 0 to 0 );
    A_rst_primitives_reg : out STD_LOGIC;
    out_dq_2 : out STD_LOGIC;
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    out_dm_0 : out STD_LOGIC;
    out_dq_0 : out STD_LOGIC;
    out_dq_6 : out STD_LOGIC;
    out_dq_3 : out STD_LOGIC;
    out_dq_1 : out STD_LOGIC;
    out_dq_4 : out STD_LOGIC;
    out_dq_7 : out STD_LOGIC;
    out_dq_5 : out STD_LOGIC;
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 );
    if_empty_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_reg[0]\ : out STD_LOGIC;
    \rd_ptr_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[2]\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    \my_empty_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_empty_reg[0]\ : out STD_LOGIC;
    in0 : out STD_LOGIC;
    phy_mc_data_full : out STD_LOGIC;
    wr_en_3 : out STD_LOGIC;
    \wr_ptr_reg[1]\ : out STD_LOGIC;
    \wr_ptr_reg[0]\ : out STD_LOGIC;
    app_rd_data : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    p_1_in : out STD_LOGIC;
    \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_stg2_wrcal_cnt_reg[0]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_61\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_62\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]\ : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    INBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pi_dqs_found_lanes_r1_reg[0]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_2\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_3\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pi_dqs_found_lanes_r1_reg[0]_4\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    INRANKA : in STD_LOGIC_VECTOR ( 1 downto 0 );
    COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    \slave_ts.oserdes_slave_ts\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_0\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_1\ : in STD_LOGIC;
    D1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D9 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ififo_rst_reg0 : in STD_LOGIC;
    ofifo_rst_reg0 : in STD_LOGIC;
    mux_wrdata_en : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    \wr_ptr_timing_reg[0]\ : in STD_LOGIC;
    calib_wrdata_en : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    my_empty : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    app_rd_data_valid_0 : in STD_LOGIC;
    app_rd_data_valid_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.tail_r_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    pi_phase_locked_all_r1_reg : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \app_rd_data[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    calib_sel : in STD_LOGIC_VECTOR ( 0 to 0 );
    COUNTERREADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_byte_lane : entity is "mig_7series_v4_2_ddr_byte_lane";
end mig_7series_0_mig_7series_v4_2_ddr_byte_lane;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_byte_lane is
  signal A_if_a_empty : STD_LOGIC;
  signal A_of_a_full : STD_LOGIC;
  signal A_of_full : STD_LOGIC;
  signal A_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal A_pi_dqs_out_of_range : STD_LOGIC;
  signal A_pi_fine_overflow : STD_LOGIC;
  signal A_po_coarse_overflow : STD_LOGIC;
  signal A_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal A_po_fine_overflow : STD_LOGIC;
  signal \^a_rst_primitives_reg\ : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : STD_LOGIC_VECTOR ( 67 downto 0 );
  signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal \^if_empty_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_6\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \pi_counter_read_val[0]_i_1\ : label is "soft_lutpair425";
  attribute SOFT_HLUTNM of \pi_counter_read_val[1]_i_1\ : label is "soft_lutpair425";
  attribute SOFT_HLUTNM of \pi_counter_read_val[2]_i_1\ : label is "soft_lutpair426";
  attribute SOFT_HLUTNM of \pi_counter_read_val[3]_i_1\ : label is "soft_lutpair426";
  attribute SOFT_HLUTNM of \pi_counter_read_val[4]_i_1\ : label is "soft_lutpair427";
  attribute SOFT_HLUTNM of \pi_counter_read_val[5]_i_1\ : label is "soft_lutpair427";
begin
  A_rst_primitives_reg <= \^a_rst_primitives_reg\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(67 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(67 downto 0);
  if_empty_r(0) <= \^if_empty_r\(0);
ddr_byte_group_io: entity work.mig_7series_0_mig_7series_v4_2_ddr_byte_group_io
     port map (
      CLK => CLK,
      CLKB0 => CLKB0,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0 => LD0,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^a_rst_primitives_reg\,
      idelay_inc => idelay_inc,
      \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq\,
      \input_[9].iserdes_dq_.iserdesdq_1\ => \pi_dqs_found_lanes_r1_reg[0]\,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      mem_dqs_out(0) => mem_dqs_out(0),
      mem_dqs_ts(0) => mem_dqs_ts(0),
      of_dqbus(35 downto 0) => of_dqbus(39 downto 4),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dm_0 => out_dm_0,
      out_dq_0 => out_dq_0,
      out_dq_1 => out_dq_1,
      out_dq_2 => out_dq_2,
      out_dq_3 => out_dq_3,
      out_dq_4 => out_dq_4,
      out_dq_5 => out_dq_5,
      out_dq_6 => out_dq_6,
      out_dq_7 => out_dq_7,
      po_oserdes_rst => po_oserdes_rst
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \if_empty_\,
      Q => \^if_empty_r\(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(10),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(4),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(11),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(5),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(12),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(6),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(13),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(7),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(14),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(8),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(15),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(9),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(16),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(10),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(17),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(11),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(24),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(25),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(26),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(27),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(28),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(29),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(30),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(31),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(32),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(33),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(34),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(35),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(36),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(37),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(38),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(39),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(40),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(41),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(42),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(43),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(44),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(45),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(46),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(47),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(48),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(49),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(50),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(51),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(52),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(53),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(54),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(55),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(56),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(57),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(58),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(59),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(60),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(61),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(62),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(63),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(64),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(65),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(66),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(67),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(68),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(69),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(6),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(70),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(71),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(72),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(73),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(74),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(75),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(76),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(77),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(78),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(66),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(79),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(67),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(7),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(8),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(2),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(9),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(3),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_7series_0_mig_7series_v4_2_ddr_if_post_fifo_9
     port map (
      CLK => CLK,
      app_rd_data(63 downto 0) => app_rd_data(63 downto 0),
      \app_rd_data[117]\(63 downto 8) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(67 downto 12),
      \app_rd_data[117]\(7 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(9 downto 2),
      \app_rd_data[117]_0\(63 downto 0) => \app_rd_data[117]\(63 downto 0),
      app_rd_data_valid => app_rd_data_valid,
      app_rd_data_valid_0 => app_rd_data_valid_0,
      app_rd_data_valid_1(0) => app_rd_data_valid_1(0),
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(63 downto 0) => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(63 downto 0),
      if_empty_r_0(0) => if_empty_r_0(0),
      ififo_rst => ififo_rst,
      my_empty(1 downto 0) => my_empty(1 downto 0),
      \my_empty_reg[0]_0\ => \my_empty_reg[3]\(0),
      \my_empty_reg[0]_1\ => \my_empty_reg[0]\,
      \my_empty_reg[3]_0\ => \my_empty_reg[3]\(1),
      \my_empty_reg[4]_rep__1_0\ => \^if_empty_r\(0),
      \out\(1 downto 0) => \out\(1 downto 0),
      p_1_in => p_1_in,
      \po_stg2_wrcal_cnt_reg[0]\ => \po_stg2_wrcal_cnt_reg[0]\,
      \po_stg2_wrcal_cnt_reg[0]_0\ => \po_stg2_wrcal_cnt_reg[0]_0\,
      \po_stg2_wrcal_cnt_reg[0]_1\ => \po_stg2_wrcal_cnt_reg[0]_1\,
      \po_stg2_wrcal_cnt_reg[0]_10\ => \po_stg2_wrcal_cnt_reg[0]_10\,
      \po_stg2_wrcal_cnt_reg[0]_11\ => \po_stg2_wrcal_cnt_reg[0]_11\,
      \po_stg2_wrcal_cnt_reg[0]_12\ => \po_stg2_wrcal_cnt_reg[0]_12\,
      \po_stg2_wrcal_cnt_reg[0]_13\ => \po_stg2_wrcal_cnt_reg[0]_13\,
      \po_stg2_wrcal_cnt_reg[0]_14\ => \po_stg2_wrcal_cnt_reg[0]_14\,
      \po_stg2_wrcal_cnt_reg[0]_15\ => \po_stg2_wrcal_cnt_reg[0]_15\,
      \po_stg2_wrcal_cnt_reg[0]_16\ => \po_stg2_wrcal_cnt_reg[0]_16\,
      \po_stg2_wrcal_cnt_reg[0]_17\ => \po_stg2_wrcal_cnt_reg[0]_17\,
      \po_stg2_wrcal_cnt_reg[0]_18\ => \po_stg2_wrcal_cnt_reg[0]_18\,
      \po_stg2_wrcal_cnt_reg[0]_19\ => \po_stg2_wrcal_cnt_reg[0]_19\,
      \po_stg2_wrcal_cnt_reg[0]_2\ => \po_stg2_wrcal_cnt_reg[0]_2\,
      \po_stg2_wrcal_cnt_reg[0]_20\ => \po_stg2_wrcal_cnt_reg[0]_20\,
      \po_stg2_wrcal_cnt_reg[0]_21\ => \po_stg2_wrcal_cnt_reg[0]_21\,
      \po_stg2_wrcal_cnt_reg[0]_22\ => \po_stg2_wrcal_cnt_reg[0]_22\,
      \po_stg2_wrcal_cnt_reg[0]_23\ => \po_stg2_wrcal_cnt_reg[0]_23\,
      \po_stg2_wrcal_cnt_reg[0]_24\ => \po_stg2_wrcal_cnt_reg[0]_24\,
      \po_stg2_wrcal_cnt_reg[0]_25\ => \po_stg2_wrcal_cnt_reg[0]_25\,
      \po_stg2_wrcal_cnt_reg[0]_26\ => \po_stg2_wrcal_cnt_reg[0]_26\,
      \po_stg2_wrcal_cnt_reg[0]_27\ => \po_stg2_wrcal_cnt_reg[0]_27\,
      \po_stg2_wrcal_cnt_reg[0]_28\ => \po_stg2_wrcal_cnt_reg[0]_28\,
      \po_stg2_wrcal_cnt_reg[0]_29\ => \po_stg2_wrcal_cnt_reg[0]_29\,
      \po_stg2_wrcal_cnt_reg[0]_3\ => \po_stg2_wrcal_cnt_reg[0]_3\,
      \po_stg2_wrcal_cnt_reg[0]_30\ => \po_stg2_wrcal_cnt_reg[0]_30\,
      \po_stg2_wrcal_cnt_reg[0]_31\ => \po_stg2_wrcal_cnt_reg[0]_31\,
      \po_stg2_wrcal_cnt_reg[0]_32\ => \po_stg2_wrcal_cnt_reg[0]_32\,
      \po_stg2_wrcal_cnt_reg[0]_33\ => \po_stg2_wrcal_cnt_reg[0]_33\,
      \po_stg2_wrcal_cnt_reg[0]_34\ => \po_stg2_wrcal_cnt_reg[0]_34\,
      \po_stg2_wrcal_cnt_reg[0]_35\ => \po_stg2_wrcal_cnt_reg[0]_35\,
      \po_stg2_wrcal_cnt_reg[0]_36\ => \po_stg2_wrcal_cnt_reg[0]_36\,
      \po_stg2_wrcal_cnt_reg[0]_37\ => \po_stg2_wrcal_cnt_reg[0]_37\,
      \po_stg2_wrcal_cnt_reg[0]_38\ => \po_stg2_wrcal_cnt_reg[0]_38\,
      \po_stg2_wrcal_cnt_reg[0]_39\ => \po_stg2_wrcal_cnt_reg[0]_39\,
      \po_stg2_wrcal_cnt_reg[0]_4\ => \po_stg2_wrcal_cnt_reg[0]_4\,
      \po_stg2_wrcal_cnt_reg[0]_40\ => \po_stg2_wrcal_cnt_reg[0]_40\,
      \po_stg2_wrcal_cnt_reg[0]_41\ => \po_stg2_wrcal_cnt_reg[0]_41\,
      \po_stg2_wrcal_cnt_reg[0]_42\ => \po_stg2_wrcal_cnt_reg[0]_42\,
      \po_stg2_wrcal_cnt_reg[0]_43\ => \po_stg2_wrcal_cnt_reg[0]_43\,
      \po_stg2_wrcal_cnt_reg[0]_44\ => \po_stg2_wrcal_cnt_reg[0]_44\,
      \po_stg2_wrcal_cnt_reg[0]_45\ => \po_stg2_wrcal_cnt_reg[0]_45\,
      \po_stg2_wrcal_cnt_reg[0]_46\ => \po_stg2_wrcal_cnt_reg[0]_46\,
      \po_stg2_wrcal_cnt_reg[0]_47\ => \po_stg2_wrcal_cnt_reg[0]_47\,
      \po_stg2_wrcal_cnt_reg[0]_48\ => \po_stg2_wrcal_cnt_reg[0]_48\,
      \po_stg2_wrcal_cnt_reg[0]_49\ => \po_stg2_wrcal_cnt_reg[0]_49\,
      \po_stg2_wrcal_cnt_reg[0]_5\ => \po_stg2_wrcal_cnt_reg[0]_5\,
      \po_stg2_wrcal_cnt_reg[0]_50\ => \po_stg2_wrcal_cnt_reg[0]_50\,
      \po_stg2_wrcal_cnt_reg[0]_51\ => \po_stg2_wrcal_cnt_reg[0]_51\,
      \po_stg2_wrcal_cnt_reg[0]_52\ => \po_stg2_wrcal_cnt_reg[0]_52\,
      \po_stg2_wrcal_cnt_reg[0]_53\ => \po_stg2_wrcal_cnt_reg[0]_53\,
      \po_stg2_wrcal_cnt_reg[0]_54\ => \po_stg2_wrcal_cnt_reg[0]_54\,
      \po_stg2_wrcal_cnt_reg[0]_55\ => \po_stg2_wrcal_cnt_reg[0]_55\,
      \po_stg2_wrcal_cnt_reg[0]_56\ => \po_stg2_wrcal_cnt_reg[0]_56\,
      \po_stg2_wrcal_cnt_reg[0]_57\ => \po_stg2_wrcal_cnt_reg[0]_57\,
      \po_stg2_wrcal_cnt_reg[0]_58\ => \po_stg2_wrcal_cnt_reg[0]_58\,
      \po_stg2_wrcal_cnt_reg[0]_59\ => \po_stg2_wrcal_cnt_reg[0]_59\,
      \po_stg2_wrcal_cnt_reg[0]_6\ => \po_stg2_wrcal_cnt_reg[0]_6\,
      \po_stg2_wrcal_cnt_reg[0]_60\ => \po_stg2_wrcal_cnt_reg[0]_60\,
      \po_stg2_wrcal_cnt_reg[0]_61\ => \po_stg2_wrcal_cnt_reg[0]_61\,
      \po_stg2_wrcal_cnt_reg[0]_62\ => \po_stg2_wrcal_cnt_reg[0]_62\,
      \po_stg2_wrcal_cnt_reg[0]_7\ => \po_stg2_wrcal_cnt_reg[0]_7\,
      \po_stg2_wrcal_cnt_reg[0]_8\ => \po_stg2_wrcal_cnt_reg[0]_8\,
      \po_stg2_wrcal_cnt_reg[0]_9\ => \po_stg2_wrcal_cnt_reg[0]_9\,
      \read_fifo.tail_r_reg[4]\(0) => \read_fifo.tail_r_reg[4]\(0),
      \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]\,
      \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]\
    );
ififo_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ififo_rst_reg0,
      Q => ififo_rst,
      R => '0'
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => A_if_a_empty,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => B"0000",
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => CLK,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_10\
     port map (
      A_of_full => A_of_full,
      CLK => CLK,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      Q(2 downto 0) => Q(2 downto 0),
      calib_wrdata_en => calib_wrdata_en,
      mc_wrdata_en => mc_wrdata_en,
      mux_wrdata_en => mux_wrdata_en,
      \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]\,
      ofifo_rst => ofifo_rst,
      out_fifo(7 downto 0) => out_fifo_0(7 downto 0),
      phy_mc_data_full => phy_mc_data_full,
      \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]\,
      \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]\,
      \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]\,
      \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]\,
      wr_en_3 => wr_en_3,
      \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0),
      \wr_ptr_timing_reg[0]_0\ => \wr_ptr_timing_reg[0]\
    );
ofifo_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofifo_rst_reg0,
      Q => ofifo_rst,
      R => '0'
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => A_of_a_full,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D1(7 downto 0) => D1(7 downto 0),
      D2(7 downto 0) => D2(7 downto 0),
      D3(7 downto 0) => D3(7 downto 0),
      D4(7 downto 0) => D4(7 downto 0),
      D5(7 downto 0) => D5(7 downto 0),
      D6(7 downto 0) => D6(7 downto 0),
      D7(7 downto 0) => D7(7 downto 0),
      D8(7 downto 0) => D8(7 downto 0),
      D9(7 downto 0) => D9(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => A_of_full,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.333000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 3.333000,
      REFCLK_PERIOD => 1.666500,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => INBURSTPENDING(0),
      COUNTERLOADEN => \pi_dqs_found_lanes_r1_reg[0]_0\,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[0]_1\,
      COUNTERREADVAL(5 downto 0) => A_pi_counter_read_val(5 downto 0),
      DQSFOUND => pi_dqs_found_lanes(0),
      DQSOUTOFRANGE => A_pi_dqs_out_of_range,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \pi_dqs_found_lanes_r1_reg[0]_2\,
      FINEINC => \pi_dqs_found_lanes_r1_reg[0]_3\,
      FINEOVERFLOW => A_pi_fine_overflow,
      FREQREFCLK => freq_refclk,
      ICLK => \^a_rst_primitives_reg\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => \phaser_in_gen.phaser_in_n_6\,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => INRANKA(1 downto 0),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => \pi_dqs_found_lanes_r1_reg[0]\,
      RSTDQSFIND => \pi_dqs_found_lanes_r1_reg[0]_4\,
      SYNCIN => sync_pulse,
      SYSCLK => CLK,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.333000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.666500,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => OUTBURSTPENDING(0),
      COARSEENABLE => \slave_ts.oserdes_slave_ts\,
      COARSEINC => \pi_dqs_found_lanes_r1_reg[0]_1\,
      COARSEOVERFLOW => A_po_coarse_overflow,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[0]_1\,
      COUNTERREADVAL(8 downto 0) => A_po_counter_read_val(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \slave_ts.oserdes_slave_ts_0\,
      FINEINC => \slave_ts.oserdes_slave_ts_1\,
      FINEOVERFLOW => A_po_fine_overflow,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => \pi_dqs_found_lanes_r1_reg[0]\,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
\pi_counter_read_val[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => A_pi_counter_read_val(0),
      I1 => calib_sel(0),
      I2 => COUNTERREADVAL(0),
      O => D(0)
    );
\pi_counter_read_val[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => A_pi_counter_read_val(1),
      I1 => calib_sel(0),
      I2 => COUNTERREADVAL(1),
      O => D(1)
    );
\pi_counter_read_val[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => A_pi_counter_read_val(2),
      I1 => calib_sel(0),
      I2 => COUNTERREADVAL(2),
      O => D(2)
    );
\pi_counter_read_val[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => A_pi_counter_read_val(3),
      I1 => calib_sel(0),
      I2 => COUNTERREADVAL(3),
      O => D(3)
    );
\pi_counter_read_val[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => A_pi_counter_read_val(4),
      I1 => calib_sel(0),
      I2 => COUNTERREADVAL(4),
      O => D(4)
    );
\pi_counter_read_val[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => A_pi_counter_read_val(5),
      I1 => calib_sel(0),
      I2 => COUNTERREADVAL(5),
      O => D(5)
    );
pi_phase_locked_all_inferred_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \phaser_in_gen.phaser_in_n_6\,
      I1 => pi_phase_locked_all_r1_reg,
      O => in0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized0\ is
  port (
    ofifo_rst : out STD_LOGIC;
    \rd_ptr_reg[0]\ : out STD_LOGIC;
    \rd_ptr_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[2]\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC;
    wr_en_4 : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    phy_mc_cmd_full : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC;
    out_fifo_2 : in STD_LOGIC;
    out_fifo_3 : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    ofifo_rst_reg_0 : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    CLK : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_empty_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \my_empty_reg[6]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[6]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[6]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    calib_cmd_wren : in STD_LOGIC;
    \wr_ptr_timing_reg[0]\ : in STD_LOGIC;
    out_fifo_4 : in STD_LOGIC_VECTOR ( 32 downto 0 );
    mux_cmd_wren : in STD_LOGIC;
    D_of_full : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized0\ : entity is "mig_7series_v4_2_ddr_byte_lane";
end \mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized0\ is
  signal B_of_a_full : STD_LOGIC;
  signal B_of_full : STD_LOGIC;
  signal B_po_coarse_overflow : STD_LOGIC;
  signal B_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal B_po_fine_overflow : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal of_q0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q5 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q6 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^ofifo_rst\ : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  ofifo_rst <= \^ofifo_rst\;
ddr_byte_group_io: entity work.\mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized0\
     port map (
      mem_dq_out(11 downto 0) => mem_dq_out(11 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clkdiv => oserdes_clkdiv,
      oserdes_dq(47 downto 44) => of_q6(7 downto 4),
      oserdes_dq(43 downto 40) => of_q5(7 downto 4),
      oserdes_dq(39 downto 36) => of_q9(3 downto 0),
      oserdes_dq(35 downto 32) => of_q8(3 downto 0),
      oserdes_dq(31 downto 28) => of_q7(3 downto 0),
      oserdes_dq(27 downto 24) => of_q6(3 downto 0),
      oserdes_dq(23 downto 20) => of_q5(3 downto 0),
      oserdes_dq(19 downto 16) => of_q4(3 downto 0),
      oserdes_dq(15 downto 12) => of_q3(3 downto 0),
      oserdes_dq(11 downto 8) => of_q2(3 downto 0),
      oserdes_dq(7 downto 4) => of_q1(3 downto 0),
      oserdes_dq(3 downto 0) => of_q0(3 downto 0),
      po_oserdes_rst => po_oserdes_rst
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_8\
     port map (
      B_of_full => B_of_full,
      CLK => CLK,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D1(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D1(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D1(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D1(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D2(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D2(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D2(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D2(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D3(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D3(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D3(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D3(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D4(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D4(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D4(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D4(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D4(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D7(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D7(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D7(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D7(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\,
      D9(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\,
      D9(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37\,
      D9(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38\,
      D9(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39\,
      Q(3 downto 0) => Q(3 downto 0),
      SR(0) => \^ofifo_rst\,
      calib_cmd_wren => calib_cmd_wren,
      mux_cmd_wren => mux_cmd_wren,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      \my_empty_reg[1]_1\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      out_fifo(32 downto 0) => out_fifo_4(32 downto 0),
      \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]\,
      \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]\,
      \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]\,
      \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]\,
      wr_en_4 => wr_en_4,
      \wr_ptr_timing_reg[0]_0\ => \wr_ptr_timing_reg[0]\
    );
ofifo_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofifo_rst_reg_0,
      Q => \^ofifo_rst\,
      R => '0'
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => B_of_a_full,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D0(3 downto 0) => \my_empty_reg[6]\(3 downto 0),
      D1(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D1(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D1(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D1(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D1(3 downto 0) => \my_empty_reg[6]_0\(3 downto 0),
      D2(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D2(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D2(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D2(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D2(3 downto 0) => \my_empty_reg[6]_1\(3 downto 0),
      D3(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D3(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D3(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D3(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D3(3 downto 0) => \my_empty_reg[6]_2\(3 downto 0),
      D4(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D4(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D4(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D4(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D4(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D4(2 downto 0) => \my_empty_reg[6]_3\(2 downto 0),
      D5(7 downto 0) => \my_empty_reg[6]_4\(7 downto 0),
      D6(7 downto 0) => \my_empty_reg[6]_5\(7 downto 0),
      D7(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D7(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D7(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D7(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D7(3 downto 0) => \my_empty_reg[6]_6\(3 downto 0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\,
      D8(3 downto 0) => \my_empty_reg[6]_7\(3 downto 0),
      D9(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\,
      D9(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37\,
      D9(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38\,
      D9(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39\,
      D9(3 downto 0) => \my_empty_reg[6]_8\(3 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => B_of_full,
      Q0(3 downto 0) => of_q0(3 downto 0),
      Q1(3 downto 0) => of_q1(3 downto 0),
      Q2(3 downto 0) => of_q2(3 downto 0),
      Q3(3 downto 0) => of_q3(3 downto 0),
      Q4(3 downto 0) => of_q4(3 downto 0),
      Q5(7 downto 0) => of_q5(7 downto 0),
      Q6(7 downto 0) => of_q6(7 downto 0),
      Q7(3 downto 0) => of_q7(3 downto 0),
      Q8(3 downto 0) => of_q8(3 downto 0),
      Q9(3 downto 0) => of_q9(3 downto 0),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => \^ofifo_rst\,
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 4,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "FALSE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.333000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.666500,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => OUTBURSTPENDING(0),
      COARSEENABLE => out_fifo_0,
      COARSEINC => out_fifo_1,
      COARSEOVERFLOW => B_po_coarse_overflow,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => out_fifo_1,
      COUNTERREADVAL(8 downto 0) => B_po_counter_read_val(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => out_fifo_2,
      FINEINC => out_fifo_3,
      FINEOVERFLOW => B_po_fine_overflow,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => ofifo_rst_reg_0,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
phy_mc_cmd_full_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => B_of_full,
      I1 => D_of_full,
      O => phy_mc_cmd_full
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized1\ is
  port (
    \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mem_dqs_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    mem_dqs_ts : out STD_LOGIC_VECTOR ( 0 to 0 );
    A_rst_primitives_reg : out STD_LOGIC;
    out_dq_13 : out STD_LOGIC;
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    out_dq_8 : out STD_LOGIC;
    out_dq_15 : out STD_LOGIC;
    out_dq_12 : out STD_LOGIC;
    out_dq_10 : out STD_LOGIC;
    out_dq_9 : out STD_LOGIC;
    out_dq_11 : out STD_LOGIC;
    out_dq_14 : out STD_LOGIC;
    out_dm_1 : out STD_LOGIC;
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC;
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    if_empty_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_reg[0]\ : out STD_LOGIC;
    \rd_ptr_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[2]\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC;
    idelay_ld_rst : out STD_LOGIC;
    init_complete_r1_timing_reg : out STD_LOGIC;
    \my_empty_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_empty_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC_VECTOR ( 65 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ : out STD_LOGIC;
    phy_rddata_en : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    wr_en_2 : out STD_LOGIC;
    \wr_ptr_reg[1]\ : out STD_LOGIC;
    \wr_ptr_reg[0]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    wr_en : out STD_LOGIC;
    \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    CLK : in STD_LOGIC;
    \input_[8].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_0 : in STD_LOGIC;
    idelay_ld_rst_reg : in STD_LOGIC;
    CLKB0_5 : in STD_LOGIC;
    INBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pi_dqs_found_lanes_r1_reg[2]_3\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    INRANKC : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[2]_4\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    \slave_ts.oserdes_slave_ts\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_0\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_1\ : in STD_LOGIC;
    D0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ififo_rst_reg0_1 : in STD_LOGIC;
    ofifo_rst_reg0_2 : in STD_LOGIC;
    \read_fifo.tail_r_reg[0]\ : in STD_LOGIC;
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[4]_rep__1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mux_wrdata_en : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    calib_wrdata_en : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    app_rd_data : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \wr_ptr_timing_reg[0]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized1\ : entity is "mig_7series_v4_2_ddr_byte_lane";
end \mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized1\ is
  signal \^a_rst_primitives_reg\ : STD_LOGIC;
  signal C_if_a_empty : STD_LOGIC;
  signal C_of_a_full : STD_LOGIC;
  signal C_of_full : STD_LOGIC;
  signal C_pi_dqs_out_of_range : STD_LOGIC;
  signal C_pi_fine_overflow : STD_LOGIC;
  signal C_po_coarse_overflow : STD_LOGIC;
  signal C_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal C_po_fine_overflow : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : STD_LOGIC_VECTOR ( 65 downto 0 );
  signal if_d0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal \^if_empty_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  A_rst_primitives_reg <= \^a_rst_primitives_reg\;
  \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(65 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(65 downto 0);
  if_empty_r(0) <= \^if_empty_r\(0);
ddr_byte_group_io: entity work.\mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized1\
     port map (
      CLK => CLK,
      CLKB0_5 => CLKB0_5,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D0(3 downto 0) => if_d0(3 downto 0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_0 => LD0_0,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^a_rst_primitives_reg\,
      idelay_inc => idelay_inc,
      idelay_ld_rst => idelay_ld_rst,
      idelay_ld_rst_reg_0 => idelay_ld_rst_reg,
      \input_[8].iserdes_dq_.iserdesdq_0\ => \input_[8].iserdes_dq_.iserdesdq\,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      mem_dqs_out(0) => mem_dqs_out(0),
      mem_dqs_ts(0) => mem_dqs_ts(0),
      of_dqbus(35 downto 12) => of_dqbus(39 downto 16),
      of_dqbus(11 downto 0) => of_dqbus(11 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dm_1 => out_dm_1,
      out_dq_10 => out_dq_10,
      out_dq_11 => out_dq_11,
      out_dq_12 => out_dq_12,
      out_dq_13 => out_dq_13,
      out_dq_14 => out_dq_14,
      out_dq_15 => out_dq_15,
      out_dq_8 => out_dq_8,
      out_dq_9 => out_dq_9,
      po_oserdes_rst => po_oserdes_rst
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \if_empty_\,
      Q => \^if_empty_r\(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(0),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(10),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(10),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(11),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(11),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(12),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(13),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(14),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(15),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(16),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(17),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(18),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(19),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(1),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(20),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(21),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(22),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(23),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(2),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(2),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(30),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(31),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(32),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(33),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(34),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(35),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(36),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(37),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(38),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(39),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(3),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(3),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(40),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(41),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(42),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(43),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(44),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(45),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(46),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(47),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(48),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(49),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(4),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(4),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(50),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(51),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(52),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(53),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(54),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(55),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(56),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(57),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(58),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(59),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(5),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(5),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(60),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(61),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(62),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(63),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(64),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(65),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(66),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(67),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(68),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(69),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(6),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(6),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(70),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(71),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(7),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(7),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(8),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(8),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(9),
      Q => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(9),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_7series_0_mig_7series_v4_2_ddr_if_post_fifo
     port map (
      CLK => CLK,
      app_rd_data(63 downto 0) => app_rd_data(63 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(63 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(63 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 24) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(65 downto 26),
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(23 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(23 downto 0),
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\(63 downto 0) => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0),
      if_empty_r_0(0) => if_empty_r_0(0),
      ififo_rst => ififo_rst,
      init_complete_r1_timing_reg => init_complete_r1_timing_reg,
      \my_empty_reg[0]_0\ => \my_empty_reg[3]\(0),
      \my_empty_reg[3]_0\ => \my_empty_reg[3]\(1),
      \my_empty_reg[4]_rep__1_0\ => \^if_empty_r\(0),
      \my_empty_reg[4]_rep__1_1\(1 downto 0) => \my_empty_reg[4]_rep__1\(1 downto 0),
      phy_rddata_en => phy_rddata_en,
      \rd_ptr_timing_reg[1]_0\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0),
      \read_fifo.tail_r_reg[0]\ => \read_fifo.tail_r_reg[0]\,
      wr_en => wr_en,
      \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]\,
      \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]\
    );
ififo_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ififo_rst_reg0_1,
      Q => ififo_rst,
      R => '0'
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => C_if_a_empty,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => if_d0(3 downto 0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => B"0000",
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => B"0000",
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => CLK,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_7\
     port map (
      CLK => CLK,
      C_of_full => C_of_full,
      D3(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D3(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D3(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D3(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D3(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D3(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D3(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D3(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      Q(2 downto 0) => Q(2 downto 0),
      calib_wrdata_en => calib_wrdata_en,
      mc_wrdata_en => mc_wrdata_en,
      mux_wrdata_en => mux_wrdata_en,
      \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]\,
      ofifo_rst => ofifo_rst,
      out_fifo => out_fifo_0,
      out_fifo_0(7 downto 0) => out_fifo_1(7 downto 0),
      \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]\,
      \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]\,
      \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]\,
      \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]\,
      wr_en_2 => wr_en_2,
      \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0),
      \wr_ptr_timing_reg[0]_0\ => \wr_ptr_timing_reg[0]\
    );
ofifo_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofifo_rst_reg0_2,
      Q => ofifo_rst,
      R => '0'
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => C_of_a_full,
      D0(7 downto 0) => D0(7 downto 0),
      D1(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      D2(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      D3(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D3(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D3(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D3(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D3(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D3(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D3(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D3(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D4(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      D5(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      D6(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      D7(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      D8(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      D9(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => C_of_full,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.333000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 3.333000,
      REFCLK_PERIOD => 1.666500,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => INBURSTPENDING(0),
      COUNTERLOADEN => \pi_dqs_found_lanes_r1_reg[2]\,
      COUNTERLOADVAL(5 downto 0) => \pi_dqs_found_lanes_r1_reg[2]_4\(5 downto 0),
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[2]_0\,
      COUNTERREADVAL(5 downto 0) => COUNTERREADVAL(5 downto 0),
      DQSFOUND => pi_dqs_found_lanes(0),
      DQSOUTOFRANGE => C_pi_dqs_out_of_range,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \pi_dqs_found_lanes_r1_reg[2]_1\,
      FINEINC => \pi_dqs_found_lanes_r1_reg[2]_2\,
      FINEOVERFLOW => C_pi_fine_overflow,
      FREQREFCLK => freq_refclk,
      ICLK => \^a_rst_primitives_reg\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => A_rst_primitives_reg_0,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => INRANKC(1 downto 0),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => idelay_ld_rst_reg,
      RSTDQSFIND => \pi_dqs_found_lanes_r1_reg[2]_3\,
      SYNCIN => sync_pulse,
      SYSCLK => CLK,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.333000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.666500,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => OUTBURSTPENDING(0),
      COARSEENABLE => \slave_ts.oserdes_slave_ts\,
      COARSEINC => \pi_dqs_found_lanes_r1_reg[2]_0\,
      COARSEOVERFLOW => C_po_coarse_overflow,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[2]_0\,
      COUNTERREADVAL(8 downto 0) => C_po_counter_read_val(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \slave_ts.oserdes_slave_ts_0\,
      FINEINC => \slave_ts.oserdes_slave_ts_1\,
      FINEOVERFLOW => C_po_fine_overflow,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => idelay_ld_rst_reg,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized2\ is
  port (
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D_of_full : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    A_rst_primitives_reg : out STD_LOGIC_VECTOR ( 9 downto 0 );
    mem_out : out STD_LOGIC_VECTOR ( 30 downto 0 );
    OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC;
    out_fifo_2 : in STD_LOGIC;
    out_fifo_3 : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    out_fifo_4 : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    CLK : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ofifo_rst : in STD_LOGIC;
    \rd_ptr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_reg[3]_3\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \rd_ptr_reg[3]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_reg[3]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_ptr_timing_reg[0]\ : in STD_LOGIC;
    calib_cmd_wren : in STD_LOGIC;
    mux_cmd_wren : in STD_LOGIC;
    out_fifo_5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    out_fifo_6 : in STD_LOGIC;
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized2\ : entity is "mig_7series_v4_2_ddr_byte_lane";
end \mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized2\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized2\ is
  signal \^d_of_full\ : STD_LOGIC;
  signal ddr_ck_out_q : STD_LOGIC_VECTOR ( 0 to 0 );
  signal of_d6 : STD_LOGIC_VECTOR ( 6 downto 5 );
  signal of_d7 : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal of_d9 : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal of_q0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q5 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q6 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal phaser_out_n_13 : STD_LOGIC;
  signal phaser_out_n_14 : STD_LOGIC;
  signal phaser_out_n_15 : STD_LOGIC;
  signal phaser_out_n_16 : STD_LOGIC;
  signal phaser_out_n_17 : STD_LOGIC;
  signal phaser_out_n_18 : STD_LOGIC;
  signal phaser_out_n_19 : STD_LOGIC;
  signal phaser_out_n_20 : STD_LOGIC;
  signal phaser_out_n_21 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED\ : STD_LOGIC;
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck\ : label is "FALSE";
  attribute BOX_TYPE of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE : string;
  attribute CAPACITANCE of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\ : label is "DONT_CARE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\ : label is "OBUFDS";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  D_of_full <= \^d_of_full\;
ddr_byte_group_io: entity work.\mig_7series_0_mig_7series_v4_2_ddr_byte_group_io__parameterized2\
     port map (
      A_rst_primitives_reg(9 downto 0) => A_rst_primitives_reg(9 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clkdiv => oserdes_clkdiv,
      oserdes_dq(39 downto 36) => of_q6(7 downto 4),
      oserdes_dq(35 downto 32) => of_q5(7 downto 4),
      oserdes_dq(31 downto 28) => of_q9(3 downto 0),
      oserdes_dq(27 downto 24) => of_q8(3 downto 0),
      oserdes_dq(23 downto 20) => of_q7(3 downto 0),
      oserdes_dq(19 downto 16) => of_q6(3 downto 0),
      oserdes_dq(15 downto 12) => of_q5(3 downto 0),
      oserdes_dq(11 downto 8) => of_q4(3 downto 0),
      oserdes_dq(7 downto 4) => of_q3(3 downto 0),
      oserdes_dq(3 downto 0) => of_q2(3 downto 0),
      po_oserdes_rst => po_oserdes_rst
    );
\ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk,
      CE => '1',
      D1 => '0',
      D2 => '1',
      Q => ddr_ck_out_q(0),
      R => '0',
      S => \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED\
    );
\ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\: unisim.vcomponents.OBUFDS
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => ddr_ck_out_q(0),
      O => ddr_ck_out(0),
      OB => ddr_ck_out(1)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\
     port map (
      CLK => CLK,
      D1(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D1(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D1(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D1(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D1(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D1(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D1(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D1(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D2(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D2(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D2(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D2(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D3(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D3(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D3(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\,
      D3(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\,
      D4(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\,
      D4(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\,
      D4(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37\,
      D4(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38\,
      D6(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\,
      D6(1 downto 0) => of_d6(6 downto 5),
      D7(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D7(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D7(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D7(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D7(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D7(1 downto 0) => of_d7(2 downto 1),
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42\,
      D9(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D9(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D9(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D9(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\,
      D9(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D9(1 downto 0) => of_d9(2 downto 1),
      calib_cmd_wren => calib_cmd_wren,
      mc_cas_n(1 downto 0) => mc_cas_n(1 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(0) => mc_ras_n(0),
      mem_out(30 downto 0) => mem_out(30 downto 0),
      mux_cmd_wren => mux_cmd_wren,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      \my_empty_reg[1]_1\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      ofifo_rst => ofifo_rst,
      out_fifo(1 downto 0) => out_fifo_5(1 downto 0),
      out_fifo_0 => out_fifo_6,
      phy_dout(31 downto 0) => phy_dout(31 downto 0),
      \rd_ptr_reg[3]_0\ => \^d_of_full\,
      \wr_ptr_timing_reg[0]_0\ => \wr_ptr_timing_reg[0]\
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D1(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D1(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D1(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D1(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D1(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D1(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D1(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D1(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D2(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D2(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D2(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D2(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D2(3 downto 0) => \rd_ptr_reg[3]\(3 downto 0),
      D3(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D3(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D3(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\,
      D3(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\,
      D3(3 downto 0) => \rd_ptr_reg[3]_0\(3 downto 0),
      D4(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\,
      D4(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\,
      D4(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37\,
      D4(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38\,
      D4(3 downto 0) => \rd_ptr_reg[3]_1\(3 downto 0),
      D5(7 downto 0) => \rd_ptr_reg[3]_2\(7 downto 0),
      D6(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\,
      D6(6 downto 5) => of_d6(6 downto 5),
      D6(4 downto 0) => \rd_ptr_reg[3]_3\(4 downto 0),
      D7(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D7(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D7(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D7(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D7(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D7(2 downto 1) => of_d7(2 downto 1),
      D7(0) => \rd_ptr_reg[3]_4\(0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42\,
      D8(3 downto 0) => \rd_ptr_reg[3]_5\(3 downto 0),
      D9(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D9(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D9(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D9(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\,
      D9(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D9(2 downto 1) => of_d9(2 downto 1),
      D9(0) => \rd_ptr_reg[3]_6\(0),
      EMPTY => out_fifo_n_2,
      FULL => \^d_of_full\,
      Q0(3 downto 0) => of_q0(3 downto 0),
      Q1(3 downto 0) => of_q1(3 downto 0),
      Q2(3 downto 0) => of_q2(3 downto 0),
      Q3(3 downto 0) => of_q3(3 downto 0),
      Q4(3 downto 0) => of_q4(3 downto 0),
      Q5(7 downto 0) => of_q5(7 downto 0),
      Q6(7 downto 0) => of_q6(7 downto 0),
      Q7(3 downto 0) => of_q7(3 downto 0),
      Q8(3 downto 0) => of_q8(3 downto 0),
      Q9(3 downto 0) => of_q9(3 downto 0),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 4,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "FALSE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.333000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 0,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.666500,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => OUTBURSTPENDING(0),
      COARSEENABLE => out_fifo_0,
      COARSEINC => out_fifo_1,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => out_fifo_1,
      COUNTERREADVAL(8) => phaser_out_n_13,
      COUNTERREADVAL(7) => phaser_out_n_14,
      COUNTERREADVAL(6) => phaser_out_n_15,
      COUNTERREADVAL(5) => phaser_out_n_16,
      COUNTERREADVAL(4) => phaser_out_n_17,
      COUNTERREADVAL(3) => phaser_out_n_18,
      COUNTERREADVAL(2) => phaser_out_n_19,
      COUNTERREADVAL(1) => phaser_out_n_20,
      COUNTERREADVAL(0) => phaser_out_n_21,
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => out_fifo_2,
      FINEINC => out_fifo_3,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => out_fifo_4,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_calib_top is
  port (
    po_ck_addr_cmd_delay_done : out STD_LOGIC;
    dqs_po_dec_done : out STD_LOGIC;
    \rd_mux_sel_r_reg[0]\ : out STD_LOGIC;
    new_cnt_cpt_r_reg : out STD_LOGIC;
    rdlvl_stg1_start_reg : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    pi_fine_dly_dec_done : out STD_LOGIC;
    pi_cnt_dec_reg : out STD_LOGIC;
    rdlvl_stg1_done_int_reg : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    prbs_rdlvl_done_pulse_reg : out STD_LOGIC;
    calib_complete : out STD_LOGIC;
    calib_cmd_wren : out STD_LOGIC;
    cnt_pwron_cke_done_r : out STD_LOGIC;
    calib_wrdata_en : out STD_LOGIC;
    phy_read_calib : out STD_LOGIC;
    tempmon_pi_f_inc : out STD_LOGIC;
    tempmon_pi_f_dec : out STD_LOGIC;
    idelay_inc : out STD_LOGIC;
    phy_dout : out STD_LOGIC_VECTOR ( 44 downto 0 );
    calib_sel : out STD_LOGIC_VECTOR ( 0 to 0 );
    calib_in_common : out STD_LOGIC;
    init_calib_complete_reg_rep_0 : out STD_LOGIC;
    \init_calib_complete_reg_rep__0_0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__1_0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__2_0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__5_0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__6_0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__8_0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__9_0\ : out STD_LOGIC;
    calib_ctl_wren_reg : out STD_LOGIC;
    \calib_sel_reg[1]_0\ : out STD_LOGIC;
    po_en_s2_c_reg : out STD_LOGIC;
    ck_po_stg2_f_en_reg : out STD_LOGIC;
    ck_po_stg2_f_indec_reg : out STD_LOGIC;
    \calib_sel_reg[1]_1\ : out STD_LOGIC;
    \calib_sel_reg[1]_2\ : out STD_LOGIC;
    \calib_sel_reg[1]_3\ : out STD_LOGIC;
    \calib_sel_reg[1]_4\ : out STD_LOGIC;
    \calib_sel_reg[1]_5\ : out STD_LOGIC;
    \calib_sel_reg[1]_6\ : out STD_LOGIC;
    \calib_sel_reg[1]_7\ : out STD_LOGIC;
    \calib_sel_reg[1]_8\ : out STD_LOGIC;
    idelay_ce_r2_reg_0 : out STD_LOGIC;
    po_en_s2_f_reg : out STD_LOGIC;
    po_en_s2_c_reg_0 : out STD_LOGIC;
    ck_po_stg2_f_indec_reg_0 : out STD_LOGIC;
    \pi_rst_stg1_cal_reg[0]\ : out STD_LOGIC;
    tempmon_pi_f_en_r_reg_0 : out STD_LOGIC;
    tempmon_pi_f_inc_r_reg_0 : out STD_LOGIC;
    pi_stg2_load_reg : out STD_LOGIC;
    \cmd_pipe_plus.mc_cas_n_reg[0]\ : out STD_LOGIC_VECTOR ( 25 downto 0 );
    \calib_zero_ctrl_reg[0]_0\ : out STD_LOGIC;
    \calib_sel_reg[1]_9\ : out STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[117]\ : out STD_LOGIC_VECTOR ( 59 downto 0 );
    init_calib_complete_reg_rep_1 : out STD_LOGIC_VECTOR ( 59 downto 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[3]\ : out STD_LOGIC;
    \my_empty_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[3]_0\ : out STD_LOGIC;
    \my_empty_reg[5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[3]_1\ : out STD_LOGIC;
    app_zq_ns : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_cal1_state_r_reg[13]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    mux_wrdata_en : out STD_LOGIC;
    mux_cmd_wren : out STD_LOGIC;
    LD0 : out STD_LOGIC;
    ififo_rst_reg0 : out STD_LOGIC;
    ofifo_rst_reg0 : out STD_LOGIC;
    LD0_0 : out STD_LOGIC;
    ififo_rst_reg0_1 : out STD_LOGIC;
    ofifo_rst_reg0_2 : out STD_LOGIC;
    D1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[120]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[127]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[124]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[122]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[121]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[123]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \write_buffer.wr_buf_out_data_reg[126]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \init_calib_complete_reg_rep__5_1\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[0]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \cmd_pipe_plus.mc_cas_n_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_cke_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_cas_n_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ : out STD_LOGIC;
    init_dqsfound_done_r_reg : out STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ : out STD_LOGIC;
    COUNTERLOADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_stg2_reg_l_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    calib_sel0 : out STD_LOGIC;
    fine_adjust_done_r_reg : out STD_LOGIC;
    rd_data_offset_cal_done : out STD_LOGIC;
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__4_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_ras_n_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\ : in STD_LOGIC;
    \complex_address_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \lane_cnt_po_r_reg[0]\ : in STD_LOGIC;
    \samp_edge_cnt1_r_reg[0]\ : in STD_LOGIC;
    first_fail_detect_reg : in STD_LOGIC;
    in0 : in STD_LOGIC;
    rdlvl_stg1_start_reg_0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    init_complete_r_timing_reg : in STD_LOGIC;
    p_128_in : in STD_LOGIC;
    \one_inc_min_limit_reg[2]\ : in STD_LOGIC;
    tempmon_sample_en : in STD_LOGIC;
    \init_state_r1_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    tempmon_sel_pi_incdec : in STD_LOGIC;
    wrcal_done_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_pwron_r_reg[0]\ : in STD_LOGIC;
    phy_rddata_en : in STD_LOGIC;
    \calib_sel_reg[1]_10\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_0\ : in STD_LOGIC;
    \calib_zero_ctrl_reg[0]_1\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : in STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC;
    \wrcal_dqs_cnt_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    delay_done_reg : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][1][4]\ : in STD_LOGIC;
    \not_empty_wait_cnt_reg[4]\ : in STD_LOGIC;
    \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : in STD_LOGIC_VECTOR ( 143 downto 0 );
    \wr_ptr_timing_reg[0]\ : in STD_LOGIC;
    \wr_en_inferred__0_i_1\ : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC;
    \wr_en_inferred__0_i_1__0\ : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_1\ : in STD_LOGIC;
    \wr_en_inferred__0_i_1__1\ : in STD_LOGIC;
    app_zq_req : in STD_LOGIC;
    \cnt_idel_dec_cpt_r_reg[0]\ : in STD_LOGIC;
    \cnt_idel_dec_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    store_sr_req_r_reg : in STD_LOGIC;
    \complex_num_writes_reg[4]\ : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_ras_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_odt : in STD_LOGIC_VECTOR ( 0 to 0 );
    mem_reg_0_15_48_53 : in STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    out_fifo : in STD_LOGIC_VECTOR ( 71 downto 0 );
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC_VECTOR ( 71 downto 0 );
    out_fifo_2 : in STD_LOGIC;
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : in STD_LOGIC_VECTOR ( 36 downto 0 );
    mem_out : in STD_LOGIC_VECTOR ( 30 downto 0 );
    out_fifo_3 : in STD_LOGIC;
    mem_reg_0_15_60_65 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_shift_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \device_temp_101_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
    mc_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \phy_ctl_wd_i1_reg[17]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \phy_ctl_wd_i1_reg[20]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[21]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[22]\ : in STD_LOGIC;
    out_fifo_4 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    out_fifo_5 : in STD_LOGIC_VECTOR ( 46 downto 0 );
    out_fifo_6 : in STD_LOGIC;
    pi_dqs_found_lanes : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_calib_top : entity is "mig_7series_v4_2_ddr_calib_top";
end mig_7series_0_mig_7series_v4_2_ddr_calib_top;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_calib_top is
  signal RSTB : STD_LOGIC;
  signal \^calib_complete\ : STD_LOGIC;
  signal \^calib_in_common\ : STD_LOGIC;
  signal \^calib_sel\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal calib_zero_ctrl : STD_LOGIC;
  signal calib_zero_inputs : STD_LOGIC;
  signal ck_po_stg2_f_en : STD_LOGIC;
  signal cmd_po_en_stg2_f : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_11\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_12\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_23\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_29\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_31\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_32\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_8\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9\ : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_2 : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_4 : STD_LOGIC;
  signal detect_pi_found_dqs : STD_LOGIC;
  signal dqs_found_prech_req : STD_LOGIC;
  signal \^dqs_po_dec_done\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_14\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_15\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_20\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_21\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_22\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_23\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_4\ : STD_LOGIC;
  signal \^fine_adjust_done_r_reg\ : STD_LOGIC;
  signal first_rdlvl_pat_r : STD_LOGIC;
  signal first_wrcal_pat_r : STD_LOGIC;
  signal \^gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ : STD_LOGIC;
  signal \^gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ : STD_LOGIC;
  signal idelay_ce : STD_LOGIC;
  signal idelay_ce_int : STD_LOGIC;
  signal idelay_ce_r1 : STD_LOGIC;
  signal idelay_inc_int : STD_LOGIC;
  signal idelay_inc_r1 : STD_LOGIC;
  signal \^init_calib_complete_reg_rep_0\ : STD_LOGIC;
  signal \^init_calib_complete_reg_rep__0_0\ : STD_LOGIC;
  signal \^init_calib_complete_reg_rep__1_0\ : STD_LOGIC;
  signal \^init_calib_complete_reg_rep__2_0\ : STD_LOGIC;
  signal \init_calib_complete_reg_rep__3_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__3_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__3_n_0\ : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \init_calib_complete_reg_rep__3_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__4_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__4_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__4_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__4_n_0\ : signal is "10";
  signal \^init_calib_complete_reg_rep__5_0\ : STD_LOGIC;
  signal \^init_calib_complete_reg_rep__6_0\ : STD_LOGIC;
  signal \init_calib_complete_reg_rep__7_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__7_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__7_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__7_n_0\ : signal is "10";
  signal \^init_calib_complete_reg_rep__8_0\ : STD_LOGIC;
  signal \^init_calib_complete_reg_rep__9_0\ : STD_LOGIC;
  signal init_dqsfound_done_r2 : STD_LOGIC;
  signal \^init_dqsfound_done_r_reg\ : STD_LOGIC;
  signal phy_if_reset : STD_LOGIC;
  signal \phy_if_reset0__0\ : STD_LOGIC;
  signal phy_if_reset_w : STD_LOGIC;
  signal pi_calib_done : STD_LOGIC;
  signal pi_dqs_found_all_bank : STD_LOGIC;
  signal pi_dqs_found_done_r1 : STD_LOGIC;
  signal pi_dqs_found_rank_done : STD_LOGIC;
  signal \^pi_fine_dly_dec_done\ : STD_LOGIC;
  signal \^po_ck_addr_cmd_delay_done\ : STD_LOGIC;
  signal \^po_stg2_wrcal_cnt_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal prbs_rdlvl_done_pulse0 : STD_LOGIC;
  signal prech_done : STD_LOGIC;
  signal rd_active_r : STD_LOGIC;
  signal \rd_byte_data_offset_reg[0]_1\ : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal \^rd_data_offset_cal_done\ : STD_LOGIC;
  signal rd_data_offset_ranks_0 : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal rdlvl_last_byte_done : STD_LOGIC;
  signal rdlvl_pi_incdec : STD_LOGIC;
  signal rdlvl_prech_req : STD_LOGIC;
  signal \^rdlvl_stg1_done_int_reg\ : STD_LOGIC;
  signal rdlvl_stg1_done_r1 : STD_LOGIC;
  signal rdlvl_stg1_rank_done : STD_LOGIC;
  signal \^rdlvl_stg1_start_reg\ : STD_LOGIC;
  signal reset_if : STD_LOGIC;
  signal reset_if_r8_reg_srl8_n_0 : STD_LOGIC;
  signal reset_if_r9 : STD_LOGIC;
  signal stg1_wr_done : STD_LOGIC;
  signal tempmon_pi_f_en_r : STD_LOGIC;
  signal \^tempmon_pi_f_inc\ : STD_LOGIC;
  signal tempmon_pi_f_inc_r : STD_LOGIC;
  signal u_ddr_phy_init_n_12 : STD_LOGIC;
  signal u_ddr_phy_init_n_2 : STD_LOGIC;
  signal u_ddr_phy_init_n_20 : STD_LOGIC;
  signal u_ddr_phy_init_n_273 : STD_LOGIC;
  signal u_ddr_phy_init_n_346 : STD_LOGIC;
  signal u_ddr_phy_init_n_347 : STD_LOGIC;
  signal u_ddr_phy_init_n_348 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_4 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_6 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_9 : STD_LOGIC;
  signal wrcal_prech_req : STD_LOGIC;
  signal wrcal_rd_wait : STD_LOGIC;
  signal wrlvl_byte_redo : STD_LOGIC;
  signal wrlvl_final_if_rst : STD_LOGIC;
  attribute syn_maxfan of \calib_sel_reg[1]\ : label is "10";
  attribute syn_maxfan of \calib_zero_inputs_reg[0]\ : label is "10";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_30\ : label is "soft_lutpair368";
  attribute SOFT_HLUTNM of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_31\ : label is "soft_lutpair368";
  attribute syn_maxfan of \gen_byte_sel_div2.calib_in_common_reg\ : label is "10";
  attribute syn_maxfan of idelay_inc_r2_reg : label is "30";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of init_calib_complete_reg : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of init_calib_complete_reg_rep : label is 1;
  attribute ORIG_CELL_NAME of init_calib_complete_reg_rep : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__0\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__0\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__1\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__1\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__2\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__2\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__3\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__3\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__3\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__3\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__4\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__4\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__4\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__4\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__5\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__5\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__6\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__6\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__7\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__7\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__7\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__7\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__8\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__8\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__9\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__9\ : label is "init_calib_complete_reg";
  attribute SOFT_HLUTNM of \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1\ : label is "soft_lutpair369";
  attribute SOFT_HLUTNM of \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1\ : label is "soft_lutpair369";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2\ : label is "soft_lutpair370";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__0\ : label is "soft_lutpair370";
  attribute srl_name : string;
  attribute srl_name of reset_if_r8_reg_srl8 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r8_reg_srl8 ";
begin
  calib_complete <= \^calib_complete\;
  calib_in_common <= \^calib_in_common\;
  calib_sel(0) <= \^calib_sel\(0);
  dqs_po_dec_done <= \^dqs_po_dec_done\;
  fine_adjust_done_r_reg <= \^fine_adjust_done_r_reg\;
  \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ <= \^gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\;
  \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ <= \^gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\;
  init_calib_complete_reg_rep_0 <= \^init_calib_complete_reg_rep_0\;
  \init_calib_complete_reg_rep__0_0\ <= \^init_calib_complete_reg_rep__0_0\;
  \init_calib_complete_reg_rep__1_0\ <= \^init_calib_complete_reg_rep__1_0\;
  \init_calib_complete_reg_rep__2_0\ <= \^init_calib_complete_reg_rep__2_0\;
  \init_calib_complete_reg_rep__5_0\ <= \^init_calib_complete_reg_rep__5_0\;
  \init_calib_complete_reg_rep__6_0\ <= \^init_calib_complete_reg_rep__6_0\;
  \init_calib_complete_reg_rep__8_0\ <= \^init_calib_complete_reg_rep__8_0\;
  \init_calib_complete_reg_rep__9_0\ <= \^init_calib_complete_reg_rep__9_0\;
  init_dqsfound_done_r_reg <= \^init_dqsfound_done_r_reg\;
  pi_fine_dly_dec_done <= \^pi_fine_dly_dec_done\;
  po_ck_addr_cmd_delay_done <= \^po_ck_addr_cmd_delay_done\;
  \po_stg2_wrcal_cnt_reg[0]\(0) <= \^po_stg2_wrcal_cnt_reg[0]\(0);
  rd_data_offset_cal_done <= \^rd_data_offset_cal_done\;
  rdlvl_stg1_done_int_reg <= \^rdlvl_stg1_done_int_reg\;
  rdlvl_stg1_start_reg <= \^rdlvl_stg1_start_reg\;
  tempmon_pi_f_inc <= \^tempmon_pi_f_inc\;
app_zq_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__9_0\,
      I1 => app_zq_req,
      O => app_zq_ns
    );
\calib_sel_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_sel_reg[1]_10\,
      Q => \^calib_sel\(0),
      R => '0'
    );
\calib_zero_ctrl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_zero_ctrl_reg[0]_1\,
      Q => calib_zero_ctrl,
      R => '0'
    );
\calib_zero_inputs_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => ddr_phy_tempmon_0_n_4,
      Q => calib_zero_inputs,
      S => \cnt_pwron_r_reg[0]\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__4_n_0\,
      I1 => out_fifo_5(15),
      I2 => out_fifo_6,
      O => \init_calib_complete_reg_rep__4_0\(3)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_4(8),
      I1 => \init_calib_complete_reg_rep__4_n_0\,
      I2 => out_fifo_5(14),
      I3 => out_fifo_6,
      O => \init_calib_complete_reg_rep__4_0\(2)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_4(5),
      I1 => \init_calib_complete_reg_rep__4_n_0\,
      I2 => out_fifo_5(13),
      I3 => out_fifo_6,
      O => \init_calib_complete_reg_rep__4_0\(1)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => out_fifo_4(2),
      I1 => \init_calib_complete_reg_rep__4_n_0\,
      I2 => out_fifo_5(12),
      I3 => out_fifo_6,
      O => \init_calib_complete_reg_rep__4_0\(0)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_ras_n(2),
      I1 => \init_calib_complete_reg_rep__4_n_0\,
      I2 => out_fifo_5(18),
      I3 => out_fifo_6,
      O => \cmd_pipe_plus.mc_ras_n_reg[2]\(2)
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_ras_n(1),
      I1 => \init_calib_complete_reg_rep__4_n_0\,
      I2 => out_fifo_5(17),
      I3 => out_fifo_6,
      O => \cmd_pipe_plus.mc_ras_n_reg[2]\(1)
    );
\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl\: entity work.mig_7series_0_mig_7series_v4_2_ddr_phy_rdlvl
     port map (
      CLK => CLK,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      D(4) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_8\,
      D(3) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9\,
      D(2) => \^rdlvl_stg1_done_int_reg\,
      D(1) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_11\,
      D(0) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_12\,
      E(0) => rd_active_r,
      \FSM_onehot_cal1_state_r_reg[7]_0\ => \lane_cnt_po_r_reg[0]\,
      Q(0) => \FSM_onehot_cal1_state_r_reg[13]\(0),
      RSTB => RSTB,
      SS(0) => SS(0),
      \cal1_cnt_cpt_r_reg[0]_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25\,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]_6\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_7\,
      \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_8\,
      calib_zero_inputs => calib_zero_inputs,
      \cnt_idel_dec_cpt_r_reg[0]_0\ => \cnt_idel_dec_cpt_r_reg[0]\,
      \cnt_idel_dec_cpt_r_reg[5]_0\(5 downto 0) => \cnt_idel_dec_cpt_r_reg[5]\(5 downto 0),
      \cnt_shift_r_reg[0]_0\(0) => \cnt_shift_r_reg[0]\(0),
      \done_cnt_reg[2]_0\ => \idelay_tap_cnt_r_reg[0][1][4]\,
      dqs_po_dec_done_r1_reg_0 => \^dqs_po_dec_done\,
      first_rdlvl_pat_r => first_rdlvl_pat_r,
      first_wrcal_pat_r => first_wrcal_pat_r,
      found_second_edge_r_reg_0 => first_fail_detect_reg,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ => \^init_dqsfound_done_r_reg\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ => \^gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ => \^gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[1]_1\ => ddr_phy_tempmon_0_n_2,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      idelay_ce_int => idelay_ce_int,
      idelay_inc_int => idelay_inc_int,
      \idelay_tap_cnt_r_reg[0][0][0]_0\ => u_ddr_phy_wrcal_n_6,
      \idelay_tap_cnt_r_reg[0][0][0]_1\(0) => \^po_stg2_wrcal_cnt_reg[0]\(0),
      \idelay_tap_cnt_r_reg[0][1][4]_0\(0) => u_ddr_phy_wrcal_n_4,
      \init_state_r[3]_i_13\ => u_ddr_phy_init_n_12,
      \init_state_r[6]_i_19\ => \^po_ck_addr_cmd_delay_done\,
      mpr_rdlvl_start_r_reg_0 => u_ddr_phy_init_n_348,
      new_cnt_cpt_r_reg_0 => new_cnt_cpt_r_reg,
      pi_cnt_dec_reg_0 => pi_cnt_dec_reg,
      pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_4\,
      \pi_dqs_found_lanes_r1_reg[2]\ => \^calib_sel\(0),
      \pi_dqs_found_lanes_r1_reg[2]_0\ => \^calib_in_common\,
      pi_fine_dly_dec_done => \^pi_fine_dly_dec_done\,
      pi_fine_dly_dec_done_reg_0 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_23\,
      pi_stg2_load_reg_0 => pi_stg2_load_reg,
      \pi_stg2_reg_l_reg[5]_0\(5 downto 0) => \pi_stg2_reg_l_reg[5]\(5 downto 0),
      prbs_rdlvl_done_pulse0 => prbs_rdlvl_done_pulse0,
      prech_done => prech_done,
      \rd_mux_sel_r_reg[0]_0\ => \rd_mux_sel_r_reg[0]\,
      \rdlvl_dqs_tap_cnt_r_reg[0][0][5]_0\(1 downto 0) => \complex_address_reg[9]\(1 downto 0),
      rdlvl_last_byte_done => rdlvl_last_byte_done,
      rdlvl_last_byte_done_int_reg_0 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_29\,
      rdlvl_pi_incdec => rdlvl_pi_incdec,
      rdlvl_prech_req => rdlvl_prech_req,
      rdlvl_stg1_done_int_reg_0 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27\,
      rdlvl_stg1_done_int_reg_1(0) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28\,
      rdlvl_stg1_done_r1 => rdlvl_stg1_done_r1,
      rdlvl_stg1_rank_done => rdlvl_stg1_rank_done,
      rdlvl_stg1_start_r_reg_0 => \^rdlvl_stg1_start_reg\,
      reset_if => reset_if,
      reset_if_r9 => reset_if_r9,
      reset_if_reg => \not_empty_wait_cnt_reg[4]\,
      \rstdiv0_sync_r1_reg_rep__13\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_31\,
      \rstdiv0_sync_r1_reg_rep__14\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22\,
      \rstdiv0_sync_r1_reg_rep__14_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_32\,
      samp_edge_cnt0_en_r => samp_edge_cnt0_en_r,
      \samp_edge_cnt1_r_reg[0]_0\ => \samp_edge_cnt1_r_reg[0]\,
      stg1_wr_done => stg1_wr_done,
      store_sr_req_r_reg_0 => store_sr_req_r_reg,
      \tap_cnt_cpt_r_reg[5]_0\(0) => \tap_cnt_cpt_r_reg[5]\(0),
      tempmon_pi_f_en_r => tempmon_pi_f_en_r,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg_0,
      tempmon_pi_f_inc_r => tempmon_pi_f_inc_r,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg_0,
      \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]\ => u_ddr_phy_wrcal_n_9
    );
ddr_phy_tempmon_0: entity work.mig_7series_0_mig_7series_v4_2_ddr_phy_tempmon
     port map (
      CLK => CLK,
      D(0) => \^rdlvl_stg1_done_int_reg\,
      SR(0) => SR(0),
      calib_sel0 => calib_sel0,
      \calib_zero_ctrl_reg[0]\ => \not_empty_wait_cnt_reg[4]\,
      \calib_zero_inputs_reg[0]\ => \^calib_complete\,
      \device_temp_101_reg[11]_0\(11 downto 0) => \device_temp_101_reg[11]\(11 downto 0),
      \four_dec_min_limit_reg[11]_0\(0) => \complex_address_reg[9]\(0),
      \four_inc_max_limit_reg[11]_0\(0) => \init_state_r1_reg[0]\(0),
      \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ => \^po_ck_addr_cmd_delay_done\,
      init_calib_complete_reg => ddr_phy_tempmon_0_n_4,
      \one_inc_min_limit_reg[2]_0\ => \one_inc_min_limit_reg[2]\,
      pi_f_dec_reg_0 => tempmon_pi_f_dec,
      pi_f_dec_reg_1 => ddr_phy_tempmon_0_n_2,
      pi_f_inc_reg_0 => \^tempmon_pi_f_inc\,
      pi_fine_dly_dec_done => \^pi_fine_dly_dec_done\,
      tempmon_sample_en => tempmon_sample_en,
      \three_dec_max_limit_reg[11]_0\ => rdlvl_stg1_start_reg_0,
      \two_inc_max_limit_reg[2]_0\ => init_complete_r_timing_reg
    );
\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr\: entity work.mig_7series_0_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr
     port map (
      A_rst_primitives => A_rst_primitives,
      CLK => CLK,
      D(0) => \^rdlvl_stg1_done_int_reg\,
      Q(0) => u_ddr_phy_init_n_20,
      SR(0) => SR(0),
      \calib_sel_reg[1]\ => \calib_sel_reg[1]_4\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_5\,
      calib_zero_ctrl => calib_zero_ctrl,
      calib_zero_inputs => calib_zero_inputs,
      ck_po_stg2_f_en => ck_po_stg2_f_en,
      ck_po_stg2_f_en_reg_0 => ck_po_stg2_f_en_reg,
      ck_po_stg2_f_indec_reg_0 => ck_po_stg2_f_indec_reg,
      ck_po_stg2_f_indec_reg_1 => ck_po_stg2_f_indec_reg_0,
      ck_po_stg2_f_indec_reg_2(0) => wrcal_done_reg(0),
      detect_pi_found_dqs => detect_pi_found_dqs,
      dqs_found_done_r_reg_0 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_14\,
      dqs_found_done_r_reg_1 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_23\,
      dqs_found_prech_req => dqs_found_prech_req,
      dqs_found_start_r_reg_0 => u_ddr_phy_init_n_347,
      fine_adjust_done_r_reg_0 => \^fine_adjust_done_r_reg\,
      first_fail_detect_reg_0 => first_fail_detect_reg,
      ififo_rst_reg0 => ififo_rst_reg0,
      ififo_rst_reg0_1 => ififo_rst_reg0_1,
      init_dqsfound_done_r2 => init_dqsfound_done_r2,
      init_dqsfound_done_r_reg_0 => \^rd_data_offset_cal_done\,
      init_dqsfound_done_r_reg_1 => \cnt_pwron_r_reg[0]\,
      \init_state_r[1]_i_14\ => u_ddr_phy_init_n_2,
      ofifo_rst_reg => \^calib_in_common\,
      ofifo_rst_reg0 => ofifo_rst_reg0,
      ofifo_rst_reg0_2 => ofifo_rst_reg0_2,
      ofifo_rst_reg_0 => \^calib_sel\(0),
      phy_if_reset => phy_if_reset,
      pi_dqs_found_all_bank => pi_dqs_found_all_bank,
      pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_4\,
      pi_dqs_found_done_r1 => pi_dqs_found_done_r1,
      pi_dqs_found_done_r1_reg => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_15\,
      pi_dqs_found_done_r1_reg_0 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_20\,
      pi_dqs_found_done_r1_reg_1 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_21\,
      pi_dqs_found_done_r1_reg_2 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_22\,
      pi_dqs_found_lanes(1 downto 0) => pi_dqs_found_lanes(1 downto 0),
      pi_dqs_found_rank_done => pi_dqs_found_rank_done,
      \pi_rst_stg1_cal_r1_reg[0]_0\ => \idelay_tap_cnt_r_reg[0][1][4]\,
      \pi_rst_stg1_cal_reg[0]_0\ => \pi_rst_stg1_cal_reg[0]\,
      po_en_s2_f => cmd_po_en_stg2_f,
      prech_done => prech_done,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(5 downto 0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5 downto 0),
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2]_0\(1 downto 0) => rd_data_offset_ranks_0(2 downto 1),
      \rd_byte_data_offset_reg[0][2]_0\(1 downto 0) => \rd_byte_data_offset_reg[0]_1\(2 downto 1),
      \stable_pass_cnt_reg[4]_0\ => u_ddr_phy_init_n_273
    );
\gen_byte_sel_div2.byte_sel_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_31\,
      Q => \^gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\,
      R => '0'
    );
\gen_byte_sel_div2.byte_sel_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30\,
      Q => \^gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\,
      R => '0'
    );
\gen_byte_sel_div2.calib_in_common_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_byte_sel_div2.calib_in_common_reg_0\,
      Q => \^calib_in_common\,
      R => \lane_cnt_po_r_reg[0]\
    );
idelay_ce_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_ce_int,
      Q => idelay_ce_r1,
      R => wrcal_done_reg(0)
    );
idelay_ce_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_ce_r1,
      Q => idelay_ce,
      R => \lane_cnt_po_r_reg[0]\
    );
idelay_inc_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_inc_int,
      Q => idelay_inc_r1,
      R => wrcal_done_reg(0)
    );
idelay_inc_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_inc_r1,
      Q => idelay_inc,
      R => \lane_cnt_po_r_reg[0]\
    );
init_calib_complete_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_complete\,
      Q => phy_dout(15),
      R => '0'
    );
init_calib_complete_reg_rep: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_complete\,
      Q => \^init_calib_complete_reg_rep_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__0\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_complete\,
      Q => \^init_calib_complete_reg_rep__0_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__1\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_complete\,
      Q => \^init_calib_complete_reg_rep__1_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__2\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_complete\,
      Q => \^init_calib_complete_reg_rep__2_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__3\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_complete\,
      Q => \init_calib_complete_reg_rep__3_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__4\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_complete\,
      Q => \init_calib_complete_reg_rep__4_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__5\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_complete\,
      Q => \^init_calib_complete_reg_rep__5_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__6\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_complete\,
      Q => \^init_calib_complete_reg_rep__6_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__7\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_complete\,
      Q => \init_calib_complete_reg_rep__7_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__8\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_complete\,
      Q => \^init_calib_complete_reg_rep__8_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__9\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_complete\,
      Q => \^init_calib_complete_reg_rep__9_0\,
      R => '0'
    );
\input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => idelay_ce,
      I1 => \^calib_sel\(0),
      I2 => \^calib_in_common\,
      I3 => calib_zero_inputs,
      O => idelay_ce_r2_reg_0
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C4"
    )
        port map (
      I0 => \^calib_sel\(0),
      I1 => idelay_ce,
      I2 => \^calib_in_common\,
      I3 => calib_zero_inputs,
      O => \calib_sel_reg[1]_1\
    );
\mb_wrlvl_off.u_phy_wrlvl_off_delay\: entity work.mig_7series_0_mig_7series_v4_2_ddr_phy_wrlvl_off_delay
     port map (
      CLK => CLK,
      Q(0) => Q(0),
      RSTB => RSTB,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]_2\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_3\,
      calib_zero_ctrl => calib_zero_ctrl,
      calib_zero_inputs => calib_zero_inputs,
      ck_po_stg2_f_en => ck_po_stg2_f_en,
      delay_done_r4_reg_0 => \^po_ck_addr_cmd_delay_done\,
      delay_done_reg_0 => delay_done_reg,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ => \^fine_adjust_done_r_reg\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ => \not_empty_wait_cnt_reg[4]\,
      init_dqsfound_done_r_reg => \^init_dqsfound_done_r_reg\,
      \lane_cnt_po_r_reg[0]_0\ => \lane_cnt_po_r_reg[0]\,
      phaser_out => \^calib_in_common\,
      phaser_out_0 => \^calib_sel\(0),
      pi_calib_done => pi_calib_done,
      pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_4\,
      pi_fine_dly_dec_done => \^pi_fine_dly_dec_done\,
      po_delay_done_r4_reg_0 => \^dqs_po_dec_done\,
      po_en_s2_c_reg_0 => po_en_s2_c_reg,
      po_en_s2_c_reg_1 => po_en_s2_c_reg_0,
      po_en_s2_f => cmd_po_en_stg2_f,
      po_en_s2_f_reg_0 => po_en_s2_f_reg,
      po_en_stg2_f_reg_0 => \idelay_tap_cnt_r_reg[0][1][4]\,
      rd_data_offset_cal_done => \^rd_data_offset_cal_done\
    );
mem_reg_0_15_0_5_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__0_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(77),
      O => init_calib_complete_reg_rep_1(3)
    );
\mem_reg_0_15_12_17_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(120),
      O => init_calib_complete_reg_rep_1(13)
    );
mem_reg_0_15_12_17_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__1_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(31),
      O => init_calib_complete_reg_rep_1(14)
    );
\mem_reg_0_15_12_17_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(130),
      O => \write_buffer.wr_buf_out_data_reg[117]\(7)
    );
\mem_reg_0_15_12_17_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(128),
      O => \write_buffer.wr_buf_out_data_reg[117]\(6)
    );
\mem_reg_0_15_18_23_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(134),
      O => \write_buffer.wr_buf_out_data_reg[117]\(9)
    );
\mem_reg_0_15_18_23_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(132),
      O => \write_buffer.wr_buf_out_data_reg[117]\(8)
    );
\mem_reg_0_15_18_23_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(138),
      O => \write_buffer.wr_buf_out_data_reg[117]\(11)
    );
\mem_reg_0_15_18_23_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(136),
      O => \write_buffer.wr_buf_out_data_reg[117]\(10)
    );
\mem_reg_0_15_18_23_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(142),
      O => \write_buffer.wr_buf_out_data_reg[117]\(13)
    );
\mem_reg_0_15_18_23_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(140),
      O => \write_buffer.wr_buf_out_data_reg[117]\(12)
    );
\mem_reg_0_15_24_29_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__2_0\,
      I1 => out_fifo_4(5),
      O => phy_dout(13)
    );
\mem_reg_0_15_24_29_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__2_0\,
      I1 => out_fifo_4(2),
      O => phy_dout(12)
    );
mem_reg_0_15_24_29_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__2_0\,
      I1 => out_fifo_4(8),
      O => phy_dout(14)
    );
\mem_reg_0_15_30_35_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(112),
      O => \write_buffer.wr_buf_out_data_reg[117]\(20)
    );
mem_reg_0_15_30_35_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__1_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(22),
      O => \write_buffer.wr_buf_out_data_reg[117]\(22)
    );
\mem_reg_0_15_36_41_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(124),
      O => init_calib_complete_reg_rep_1(26)
    );
mem_reg_0_15_36_41_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__1_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(19),
      O => \write_buffer.wr_buf_out_data_reg[117]\(27)
    );
\mem_reg_0_15_36_41_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__1_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(26),
      O => init_calib_complete_reg_rep_1(28)
    );
\mem_reg_0_15_48_53_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__0_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(65),
      O => \write_buffer.wr_buf_out_data_reg[117]\(36)
    );
\mem_reg_0_15_48_53_i_6__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__0_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(73),
      O => init_calib_complete_reg_rep_1(36)
    );
\mem_reg_0_15_54_59_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__1_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(27),
      O => init_calib_complete_reg_rep_1(40)
    );
mem_reg_0_15_60_65_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(116),
      O => \write_buffer.wr_buf_out_data_reg[117]\(46)
    );
mem_reg_0_15_60_65_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__1_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(23),
      O => \write_buffer.wr_buf_out_data_reg[117]\(47)
    );
\mem_reg_0_15_60_65_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__1_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(30),
      O => init_calib_complete_reg_rep_1(47)
    );
\mem_reg_0_15_6_11_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__2_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(18),
      O => \write_buffer.wr_buf_out_data_reg[117]\(1)
    );
\mem_reg_0_15_72_77_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(131),
      O => init_calib_complete_reg_rep_1(53)
    );
\mem_reg_0_15_72_77_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(129),
      O => init_calib_complete_reg_rep_1(52)
    );
\mem_reg_0_15_72_77_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(135),
      O => init_calib_complete_reg_rep_1(55)
    );
\mem_reg_0_15_72_77_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(133),
      O => init_calib_complete_reg_rep_1(54)
    );
\mem_reg_0_15_72_77_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(139),
      O => init_calib_complete_reg_rep_1(57)
    );
mem_reg_0_15_72_77_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__0_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(69),
      O => \write_buffer.wr_buf_out_data_reg[117]\(56)
    );
\mem_reg_0_15_72_77_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(137),
      O => init_calib_complete_reg_rep_1(56)
    );
\mem_reg_0_15_78_79_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(143),
      O => init_calib_complete_reg_rep_1(59)
    );
\mem_reg_0_15_78_79_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(141),
      O => init_calib_complete_reg_rep_1(58)
    );
\out_fifo_i_10__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(120),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo_1(15),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[120]\(7)
    );
out_fifo_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(66),
      I1 => \^init_calib_complete_reg_rep__8_0\,
      I2 => out_fifo(4),
      I3 => out_fifo_0,
      O => D1(4)
    );
out_fifo_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(50),
      I1 => \^init_calib_complete_reg_rep__8_0\,
      I2 => out_fifo(3),
      I3 => out_fifo_0,
      O => D1(3)
    );
out_fifo_i_16: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(18),
      I1 => \^init_calib_complete_reg_rep__8_0\,
      I2 => out_fifo(1),
      I3 => out_fifo_0,
      O => D1(1)
    );
\out_fifo_i_17__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(8),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo_1(8),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[120]\(0)
    );
out_fifo_i_18: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__8_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(142),
      I2 => out_fifo(15),
      I3 => out_fifo_0,
      O => D2(7)
    );
out_fifo_i_19: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__8_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(140),
      I2 => out_fifo(14),
      I3 => out_fifo_0,
      O => D2(6)
    );
out_fifo_i_20: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__8_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(138),
      I2 => out_fifo(13),
      I3 => out_fifo_0,
      O => D2(5)
    );
\out_fifo_i_20__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(95),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo_1(21),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[127]\(5)
    );
out_fifo_i_21: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__8_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(136),
      I2 => out_fifo(12),
      I3 => out_fifo_0,
      O => D2(4)
    );
out_fifo_i_22: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__8_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(134),
      I2 => out_fifo(11),
      I3 => out_fifo_0,
      O => D2(3)
    );
out_fifo_i_23: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__8_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(132),
      I2 => out_fifo(10),
      I3 => out_fifo_0,
      O => D2(2)
    );
out_fifo_i_24: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__8_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(130),
      I2 => out_fifo(9),
      I3 => out_fifo_0,
      O => D2(1)
    );
\out_fifo_i_24__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(31),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo_1(17),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[127]\(1)
    );
out_fifo_i_25: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__8_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(128),
      I2 => out_fifo(8),
      I3 => out_fifo_0,
      O => D2(0)
    );
\out_fifo_i_25__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(15),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo_1(16),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[127]\(0)
    );
out_fifo_i_26: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(112),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(23),
      I3 => out_fifo_0,
      O => D3(7)
    );
out_fifo_i_33: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(0),
      I1 => \^init_calib_complete_reg_rep__8_0\,
      I2 => out_fifo(16),
      I3 => out_fifo_0,
      O => D3(0)
    );
\out_fifo_i_34__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(124),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo_1(31),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[124]\(7)
    );
out_fifo_i_37: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(70),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(28),
      I3 => out_fifo_0,
      O => D4(4)
    );
out_fifo_i_38: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(54),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(27),
      I3 => out_fifo_0,
      O => D4(3)
    );
out_fifo_i_40: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(22),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(25),
      I3 => out_fifo_0,
      O => D4(1)
    );
\out_fifo_i_41__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(12),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo_1(24),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[124]\(0)
    );
out_fifo_i_44: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(83),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(37),
      I3 => out_fifo_0,
      O => D5(5)
    );
\out_fifo_i_45__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(74),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo_1(36),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[122]\(4)
    );
\out_fifo_i_46__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(58),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo_1(35),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[122]\(3)
    );
out_fifo_i_48: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(19),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(33),
      I3 => out_fifo_0,
      O => D5(1)
    );
\out_fifo_i_48__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(26),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo_1(33),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[122]\(1)
    );
out_fifo_i_49: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(3),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(32),
      I3 => out_fifo_0,
      O => D5(0)
    );
out_fifo_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(77),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo_1(4),
      I3 => out_fifo_2,
      O => D0(4)
    );
out_fifo_i_53: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(65),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(44),
      I3 => out_fifo_0,
      O => D6(4)
    );
\out_fifo_i_53__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(73),
      I1 => \^init_calib_complete_reg_rep__5_0\,
      I2 => out_fifo_1(44),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[121]\(4)
    );
out_fifo_i_55: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(33),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(42),
      I3 => out_fifo_0,
      O => D6(2)
    );
\out_fifo_i_55__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(41),
      I1 => \^init_calib_complete_reg_rep__5_0\,
      I2 => out_fifo_1(42),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[121]\(2)
    );
out_fifo_i_58: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(116),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(55),
      I3 => out_fifo_0,
      O => D7(7)
    );
\out_fifo_i_60__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(91),
      I1 => \^init_calib_complete_reg_rep__5_0\,
      I2 => out_fifo_1(53),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[123]\(5)
    );
\out_fifo_i_64__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(27),
      I1 => \^init_calib_complete_reg_rep__5_0\,
      I2 => out_fifo_1(49),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[123]\(1)
    );
out_fifo_i_65: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(4),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(48),
      I3 => out_fifo_0,
      O => D7(0)
    );
\out_fifo_i_65__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(11),
      I1 => \^init_calib_complete_reg_rep__5_0\,
      I2 => out_fifo_1(48),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[123]\(0)
    );
out_fifo_i_68: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(87),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(61),
      I3 => out_fifo_0,
      O => D8(5)
    );
\out_fifo_i_69__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(78),
      I1 => \^init_calib_complete_reg_rep__5_0\,
      I2 => out_fifo_1(60),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[126]\(4)
    );
out_fifo_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(45),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo_1(2),
      I3 => out_fifo_2,
      O => D0(2)
    );
\out_fifo_i_70__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(62),
      I1 => \^init_calib_complete_reg_rep__5_0\,
      I2 => out_fifo_1(59),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[126]\(3)
    );
out_fifo_i_72: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(23),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(57),
      I3 => out_fifo_0,
      O => D8(1)
    );
\out_fifo_i_72__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(30),
      I1 => \^init_calib_complete_reg_rep__5_0\,
      I2 => out_fifo_1(57),
      I3 => out_fifo_2,
      O => \write_buffer.wr_buf_out_data_reg[126]\(1)
    );
out_fifo_i_73: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(7),
      I1 => \init_calib_complete_reg_rep__7_n_0\,
      I2 => out_fifo(56),
      I3 => out_fifo_0,
      O => D8(0)
    );
\out_fifo_i_74__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__5_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(143),
      I2 => out_fifo_1(71),
      I3 => out_fifo_2,
      O => \init_calib_complete_reg_rep__5_1\(7)
    );
\out_fifo_i_75__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__5_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(141),
      I2 => out_fifo_1(70),
      I3 => out_fifo_2,
      O => \init_calib_complete_reg_rep__5_1\(6)
    );
\out_fifo_i_76__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__5_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(139),
      I2 => out_fifo_1(69),
      I3 => out_fifo_2,
      O => \init_calib_complete_reg_rep__5_1\(5)
    );
out_fifo_i_77: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(69),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo(68),
      I3 => out_fifo_0,
      O => D9(4)
    );
\out_fifo_i_77__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__5_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(137),
      I2 => out_fifo_1(68),
      I3 => out_fifo_2,
      O => \init_calib_complete_reg_rep__5_1\(4)
    );
\out_fifo_i_78__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__5_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(135),
      I2 => out_fifo_1(67),
      I3 => out_fifo_2,
      O => \init_calib_complete_reg_rep__5_1\(3)
    );
out_fifo_i_79: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(37),
      I1 => \^init_calib_complete_reg_rep__6_0\,
      I2 => out_fifo(66),
      I3 => out_fifo_0,
      O => D9(2)
    );
\out_fifo_i_79__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__5_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(133),
      I2 => out_fifo_1(66),
      I3 => out_fifo_2,
      O => \init_calib_complete_reg_rep__5_1\(2)
    );
\out_fifo_i_80__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__5_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(131),
      I2 => out_fifo_1(65),
      I3 => out_fifo_2,
      O => \init_calib_complete_reg_rep__5_1\(1)
    );
\out_fifo_i_81__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \^init_calib_complete_reg_rep__5_0\,
      I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(129),
      I2 => out_fifo_1(64),
      I3 => out_fifo_2,
      O => \init_calib_complete_reg_rep__5_1\(0)
    );
\phaser_in_gen.phaser_in_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \^calib_sel\(0),
      I1 => \^calib_in_common\,
      I2 => calib_zero_inputs,
      O => \calib_sel_reg[1]_0\
    );
\phaser_in_gen.phaser_in_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^calib_sel\(0),
      I1 => \^calib_in_common\,
      I2 => calib_zero_inputs,
      O => \calib_sel_reg[1]_9\
    );
\phaser_out_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => calib_zero_ctrl,
      I1 => \^calib_in_common\,
      I2 => calib_zero_inputs,
      O => \calib_zero_ctrl_reg[0]_0\
    );
phy_if_reset0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => phy_if_reset_w,
      I1 => reset_if,
      I2 => wrlvl_final_if_rst,
      O => \phy_if_reset0__0\
    );
phy_if_reset_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \phy_if_reset0__0\,
      Q => phy_if_reset,
      R => '0'
    );
reset_if_r8_reg_srl8: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => reset_if,
      Q => reset_if_r8_reg_srl8_n_0
    );
reset_if_r9_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => reset_if_r8_reg_srl8_n_0,
      Q => reset_if_r9,
      R => '0'
    );
reset_if_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_32\,
      Q => reset_if,
      R => '0'
    );
tempmon_pi_f_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tempmon_sel_pi_incdec,
      Q => tempmon_pi_f_en_r,
      R => \lane_cnt_po_r_reg[0]\
    );
tempmon_pi_f_inc_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^tempmon_pi_f_inc\,
      Q => tempmon_pi_f_inc_r,
      R => wrcal_done_reg(0)
    );
u_ddr_phy_init: entity work.mig_7series_0_mig_7series_v4_2_ddr_phy_init
     port map (
      CLK => CLK,
      D(4) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_8\,
      D(3) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9\,
      D(2) => \^rdlvl_stg1_done_int_reg\,
      D(1) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_11\,
      D(0) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_12\,
      D0(5 downto 3) => D0(7 downto 5),
      D0(2) => D0(3),
      D0(1 downto 0) => D0(1 downto 0),
      D1(4 downto 2) => D1(7 downto 5),
      D1(1) => D1(2),
      D1(0) => D1(0),
      D3(5 downto 0) => D3(6 downto 1),
      D4(4 downto 2) => D4(7 downto 5),
      D4(1) => D4(2),
      D4(0) => D4(0),
      D5(4 downto 3) => D5(7 downto 6),
      D5(2 downto 0) => D5(4 downto 2),
      D6(5 downto 3) => D6(7 downto 5),
      D6(2) => D6(3),
      D6(1 downto 0) => D6(1 downto 0),
      D7(5 downto 0) => D7(6 downto 1),
      D8(4 downto 3) => D8(7 downto 6),
      D8(2 downto 0) => D8(4 downto 2),
      D9(5 downto 3) => D9(7 downto 5),
      D9(2) => D9(3),
      D9(1 downto 0) => D9(1 downto 0),
      E(0) => E(0),
      Q(0) => u_ddr_phy_init_n_20,
      SR(0) => SR(0),
      \back_to_back_reads_4_1.num_reads_reg[1]_0\ => \idelay_tap_cnt_r_reg[0][1][4]\,
      burst_addr_r_reg_0 => u_ddr_phy_wrcal_n_9,
      calib_ctl_wren_reg_0 => calib_cmd_wren,
      calib_ctl_wren_reg_1 => calib_ctl_wren_reg,
      \calib_data_offset_0_reg[0]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_22\,
      \calib_data_offset_0_reg[2]_0\(1 downto 0) => rd_data_offset_ranks_0(2 downto 1),
      \calib_data_offset_0_reg[2]_1\(1 downto 0) => \rd_byte_data_offset_reg[0]_1\(2 downto 1),
      \calib_data_offset_0_reg[3]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_21\,
      \calib_data_offset_0_reg[4]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_20\,
      \calib_data_offset_0_reg[5]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_15\,
      \calib_seq_reg[1]_0\(10 downto 0) => D(10 downto 0),
      calib_wrdata_en => calib_wrdata_en,
      \cmd_pipe_plus.mc_cas_n_reg[0]\(25 downto 0) => \cmd_pipe_plus.mc_cas_n_reg[0]\(25 downto 0),
      \cmd_pipe_plus.mc_cas_n_reg[0]_0\(0) => \cmd_pipe_plus.mc_cas_n_reg[0]_0\(0),
      \cmd_pipe_plus.mc_cas_n_reg[0]_1\(0) => \cmd_pipe_plus.mc_cas_n_reg[0]_1\(0),
      \cmd_pipe_plus.mc_cke_reg[3]\(3 downto 0) => \cmd_pipe_plus.mc_cke_reg[3]\(3 downto 0),
      \cmd_pipe_plus.mc_ras_n_reg[0]\(0) => \cmd_pipe_plus.mc_ras_n_reg[2]\(0),
      \cmd_pipe_plus.mc_we_n_reg[0]\(4 downto 0) => \cmd_pipe_plus.mc_we_n_reg[0]\(4 downto 0),
      cnt_pwron_cke_done_r_reg_0 => cnt_pwron_cke_done_r,
      cnt_pwron_cke_done_r_reg_1(0) => Q(0),
      \cnt_pwron_r_reg[0]_0\ => \cnt_pwron_r_reg[0]\,
      \complex_address_reg[9]_0\(1 downto 0) => \complex_address_reg[9]\(1 downto 0),
      \complex_num_writes_reg[4]_0\ => \complex_num_writes_reg[4]\,
      \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ => \^init_calib_complete_reg_rep__1_0\,
      \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ => \^init_calib_complete_reg_rep__2_0\,
      \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(36 downto 0) => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(36 downto 0),
      \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(5 downto 4) => out_fifo_4(7 downto 6),
      \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(3 downto 2) => out_fifo_4(4 downto 3),
      \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\(1 downto 0) => out_fifo_4(1 downto 0),
      \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ => \^init_calib_complete_reg_rep__0_0\,
      detect_pi_found_dqs => detect_pi_found_dqs,
      detect_pi_found_dqs_reg_0 => u_ddr_phy_init_n_273,
      dqs_found_prech_req => dqs_found_prech_req,
      first_rdlvl_pat_r => first_rdlvl_pat_r,
      first_wrcal_pat_r => first_wrcal_pat_r,
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(7 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\(7 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[11]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[11]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(7 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]\(7 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(7 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\(7 downto 0),
      in0 => in0,
      init_calib_complete_reg_0 => \^calib_complete\,
      init_complete_r_timing_reg_0 => init_complete_r_timing_reg,
      init_dqsfound_done_r2 => init_dqsfound_done_r2,
      \init_state_r1_reg[0]_0\(0) => \init_state_r1_reg[0]\(0),
      \init_state_r[2]_i_11_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27\,
      \init_state_r[2]_i_2_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_14\,
      \init_state_r[6]_i_9_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_23\,
      \init_state_r_reg[1]_i_7_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_23\,
      \init_state_r_reg[3]_i_10_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_29\,
      mc_cas_n(0) => mc_cas_n(0),
      mc_cmd(1 downto 0) => mc_cmd(1 downto 0),
      mc_odt(0) => mc_odt(0),
      mc_ras_n(0) => mc_ras_n(0),
      mc_wrdata_en => mc_wrdata_en,
      mem_out(30 downto 0) => mem_out(30 downto 0),
      mem_reg_0_15_48_53(0) => mem_reg_0_15_48_53(0),
      mem_reg_0_15_60_65(1 downto 0) => mem_reg_0_15_60_65(1 downto 0),
      mpr_rdlvl_start_reg_0 => u_ddr_phy_init_n_348,
      mux_cmd_wren => mux_cmd_wren,
      mux_wrdata_en => mux_wrdata_en,
      \my_empty_reg[3]\ => \my_empty_reg[3]\,
      \my_empty_reg[3]_0\ => \my_empty_reg[3]_0\,
      \my_empty_reg[3]_1\ => \my_empty_reg[3]_1\,
      \my_empty_reg[5]\(0) => \my_empty_reg[5]\(0),
      \my_empty_reg[5]_0\(0) => \my_empty_reg[5]_0\(0),
      \one_rank.stg1_wr_done_reg_0\ => u_ddr_phy_init_n_12,
      \out\ => \out\,
      out_fifo(87 downto 85) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(127 downto 125),
      out_fifo(84 downto 82) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(123 downto 121),
      out_fifo(81 downto 79) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(119 downto 117),
      out_fifo(78 downto 76) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(115 downto 113),
      out_fifo(75 downto 60) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(111 downto 96),
      out_fifo(59 downto 57) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(94 downto 92),
      out_fifo(56 downto 54) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(90 downto 88),
      out_fifo(53 downto 51) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(86 downto 84),
      out_fifo(50 downto 47) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(82 downto 79),
      out_fifo(46 downto 45) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(76 downto 75),
      out_fifo(44 downto 43) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(72 downto 71),
      out_fifo(42 downto 41) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(68 downto 67),
      out_fifo(40 downto 39) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(64 downto 63),
      out_fifo(38 downto 36) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(61 downto 59),
      out_fifo(35 downto 33) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(57 downto 55),
      out_fifo(32 downto 30) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(53 downto 51),
      out_fifo(29 downto 26) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(49 downto 46),
      out_fifo(25 downto 23) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(44 downto 42),
      out_fifo(22 downto 20) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(40 downto 38),
      out_fifo(19 downto 17) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(36 downto 34),
      out_fifo(16) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(32),
      out_fifo(15 downto 14) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(29 downto 28),
      out_fifo(13 downto 12) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(25 downto 24),
      out_fifo(11 downto 10) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(21 downto 20),
      out_fifo(9 downto 8) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(17 downto 16),
      out_fifo(7 downto 6) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(14 downto 13),
      out_fifo(5 downto 4) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(10 downto 9),
      out_fifo(3 downto 2) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(6 downto 5),
      out_fifo(1 downto 0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(2 downto 1),
      out_fifo_0 => \^init_calib_complete_reg_rep__8_0\,
      out_fifo_1(43 downto 41) => out_fifo(71 downto 69),
      out_fifo_1(40) => out_fifo(67),
      out_fifo_1(39 downto 36) => out_fifo(65 downto 62),
      out_fifo_1(35 downto 33) => out_fifo(60 downto 58),
      out_fifo_1(32 downto 27) => out_fifo(54 downto 49),
      out_fifo_1(26 downto 24) => out_fifo(47 downto 45),
      out_fifo_1(23) => out_fifo(43),
      out_fifo_1(22 downto 19) => out_fifo(41 downto 38),
      out_fifo_1(18 downto 16) => out_fifo(36 downto 34),
      out_fifo_1(15 downto 13) => out_fifo(31 downto 29),
      out_fifo_1(12) => out_fifo(26),
      out_fifo_1(11) => out_fifo(24),
      out_fifo_1(10 downto 5) => out_fifo(22 downto 17),
      out_fifo_1(4 downto 2) => out_fifo(7 downto 5),
      out_fifo_1(1) => out_fifo(2),
      out_fifo_1(0) => out_fifo(0),
      out_fifo_10 => \^init_calib_complete_reg_rep__9_0\,
      out_fifo_11 => out_fifo_3,
      out_fifo_2 => out_fifo_0,
      out_fifo_3 => \init_calib_complete_reg_rep__7_n_0\,
      out_fifo_4 => \^init_calib_complete_reg_rep__6_0\,
      out_fifo_5(43 downto 41) => out_fifo_1(63 downto 61),
      out_fifo_5(40) => out_fifo_1(58),
      out_fifo_5(39 downto 37) => out_fifo_1(56 downto 54),
      out_fifo_5(36 downto 34) => out_fifo_1(52 downto 50),
      out_fifo_5(33 downto 31) => out_fifo_1(47 downto 45),
      out_fifo_5(30) => out_fifo_1(43),
      out_fifo_5(29 downto 25) => out_fifo_1(41 downto 37),
      out_fifo_5(24) => out_fifo_1(34),
      out_fifo_5(23) => out_fifo_1(32),
      out_fifo_5(22 downto 17) => out_fifo_1(30 downto 25),
      out_fifo_5(16 downto 15) => out_fifo_1(23 downto 22),
      out_fifo_5(14 downto 12) => out_fifo_1(20 downto 18),
      out_fifo_5(11 downto 6) => out_fifo_1(14 downto 9),
      out_fifo_5(5 downto 3) => out_fifo_1(7 downto 5),
      out_fifo_5(2) => out_fifo_1(3),
      out_fifo_5(1 downto 0) => out_fifo_1(1 downto 0),
      out_fifo_6 => out_fifo_2,
      out_fifo_7 => \^init_calib_complete_reg_rep__5_0\,
      out_fifo_8(40 downto 13) => out_fifo_5(46 downto 19),
      out_fifo_8(12) => out_fifo_5(16),
      out_fifo_8(11 downto 0) => out_fifo_5(11 downto 0),
      out_fifo_9 => out_fifo_6,
      p_128_in => p_128_in,
      \phy_ctl_wd_i1_reg[17]\ => \phy_ctl_wd_i1_reg[17]\,
      \phy_ctl_wd_i1_reg[19]\(1 downto 0) => \phy_ctl_wd_i1_reg[19]\(1 downto 0),
      \phy_ctl_wd_i1_reg[20]\ => \phy_ctl_wd_i1_reg[20]\,
      \phy_ctl_wd_i1_reg[21]\ => \phy_ctl_wd_i1_reg[21]\,
      \phy_ctl_wd_i1_reg[22]\ => \init_calib_complete_reg_rep__3_n_0\,
      \phy_ctl_wd_i1_reg[22]_0\ => \phy_ctl_wd_i1_reg[22]\,
      phy_ctl_wr_i1_reg => \init_calib_complete_reg_rep__4_n_0\,
      phy_dout(40 downto 12) => phy_dout(44 downto 16),
      phy_dout(11 downto 0) => phy_dout(11 downto 0),
      phy_read_calib => phy_read_calib,
      pi_calib_done => pi_calib_done,
      pi_dqs_found_all_bank => pi_dqs_found_all_bank,
      pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_4\,
      pi_dqs_found_done_r1 => pi_dqs_found_done_r1,
      pi_dqs_found_rank_done => pi_dqs_found_rank_done,
      pi_dqs_found_start_reg_0 => u_ddr_phy_init_n_347,
      prbs_rdlvl_done_pulse0 => prbs_rdlvl_done_pulse0,
      prbs_rdlvl_done_pulse_reg_0 => prbs_rdlvl_done_pulse_reg,
      prech_done => prech_done,
      prech_req_posedge_r_reg_0 => u_ddr_phy_init_n_2,
      rdlvl_last_byte_done => rdlvl_last_byte_done,
      rdlvl_pi_incdec => rdlvl_pi_incdec,
      rdlvl_prech_req => rdlvl_prech_req,
      rdlvl_stg1_done_r1 => rdlvl_stg1_done_r1,
      rdlvl_stg1_rank_done => rdlvl_stg1_rank_done,
      rdlvl_stg1_start_reg_0 => \^rdlvl_stg1_start_reg\,
      rdlvl_stg1_start_reg_1 => rdlvl_stg1_start_reg_0,
      stg1_wr_done => stg1_wr_done,
      \stg1_wr_rd_cnt_reg[3]_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22\,
      \wr_en_inferred__0_i_1_0\ => \wr_en_inferred__0_i_1\,
      \wr_en_inferred__0_i_1__0_0\ => \wr_en_inferred__0_i_1__0\,
      \wr_en_inferred__0_i_1__1_0\ => \wr_en_inferred__0_i_1__1\,
      \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]\,
      \wr_ptr_timing_reg[0]_0\ => \^init_calib_complete_reg_rep_0\,
      \wr_ptr_timing_reg[0]_1\ => \wr_ptr_timing_reg[0]_0\,
      \wr_ptr_timing_reg[0]_2\ => \wr_ptr_timing_reg[0]_1\,
      wrcal_prech_req => wrcal_prech_req,
      wrcal_rd_wait => wrcal_rd_wait,
      \wrcal_reads_reg[0]_0\ => \not_empty_wait_cnt_reg[4]\,
      wrcal_start_reg_0 => u_ddr_phy_init_n_346,
      \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[127]_0\(0) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28\,
      \write_buffer.wr_buf_out_data_reg[104]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[120]\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[108]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[124]\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[117]\(43 downto 41) => \write_buffer.wr_buf_out_data_reg[117]\(59 downto 57),
      \write_buffer.wr_buf_out_data_reg[117]\(40 downto 33) => \write_buffer.wr_buf_out_data_reg[117]\(55 downto 48),
      \write_buffer.wr_buf_out_data_reg[117]\(32 downto 24) => \write_buffer.wr_buf_out_data_reg[117]\(45 downto 37),
      \write_buffer.wr_buf_out_data_reg[117]\(23 downto 16) => \write_buffer.wr_buf_out_data_reg[117]\(35 downto 28),
      \write_buffer.wr_buf_out_data_reg[117]\(15 downto 12) => \write_buffer.wr_buf_out_data_reg[117]\(26 downto 23),
      \write_buffer.wr_buf_out_data_reg[117]\(11) => \write_buffer.wr_buf_out_data_reg[117]\(21),
      \write_buffer.wr_buf_out_data_reg[117]\(10 downto 5) => \write_buffer.wr_buf_out_data_reg[117]\(19 downto 14),
      \write_buffer.wr_buf_out_data_reg[117]\(4 downto 1) => \write_buffer.wr_buf_out_data_reg[117]\(5 downto 2),
      \write_buffer.wr_buf_out_data_reg[117]\(0) => \write_buffer.wr_buf_out_data_reg[117]\(0),
      \write_buffer.wr_buf_out_data_reg[121]\(5 downto 3) => \write_buffer.wr_buf_out_data_reg[121]\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[121]\(2) => \write_buffer.wr_buf_out_data_reg[121]\(3),
      \write_buffer.wr_buf_out_data_reg[121]\(1 downto 0) => \write_buffer.wr_buf_out_data_reg[121]\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[122]\(4 downto 2) => \write_buffer.wr_buf_out_data_reg[122]\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[122]\(1) => \write_buffer.wr_buf_out_data_reg[122]\(2),
      \write_buffer.wr_buf_out_data_reg[122]\(0) => \write_buffer.wr_buf_out_data_reg[122]\(0),
      \write_buffer.wr_buf_out_data_reg[123]\(4 downto 3) => \write_buffer.wr_buf_out_data_reg[123]\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[123]\(2 downto 0) => \write_buffer.wr_buf_out_data_reg[123]\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[126]\(43 downto 40) => init_calib_complete_reg_rep_1(51 downto 48),
      \write_buffer.wr_buf_out_data_reg[126]\(39 downto 34) => init_calib_complete_reg_rep_1(46 downto 41),
      \write_buffer.wr_buf_out_data_reg[126]\(33 downto 31) => init_calib_complete_reg_rep_1(39 downto 37),
      \write_buffer.wr_buf_out_data_reg[126]\(30 downto 24) => init_calib_complete_reg_rep_1(35 downto 29),
      \write_buffer.wr_buf_out_data_reg[126]\(23) => init_calib_complete_reg_rep_1(27),
      \write_buffer.wr_buf_out_data_reg[126]\(22 downto 12) => init_calib_complete_reg_rep_1(25 downto 15),
      \write_buffer.wr_buf_out_data_reg[126]\(11 downto 3) => init_calib_complete_reg_rep_1(12 downto 4),
      \write_buffer.wr_buf_out_data_reg[126]\(2 downto 0) => init_calib_complete_reg_rep_1(2 downto 0),
      \write_buffer.wr_buf_out_data_reg[126]_0\(4 downto 2) => \write_buffer.wr_buf_out_data_reg[126]\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[126]_0\(1) => \write_buffer.wr_buf_out_data_reg[126]\(2),
      \write_buffer.wr_buf_out_data_reg[126]_0\(0) => \write_buffer.wr_buf_out_data_reg[126]\(0),
      \write_buffer.wr_buf_out_data_reg[127]\(4 downto 3) => \write_buffer.wr_buf_out_data_reg[127]\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[127]\(2 downto 0) => \write_buffer.wr_buf_out_data_reg[127]\(4 downto 2),
      wrlvl_byte_redo => wrlvl_byte_redo,
      wrlvl_final_if_rst => wrlvl_final_if_rst
    );
u_ddr_phy_wrcal: entity work.mig_7series_0_mig_7series_v4_2_ddr_phy_wrcal
     port map (
      CLK => CLK,
      E(0) => rd_active_r,
      LD0 => LD0,
      LD0_0 => LD0_0,
      cal1_dq_idel_ce_reg => u_ddr_phy_wrcal_n_6,
      \cal2_state_r[3]_i_3_0\ => u_ddr_phy_init_n_346,
      calib_zero_inputs => calib_zero_inputs,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0]_0\ => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0]\,
      \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]_0\ => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\,
      \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4]_0\ => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4]\,
      \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]_0\ => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\,
      idelay_ce_int => idelay_ce_int,
      idelay_ld_reg_0(0) => u_ddr_phy_wrcal_n_4,
      idelay_ld_rst => idelay_ld_rst,
      \idelay_tap_cnt_r_reg[0][1][4]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25\,
      \idelay_tap_cnt_r_reg[0][1][4]_0\ => \idelay_tap_cnt_r_reg[0][1][4]\,
      \input_[9].iserdes_dq_.idelay_dq.idelaye2\ => \^calib_in_common\,
      \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\ => \^calib_sel\(0),
      \not_empty_wait_cnt_reg[4]_0\ => \not_empty_wait_cnt_reg[4]\,
      phy_if_reset_w => phy_if_reset_w,
      phy_rddata_en => phy_rddata_en,
      \po_stg2_wrcal_cnt_reg[0]_0\(0) => \^po_stg2_wrcal_cnt_reg[0]\(0),
      prech_done => prech_done,
      wrcal_done_reg_0 => u_ddr_phy_wrcal_n_9,
      wrcal_done_reg_1(0) => wrcal_done_reg(0),
      \wrcal_dqs_cnt_r_reg[1]_0\(0) => \wrcal_dqs_cnt_r_reg[1]\(0),
      wrcal_prech_req => wrcal_prech_req,
      wrcal_rd_wait => wrcal_rd_wait,
      wrlvl_byte_redo => wrlvl_byte_redo
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_rank_common is
  port (
    maint_prescaler_tick_r : out STD_LOGIC;
    \maintenance_request.maint_srx_r_lcl_reg_0\ : out STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg_0\ : out STD_LOGIC;
    \maintenance_request.maint_zq_r_lcl_reg_0\ : out STD_LOGIC;
    \maintenance_request.maint_req_r_lcl_reg_0\ : out STD_LOGIC;
    \periodic_read_request.periodic_rd_r_lcl_reg_0\ : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    \maintenance_request.maint_rank_r_lcl_reg[0]_0\ : out STD_LOGIC;
    \periodic_read_request.periodic_rd_grant_r\ : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    maint_ref_zq_wip : out STD_LOGIC;
    \periodic_read_request.periodic_rd_grant_r_reg[0]_0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__9\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \maintenance_request.maint_sre_r_lcl_reg_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \maintenance_request.maint_srx_r_lcl_reg_1\ : out STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg_2\ : out STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg_3\ : out STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    app_zq_ns : in STD_LOGIC;
    maint_ref_zq_wip_r_reg_0 : in STD_LOGIC;
    maint_ref_zq_wip_r_reg_1 : in STD_LOGIC;
    \grant_r_reg[0]\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r\ : in STD_LOGIC;
    insert_maint_r1 : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r_reg\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r\ : in STD_LOGIC;
    \last_master_r_reg[2]\ : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    \refresh_generation.refresh_bank_r\ : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    cke_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    insert_maint_r : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ : in STD_LOGIC;
    maint_wip_r : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_rank_common : entity is "mig_7series_v4_2_rank_common";
end mig_7series_0_mig_7series_v4_2_rank_common;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_rank_common is
  signal app_ref_ack_ns : STD_LOGIC;
  signal app_ref_ns : STD_LOGIC;
  signal app_ref_r : STD_LOGIC;
  signal \^app_sr_active\ : STD_LOGIC;
  signal app_sr_active_r_i_1_n_0 : STD_LOGIC;
  signal app_zq_r : STD_LOGIC;
  signal \maint_prescaler.maint_prescaler_r0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \maint_prescaler.maint_prescaler_r0_0\ : STD_LOGIC;
  signal \maint_prescaler.maint_prescaler_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \maint_prescaler.maint_prescaler_r_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \maint_prescaler.maint_prescaler_tick_ns\ : STD_LOGIC;
  signal \^maint_prescaler_tick_r\ : STD_LOGIC;
  signal \maintenance_request.maint_arb0_n_0\ : STD_LOGIC;
  signal \^maintenance_request.maint_rank_r_lcl_reg[0]_0\ : STD_LOGIC;
  signal \^maintenance_request.maint_req_r_lcl_reg_0\ : STD_LOGIC;
  signal \maintenance_request.maint_sre_ns\ : STD_LOGIC;
  signal \^maintenance_request.maint_sre_r_lcl_reg_0\ : STD_LOGIC;
  signal \maintenance_request.maint_srx_ns\ : STD_LOGIC;
  signal \maintenance_request.maint_srx_r_lcl_i_2_n_0\ : STD_LOGIC;
  signal \^maintenance_request.maint_srx_r_lcl_reg_0\ : STD_LOGIC;
  signal \maintenance_request.maint_zq_ns\ : STD_LOGIC;
  signal \^maintenance_request.maint_zq_r_lcl_reg_0\ : STD_LOGIC;
  signal \maintenance_request.new_maint_rank_r\ : STD_LOGIC;
  signal \maintenance_request.upd_last_master_ns\ : STD_LOGIC;
  signal \maintenance_request.upd_last_master_r\ : STD_LOGIC;
  signal \^periodic_read_request.periodic_rd_grant_r\ : STD_LOGIC;
  signal \periodic_read_request.periodic_rd_grant_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \periodic_read_request.periodic_rd_ns\ : STD_LOGIC;
  signal \periodic_read_request.periodic_rd_r_cnt\ : STD_LOGIC;
  signal \periodic_read_request.periodic_rd_r_cnt_i_1_n_0\ : STD_LOGIC;
  signal \^periodic_read_request.periodic_rd_r_lcl_reg_0\ : STD_LOGIC;
  signal \periodic_read_request.upd_last_master_ns\ : STD_LOGIC;
  signal \periodic_read_request.upd_last_master_r\ : STD_LOGIC;
  signal \refresh_generation.refresh_bank_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \refresh_generation.refresh_bank_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \refresh_timer.refresh_timer_r0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \refresh_timer.refresh_timer_r0_1\ : STD_LOGIC;
  signal \refresh_timer.refresh_timer_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \refresh_timer.refresh_timer_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \refresh_timer.refresh_timer_r[5]_i_5_n_0\ : STD_LOGIC;
  signal \refresh_timer.refresh_timer_r_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal sel : STD_LOGIC;
  signal \sr_cntrl.ckesr_timer.ckesr_timer_r\ : STD_LOGIC;
  signal \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \sr_cntrl.sre_request_logic.sre_request_ns\ : STD_LOGIC;
  signal \sr_cntrl.sre_request_logic.sre_request_r\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of app_ref_ack_r_i_1 : label is "soft_lutpair607";
  attribute SOFT_HLUTNM of app_sr_active_r_i_1 : label is "soft_lutpair608";
  attribute SOFT_HLUTNM of cke_r_i_1 : label is "soft_lutpair608";
  attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[0]_i_1\ : label is "soft_lutpair612";
  attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[1]_i_1\ : label is "soft_lutpair612";
  attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[2]_i_1\ : label is "soft_lutpair609";
  attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[3]_i_3\ : label is "soft_lutpair609";
  attribute SOFT_HLUTNM of \periodic_rd_generation.periodic_rd_cntr1_r_i_1\ : label is "soft_lutpair610";
  attribute SOFT_HLUTNM of \periodic_read_request.periodic_rd_grant_r[0]_i_1\ : label is "soft_lutpair605";
  attribute SOFT_HLUTNM of \periodic_read_request.periodic_rd_r_cnt_i_1\ : label is "soft_lutpair610";
  attribute SOFT_HLUTNM of \periodic_read_request.upd_last_master_r_i_1\ : label is "soft_lutpair605";
  attribute SOFT_HLUTNM of \refresh_generation.refresh_bank_r[0]_i_1\ : label is "soft_lutpair607";
  attribute SOFT_HLUTNM of \refresh_generation.refresh_bank_r[0]_i_2\ : label is "soft_lutpair604";
  attribute SOFT_HLUTNM of \refresh_generation.refresh_bank_r[0]_i_3\ : label is "soft_lutpair603";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[1]_i_1\ : label is "soft_lutpair603";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[2]_i_1\ : label is "soft_lutpair611";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[3]_i_1\ : label is "soft_lutpair606";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[4]_i_1\ : label is "soft_lutpair606";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[5]_i_5\ : label is "soft_lutpair611";
  attribute SOFT_HLUTNM of \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1\ : label is "soft_lutpair604";
begin
  app_sr_active <= \^app_sr_active\;
  maint_prescaler_tick_r <= \^maint_prescaler_tick_r\;
  \maintenance_request.maint_rank_r_lcl_reg[0]_0\ <= \^maintenance_request.maint_rank_r_lcl_reg[0]_0\;
  \maintenance_request.maint_req_r_lcl_reg_0\ <= \^maintenance_request.maint_req_r_lcl_reg_0\;
  \maintenance_request.maint_sre_r_lcl_reg_0\ <= \^maintenance_request.maint_sre_r_lcl_reg_0\;
  \maintenance_request.maint_srx_r_lcl_reg_0\ <= \^maintenance_request.maint_srx_r_lcl_reg_0\;
  \maintenance_request.maint_zq_r_lcl_reg_0\ <= \^maintenance_request.maint_zq_r_lcl_reg_0\;
  \periodic_read_request.periodic_rd_grant_r\ <= \^periodic_read_request.periodic_rd_grant_r\;
  \periodic_read_request.periodic_rd_r_lcl_reg_0\ <= \^periodic_read_request.periodic_rd_r_lcl_reg_0\;
app_ref_ack_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => app_ref_r,
      I1 => \refresh_generation.refresh_bank_r\,
      I2 => \grant_r_reg[0]\,
      O => app_ref_ack_ns
    );
app_ref_ack_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => app_ref_ack_ns,
      Q => app_ref_ack,
      R => '0'
    );
app_ref_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F200"
    )
        port map (
      I0 => app_ref_r,
      I1 => \refresh_generation.refresh_bank_r\,
      I2 => app_ref_req,
      I3 => \grant_r_reg[0]\,
      O => app_ref_ns
    );
app_ref_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => app_ref_ns,
      Q => app_ref_r,
      R => '0'
    );
app_sr_active_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I1 => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      I2 => insert_maint_r1,
      I3 => \^app_sr_active\,
      O => app_sr_active_r_i_1_n_0
    );
app_sr_active_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => app_sr_active_r_i_1_n_0,
      Q => \^app_sr_active\,
      R => '0'
    );
app_zq_ack_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => app_zq_r,
      Q => app_zq_ack,
      R => '0'
    );
app_zq_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => app_zq_ns,
      Q => app_zq_r,
      R => '0'
    );
auto_pre_r_lcl_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FF10FF101010FF"
    )
        port map (
      I0 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I1 => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      I2 => \^maintenance_request.maint_rank_r_lcl_reg[0]_0\,
      I3 => maint_wip_r,
      I4 => \^maintenance_request.maint_req_r_lcl_reg_0\,
      I5 => \maint_controller.maint_hit_busies_r_reg[3]\,
      O => \maintenance_request.maint_sre_r_lcl_reg_3\
    );
cke_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3F20"
    )
        port map (
      I0 => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      I1 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I2 => insert_maint_r1,
      I3 => cke_r_reg(0),
      O => D(0)
    );
\maint_controller.maint_hit_busies_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAEAEFFAEAEAEAE"
    )
        port map (
      I0 => maint_wip_r,
      I1 => \^maintenance_request.maint_req_r_lcl_reg_0\,
      I2 => \maint_controller.maint_hit_busies_r_reg[3]\,
      I3 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I4 => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      I5 => \^maintenance_request.maint_rank_r_lcl_reg[0]_0\,
      O => \maint_controller.maint_wip_r_lcl_reg\
    );
\maint_prescaler.maint_prescaler_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \maint_prescaler.maint_prescaler_r_reg\(0),
      O => \maint_prescaler.maint_prescaler_r0\(0)
    );
\maint_prescaler.maint_prescaler_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \maint_prescaler.maint_prescaler_r_reg\(1),
      I1 => \maint_prescaler.maint_prescaler_r_reg\(0),
      O => \maint_prescaler.maint_prescaler_r0\(1)
    );
\maint_prescaler.maint_prescaler_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => \maint_prescaler.maint_prescaler_r_reg\(0),
      I1 => \maint_prescaler.maint_prescaler_r_reg\(1),
      I2 => \maint_prescaler.maint_prescaler_r_reg\(2),
      O => \maint_prescaler.maint_prescaler_r0\(2)
    );
\maint_prescaler.maint_prescaler_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0010FFFF"
    )
        port map (
      I0 => \maint_prescaler.maint_prescaler_r_reg\(2),
      I1 => \maint_prescaler.maint_prescaler_r_reg\(3),
      I2 => \maint_prescaler.maint_prescaler_r_reg\(0),
      I3 => \maint_prescaler.maint_prescaler_r_reg\(1),
      I4 => \grant_r_reg[0]\,
      O => \maint_prescaler.maint_prescaler_r0_0\
    );
\maint_prescaler.maint_prescaler_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \maint_prescaler.maint_prescaler_r_reg\(0),
      I1 => \maint_prescaler.maint_prescaler_r_reg\(1),
      I2 => \maint_prescaler.maint_prescaler_r_reg\(2),
      I3 => \maint_prescaler.maint_prescaler_r_reg\(3),
      O => sel
    );
\maint_prescaler.maint_prescaler_r[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \maint_prescaler.maint_prescaler_r_reg\(3),
      I1 => \maint_prescaler.maint_prescaler_r_reg\(0),
      I2 => \maint_prescaler.maint_prescaler_r_reg\(1),
      I3 => \maint_prescaler.maint_prescaler_r_reg\(2),
      O => \maint_prescaler.maint_prescaler_r[3]_i_3_n_0\
    );
\maint_prescaler.maint_prescaler_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r0\(0),
      Q => \maint_prescaler.maint_prescaler_r_reg\(0),
      S => \maint_prescaler.maint_prescaler_r0_0\
    );
\maint_prescaler.maint_prescaler_r_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r0\(1),
      Q => \maint_prescaler.maint_prescaler_r_reg\(1),
      S => \maint_prescaler.maint_prescaler_r0_0\
    );
\maint_prescaler.maint_prescaler_r_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r0\(2),
      Q => \maint_prescaler.maint_prescaler_r_reg\(2),
      S => \maint_prescaler.maint_prescaler_r0_0\
    );
\maint_prescaler.maint_prescaler_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r[3]_i_3_n_0\,
      Q => \maint_prescaler.maint_prescaler_r_reg\(3),
      S => \maint_prescaler.maint_prescaler_r0_0\
    );
\maint_prescaler.maint_prescaler_tick_r_lcl_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \maint_prescaler.maint_prescaler_r_reg\(1),
      I1 => \maint_prescaler.maint_prescaler_r_reg\(0),
      I2 => \maint_prescaler.maint_prescaler_r_reg\(3),
      I3 => \maint_prescaler.maint_prescaler_r_reg\(2),
      O => \maint_prescaler.maint_prescaler_tick_ns\
    );
\maint_prescaler.maint_prescaler_tick_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maint_prescaler.maint_prescaler_tick_ns\,
      Q => \^maint_prescaler_tick_r\,
      R => '0'
    );
maint_ref_zq_wip_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => maint_ref_zq_wip_r_reg_1,
      Q => maint_ref_zq_wip,
      R => maint_ref_zq_wip_r_reg_0
    );
\maintenance_request.maint_arb0\: entity work.mig_7series_0_mig_7series_v4_2_round_robin_arb
     port map (
      CLK => CLK,
      app_sr_req => app_sr_req,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]\,
      \last_master_r_reg[2]_0\ => \last_master_r_reg[2]\,
      \maintenance_request.maint_rank_r_lcl_reg[0]\ => \maintenance_request.maint_arb0_n_0\,
      \maintenance_request.maint_rank_r_lcl_reg[0]_0\ => \^maintenance_request.maint_rank_r_lcl_reg[0]_0\,
      \maintenance_request.maint_rank_r_lcl_reg[0]_1\ => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      \maintenance_request.maint_sre_ns\ => \maintenance_request.maint_sre_ns\,
      \maintenance_request.maint_sre_r_lcl_reg\ => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      \maintenance_request.maint_srx_ns\ => \maintenance_request.maint_srx_ns\,
      \maintenance_request.maint_srx_r_lcl_reg\ => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      \maintenance_request.maint_srx_r_lcl_reg_0\ => \maintenance_request.maint_srx_r_lcl_i_2_n_0\,
      \maintenance_request.new_maint_rank_r\ => \maintenance_request.new_maint_rank_r\,
      \maintenance_request.upd_last_master_r\ => \maintenance_request.upd_last_master_r\,
      \refresh_generation.refresh_bank_r\ => \refresh_generation.refresh_bank_r\,
      \sr_cntrl.ckesr_timer.ckesr_timer_r\ => \sr_cntrl.ckesr_timer.ckesr_timer_r\,
      \sr_cntrl.sre_request_logic.sre_request_r\ => \sr_cntrl.sre_request_logic.sre_request_r\
    );
\maintenance_request.maint_rank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.maint_arb0_n_0\,
      Q => \^maintenance_request.maint_rank_r_lcl_reg[0]_0\,
      R => '0'
    );
\maintenance_request.maint_req_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.new_maint_rank_r\,
      Q => \^maintenance_request.maint_req_r_lcl_reg_0\,
      R => '0'
    );
\maintenance_request.maint_sre_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.maint_sre_ns\,
      Q => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      R => '0'
    );
\maintenance_request.maint_srx_r_lcl_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \sr_cntrl.ckesr_timer.ckesr_timer_r\,
      I1 => app_sr_req,
      O => \maintenance_request.maint_srx_r_lcl_i_2_n_0\
    );
\maintenance_request.maint_srx_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.maint_srx_ns\,
      Q => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      R => '0'
    );
\maintenance_request.maint_zq_r_lcl_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0D00"
    )
        port map (
      I0 => \maintenance_request.upd_last_master_r\,
      I1 => \maintenance_request.new_maint_rank_r\,
      I2 => \last_master_r_reg[2]\,
      I3 => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      O => \maintenance_request.maint_zq_ns\
    );
\maintenance_request.maint_zq_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.maint_zq_ns\,
      Q => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      R => '0'
    );
\maintenance_request.new_maint_rank_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.upd_last_master_r\,
      Q => \maintenance_request.new_maint_rank_r\,
      R => '0'
    );
\maintenance_request.upd_last_master_r_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2030"
    )
        port map (
      I0 => \sr_cntrl.sre_request_logic.sre_request_r\,
      I1 => maint_wip_r,
      I2 => \grant_r_reg[0]\,
      I3 => \refresh_generation.refresh_bank_r\,
      O => \maintenance_request.upd_last_master_ns\
    );
\maintenance_request.upd_last_master_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.upd_last_master_ns\,
      Q => \maintenance_request.upd_last_master_r\,
      R => '0'
    );
\periodic_rd_generation.periodic_rd_cntr1_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^periodic_read_request.periodic_rd_grant_r\,
      I1 => \periodic_rd_generation.periodic_rd_cntr1_r_reg\,
      I2 => \periodic_rd_generation.periodic_rd_cntr1_r\,
      O => \periodic_read_request.periodic_rd_grant_r_reg[0]_0\
    );
\periodic_read_request.periodic_rd_grant_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1000"
    )
        port map (
      I0 => \^periodic_read_request.periodic_rd_r_lcl_reg_0\,
      I1 => \periodic_read_request.upd_last_master_r\,
      I2 => \grant_r_reg[0]\,
      I3 => \periodic_rd_generation.periodic_rd_request_r\,
      I4 => \^periodic_read_request.periodic_rd_grant_r\,
      O => \periodic_read_request.periodic_rd_grant_r[0]_i_1_n_0\
    );
\periodic_read_request.periodic_rd_grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_read_request.periodic_rd_grant_r[0]_i_1_n_0\,
      Q => \^periodic_read_request.periodic_rd_grant_r\,
      R => '0'
    );
\periodic_read_request.periodic_rd_r_cnt_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^periodic_read_request.periodic_rd_r_lcl_reg_0\,
      I1 => \periodic_rd_generation.periodic_rd_cntr1_r_reg\,
      I2 => \periodic_read_request.periodic_rd_r_cnt\,
      O => \periodic_read_request.periodic_rd_r_cnt_i_1_n_0\
    );
\periodic_read_request.periodic_rd_r_cnt_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_read_request.periodic_rd_r_cnt_i_1_n_0\,
      Q => \periodic_read_request.periodic_rd_r_cnt\,
      R => maint_ref_zq_wip_r_reg_0
    );
\periodic_read_request.periodic_rd_r_lcl_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B0A0F0A0"
    )
        port map (
      I0 => \periodic_read_request.upd_last_master_r\,
      I1 => \periodic_rd_generation.periodic_rd_cntr1_r_reg\,
      I2 => \grant_r_reg[0]\,
      I3 => \^periodic_read_request.periodic_rd_r_lcl_reg_0\,
      I4 => \periodic_read_request.periodic_rd_r_cnt\,
      O => \periodic_read_request.periodic_rd_ns\
    );
\periodic_read_request.periodic_rd_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_read_request.periodic_rd_ns\,
      Q => \^periodic_read_request.periodic_rd_r_lcl_reg_0\,
      R => '0'
    );
\periodic_read_request.upd_last_master_r_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^periodic_read_request.periodic_rd_r_lcl_reg_0\,
      I1 => \periodic_read_request.upd_last_master_r\,
      I2 => \grant_r_reg[0]\,
      I3 => \periodic_rd_generation.periodic_rd_request_r\,
      O => \periodic_read_request.upd_last_master_ns\
    );
\periodic_read_request.upd_last_master_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_read_request.upd_last_master_ns\,
      Q => \periodic_read_request.upd_last_master_r\,
      R => '0'
    );
q_has_rd_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10FF"
    )
        port map (
      I0 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I1 => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      I2 => \^maintenance_request.maint_rank_r_lcl_reg[0]_0\,
      I3 => \^maintenance_request.maint_req_r_lcl_reg_0\,
      O => \maintenance_request.maint_sre_r_lcl_reg_2\
    );
\refresh_generation.refresh_bank_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2880"
    )
        port map (
      I0 => \grant_r_reg[0]\,
      I1 => \refresh_generation.refresh_bank_r\,
      I2 => \refresh_generation.refresh_bank_r[0]_i_2_n_0\,
      I3 => \refresh_generation.refresh_bank_r[0]_i_3_n_0\,
      O => \init_calib_complete_reg_rep__9\
    );
\refresh_generation.refresh_bank_r[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => \^maintenance_request.maint_rank_r_lcl_reg[0]_0\,
      I1 => insert_maint_r1,
      I2 => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      I3 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I4 => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      O => \refresh_generation.refresh_bank_r[0]_i_2_n_0\
    );
\refresh_generation.refresh_bank_r[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BFFF"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(1),
      I1 => \refresh_timer.refresh_timer_r_reg\(0),
      I2 => \^maint_prescaler_tick_r\,
      I3 => \refresh_timer.refresh_timer_r[5]_i_4_n_0\,
      I4 => app_ref_req,
      O => \refresh_generation.refresh_bank_r[0]_i_3_n_0\
    );
\refresh_timer.refresh_timer_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(0),
      O => \refresh_timer.refresh_timer_r0\(0)
    );
\refresh_timer.refresh_timer_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(1),
      I1 => \refresh_timer.refresh_timer_r_reg\(0),
      O => \refresh_timer.refresh_timer_r0\(1)
    );
\refresh_timer.refresh_timer_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(2),
      I1 => \refresh_timer.refresh_timer_r_reg\(1),
      I2 => \refresh_timer.refresh_timer_r_reg\(0),
      O => \refresh_timer.refresh_timer_r0\(2)
    );
\refresh_timer.refresh_timer_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(3),
      I1 => \refresh_timer.refresh_timer_r_reg\(2),
      I2 => \refresh_timer.refresh_timer_r_reg\(0),
      I3 => \refresh_timer.refresh_timer_r_reg\(1),
      O => \refresh_timer.refresh_timer_r0\(3)
    );
\refresh_timer.refresh_timer_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(4),
      I1 => \refresh_timer.refresh_timer_r_reg\(3),
      I2 => \refresh_timer.refresh_timer_r_reg\(1),
      I3 => \refresh_timer.refresh_timer_r_reg\(0),
      I4 => \refresh_timer.refresh_timer_r_reg\(2),
      O => \refresh_timer.refresh_timer_r0\(4)
    );
\refresh_timer.refresh_timer_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4000FFFF"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(1),
      I1 => \refresh_timer.refresh_timer_r_reg\(0),
      I2 => \^maint_prescaler_tick_r\,
      I3 => \refresh_timer.refresh_timer_r[5]_i_4_n_0\,
      I4 => \grant_r_reg[0]\,
      O => \refresh_timer.refresh_timer_r[5]_i_1_n_0\
    );
\refresh_timer.refresh_timer_r[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEF0000"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(4),
      I1 => \refresh_timer.refresh_timer_r_reg\(3),
      I2 => \refresh_timer.refresh_timer_r[5]_i_5_n_0\,
      I3 => \refresh_timer.refresh_timer_r_reg\(5),
      I4 => \^maint_prescaler_tick_r\,
      O => \refresh_timer.refresh_timer_r0_1\
    );
\refresh_timer.refresh_timer_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(4),
      I1 => \refresh_timer.refresh_timer_r_reg\(3),
      I2 => \refresh_timer.refresh_timer_r_reg\(2),
      I3 => \refresh_timer.refresh_timer_r_reg\(0),
      I4 => \refresh_timer.refresh_timer_r_reg\(1),
      I5 => \refresh_timer.refresh_timer_r_reg\(5),
      O => \refresh_timer.refresh_timer_r0\(5)
    );
\refresh_timer.refresh_timer_r[5]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(5),
      I1 => \refresh_timer.refresh_timer_r_reg\(4),
      I2 => \refresh_timer.refresh_timer_r_reg\(3),
      I3 => \refresh_timer.refresh_timer_r_reg\(2),
      O => \refresh_timer.refresh_timer_r[5]_i_4_n_0\
    );
\refresh_timer.refresh_timer_r[5]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg\(1),
      I1 => \refresh_timer.refresh_timer_r_reg\(0),
      I2 => \refresh_timer.refresh_timer_r_reg\(2),
      O => \refresh_timer.refresh_timer_r[5]_i_5_n_0\
    );
\refresh_timer.refresh_timer_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \refresh_timer.refresh_timer_r0_1\,
      D => \refresh_timer.refresh_timer_r0\(0),
      Q => \refresh_timer.refresh_timer_r_reg\(0),
      S => \refresh_timer.refresh_timer_r[5]_i_1_n_0\
    );
\refresh_timer.refresh_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \refresh_timer.refresh_timer_r0_1\,
      D => \refresh_timer.refresh_timer_r0\(1),
      Q => \refresh_timer.refresh_timer_r_reg\(1),
      R => \refresh_timer.refresh_timer_r[5]_i_1_n_0\
    );
\refresh_timer.refresh_timer_r_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \refresh_timer.refresh_timer_r0_1\,
      D => \refresh_timer.refresh_timer_r0\(2),
      Q => \refresh_timer.refresh_timer_r_reg\(2),
      S => \refresh_timer.refresh_timer_r[5]_i_1_n_0\
    );
\refresh_timer.refresh_timer_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \refresh_timer.refresh_timer_r0_1\,
      D => \refresh_timer.refresh_timer_r0\(3),
      Q => \refresh_timer.refresh_timer_r_reg\(3),
      R => \refresh_timer.refresh_timer_r[5]_i_1_n_0\
    );
\refresh_timer.refresh_timer_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \refresh_timer.refresh_timer_r0_1\,
      D => \refresh_timer.refresh_timer_r0\(4),
      Q => \refresh_timer.refresh_timer_r_reg\(4),
      R => \refresh_timer.refresh_timer_r[5]_i_1_n_0\
    );
\refresh_timer.refresh_timer_r_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \refresh_timer.refresh_timer_r0_1\,
      D => \refresh_timer.refresh_timer_r0\(5),
      Q => \refresh_timer.refresh_timer_r_reg\(5),
      S => \refresh_timer.refresh_timer_r[5]_i_1_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      I1 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I2 => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      I3 => insert_maint_r,
      O => \maintenance_request.maint_srx_r_lcl_reg_1\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF01000000"
    )
        port map (
      I0 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I1 => \^maintenance_request.maint_zq_r_lcl_reg_0\,
      I2 => \last_master_r_reg[2]\,
      I3 => \^maintenance_request.maint_srx_r_lcl_reg_0\,
      I4 => insert_maint_r,
      I5 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\,
      O => \maintenance_request.maint_sre_r_lcl_reg_1\(0)
    );
\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I1 => insert_maint_r1,
      O => \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0\
    );
\sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0\,
      Q => \sr_cntrl.ckesr_timer.ckesr_timer_r\,
      R => '0'
    );
\sr_cntrl.sre_request_logic.sre_request_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000FFF0808"
    )
        port map (
      I0 => \grant_r_reg[0]\,
      I1 => app_sr_req,
      I2 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I3 => insert_maint_r1,
      I4 => \sr_cntrl.sre_request_logic.sre_request_r\,
      I5 => \last_master_r_reg[2]\,
      O => \sr_cntrl.sre_request_logic.sre_request_ns\
    );
\sr_cntrl.sre_request_logic.sre_request_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \sr_cntrl.sre_request_logic.sre_request_ns\,
      Q => \sr_cntrl.sre_request_logic.sre_request_r\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ui_top is
  port (
    app_rdy_r_reg : out STD_LOGIC;
    app_en_r2 : out STD_LOGIC;
    ram_init_done_r : out STD_LOGIC;
    app_wdf_rdy : out STD_LOGIC;
    \app_addr_r2_reg[22]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r2_reg[22]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r2_reg[22]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r2_reg[22]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_145_out : out STD_LOGIC;
    p_28_out : out STD_LOGIC;
    p_67_out : out STD_LOGIC;
    p_106_out : out STD_LOGIC;
    \app_cmd_r2_reg[0]\ : out STD_LOGIC;
    was_wr0 : out STD_LOGIC;
    S : out STD_LOGIC_VECTOR ( 2 downto 0 );
    row : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \app_addr_r1_reg[25]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    req_wr_r_lcl0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \app_addr_r1_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    \write_buffer.wr_buf_out_data_reg[37]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 143 downto 0 );
    \write_buffer.wr_buf_out_data_reg[78]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
    CLK : in STD_LOGIC;
    \pointer_ram.pointer_we\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[5]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
    rb_hit_busy_r_reg : in STD_LOGIC;
    req_bank_r : in STD_LOGIC_VECTOR ( 11 downto 0 );
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r_reg_2 : in STD_LOGIC;
    periodic_rd_r : in STD_LOGIC;
    periodic_rd_cntr_r : in STD_LOGIC;
    periodic_rd_ack_r : in STD_LOGIC;
    accept_ns : in STD_LOGIC;
    app_en : in STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[0]\ : in STD_LOGIC;
    app_wdf_wren : in STD_LOGIC;
    app_wdf_end : in STD_LOGIC;
    app_wdf_mask : in STD_LOGIC_VECTOR ( 15 downto 0 );
    app_wdf_data : in STD_LOGIC_VECTOR ( 127 downto 0 );
    \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : in STD_LOGIC;
    \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : in STD_LOGIC;
    \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : in STD_LOGIC;
    app_addr : in STD_LOGIC_VECTOR ( 25 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ui_top : entity is "mig_7series_v4_2_ui_top";
end mig_7series_0_mig_7series_v4_2_ui_top;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ui_top is
  signal app_cmd_r2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal app_rdy_ns : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \pointer_ram.pointer_wr_addr\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pointer_ram.pointer_wr_data\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^ram_init_done_r\ : STD_LOGIC;
  signal \read_data_indx.rd_data_indx_r_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \strict_mode.rd_data_buf_addr_r_lcl\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal ui_cmd0_n_39 : STD_LOGIC;
  signal ui_cmd0_n_40 : STD_LOGIC;
  signal ui_cmd0_n_41 : STD_LOGIC;
  signal ui_cmd0_n_42 : STD_LOGIC;
  signal ui_cmd0_n_43 : STD_LOGIC;
  signal use_addr : STD_LOGIC;
  signal wr_accepted : STD_LOGIC;
  signal wr_data_buf_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_req_counter.wr_req_cnt_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  ram_init_done_r <= \^ram_init_done_r\;
ui_cmd0: entity work.mig_7series_0_mig_7series_v4_2_ui_cmd
     port map (
      CLK => CLK,
      D(3 downto 0) => D(3 downto 0),
      E(0) => app_rdy_r_reg,
      S(2 downto 0) => S(2 downto 0),
      app_addr(25 downto 0) => app_addr(25 downto 0),
      \app_addr_r1_reg[0]_0\ => \wr_req_counter.wr_req_cnt_r_reg[0]\,
      \app_addr_r1_reg[23]_0\ => \app_addr_r1_reg[25]\(0),
      \app_addr_r1_reg[25]_0\(1 downto 0) => \app_addr_r1_reg[25]\(2 downto 1),
      \app_addr_r1_reg[9]_0\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0),
      \app_addr_r2_reg[22]_0\(0) => \app_addr_r2_reg[22]\(0),
      \app_addr_r2_reg[22]_1\(0) => \app_addr_r2_reg[22]_0\(0),
      \app_addr_r2_reg[22]_2\(0) => \app_addr_r2_reg[22]_1\(0),
      \app_addr_r2_reg[22]_3\(0) => \app_addr_r2_reg[22]_2\(0),
      app_cmd(1 downto 0) => app_cmd(1 downto 0),
      app_cmd_r2(1 downto 0) => app_cmd_r2(1 downto 0),
      \app_cmd_r2_reg[0]_0\ => \app_cmd_r2_reg[0]\,
      app_en => app_en,
      app_en_r2_reg_0 => app_en_r2,
      app_en_r2_reg_1 => ui_cmd0_n_39,
      app_rdy_ns => app_rdy_ns,
      p_0_in(0) => p_0_in(0),
      p_106_out => p_106_out,
      p_145_out => p_145_out,
      p_28_out => p_28_out,
      p_67_out => p_67_out,
      periodic_rd_ack_r => periodic_rd_ack_r,
      periodic_rd_cntr_r => periodic_rd_cntr_r,
      periodic_rd_r => periodic_rd_r,
      rb_hit_busy_r_reg => rb_hit_busy_r_reg,
      rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_0,
      rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_1,
      rb_hit_busy_r_reg_2 => rb_hit_busy_r_reg_2,
      \read_data_indx.rd_data_upd_indx_r_reg\ => ui_cmd0_n_43,
      req_bank_r(11 downto 0) => req_bank_r(11 downto 0),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      row(12 downto 0) => row(12 downto 0),
      row_hit_r_reg(12 downto 0) => row_hit_r_reg(12 downto 0),
      \strict_mode.rd_data_buf_addr_r_lcl\(3 downto 0) => \strict_mode.rd_data_buf_addr_r_lcl\(3 downto 0),
      \strict_mode.rd_data_buf_addr_r_lcl_reg[0]\ => ui_cmd0_n_40,
      \strict_mode.rd_data_buf_addr_r_lcl_reg[1]\ => ui_cmd0_n_41,
      use_addr => use_addr,
      was_wr0 => was_wr0,
      wr_accepted => wr_accepted,
      wr_data_buf_addr(3 downto 0) => wr_data_buf_addr(3 downto 0),
      \wr_req_counter.wr_req_cnt_r\(0) => \wr_req_counter.wr_req_cnt_r\(0),
      \wr_req_counter.wr_req_cnt_r_reg[0]\ => ui_cmd0_n_42
    );
ui_rd_data0: entity work.mig_7series_0_mig_7series_v4_2_ui_rd_data
     port map (
      ADDRD(3 downto 0) => \pointer_ram.pointer_wr_addr\(3 downto 0),
      CLK => CLK,
      Q(3 downto 0) => \read_data_indx.rd_data_indx_r_reg\(3 downto 0),
      app_cmd_r2(1 downto 0) => app_cmd_r2(1 downto 0),
      \pointer_ram.pointer_wr_data\(3 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 0),
      \pointer_ram.rams[1].RAM32M0\(3 downto 0) => \write_buffer.wr_buf_out_data_reg[5]\(3 downto 0),
      \rd_buf_indx.ram_init_done_r_lcl_reg_0\ => \^ram_init_done_r\,
      \strict_mode.rd_data_buf_addr_r_lcl\(3 downto 0) => \strict_mode.rd_data_buf_addr_r_lcl\(3 downto 0),
      \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0\ => \wr_req_counter.wr_req_cnt_r_reg[0]\,
      \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1\ => ui_cmd0_n_39,
      \strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0\ => ui_cmd0_n_40,
      \strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0\ => ui_cmd0_n_41,
      use_addr => use_addr
    );
ui_wr_data0: entity work.mig_7series_0_mig_7series_v4_2_ui_wr_data
     port map (
      ADDRD(3 downto 0) => \pointer_ram.pointer_wr_addr\(3 downto 0),
      CLK => CLK,
      E(0) => E(0),
      Q(3 downto 0) => \read_data_indx.rd_data_indx_r_reg\(3 downto 0),
      accept_ns => accept_ns,
      app_rdy_ns => app_rdy_ns,
      app_wdf_data(127 downto 0) => app_wdf_data(127 downto 0),
      app_wdf_end => app_wdf_end,
      app_wdf_mask(15 downto 0) => app_wdf_mask(15 downto 0),
      app_wdf_rdy => app_wdf_rdy,
      app_wdf_wren => app_wdf_wren,
      \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\,
      \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\,
      \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\,
      p_0_in(0) => p_0_in(0),
      \pointer_ram.pointer_we\ => \pointer_ram.pointer_we\,
      \pointer_ram.pointer_wr_data\(3 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 0),
      ram_init_done_r => \^ram_init_done_r\,
      wr_accepted => wr_accepted,
      wr_data_buf_addr(3 downto 0) => wr_data_buf_addr(3 downto 0),
      \wr_req_counter.wr_req_cnt_r_reg[0]_0\(0) => \wr_req_counter.wr_req_cnt_r\(0),
      \wr_req_counter.wr_req_cnt_r_reg[0]_1\ => ui_cmd0_n_42,
      \wr_req_counter.wr_req_cnt_r_reg[0]_2\ => \wr_req_counter.wr_req_cnt_r_reg[0]\,
      \wr_req_counter.wr_req_cnt_r_reg[4]_0\ => ui_cmd0_n_43,
      \write_buffer.wr_buf_out_data_reg[143]_0\(143 downto 0) => Q(143 downto 0),
      \write_buffer.wr_buf_out_data_reg[37]_0\(11 downto 0) => \write_buffer.wr_buf_out_data_reg[37]\(11 downto 0),
      \write_buffer.wr_buf_out_data_reg[5]_0\(3 downto 0) => \write_buffer.wr_buf_out_data_reg[5]\(3 downto 0),
      \write_buffer.wr_buf_out_data_reg[78]_0\(11 downto 0) => \write_buffer.wr_buf_out_data_reg[78]\(11 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_arb_mux is
  port (
    rnk_config_valid_r : out STD_LOGIC;
    granted_col_r_reg : out STD_LOGIC;
    insert_maint_r1_lcl_reg : out STD_LOGIC;
    DIC : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    rd_wr_r_lcl_reg : out STD_LOGIC;
    granted_col_r_reg_0 : out STD_LOGIC;
    granted_col_r_reg_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_odt_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \periodic_rd_generation.read_this_rank\ : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rd_wr_r_lcl_reg_0 : out STD_LOGIC;
    rd_wr_r_lcl_reg_1 : out STD_LOGIC;
    rd_wr_r_lcl_reg_2 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_aux_out0_1 : out STD_LOGIC;
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \grant_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
    \grant_r_reg[3]_1\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    col_wr_data_buf_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \grant_r_reg[3]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    granted_row_r_reg : out STD_LOGIC;
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_cs_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    override_demand_ns : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[3]_3\ : out STD_LOGIC;
    \grant_r_reg[3]_4\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rstdiv0_sync_r1_reg_rep__11\ : out STD_LOGIC;
    \grant_r_reg[3]_5\ : out STD_LOGIC;
    \wr_this_rank_r_reg[0]\ : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    act_this_rank : out STD_LOGIC;
    \grant_r_reg[3]_6\ : out STD_LOGIC;
    \grant_r_reg[3]_7\ : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    \genblk3[1].rnk_config_strobe_r_reg[1]\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    rnk_config_strobe_ns : in STD_LOGIC;
    rnk_config_valid_ns : in STD_LOGIC;
    insert_maint_r1_lcl_reg_0 : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC;
    cke_r_reg : in STD_LOGIC;
    cke_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \col_mux.col_periodic_rd_r_reg\ : in STD_LOGIC;
    granted_col_r_reg_2 : in STD_LOGIC;
    col_wait_r : in STD_LOGIC;
    \grant_r_reg[0]_0\ : in STD_LOGIC;
    \grant_r_reg[0]_1\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_odt_reg[0]\ : in STD_LOGIC;
    \grant_r_reg[0]_2\ : in STD_LOGIC;
    \grant_r_reg[0]_3\ : in STD_LOGIC;
    \grant_r_reg[2]_0\ : in STD_LOGIC;
    \grant_r_reg[0]_4\ : in STD_LOGIC;
    \grant_r_reg[2]_1\ : in STD_LOGIC;
    rd_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \grant_r_reg[1]_0\ : in STD_LOGIC;
    \grant_r_reg[2]_2\ : in STD_LOGIC;
    \grant_r_reg[1]_1\ : in STD_LOGIC;
    col_wait_r_0 : in STD_LOGIC;
    \grant_r[1]_i_3\ : in STD_LOGIC;
    \grant_r[3]_i_2\ : in STD_LOGIC;
    granted_col_r_reg_3 : in STD_LOGIC;
    granted_col_r_reg_4 : in STD_LOGIC;
    granted_col_r_reg_5 : in STD_LOGIC;
    granted_col_r_reg_6 : in STD_LOGIC;
    granted_col_r_reg_7 : in STD_LOGIC;
    \grant_r[3]_i_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_address_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \cmd_pipe_plus.mc_address_reg[9]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    auto_pre_r : in STD_LOGIC;
    auto_pre_r_1 : in STD_LOGIC;
    auto_pre_r_2 : in STD_LOGIC;
    auto_pre_r_3 : in STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[5]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    req_data_buf_addr_r : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    row_cmd_wr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[1]\ : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[38]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
    req_row_r : in STD_LOGIC_VECTOR ( 38 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_cas_n_reg[1]\ : in STD_LOGIC;
    maint_rank_r : in STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[1]_0\ : in STD_LOGIC;
    demand_act_priority_r : in STD_LOGIC;
    granted_row_r_reg_0 : in STD_LOGIC;
    granted_row_r_reg_1 : in STD_LOGIC;
    \grant_r_reg[0]_5\ : in STD_LOGIC;
    \grant_r_reg[0]_6\ : in STD_LOGIC;
    \grant_r_reg[0]_7\ : in STD_LOGIC;
    \grant_r_reg[2]_3\ : in STD_LOGIC;
    \grant_r_reg[3]_8\ : in STD_LOGIC;
    \grant_r_reg[3]_9\ : in STD_LOGIC;
    demand_act_priority_r_4 : in STD_LOGIC;
    demand_act_priority_r_5 : in STD_LOGIC;
    \grant_r_reg[3]_10\ : in STD_LOGIC;
    inhbt_act_faw_r : in STD_LOGIC;
    wr_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \last_master_r_reg[3]\ : in STD_LOGIC;
    act_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    demand_act_priority_r_6 : in STD_LOGIC;
    demand_priority_r : in STD_LOGIC;
    override_demand_r : in STD_LOGIC;
    demand_priority_r_7 : in STD_LOGIC;
    demanded_prior_r : in STD_LOGIC;
    demanded_prior_r_8 : in STD_LOGIC;
    demanded_prior_r_9 : in STD_LOGIC;
    demand_priority_r_10 : in STD_LOGIC;
    demanded_prior_r_11 : in STD_LOGIC;
    demand_priority_r_12 : in STD_LOGIC;
    ofs_rdy_r : in STD_LOGIC;
    ofs_rdy_r_13 : in STD_LOGIC;
    ofs_rdy_r_14 : in STD_LOGIC;
    ofs_rdy_r_15 : in STD_LOGIC;
    \grant_r[3]_i_5_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r[3]_i_8\ : in STD_LOGIC;
    \grant_r_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_arb_mux : entity is "mig_7series_v4_2_arb_mux";
end mig_7series_0_mig_7series_v4_2_arb_mux;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_arb_mux is
  signal \^dic\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \col_mux.col_periodic_rd_r\ : STD_LOGIC;
  signal \^col_rd_wr\ : STD_LOGIC;
  signal col_rd_wr_r : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal rnk_config_r : STD_LOGIC;
begin
  DIC(0) <= \^dic\(0);
  col_rd_wr <= \^col_rd_wr\;
arb_row_col0: entity work.mig_7series_0_mig_7series_v4_2_arb_row_col
     port map (
      CLK => CLK,
      DIC(0) => \^dic\(0),
      E(0) => E(0),
      Q(3 downto 0) => Q(3 downto 0),
      act_this_rank => act_this_rank,
      act_this_rank_r(3 downto 0) => act_this_rank_r(3 downto 0),
      act_wait_r_lcl_reg(2 downto 0) => act_wait_r_lcl_reg(2 downto 0),
      auto_pre_r => auto_pre_r,
      auto_pre_r_1 => auto_pre_r_1,
      auto_pre_r_2 => auto_pre_r_2,
      auto_pre_r_3 => auto_pre_r_3,
      \cmd_pipe_plus.mc_address_reg[23]\ => \cmd_pipe_plus.mc_address_reg[23]\,
      \cmd_pipe_plus.mc_address_reg[38]\(12 downto 0) => \cmd_pipe_plus.mc_address_reg[38]\(12 downto 0),
      \cmd_pipe_plus.mc_address_reg[9]\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[9]\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[9]_0\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[9]_0\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[9]_1\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[9]_1\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[9]_2\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[9]_2\(9 downto 0),
      \cmd_pipe_plus.mc_bank_reg[5]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[5]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[5]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[5]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]_0\(2 downto 0),
      \cmd_pipe_plus.mc_cas_n_reg[1]\ => \cmd_pipe_plus.mc_cas_n_reg[1]\,
      \cmd_pipe_plus.mc_data_offset_reg[2]\(1 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[2]\(1 downto 0),
      \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_odt_reg[0]\,
      \cmd_pipe_plus.mc_we_n_reg[1]\ => \cmd_pipe_plus.mc_we_n_reg[1]\,
      \cmd_pipe_plus.mc_we_n_reg[1]_0\ => \cmd_pipe_plus.mc_we_n_reg[1]_0\,
      \col_mux.col_periodic_rd_r\ => \col_mux.col_periodic_rd_r\,
      \col_mux.col_periodic_rd_r_reg\ => \col_mux.col_periodic_rd_r_reg\,
      col_rd_wr => \^col_rd_wr\,
      col_rd_wr_r => col_rd_wr_r,
      col_wait_r => col_wait_r,
      col_wait_r_0 => col_wait_r_0,
      col_wr_data_buf_addr(3 downto 0) => col_wr_data_buf_addr(3 downto 0),
      \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0),
      demand_act_priority_r => demand_act_priority_r,
      demand_act_priority_r_4 => demand_act_priority_r_4,
      demand_act_priority_r_5 => demand_act_priority_r_5,
      demand_act_priority_r_6 => demand_act_priority_r_6,
      demand_priority_r => demand_priority_r,
      demand_priority_r_10 => demand_priority_r_10,
      demand_priority_r_12 => demand_priority_r_12,
      demand_priority_r_7 => demand_priority_r_7,
      demanded_prior_r => demanded_prior_r,
      demanded_prior_r_11 => demanded_prior_r_11,
      demanded_prior_r_8 => demanded_prior_r_8,
      demanded_prior_r_9 => demanded_prior_r_9,
      demanded_prior_r_reg => demanded_prior_r_reg,
      demanded_prior_r_reg_0 => demanded_prior_r_reg_0,
      \genblk3[1].rnk_config_strobe_r_reg[1]_0\ => \genblk3[1].rnk_config_strobe_r_reg[1]\,
      \genblk3[2].rnk_config_strobe_r_reg[2]_0\ => override_demand_ns,
      \grant_r[1]_i_3\ => \grant_r[1]_i_3\,
      \grant_r[3]_i_2\ => \grant_r[3]_i_2\,
      \grant_r[3]_i_5\(0) => \grant_r[3]_i_5\(0),
      \grant_r[3]_i_5_0\(0) => \grant_r[3]_i_5_0\(0),
      \grant_r[3]_i_8\ => \grant_r[3]_i_8\,
      \grant_r_reg[0]\ => \grant_r_reg[0]\,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]_0\,
      \grant_r_reg[0]_1\ => \grant_r_reg[0]_1\,
      \grant_r_reg[0]_2\ => \grant_r_reg[0]_2\,
      \grant_r_reg[0]_3\ => \grant_r_reg[0]_3\,
      \grant_r_reg[0]_4\ => \grant_r_reg[0]_4\,
      \grant_r_reg[0]_5\ => \grant_r_reg[0]_5\,
      \grant_r_reg[0]_6\ => \grant_r_reg[0]_6\,
      \grant_r_reg[0]_7\ => \grant_r_reg[0]_7\,
      \grant_r_reg[1]\ => \grant_r_reg[1]\,
      \grant_r_reg[1]_0\ => \grant_r_reg[1]_0\,
      \grant_r_reg[1]_1\ => \grant_r_reg[1]_1\,
      \grant_r_reg[1]_2\(0) => \grant_r_reg[1]_2\(0),
      \grant_r_reg[2]\(1 downto 0) => \grant_r_reg[2]\(1 downto 0),
      \grant_r_reg[2]_0\ => \grant_r_reg[2]_0\,
      \grant_r_reg[2]_1\ => \grant_r_reg[2]_1\,
      \grant_r_reg[2]_2\ => \grant_r_reg[2]_2\,
      \grant_r_reg[2]_3\ => \grant_r_reg[2]_3\,
      \grant_r_reg[3]\ => \grant_r_reg[3]\,
      \grant_r_reg[3]_0\(36 downto 0) => \grant_r_reg[3]_0\(36 downto 0),
      \grant_r_reg[3]_1\(8 downto 0) => \grant_r_reg[3]_1\(8 downto 0),
      \grant_r_reg[3]_10\ => \grant_r_reg[3]_10\,
      \grant_r_reg[3]_2\(3 downto 0) => \grant_r_reg[3]_2\(3 downto 0),
      \grant_r_reg[3]_3\ => \grant_r_reg[3]_3\,
      \grant_r_reg[3]_4\(3 downto 0) => \grant_r_reg[3]_4\(3 downto 0),
      \grant_r_reg[3]_5\ => \grant_r_reg[3]_5\,
      \grant_r_reg[3]_6\ => \grant_r_reg[3]_6\,
      \grant_r_reg[3]_7\ => \grant_r_reg[3]_7\,
      \grant_r_reg[3]_8\ => \grant_r_reg[3]_8\,
      \grant_r_reg[3]_9\ => \grant_r_reg[3]_9\,
      granted_col_r_reg_0 => granted_col_r_reg,
      granted_col_r_reg_1 => granted_col_r_reg_0,
      granted_col_r_reg_2(1 downto 0) => granted_col_r_reg_1(1 downto 0),
      granted_col_r_reg_3 => granted_col_r_reg_2,
      granted_col_r_reg_4 => granted_col_r_reg_3,
      granted_col_r_reg_5 => granted_col_r_reg_4,
      granted_col_r_reg_6 => granted_col_r_reg_5,
      granted_col_r_reg_7 => granted_col_r_reg_6,
      granted_col_r_reg_8 => granted_col_r_reg_7,
      granted_row_r_reg_0 => granted_row_r_reg,
      granted_row_r_reg_1 => granted_row_r_reg_0,
      granted_row_r_reg_2 => granted_row_r_reg_1,
      inhbt_act_faw_r => inhbt_act_faw_r,
      insert_maint_r1_lcl_reg_0 => insert_maint_r1_lcl_reg,
      insert_maint_r1_lcl_reg_1 => insert_maint_r1_lcl_reg_0,
      \last_master_r_reg[3]\ => \last_master_r_reg[3]\,
      maint_rank_r => maint_rank_r,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      mc_aux_out0_1 => mc_aux_out0_1,
      mc_cas_n_ns(2 downto 0) => mc_cas_n_ns(2 downto 0),
      mc_cs_n_ns(0) => mc_cs_n_ns(0),
      mc_odt_ns(0) => mc_odt_ns(0),
      mc_ras_n_ns(2 downto 0) => mc_ras_n_ns(2 downto 0),
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r_13 => ofs_rdy_r_13,
      ofs_rdy_r_14 => ofs_rdy_r_14,
      ofs_rdy_r_15 => ofs_rdy_r_15,
      override_demand_r => override_demand_r,
      p_0_in => p_0_in,
      \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\,
      \pre_4_1_1T_arb.granted_pre_r_reg_0\ => \pre_4_1_1T_arb.granted_pre_r_reg\,
      rd_this_rank_r(3 downto 0) => rd_this_rank_r(3 downto 0),
      rd_wr_r(3 downto 0) => rd_wr_r(3 downto 0),
      rd_wr_r_lcl_reg => rd_wr_r_lcl_reg,
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg_0,
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_1,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_2,
      req_data_buf_addr_r(15 downto 0) => req_data_buf_addr_r(15 downto 0),
      req_periodic_rd_r(3 downto 0) => req_periodic_rd_r(3 downto 0),
      req_row_r(38 downto 0) => req_row_r(38 downto 0),
      rnk_config_r => rnk_config_r,
      rnk_config_strobe_ns => rnk_config_strobe_ns,
      rnk_config_valid_ns => rnk_config_valid_ns,
      rnk_config_valid_r_lcl_reg_0 => rnk_config_valid_r,
      row_cmd_wr(3 downto 0) => row_cmd_wr(3 downto 0),
      \rstdiv0_sync_r1_reg_rep__11\ => \rstdiv0_sync_r1_reg_rep__11\,
      wr_this_rank_r(3 downto 0) => wr_this_rank_r(3 downto 0),
      \wr_this_rank_r_reg[0]\ => \wr_this_rank_r_reg[0]\
    );
arb_select0: entity work.mig_7series_0_mig_7series_v4_2_arb_select
     port map (
      CLK => CLK,
      D(0) => D(0),
      DIC(0) => \^dic\(0),
      cke_r_reg_0 => cke_r_reg,
      cke_r_reg_1(0) => cke_r_reg_0(0),
      \col_mux.col_periodic_rd_r\ => \col_mux.col_periodic_rd_r\,
      col_rd_wr => \^col_rd_wr\,
      col_rd_wr_r => col_rd_wr_r,
      p_0_in => p_0_in,
      rnk_config_r => rnk_config_r
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_phy_4lanes is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mem_dqs_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mem_dqs_ts : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC;
    A_rst_primitives_reg_1 : out STD_LOGIC;
    out_dq_2 : out STD_LOGIC;
    mem_dq_ts : out STD_LOGIC_VECTOR ( 17 downto 0 );
    out_dm_0 : out STD_LOGIC;
    out_dq_0 : out STD_LOGIC;
    out_dq_6 : out STD_LOGIC;
    out_dq_3 : out STD_LOGIC;
    out_dq_1 : out STD_LOGIC;
    out_dq_4 : out STD_LOGIC;
    out_dq_7 : out STD_LOGIC;
    out_dq_5 : out STD_LOGIC;
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rd_ptr_reg[0]\ : out STD_LOGIC;
    \rd_ptr_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[2]\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC;
    \rd_ptr_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    \rd_ptr_reg[2]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg_2 : out STD_LOGIC;
    out_dq_13 : out STD_LOGIC;
    out_dq_8 : out STD_LOGIC;
    out_dq_15 : out STD_LOGIC;
    out_dq_12 : out STD_LOGIC;
    out_dq_10 : out STD_LOGIC;
    out_dq_9 : out STD_LOGIC;
    out_dq_11 : out STD_LOGIC;
    out_dq_14 : out STD_LOGIC;
    out_dm_1 : out STD_LOGIC;
    \rd_ptr_reg[0]_1\ : out STD_LOGIC;
    \rd_ptr_reg[1]_1\ : out STD_LOGIC;
    \rd_ptr_reg[2]_1\ : out STD_LOGIC;
    \rd_ptr_reg[3]_1\ : out STD_LOGIC;
    phy_mc_ctl_full : out STD_LOGIC;
    ref_dll_lock : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_empty_reg[1]\ : out STD_LOGIC;
    init_complete_r1_timing_reg : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    \my_empty_reg[1]_2\ : out STD_LOGIC;
    \FSM_onehot_cal1_state_r_reg[13]\ : out STD_LOGIC;
    \pi_counter_read_val_reg[5]_0\ : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    \my_empty_reg[0]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 65 downto 0 );
    app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ : out STD_LOGIC;
    \pi_counter_read_val_reg[5]_1\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_rddata_en : out STD_LOGIC;
    in0 : out STD_LOGIC;
    phy_mc_data_full : out STD_LOGIC;
    wr_en_2 : out STD_LOGIC;
    wr_en_3 : out STD_LOGIC;
    phy_mc_cmd_full : out STD_LOGIC;
    wr_en_4 : out STD_LOGIC;
    \wr_ptr_reg[0]\ : out STD_LOGIC;
    \wr_ptr_reg[1]\ : out STD_LOGIC;
    \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \wr_ptr_reg[0]_0\ : out STD_LOGIC;
    \wr_ptr_reg[1]_0\ : out STD_LOGIC;
    \wr_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    A_rst_primitives_reg_3 : out STD_LOGIC_VECTOR ( 9 downto 0 );
    mem_out : out STD_LOGIC_VECTOR ( 30 downto 0 );
    wr_en : out STD_LOGIC;
    p_1_in : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_61\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_62\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[0]_3\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \slave_ts.oserdes_slave_ts\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_0\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_1\ : in STD_LOGIC;
    D1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D9 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ififo_rst_reg0 : in STD_LOGIC;
    ofifo_rst_reg0 : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC;
    out_fifo_2 : in STD_LOGIC;
    \my_empty_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \my_empty_reg[6]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[6]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[6]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \input_[8].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    LD0_0 : in STD_LOGIC;
    CLKB0_5 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_2\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_3\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_4\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \slave_ts.oserdes_slave_ts_2\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_3\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_4\ : in STD_LOGIC;
    D0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ififo_rst_reg0_1 : in STD_LOGIC;
    ofifo_rst_reg0_2 : in STD_LOGIC;
    phy_ctl_wr_i2 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
    RST0 : in STD_LOGIC;
    rst_out_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_reg[3]_6\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \rd_ptr_reg[3]_7\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_reg[3]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_9\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_ptr_timing_reg[0]\ : in STD_LOGIC;
    calib_cmd_wren : in STD_LOGIC;
    app_rd_data_valid_0 : in STD_LOGIC;
    mux_wrdata_en : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC;
    calib_wrdata_en : in STD_LOGIC;
    out_fifo_3 : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_1\ : in STD_LOGIC;
    out_fifo_4 : in STD_LOGIC_VECTOR ( 32 downto 0 );
    \cnt_idel_dec_cpt_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    out_fifo_5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    app_rd_data_valid_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.tail_r_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    mux_cmd_wren : in STD_LOGIC;
    out_fifo_7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \app_rd_data[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    calib_sel : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_phy_4lanes : entity is "mig_7series_v4_2_ddr_phy_4lanes";
end mig_7series_0_mig_7series_v4_2_ddr_phy_4lanes;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_phy_4lanes is
  signal A_pi_rst_div2 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of A_pi_rst_div2 : signal is "true";
  signal \^a_rst_primitives_reg_0\ : STD_LOGIC;
  signal B_pi_rst_div2 : STD_LOGIC;
  attribute async_reg of B_pi_rst_div2 : signal is "true";
  signal C_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal C_pi_rst_div2 : STD_LOGIC;
  attribute async_reg of C_pi_rst_div2 : signal is "true";
  signal D_of_full : STD_LOGIC;
  signal D_pi_rst_div2 : STD_LOGIC;
  attribute async_reg of D_pi_rst_div2 : signal is "true";
  signal \^app_rd_data\ : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_176\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_177\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_178\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_179\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_180\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_181\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C_n_24\ : STD_LOGIC;
  signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_empty_r : STD_LOGIC_VECTOR ( 3 to 3 );
  signal if_empty_r_1 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal ofifo_rst : STD_LOGIC;
  signal phaser_ctl_bus : STD_LOGIC_VECTOR ( 3 to 3 );
  signal phy_control_i_n_0 : STD_LOGIC;
  signal phy_control_i_n_1 : STD_LOGIC;
  signal phy_control_i_n_10 : STD_LOGIC;
  signal phy_control_i_n_11 : STD_LOGIC;
  signal phy_control_i_n_14 : STD_LOGIC;
  signal phy_control_i_n_15 : STD_LOGIC;
  signal phy_control_i_n_16 : STD_LOGIC;
  signal phy_control_i_n_17 : STD_LOGIC;
  signal phy_control_i_n_18 : STD_LOGIC;
  signal phy_control_i_n_19 : STD_LOGIC;
  signal phy_control_i_n_20 : STD_LOGIC;
  signal phy_control_i_n_21 : STD_LOGIC;
  signal phy_control_i_n_23 : STD_LOGIC;
  signal phy_control_i_n_24 : STD_LOGIC;
  signal phy_control_i_n_25 : STD_LOGIC;
  signal phy_control_i_n_3 : STD_LOGIC;
  signal phy_control_i_n_4 : STD_LOGIC;
  signal phy_control_i_n_5 : STD_LOGIC;
  signal phy_control_i_n_6 : STD_LOGIC;
  signal phy_control_i_n_7 : STD_LOGIC;
  signal phy_control_i_n_8 : STD_LOGIC;
  signal phy_control_i_n_9 : STD_LOGIC;
  signal phy_encalib : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^pi_counter_read_val_reg[5]_0\ : STD_LOGIC;
  signal \^pi_counter_read_val_reg[5]_1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rclk_delay_11 : STD_LOGIC;
  signal \rclk_delay_reg[10]_srl11_i_1_n_0\ : STD_LOGIC;
  signal \rclk_delay_reg[10]_srl11_n_0\ : STD_LOGIC;
  signal \^ref_dll_lock\ : STD_LOGIC;
  signal rst_out_i_1_n_0 : STD_LOGIC;
  signal rst_out_reg_n_0 : STD_LOGIC;
  signal rst_primitives : STD_LOGIC;
  signal rst_primitives_i_1_n_0 : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of phaser_ref_i : label is "PRIMITIVE";
  attribute BOX_TYPE of phy_control_i : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg ";
  attribute srl_name : string;
  attribute srl_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 ";
begin
  A_rst_primitives_reg_0 <= \^a_rst_primitives_reg_0\;
  app_rd_data(127 downto 0) <= \^app_rd_data\(127 downto 0);
  \pi_counter_read_val_reg[5]_0\ <= \^pi_counter_read_val_reg[5]_0\;
  \pi_counter_read_val_reg[5]_1\(5 downto 0) <= \^pi_counter_read_val_reg[5]_1\(5 downto 0);
  ref_dll_lock <= \^ref_dll_lock\;
A_rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rst_primitives,
      Q => \^a_rst_primitives_reg_0\,
      R => '0'
    );
\FSM_onehot_cal1_state_r[16]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^pi_counter_read_val_reg[5]_1\(5),
      I1 => \^pi_counter_read_val_reg[5]_1\(1),
      I2 => \^pi_counter_read_val_reg[5]_1\(2),
      I3 => \^pi_counter_read_val_reg[5]_1\(3),
      I4 => \^pi_counter_read_val_reg[5]_1\(0),
      I5 => \^pi_counter_read_val_reg[5]_1\(4),
      O => \^pi_counter_read_val_reg[5]_0\
    );
\FSM_onehot_cal1_state_r[34]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pi_counter_read_val_reg[5]_0\,
      I1 => \cnt_idel_dec_cpt_r_reg[0]\(0),
      O => \FSM_onehot_cal1_state_r_reg[13]\
    );
\ddr_byte_lane_A.ddr_byte_lane_A\: entity work.mig_7series_0_mig_7series_v4_2_ddr_byte_lane
     port map (
      A_rst_primitives_reg => A_rst_primitives_reg_1,
      CLK => CLK,
      CLKB0 => CLKB0,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      COUNTERREADVAL(5 downto 0) => C_pi_counter_read_val(5 downto 0),
      D(5) => \ddr_byte_lane_A.ddr_byte_lane_A_n_176\,
      D(4) => \ddr_byte_lane_A.ddr_byte_lane_A_n_177\,
      D(3) => \ddr_byte_lane_A.ddr_byte_lane_A_n_178\,
      D(2) => \ddr_byte_lane_A.ddr_byte_lane_A_n_179\,
      D(1) => \ddr_byte_lane_A.ddr_byte_lane_A_n_180\,
      D(0) => \ddr_byte_lane_A.ddr_byte_lane_A_n_181\,
      D1(7 downto 0) => D1(7 downto 0),
      D2(7 downto 0) => D2(7 downto 0),
      D3(7 downto 0) => D3(7 downto 0),
      D4(7 downto 0) => D4(7 downto 0),
      D5(7 downto 0) => D5(7 downto 0),
      D6(7 downto 0) => D6(7 downto 0),
      D7(7 downto 0) => D7(7 downto 0),
      D8(7 downto 0) => D8(7 downto 0),
      D9(7 downto 0) => D9(7 downto 0),
      INBURSTPENDING(0) => phy_control_i_n_21,
      INRANKA(1) => phy_control_i_n_4,
      INRANKA(0) => phy_control_i_n_5,
      LD0 => LD0,
      OUTBURSTPENDING(0) => phy_control_i_n_25,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(4 downto 2),
      app_rd_data(63 downto 56) => \^app_rd_data\(119 downto 112),
      app_rd_data(55 downto 48) => \^app_rd_data\(103 downto 96),
      app_rd_data(47 downto 40) => \^app_rd_data\(87 downto 80),
      app_rd_data(39 downto 32) => \^app_rd_data\(71 downto 64),
      app_rd_data(31 downto 24) => \^app_rd_data\(55 downto 48),
      app_rd_data(23 downto 16) => \^app_rd_data\(39 downto 32),
      app_rd_data(15 downto 8) => \^app_rd_data\(23 downto 16),
      app_rd_data(7 downto 0) => \^app_rd_data\(7 downto 0),
      \app_rd_data[117]\(63 downto 0) => \app_rd_data[117]\(63 downto 0),
      app_rd_data_valid => app_rd_data_valid,
      app_rd_data_valid_0 => app_rd_data_valid_0,
      app_rd_data_valid_1(0) => app_rd_data_valid_1(0),
      calib_sel(0) => calib_sel(0),
      calib_wrdata_en => calib_wrdata_en,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(67 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0),
      freq_refclk => freq_refclk,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(63 downto 56) => \^app_rd_data\(127 downto 120),
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(55 downto 48) => \^app_rd_data\(111 downto 104),
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(47 downto 40) => \^app_rd_data\(95 downto 88),
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(39 downto 32) => \^app_rd_data\(79 downto 72),
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(31 downto 24) => \^app_rd_data\(63 downto 56),
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(23 downto 16) => \^app_rd_data\(47 downto 40),
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(15 downto 8) => \^app_rd_data\(31 downto 24),
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(7 downto 0) => \^app_rd_data\(15 downto 8),
      idelay_inc => idelay_inc,
      if_empty_r(0) => if_empty_r(3),
      if_empty_r_0(0) => if_empty_r_1(3),
      ififo_rst_reg0 => ififo_rst_reg0,
      in0 => in0,
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq\,
      mc_wrdata_en => mc_wrdata_en,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      mem_dqs_in(0) => mem_dqs_in(0),
      mem_dqs_out(0) => mem_dqs_out(0),
      mem_dqs_ts(0) => mem_dqs_ts(0),
      mem_refclk => mem_refclk,
      mux_wrdata_en => mux_wrdata_en,
      my_empty(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\(3),
      my_empty(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\(0),
      \my_empty_reg[0]\ => \my_empty_reg[0]\,
      \my_empty_reg[1]\ => \my_empty_reg[1]_0\,
      \my_empty_reg[3]\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(3),
      \my_empty_reg[3]\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0),
      ofifo_rst_reg0 => ofifo_rst_reg0,
      \out\(1 downto 0) => \out\(1 downto 0),
      out_dm_0 => out_dm_0,
      out_dq_0 => out_dq_0,
      out_dq_1 => out_dq_1,
      out_dq_2 => out_dq_2,
      out_dq_3 => out_dq_3,
      out_dq_4 => out_dq_4,
      out_dq_5 => out_dq_5,
      out_dq_6 => out_dq_6,
      out_dq_7 => out_dq_7,
      out_fifo_0(7 downto 0) => out_fifo_5(7 downto 0),
      p_1_in => p_1_in,
      phy_mc_data_full => phy_mc_data_full,
      pi_dqs_found_lanes(0) => pi_dqs_found_lanes(0),
      \pi_dqs_found_lanes_r1_reg[0]\ => \^a_rst_primitives_reg_0\,
      \pi_dqs_found_lanes_r1_reg[0]_0\ => \pi_dqs_found_lanes_r1_reg[0]\,
      \pi_dqs_found_lanes_r1_reg[0]_1\ => \pi_dqs_found_lanes_r1_reg[0]_0\,
      \pi_dqs_found_lanes_r1_reg[0]_2\ => \pi_dqs_found_lanes_r1_reg[0]_1\,
      \pi_dqs_found_lanes_r1_reg[0]_3\ => \pi_dqs_found_lanes_r1_reg[0]_2\,
      \pi_dqs_found_lanes_r1_reg[0]_4\ => \pi_dqs_found_lanes_r1_reg[0]_3\,
      pi_phase_locked_all_r1_reg => \ddr_byte_lane_C.ddr_byte_lane_C_n_24\,
      \po_stg2_wrcal_cnt_reg[0]\ => \po_stg2_wrcal_cnt_reg[0]\,
      \po_stg2_wrcal_cnt_reg[0]_0\ => \po_stg2_wrcal_cnt_reg[0]_0\,
      \po_stg2_wrcal_cnt_reg[0]_1\ => \po_stg2_wrcal_cnt_reg[0]_1\,
      \po_stg2_wrcal_cnt_reg[0]_10\ => \po_stg2_wrcal_cnt_reg[0]_10\,
      \po_stg2_wrcal_cnt_reg[0]_11\ => \po_stg2_wrcal_cnt_reg[0]_11\,
      \po_stg2_wrcal_cnt_reg[0]_12\ => \po_stg2_wrcal_cnt_reg[0]_12\,
      \po_stg2_wrcal_cnt_reg[0]_13\ => \po_stg2_wrcal_cnt_reg[0]_13\,
      \po_stg2_wrcal_cnt_reg[0]_14\ => \po_stg2_wrcal_cnt_reg[0]_14\,
      \po_stg2_wrcal_cnt_reg[0]_15\ => \po_stg2_wrcal_cnt_reg[0]_15\,
      \po_stg2_wrcal_cnt_reg[0]_16\ => \po_stg2_wrcal_cnt_reg[0]_16\,
      \po_stg2_wrcal_cnt_reg[0]_17\ => \po_stg2_wrcal_cnt_reg[0]_17\,
      \po_stg2_wrcal_cnt_reg[0]_18\ => \po_stg2_wrcal_cnt_reg[0]_18\,
      \po_stg2_wrcal_cnt_reg[0]_19\ => \po_stg2_wrcal_cnt_reg[0]_19\,
      \po_stg2_wrcal_cnt_reg[0]_2\ => \po_stg2_wrcal_cnt_reg[0]_2\,
      \po_stg2_wrcal_cnt_reg[0]_20\ => \po_stg2_wrcal_cnt_reg[0]_20\,
      \po_stg2_wrcal_cnt_reg[0]_21\ => \po_stg2_wrcal_cnt_reg[0]_21\,
      \po_stg2_wrcal_cnt_reg[0]_22\ => \po_stg2_wrcal_cnt_reg[0]_22\,
      \po_stg2_wrcal_cnt_reg[0]_23\ => \po_stg2_wrcal_cnt_reg[0]_23\,
      \po_stg2_wrcal_cnt_reg[0]_24\ => \po_stg2_wrcal_cnt_reg[0]_24\,
      \po_stg2_wrcal_cnt_reg[0]_25\ => \po_stg2_wrcal_cnt_reg[0]_25\,
      \po_stg2_wrcal_cnt_reg[0]_26\ => \po_stg2_wrcal_cnt_reg[0]_26\,
      \po_stg2_wrcal_cnt_reg[0]_27\ => \po_stg2_wrcal_cnt_reg[0]_27\,
      \po_stg2_wrcal_cnt_reg[0]_28\ => \po_stg2_wrcal_cnt_reg[0]_28\,
      \po_stg2_wrcal_cnt_reg[0]_29\ => \po_stg2_wrcal_cnt_reg[0]_29\,
      \po_stg2_wrcal_cnt_reg[0]_3\ => \po_stg2_wrcal_cnt_reg[0]_3\,
      \po_stg2_wrcal_cnt_reg[0]_30\ => \po_stg2_wrcal_cnt_reg[0]_30\,
      \po_stg2_wrcal_cnt_reg[0]_31\ => \po_stg2_wrcal_cnt_reg[0]_31\,
      \po_stg2_wrcal_cnt_reg[0]_32\ => \po_stg2_wrcal_cnt_reg[0]_32\,
      \po_stg2_wrcal_cnt_reg[0]_33\ => \po_stg2_wrcal_cnt_reg[0]_33\,
      \po_stg2_wrcal_cnt_reg[0]_34\ => \po_stg2_wrcal_cnt_reg[0]_34\,
      \po_stg2_wrcal_cnt_reg[0]_35\ => \po_stg2_wrcal_cnt_reg[0]_35\,
      \po_stg2_wrcal_cnt_reg[0]_36\ => \po_stg2_wrcal_cnt_reg[0]_36\,
      \po_stg2_wrcal_cnt_reg[0]_37\ => \po_stg2_wrcal_cnt_reg[0]_37\,
      \po_stg2_wrcal_cnt_reg[0]_38\ => \po_stg2_wrcal_cnt_reg[0]_38\,
      \po_stg2_wrcal_cnt_reg[0]_39\ => \po_stg2_wrcal_cnt_reg[0]_39\,
      \po_stg2_wrcal_cnt_reg[0]_4\ => \po_stg2_wrcal_cnt_reg[0]_4\,
      \po_stg2_wrcal_cnt_reg[0]_40\ => \po_stg2_wrcal_cnt_reg[0]_40\,
      \po_stg2_wrcal_cnt_reg[0]_41\ => \po_stg2_wrcal_cnt_reg[0]_41\,
      \po_stg2_wrcal_cnt_reg[0]_42\ => \po_stg2_wrcal_cnt_reg[0]_42\,
      \po_stg2_wrcal_cnt_reg[0]_43\ => \po_stg2_wrcal_cnt_reg[0]_43\,
      \po_stg2_wrcal_cnt_reg[0]_44\ => \po_stg2_wrcal_cnt_reg[0]_44\,
      \po_stg2_wrcal_cnt_reg[0]_45\ => \po_stg2_wrcal_cnt_reg[0]_45\,
      \po_stg2_wrcal_cnt_reg[0]_46\ => \po_stg2_wrcal_cnt_reg[0]_46\,
      \po_stg2_wrcal_cnt_reg[0]_47\ => \po_stg2_wrcal_cnt_reg[0]_47\,
      \po_stg2_wrcal_cnt_reg[0]_48\ => \po_stg2_wrcal_cnt_reg[0]_48\,
      \po_stg2_wrcal_cnt_reg[0]_49\ => \po_stg2_wrcal_cnt_reg[0]_49\,
      \po_stg2_wrcal_cnt_reg[0]_5\ => \po_stg2_wrcal_cnt_reg[0]_5\,
      \po_stg2_wrcal_cnt_reg[0]_50\ => \po_stg2_wrcal_cnt_reg[0]_50\,
      \po_stg2_wrcal_cnt_reg[0]_51\ => \po_stg2_wrcal_cnt_reg[0]_51\,
      \po_stg2_wrcal_cnt_reg[0]_52\ => \po_stg2_wrcal_cnt_reg[0]_52\,
      \po_stg2_wrcal_cnt_reg[0]_53\ => \po_stg2_wrcal_cnt_reg[0]_53\,
      \po_stg2_wrcal_cnt_reg[0]_54\ => \po_stg2_wrcal_cnt_reg[0]_54\,
      \po_stg2_wrcal_cnt_reg[0]_55\ => \po_stg2_wrcal_cnt_reg[0]_55\,
      \po_stg2_wrcal_cnt_reg[0]_56\ => \po_stg2_wrcal_cnt_reg[0]_56\,
      \po_stg2_wrcal_cnt_reg[0]_57\ => \po_stg2_wrcal_cnt_reg[0]_57\,
      \po_stg2_wrcal_cnt_reg[0]_58\ => \po_stg2_wrcal_cnt_reg[0]_58\,
      \po_stg2_wrcal_cnt_reg[0]_59\ => \po_stg2_wrcal_cnt_reg[0]_59\,
      \po_stg2_wrcal_cnt_reg[0]_6\ => \po_stg2_wrcal_cnt_reg[0]_6\,
      \po_stg2_wrcal_cnt_reg[0]_60\ => \po_stg2_wrcal_cnt_reg[0]_60\,
      \po_stg2_wrcal_cnt_reg[0]_61\ => \po_stg2_wrcal_cnt_reg[0]_61\,
      \po_stg2_wrcal_cnt_reg[0]_62\ => \po_stg2_wrcal_cnt_reg[0]_62\,
      \po_stg2_wrcal_cnt_reg[0]_7\ => \po_stg2_wrcal_cnt_reg[0]_7\,
      \po_stg2_wrcal_cnt_reg[0]_8\ => \po_stg2_wrcal_cnt_reg[0]_8\,
      \po_stg2_wrcal_cnt_reg[0]_9\ => \po_stg2_wrcal_cnt_reg[0]_9\,
      \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\,
      \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\,
      \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\,
      \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\,
      \read_fifo.tail_r_reg[4]\(0) => \read_fifo.tail_r_reg[4]\(0),
      \slave_ts.oserdes_slave_ts\ => \slave_ts.oserdes_slave_ts\,
      \slave_ts.oserdes_slave_ts_0\ => \slave_ts.oserdes_slave_ts_0\,
      \slave_ts.oserdes_slave_ts_1\ => \slave_ts.oserdes_slave_ts_1\,
      sync_pulse => sync_pulse,
      wr_en_3 => wr_en_3,
      \wr_ptr_reg[0]\ => \wr_ptr_reg[0]\,
      \wr_ptr_reg[1]\ => \wr_ptr_reg[1]\,
      \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0),
      \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]_0\
    );
\ddr_byte_lane_B.ddr_byte_lane_B\: entity work.\mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized0\
     port map (
      CLK => CLK,
      D_of_full => D_of_full,
      OUTBURSTPENDING(0) => phy_control_i_n_24,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0),
      calib_cmd_wren => calib_cmd_wren,
      freq_refclk => freq_refclk,
      mem_dq_out(11 downto 0) => mem_dq_out(11 downto 0),
      mem_refclk => mem_refclk,
      mux_cmd_wren => mux_cmd_wren,
      \my_empty_reg[1]\ => \my_empty_reg[1]_2\,
      \my_empty_reg[6]\(3 downto 0) => \my_empty_reg[6]\(3 downto 0),
      \my_empty_reg[6]_0\(3 downto 0) => \my_empty_reg[6]_0\(3 downto 0),
      \my_empty_reg[6]_1\(3 downto 0) => \my_empty_reg[6]_1\(3 downto 0),
      \my_empty_reg[6]_2\(3 downto 0) => \my_empty_reg[6]_2\(3 downto 0),
      \my_empty_reg[6]_3\(2 downto 0) => \my_empty_reg[6]_3\(2 downto 0),
      \my_empty_reg[6]_4\(7 downto 0) => \my_empty_reg[6]_4\(7 downto 0),
      \my_empty_reg[6]_5\(7 downto 0) => \my_empty_reg[6]_5\(7 downto 0),
      \my_empty_reg[6]_6\(3 downto 0) => \my_empty_reg[6]_6\(3 downto 0),
      \my_empty_reg[6]_7\(3 downto 0) => \my_empty_reg[6]_7\(3 downto 0),
      \my_empty_reg[6]_8\(3 downto 0) => \my_empty_reg[6]_8\(3 downto 0),
      ofifo_rst => ofifo_rst,
      ofifo_rst_reg_0 => \^a_rst_primitives_reg_0\,
      out_fifo_0 => out_fifo,
      out_fifo_1 => out_fifo_0,
      out_fifo_2 => out_fifo_1,
      out_fifo_3 => out_fifo_2,
      out_fifo_4(32 downto 0) => out_fifo_4(32 downto 0),
      phy_mc_cmd_full => phy_mc_cmd_full,
      \rd_ptr_reg[0]\ => \rd_ptr_reg[0]_0\,
      \rd_ptr_reg[1]\ => \rd_ptr_reg[1]_0\,
      \rd_ptr_reg[2]\ => \rd_ptr_reg[2]_0\,
      \rd_ptr_reg[3]\ => \rd_ptr_reg[3]_0\,
      sync_pulse => sync_pulse,
      wr_en_4 => wr_en_4,
      \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]_1\
    );
\ddr_byte_lane_C.ddr_byte_lane_C\: entity work.\mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized1\
     port map (
      A_rst_primitives_reg => A_rst_primitives_reg_2,
      A_rst_primitives_reg_0 => \ddr_byte_lane_C.ddr_byte_lane_C_n_24\,
      CLK => CLK,
      CLKB0_5 => CLKB0_5,
      COUNTERREADVAL(5 downto 0) => C_pi_counter_read_val(5 downto 0),
      D0(7 downto 0) => D0(7 downto 0),
      INBURSTPENDING(0) => phy_control_i_n_19,
      INRANKC(1) => phy_control_i_n_8,
      INRANKC(0) => phy_control_i_n_9,
      LD0_0 => LD0_0,
      OUTBURSTPENDING(0) => phy_control_i_n_23,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(4 downto 2),
      app_rd_data(63 downto 56) => \^app_rd_data\(119 downto 112),
      app_rd_data(55 downto 48) => \^app_rd_data\(103 downto 96),
      app_rd_data(47 downto 40) => \^app_rd_data\(87 downto 80),
      app_rd_data(39 downto 32) => \^app_rd_data\(71 downto 64),
      app_rd_data(31 downto 24) => \^app_rd_data\(55 downto 48),
      app_rd_data(23 downto 16) => \^app_rd_data\(39 downto 32),
      app_rd_data(15 downto 8) => \^app_rd_data\(23 downto 16),
      app_rd_data(7 downto 0) => \^app_rd_data\(7 downto 0),
      calib_wrdata_en => calib_wrdata_en,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(63 downto 56) => \^app_rd_data\(127 downto 120),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(55 downto 48) => \^app_rd_data\(111 downto 104),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(47 downto 40) => \^app_rd_data\(95 downto 88),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(39 downto 32) => \^app_rd_data\(79 downto 72),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(31 downto 24) => \^app_rd_data\(63 downto 56),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(23 downto 16) => \^app_rd_data\(47 downto 40),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(15 downto 8) => \^app_rd_data\(31 downto 24),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(7 downto 0) => \^app_rd_data\(15 downto 8),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(65 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0) => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0),
      idelay_inc => idelay_inc,
      idelay_ld_rst => idelay_ld_rst,
      idelay_ld_rst_reg => \^a_rst_primitives_reg_0\,
      if_empty_r(0) => if_empty_r_1(3),
      if_empty_r_0(0) => if_empty_r(3),
      ififo_rst_reg0_1 => ififo_rst_reg0_1,
      init_complete_r1_timing_reg => init_complete_r1_timing_reg,
      \input_[8].iserdes_dq_.iserdesdq\ => \input_[8].iserdes_dq_.iserdesdq\,
      mc_wrdata_en => mc_wrdata_en,
      mem_dq_in(7 downto 0) => mem_dq_in(15 downto 8),
      mem_dq_ts(8 downto 0) => mem_dq_ts(17 downto 9),
      mem_dqs_in(0) => mem_dqs_in(1),
      mem_dqs_out(0) => mem_dqs_out(1),
      mem_dqs_ts(0) => mem_dqs_ts(1),
      mem_refclk => mem_refclk,
      mux_wrdata_en => mux_wrdata_en,
      \my_empty_reg[1]\ => \my_empty_reg[1]_1\,
      \my_empty_reg[3]\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\(3),
      \my_empty_reg[3]\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\(0),
      \my_empty_reg[4]_rep__1\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(3),
      \my_empty_reg[4]_rep__1\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0),
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      ofifo_rst_reg0_2 => ofifo_rst_reg0_2,
      out_dm_1 => out_dm_1,
      out_dq_10 => out_dq_10,
      out_dq_11 => out_dq_11,
      out_dq_12 => out_dq_12,
      out_dq_13 => out_dq_13,
      out_dq_14 => out_dq_14,
      out_dq_15 => out_dq_15,
      out_dq_8 => out_dq_8,
      out_dq_9 => out_dq_9,
      out_fifo_0 => out_fifo_3,
      out_fifo_1(7 downto 0) => out_fifo_6(7 downto 0),
      phy_rddata_en => phy_rddata_en,
      pi_dqs_found_lanes(0) => pi_dqs_found_lanes(1),
      \pi_dqs_found_lanes_r1_reg[2]\ => \pi_dqs_found_lanes_r1_reg[2]\,
      \pi_dqs_found_lanes_r1_reg[2]_0\ => \pi_dqs_found_lanes_r1_reg[2]_0\,
      \pi_dqs_found_lanes_r1_reg[2]_1\ => \pi_dqs_found_lanes_r1_reg[2]_1\,
      \pi_dqs_found_lanes_r1_reg[2]_2\ => \pi_dqs_found_lanes_r1_reg[2]_2\,
      \pi_dqs_found_lanes_r1_reg[2]_3\ => \pi_dqs_found_lanes_r1_reg[2]_3\,
      \pi_dqs_found_lanes_r1_reg[2]_4\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[2]_4\(5 downto 0),
      \rd_ptr_reg[0]\ => \rd_ptr_reg[0]_1\,
      \rd_ptr_reg[1]\ => \rd_ptr_reg[1]_1\,
      \rd_ptr_reg[2]\ => \rd_ptr_reg[2]_1\,
      \rd_ptr_reg[3]\ => \rd_ptr_reg[3]_1\,
      \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0),
      \read_fifo.tail_r_reg[0]\ => app_rd_data_valid_0,
      \slave_ts.oserdes_slave_ts\ => \slave_ts.oserdes_slave_ts_2\,
      \slave_ts.oserdes_slave_ts_0\ => \slave_ts.oserdes_slave_ts_3\,
      \slave_ts.oserdes_slave_ts_1\ => \slave_ts.oserdes_slave_ts_4\,
      sync_pulse => sync_pulse,
      wr_en => wr_en,
      wr_en_2 => wr_en_2,
      \wr_ptr_reg[0]\ => \wr_ptr_reg[0]_0\,
      \wr_ptr_reg[1]\ => \wr_ptr_reg[1]_0\,
      \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]_1\(3 downto 0),
      \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]_0\
    );
\ddr_byte_lane_D.ddr_byte_lane_D\: entity work.\mig_7series_0_mig_7series_v4_2_ddr_byte_lane__parameterized2\
     port map (
      A_rst_primitives_reg(9 downto 0) => A_rst_primitives_reg_3(9 downto 0),
      CLK => CLK,
      D_of_full => D_of_full,
      OUTBURSTPENDING(0) => phaser_ctl_bus(3),
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      calib_cmd_wren => calib_cmd_wren,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      freq_refclk => freq_refclk,
      mc_cas_n(1 downto 0) => mc_cas_n(1 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(0) => mc_ras_n(0),
      mem_out(30 downto 0) => mem_out(30 downto 0),
      mem_refclk => mem_refclk,
      mux_cmd_wren => mux_cmd_wren,
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      ofifo_rst => ofifo_rst,
      out_fifo_0 => out_fifo,
      out_fifo_1 => out_fifo_0,
      out_fifo_2 => out_fifo_1,
      out_fifo_3 => out_fifo_2,
      out_fifo_4 => \^a_rst_primitives_reg_0\,
      out_fifo_5(1 downto 0) => out_fifo_7(1 downto 0),
      out_fifo_6 => \wr_ptr_timing_reg[0]_0\,
      phy_dout(31 downto 0) => phy_dout(31 downto 0),
      \rd_ptr_reg[3]\(3 downto 0) => \rd_ptr_reg[3]_2\(3 downto 0),
      \rd_ptr_reg[3]_0\(3 downto 0) => \rd_ptr_reg[3]_3\(3 downto 0),
      \rd_ptr_reg[3]_1\(3 downto 0) => \rd_ptr_reg[3]_4\(3 downto 0),
      \rd_ptr_reg[3]_2\(7 downto 0) => \rd_ptr_reg[3]_5\(7 downto 0),
      \rd_ptr_reg[3]_3\(4 downto 0) => \rd_ptr_reg[3]_6\(4 downto 0),
      \rd_ptr_reg[3]_4\(0) => \rd_ptr_reg[3]_7\(0),
      \rd_ptr_reg[3]_5\(3 downto 0) => \rd_ptr_reg[3]_8\(3 downto 0),
      \rd_ptr_reg[3]_6\(0) => \rd_ptr_reg[3]_9\(0),
      sync_pulse => sync_pulse,
      \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]\
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => A_pi_rst_div2
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => B_pi_rst_div2
    );
i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => C_pi_rst_div2
    );
i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => D_pi_rst_div2
    );
mcGo_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rst_out_reg_n_0,
      Q => D(0),
      R => '0'
    );
phaser_ref_i: unisim.vcomponents.PHASER_REF
    generic map(
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0'
    )
        port map (
      CLKIN => freq_refclk,
      LOCKED => \^ref_dll_lock\,
      PWRDWN => '0',
      RST => RST0
    );
phy_control_i: unisim.vcomponents.PHY_CONTROL
    generic map(
      AO_TOGGLE => 1,
      AO_WRLVL_EN => B"0000",
      BURST_MODE => "TRUE",
      CLK_RATIO => 4,
      CMD_OFFSET => 9,
      CO_DURATION => 1,
      DATA_CTL_A_N => "TRUE",
      DATA_CTL_B_N => "FALSE",
      DATA_CTL_C_N => "TRUE",
      DATA_CTL_D_N => "FALSE",
      DISABLE_SEQ_MATCH => "TRUE",
      DI_DURATION => 1,
      DO_DURATION => 1,
      EVENTS_DELAY => 18,
      FOUR_WINDOW_CLOCKS => 63,
      MULTI_REGION => "FALSE",
      PHY_COUNT_ENABLE => "FALSE",
      RD_CMD_OFFSET_0 => 10,
      RD_CMD_OFFSET_1 => 10,
      RD_CMD_OFFSET_2 => 10,
      RD_CMD_OFFSET_3 => 10,
      RD_DURATION_0 => 6,
      RD_DURATION_1 => 6,
      RD_DURATION_2 => 6,
      RD_DURATION_3 => 6,
      SYNC_MODE => "FALSE",
      WR_CMD_OFFSET_0 => 8,
      WR_CMD_OFFSET_1 => 8,
      WR_CMD_OFFSET_2 => 8,
      WR_CMD_OFFSET_3 => 8,
      WR_DURATION_0 => 7,
      WR_DURATION_1 => 7,
      WR_DURATION_2 => 7,
      WR_DURATION_3 => 7
    )
        port map (
      AUXOUTPUT(3) => phy_control_i_n_14,
      AUXOUTPUT(2) => phy_control_i_n_15,
      AUXOUTPUT(1) => phy_control_i_n_16,
      AUXOUTPUT(0) => phy_control_i_n_17,
      INBURSTPENDING(3) => phy_control_i_n_18,
      INBURSTPENDING(2) => phy_control_i_n_19,
      INBURSTPENDING(1) => phy_control_i_n_20,
      INBURSTPENDING(0) => phy_control_i_n_21,
      INRANKA(1) => phy_control_i_n_4,
      INRANKA(0) => phy_control_i_n_5,
      INRANKB(1) => phy_control_i_n_6,
      INRANKB(0) => phy_control_i_n_7,
      INRANKC(1) => phy_control_i_n_8,
      INRANKC(0) => phy_control_i_n_9,
      INRANKD(1) => phy_control_i_n_10,
      INRANKD(0) => phy_control_i_n_11,
      MEMREFCLK => mem_refclk,
      OUTBURSTPENDING(3) => phaser_ctl_bus(3),
      OUTBURSTPENDING(2) => phy_control_i_n_23,
      OUTBURSTPENDING(1) => phy_control_i_n_24,
      OUTBURSTPENDING(0) => phy_control_i_n_25,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      PHYCLK => CLK,
      PHYCTLALMOSTFULL => phy_control_i_n_0,
      PHYCTLEMPTY => phy_control_i_n_1,
      PHYCTLFULL => phy_mc_ctl_full,
      PHYCTLMSTREMPTY => phy_control_i_n_1,
      PHYCTLREADY => phy_control_i_n_3,
      PHYCTLWD(31 downto 25) => B"0000000",
      PHYCTLWD(24 downto 17) => Q(10 downto 3),
      PHYCTLWD(16 downto 3) => B"00000000000000",
      PHYCTLWD(2 downto 0) => Q(2 downto 0),
      PHYCTLWRENABLE => phy_ctl_wr_i2,
      PLLLOCK => pll_locked,
      READCALIBENABLE => phy_read_calib,
      REFDLLLOCK => \^ref_dll_lock\,
      RESET => SR(0),
      SYNCIN => sync_pulse,
      WRITECALIBENABLE => '0'
    );
\pi_counter_read_val_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_A.ddr_byte_lane_A_n_181\,
      Q => \^pi_counter_read_val_reg[5]_1\(0),
      R => '0'
    );
\pi_counter_read_val_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_A.ddr_byte_lane_A_n_180\,
      Q => \^pi_counter_read_val_reg[5]_1\(1),
      R => '0'
    );
\pi_counter_read_val_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_A.ddr_byte_lane_A_n_179\,
      Q => \^pi_counter_read_val_reg[5]_1\(2),
      R => '0'
    );
\pi_counter_read_val_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_A.ddr_byte_lane_A_n_178\,
      Q => \^pi_counter_read_val_reg[5]_1\(3),
      R => '0'
    );
\pi_counter_read_val_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_A.ddr_byte_lane_A_n_177\,
      Q => \^pi_counter_read_val_reg[5]_1\(4),
      R => '0'
    );
\pi_counter_read_val_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_A.ddr_byte_lane_A_n_176\,
      Q => \^pi_counter_read_val_reg[5]_1\(5),
      R => '0'
    );
\rclk_delay_reg[10]_srl11\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '1',
      CE => '1',
      CLK => CLK,
      D => \rclk_delay_reg[10]_srl11_i_1_n_0\,
      Q => \rclk_delay_reg[10]_srl11_n_0\
    );
\rclk_delay_reg[10]_srl11_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rst_primitives,
      O => \rclk_delay_reg[10]_srl11_i_1_n_0\
    );
\rclk_delay_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rclk_delay_reg[10]_srl11_n_0\,
      Q => rclk_delay_11,
      R => '0'
    );
rst_out_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rclk_delay_11,
      I1 => rst_out_reg_n_0,
      O => rst_out_i_1_n_0
    );
rst_out_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      CLR => rst_out_reg_0(0),
      D => rst_out_i_1_n_0,
      Q => rst_out_reg_n_0
    );
rst_primitives_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => phy_control_i_n_3,
      O => rst_primitives_i_1_n_0
    );
rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rst_primitives_i_1_n_0,
      Q => rst_primitives,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_rank_mach is
  port (
    maint_srx_r : out STD_LOGIC;
    maint_sre_r : out STD_LOGIC;
    maint_zq_r : out STD_LOGIC;
    maint_req_r : out STD_LOGIC;
    \periodic_read_request.periodic_rd_r_lcl_reg\ : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    inhbt_act_faw_r : out STD_LOGIC;
    maint_rank_r : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    maint_ref_zq_wip : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \maintenance_request.maint_sre_r_lcl_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    \maintenance_request.maint_srx_r_lcl_reg\ : out STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg_0\ : out STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg_1\ : out STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    act_this_rank : in STD_LOGIC;
    CLK : in STD_LOGIC;
    app_zq_ns : in STD_LOGIC;
    \periodic_rd_generation.read_this_rank\ : in STD_LOGIC;
    maint_ref_zq_wip_r_reg : in STD_LOGIC;
    \grant_r_reg[0]\ : in STD_LOGIC;
    insert_maint_r1 : in STD_LOGIC;
    maint_wip_r : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_cntr1_r_reg\ : in STD_LOGIC;
    \last_master_r_reg[2]\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r_reg\ : in STD_LOGIC;
    \inhbt_act_faw.faw_cnt_r_reg[0]\ : in STD_LOGIC;
    \inhbt_act_faw.faw_cnt_r_reg[0]_0\ : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    cke_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    insert_maint_r : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ : in STD_LOGIC;
    \rtw_timer.rtw_cnt_r_reg[1]\ : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]_0\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]_1\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_rank_mach : entity is "mig_7series_v4_2_rank_mach";
end mig_7series_0_mig_7series_v4_2_rank_mach;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_rank_mach is
  signal maint_prescaler_tick_r : STD_LOGIC;
  signal \^maint_ref_zq_wip\ : STD_LOGIC;
  signal \periodic_rd_generation.periodic_rd_cntr1_r\ : STD_LOGIC;
  signal \periodic_rd_generation.periodic_rd_request_r\ : STD_LOGIC;
  signal \periodic_read_request.periodic_rd_grant_r\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0_n_4\ : STD_LOGIC;
  signal rank_common0_n_12 : STD_LOGIC;
  signal rank_common0_n_13 : STD_LOGIC;
  signal \refresh_generation.refresh_bank_r\ : STD_LOGIC;
begin
  maint_ref_zq_wip <= \^maint_ref_zq_wip\;
\rank_cntrl[0].rank_cntrl0\: entity work.mig_7series_0_mig_7series_v4_2_rank_cntrl
     port map (
      CLK => CLK,
      Q(0) => Q(0),
      act_this_rank => act_this_rank,
      \inhbt_act_faw.faw_cnt_r_reg[0]_0\ => \inhbt_act_faw.faw_cnt_r_reg[0]\,
      \inhbt_act_faw.faw_cnt_r_reg[0]_1\ => \inhbt_act_faw.faw_cnt_r_reg[0]_0\,
      inhbt_act_faw_r => inhbt_act_faw_r,
      \init_calib_complete_reg_rep__9\ => \rank_cntrl[0].rank_cntrl0_n_4\,
      insert_maint_r1 => insert_maint_r1,
      maint_prescaler_tick_r => maint_prescaler_tick_r,
      maint_ref_zq_wip => \^maint_ref_zq_wip\,
      maint_wip_r => maint_wip_r,
      \periodic_rd_generation.periodic_rd_cntr1_r\ => \periodic_rd_generation.periodic_rd_cntr1_r\,
      \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\ => maint_ref_zq_wip_r_reg,
      \periodic_rd_generation.periodic_rd_cntr1_r_reg_1\ => rank_common0_n_12,
      \periodic_rd_generation.periodic_rd_request_r\ => \periodic_rd_generation.periodic_rd_request_r\,
      \periodic_rd_generation.periodic_rd_request_r_reg_0\ => \grant_r_reg[0]\,
      \periodic_rd_generation.periodic_rd_request_r_reg_1\ => \periodic_rd_generation.periodic_rd_request_r_reg\,
      \periodic_rd_generation.periodic_rd_request_r_reg_2\ => \periodic_rd_generation.periodic_rd_cntr1_r_reg\,
      \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\,
      \periodic_read_request.periodic_rd_grant_r\ => \periodic_read_request.periodic_rd_grant_r\,
      \refresh_generation.refresh_bank_r\ => \refresh_generation.refresh_bank_r\,
      \refresh_generation.refresh_bank_r_reg[0]_0\ => rank_common0_n_13,
      \rtw_timer.rtw_cnt_r_reg[0]_0\ => \last_master_r_reg[2]\,
      \rtw_timer.rtw_cnt_r_reg[1]_0\ => \rtw_timer.rtw_cnt_r_reg[1]\,
      \wtr_timer.wtr_cnt_r_reg[0]_0\ => \wtr_timer.wtr_cnt_r_reg[0]\,
      \wtr_timer.wtr_cnt_r_reg[0]_1\ => \wtr_timer.wtr_cnt_r_reg[0]_0\,
      \wtr_timer.wtr_cnt_r_reg[0]_2\ => \wtr_timer.wtr_cnt_r_reg[0]_1\,
      \wtr_timer.wtr_cnt_r_reg[1]_0\(0) => \wtr_timer.wtr_cnt_r_reg[1]\(0),
      \wtr_timer.wtr_cnt_r_reg[1]_1\ => \wtr_timer.wtr_cnt_r_reg[1]_0\
    );
rank_common0: entity work.mig_7series_0_mig_7series_v4_2_rank_common
     port map (
      CLK => CLK,
      D(0) => D(0),
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_zq_ack => app_zq_ack,
      app_zq_ns => app_zq_ns,
      cke_r_reg(0) => cke_r_reg(0),
      \grant_r_reg[0]\ => \grant_r_reg[0]\,
      \init_calib_complete_reg_rep__9\ => rank_common0_n_13,
      insert_maint_r => insert_maint_r,
      insert_maint_r1 => insert_maint_r1,
      \last_master_r_reg[2]\ => \last_master_r_reg[2]\,
      \maint_controller.maint_hit_busies_r_reg[3]\ => \maint_controller.maint_hit_busies_r_reg[3]\,
      \maint_controller.maint_wip_r_lcl_reg\ => \maint_controller.maint_wip_r_lcl_reg\,
      maint_prescaler_tick_r => maint_prescaler_tick_r,
      maint_ref_zq_wip => \^maint_ref_zq_wip\,
      maint_ref_zq_wip_r_reg_0 => maint_ref_zq_wip_r_reg,
      maint_ref_zq_wip_r_reg_1 => \rank_cntrl[0].rank_cntrl0_n_4\,
      maint_wip_r => maint_wip_r,
      \maintenance_request.maint_rank_r_lcl_reg[0]_0\ => maint_rank_r,
      \maintenance_request.maint_req_r_lcl_reg_0\ => maint_req_r,
      \maintenance_request.maint_sre_r_lcl_reg_0\ => maint_sre_r,
      \maintenance_request.maint_sre_r_lcl_reg_1\(0) => \maintenance_request.maint_sre_r_lcl_reg\(0),
      \maintenance_request.maint_sre_r_lcl_reg_2\ => \maintenance_request.maint_sre_r_lcl_reg_0\,
      \maintenance_request.maint_sre_r_lcl_reg_3\ => \maintenance_request.maint_sre_r_lcl_reg_1\,
      \maintenance_request.maint_srx_r_lcl_reg_0\ => maint_srx_r,
      \maintenance_request.maint_srx_r_lcl_reg_1\ => \maintenance_request.maint_srx_r_lcl_reg\,
      \maintenance_request.maint_zq_r_lcl_reg_0\ => maint_zq_r,
      \periodic_rd_generation.periodic_rd_cntr1_r\ => \periodic_rd_generation.periodic_rd_cntr1_r\,
      \periodic_rd_generation.periodic_rd_cntr1_r_reg\ => \periodic_rd_generation.periodic_rd_cntr1_r_reg\,
      \periodic_rd_generation.periodic_rd_request_r\ => \periodic_rd_generation.periodic_rd_request_r\,
      \periodic_read_request.periodic_rd_grant_r\ => \periodic_read_request.periodic_rd_grant_r\,
      \periodic_read_request.periodic_rd_grant_r_reg[0]_0\ => rank_common0_n_12,
      \periodic_read_request.periodic_rd_r_lcl_reg_0\ => \periodic_read_request.periodic_rd_r_lcl_reg\,
      \refresh_generation.refresh_bank_r\ => \refresh_generation.refresh_bank_r\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_bank_mach is
  port (
    periodic_rd_ack_r_lcl_reg : out STD_LOGIC;
    accept_ns : out STD_LOGIC;
    insert_maint_r : out STD_LOGIC;
    maint_wip_r : out STD_LOGIC;
    sent_col : out STD_LOGIC;
    insert_maint_r1 : out STD_LOGIC;
    DIC : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    bm_end_r1_2 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : out STD_LOGIC;
    bm_end_r1_4 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : out STD_LOGIC;
    periodic_rd_cntr_r_reg : out STD_LOGIC;
    granted_col_r_reg : out STD_LOGIC;
    granted_col_r_reg_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_odt_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \periodic_rd_generation.read_this_rank\ : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rd_wr_r_lcl_reg : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_aux_out0_1 : out STD_LOGIC;
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \grant_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
    \grant_r_reg[3]_1\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    col_wr_data_buf_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    idle_r_lcl_reg : out STD_LOGIC;
    idle_r_lcl_reg_0 : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    idle_r_lcl_reg_2 : out STD_LOGIC;
    \req_row_r_lcl_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_cs_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[3]_2\ : out STD_LOGIC;
    \wr_this_rank_r_reg[0]\ : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    act_this_rank : out STD_LOGIC;
    \grant_r_reg[3]_3\ : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__12\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    was_wr0 : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    periodic_rd_cntr_r_reg_0 : in STD_LOGIC;
    cke_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_wr_r_lcl0 : in STD_LOGIC;
    p_145_out : in STD_LOGIC;
    p_106_out : in STD_LOGIC;
    p_67_out : in STD_LOGIC;
    p_28_out : in STD_LOGIC;
    phy_mc_cmd_full : in STD_LOGIC;
    phy_mc_ctl_full : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 2 downto 0 );
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r_lcl_reg : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_odt_reg[0]\ : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    phy_mc_data_full : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    ras_timer_zero_r_reg : in STD_LOGIC;
    act_wait_r_lcl_reg_0 : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    q_has_rd_r_reg : in STD_LOGIC;
    act_wait_r_lcl_reg_3 : in STD_LOGIC;
    auto_pre_r_lcl_reg : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    maint_sre_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    maint_rank_r : in STD_LOGIC;
    was_priority_reg : in STD_LOGIC;
    app_en_r2 : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    row : in STD_LOGIC_VECTOR ( 12 downto 0 );
    inhbt_act_faw_r : in STD_LOGIC;
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    ras_timer_zero_r_reg_2 : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r[3]_i_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\ : in STD_LOGIC;
    \req_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_bank_mach : entity is "mig_7series_v4_2_bank_mach";
end mig_7series_0_mig_7series_v4_2_bank_mach;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_bank_mach is
  signal accept_internal_r : STD_LOGIC;
  signal \^accept_ns\ : STD_LOGIC;
  signal act_this_rank_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal arb_mux0_n_10 : STD_LOGIC;
  signal arb_mux0_n_101 : STD_LOGIC;
  signal arb_mux0_n_102 : STD_LOGIC;
  signal arb_mux0_n_103 : STD_LOGIC;
  signal arb_mux0_n_104 : STD_LOGIC;
  signal arb_mux0_n_105 : STD_LOGIC;
  signal arb_mux0_n_21 : STD_LOGIC;
  signal arb_mux0_n_22 : STD_LOGIC;
  signal arb_mux0_n_82 : STD_LOGIC;
  signal arb_mux0_n_88 : STD_LOGIC;
  signal arb_mux0_n_89 : STD_LOGIC;
  signal arb_mux0_n_90 : STD_LOGIC;
  signal arb_mux0_n_95 : STD_LOGIC;
  signal \arb_row_col0/rnk_config_strobe_ns\ : STD_LOGIC;
  signal \arb_row_col0/rnk_config_valid_ns\ : STD_LOGIC;
  signal auto_pre_r : STD_LOGIC;
  signal auto_pre_r_1 : STD_LOGIC;
  signal auto_pre_r_10 : STD_LOGIC;
  signal auto_pre_r_16 : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_18\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_19\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_20\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_21\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_22\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_23\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_24\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_26\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_27\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_28\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_29\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_32\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_33\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_35\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_36\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_37\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_38\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_39\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_40\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_41\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_42\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_56\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_57\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_58\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_59\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_60\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_61\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_62\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_17\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_19\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_21\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_22\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_23\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_24\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_25\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_26\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_28\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_31\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_32\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_33\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_34\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_36\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_37\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_38\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_39\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_40\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_54\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_18\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_19\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_23\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_27\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_28\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_30\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_31\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_32\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_33\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_34\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_35\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_37\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_38\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_39\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_53\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_54\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_55\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_16\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_17\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_18\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_19\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_20\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_21\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_22\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_24\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_25\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_26\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_28\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_29\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_30\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_31\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_32\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_46\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_47\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_48\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_49\ : STD_LOGIC;
  signal bank_common0_n_11 : STD_LOGIC;
  signal bank_common0_n_12 : STD_LOGIC;
  signal bank_common0_n_13 : STD_LOGIC;
  signal bank_common0_n_14 : STD_LOGIC;
  signal bank_common0_n_15 : STD_LOGIC;
  signal bank_common0_n_16 : STD_LOGIC;
  signal bank_common0_n_17 : STD_LOGIC;
  signal bank_common0_n_8 : STD_LOGIC;
  signal bank_common0_n_9 : STD_LOGIC;
  signal \bank_compare0/req_col_r\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \bank_compare0/req_col_r_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \bank_compare0/req_col_r_15\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \bank_compare0/req_col_r_7\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \bank_queue0/q_entry_ns\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \bank_state0/col_wait_r\ : STD_LOGIC;
  signal \bank_state0/col_wait_r_2\ : STD_LOGIC;
  signal \bank_state0/demand_act_priority_r\ : STD_LOGIC;
  signal \bank_state0/demand_act_priority_r_14\ : STD_LOGIC;
  signal \bank_state0/demand_act_priority_r_20\ : STD_LOGIC;
  signal \bank_state0/demand_act_priority_r_6\ : STD_LOGIC;
  signal \bank_state0/demand_priority_r\ : STD_LOGIC;
  signal \bank_state0/demand_priority_r_13\ : STD_LOGIC;
  signal \bank_state0/demand_priority_r_19\ : STD_LOGIC;
  signal \bank_state0/demand_priority_r_5\ : STD_LOGIC;
  signal \bank_state0/demanded_prior_r\ : STD_LOGIC;
  signal \bank_state0/demanded_prior_r_12\ : STD_LOGIC;
  signal \bank_state0/demanded_prior_r_18\ : STD_LOGIC;
  signal \bank_state0/demanded_prior_r_4\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r0\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r0_8\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r0_9\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r_11\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r_17\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r_3\ : STD_LOGIC;
  signal \bank_state0/override_demand_ns\ : STD_LOGIC;
  signal \bank_state0/override_demand_r\ : STD_LOGIC;
  signal hi_priority : STD_LOGIC;
  signal idle_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^idle_r_lcl_reg\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_0\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_1\ : STD_LOGIC;
  signal \^idle_r_lcl_reg_2\ : STD_LOGIC;
  signal \^insert_maint_r\ : STD_LOGIC;
  signal \maint_controller.maint_hit_busies_ns\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \maint_controller.maint_hit_busies_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal ordered_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal p_130_out : STD_LOGIC;
  signal p_13_out : STD_LOGIC;
  signal p_9_in : STD_LOGIC;
  signal periodic_rd_ack_ns : STD_LOGIC;
  signal \^periodic_rd_ack_r_lcl_reg\ : STD_LOGIC;
  signal periodic_rd_insert : STD_LOGIC;
  signal q_entry_r : STD_LOGIC_VECTOR ( 1 to 1 );
  signal rb_hit_busies_r : STD_LOGIC_VECTOR ( 5 downto 3 );
  signal rb_hit_busy_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_this_rank_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_wr_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^req_bank_r_lcl_reg[2]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^req_bank_r_lcl_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^req_bank_r_lcl_reg[2]_1\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^req_bank_r_lcl_reg[2]_2\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal req_data_buf_addr_r : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal req_periodic_rd_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal req_row_r : STD_LOGIC_VECTOR ( 50 downto 9 );
  signal \^req_row_r_lcl_reg[12]\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal rnk_config_valid_r : STD_LOGIC;
  signal row_cmd_wr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sending_col : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sending_pre : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sending_row : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^sent_col\ : STD_LOGIC;
  signal was_priority : STD_LOGIC;
  signal was_wr : STD_LOGIC;
  signal wr_this_rank_r : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
  accept_ns <= \^accept_ns\;
  idle_r_lcl_reg <= \^idle_r_lcl_reg\;
  idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\;
  idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\;
  idle_r_lcl_reg_2 <= \^idle_r_lcl_reg_2\;
  insert_maint_r <= \^insert_maint_r\;
  periodic_rd_ack_r_lcl_reg <= \^periodic_rd_ack_r_lcl_reg\;
  \req_bank_r_lcl_reg[2]\(2 downto 0) <= \^req_bank_r_lcl_reg[2]\(2 downto 0);
  \req_bank_r_lcl_reg[2]_0\(2 downto 0) <= \^req_bank_r_lcl_reg[2]_0\(2 downto 0);
  \req_bank_r_lcl_reg[2]_1\(2 downto 0) <= \^req_bank_r_lcl_reg[2]_1\(2 downto 0);
  \req_bank_r_lcl_reg[2]_2\(2 downto 0) <= \^req_bank_r_lcl_reg[2]_2\(2 downto 0);
  \req_row_r_lcl_reg[12]\(12 downto 0) <= \^req_row_r_lcl_reg[12]\(12 downto 0);
  sent_col <= \^sent_col\;
arb_mux0: entity work.mig_7series_0_mig_7series_v4_2_arb_mux
     port map (
      CLK => CLK,
      D(0) => D(0),
      DIC(0) => DIC(0),
      E(0) => E(0),
      Q(3 downto 0) => sending_col(3 downto 0),
      act_this_rank => act_this_rank,
      act_this_rank_r(3 downto 0) => act_this_rank_r(3 downto 0),
      act_wait_r_lcl_reg(2 downto 0) => act_wait_r_lcl_reg(2 downto 0),
      auto_pre_r => auto_pre_r,
      auto_pre_r_1 => auto_pre_r_16,
      auto_pre_r_2 => auto_pre_r_10,
      auto_pre_r_3 => auto_pre_r_1,
      cke_r_reg => periodic_rd_cntr_r_reg_0,
      cke_r_reg_0(0) => cke_r_reg(0),
      \cmd_pipe_plus.mc_address_reg[23]\ => \bank_cntrl[0].bank0_n_42\,
      \cmd_pipe_plus.mc_address_reg[38]\(12 downto 0) => \^req_row_r_lcl_reg[12]\(12 downto 0),
      \cmd_pipe_plus.mc_address_reg[9]\(9 downto 0) => \bank_compare0/req_col_r\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[9]_0\(9 downto 0) => \bank_compare0/req_col_r_15\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[9]_1\(9 downto 0) => \bank_compare0/req_col_r_7\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[9]_2\(9 downto 0) => \bank_compare0/req_col_r_0\(9 downto 0),
      \cmd_pipe_plus.mc_bank_reg[5]\(2 downto 0) => \^req_bank_r_lcl_reg[2]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[5]_0\(2 downto 0) => \^req_bank_r_lcl_reg[2]_2\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) => \^req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]_0\(2 downto 0) => \^req_bank_r_lcl_reg[2]_1\(2 downto 0),
      \cmd_pipe_plus.mc_cas_n_reg[1]\ => \rtp_timer_r_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_reg[2]\(1 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[2]\(1 downto 0),
      \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_odt_reg[0]\,
      \cmd_pipe_plus.mc_we_n_reg[1]\ => \bank_cntrl[3].bank0_n_46\,
      \cmd_pipe_plus.mc_we_n_reg[1]_0\ => \bank_cntrl[0].bank0_n_22\,
      \col_mux.col_periodic_rd_r_reg\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\,
      col_rd_wr => col_rd_wr,
      col_wait_r => \bank_state0/col_wait_r_2\,
      col_wait_r_0 => \bank_state0/col_wait_r\,
      col_wr_data_buf_addr(3 downto 0) => col_wr_data_buf_addr(3 downto 0),
      \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0),
      demand_act_priority_r => \bank_state0/demand_act_priority_r\,
      demand_act_priority_r_4 => \bank_state0/demand_act_priority_r_20\,
      demand_act_priority_r_5 => \bank_state0/demand_act_priority_r_14\,
      demand_act_priority_r_6 => \bank_state0/demand_act_priority_r_6\,
      demand_priority_r => \bank_state0/demand_priority_r_19\,
      demand_priority_r_10 => \bank_state0/demand_priority_r_5\,
      demand_priority_r_12 => \bank_state0/demand_priority_r_13\,
      demand_priority_r_7 => \bank_state0/demand_priority_r\,
      demanded_prior_r => \bank_state0/demanded_prior_r\,
      demanded_prior_r_11 => \bank_state0/demanded_prior_r_12\,
      demanded_prior_r_8 => \bank_state0/demanded_prior_r_18\,
      demanded_prior_r_9 => \bank_state0/demanded_prior_r_4\,
      demanded_prior_r_reg => arb_mux0_n_103,
      demanded_prior_r_reg_0 => arb_mux0_n_104,
      \genblk3[1].rnk_config_strobe_r_reg[1]\ => arb_mux0_n_105,
      \grant_r[1]_i_3\ => \bank_cntrl[0].bank0_n_24\,
      \grant_r[3]_i_2\ => \bank_cntrl[3].bank0_n_22\,
      \grant_r[3]_i_5\(0) => Q(0),
      \grant_r[3]_i_5_0\(0) => \grant_r[3]_i_5\(0),
      \grant_r[3]_i_8\ => rnk_config_valid_r_lcl_reg,
      \grant_r_reg[0]\ => \grant_r_reg[0]\,
      \grant_r_reg[0]_0\ => \bank_cntrl[3].bank0_n_16\,
      \grant_r_reg[0]_1\ => \bank_cntrl[0].bank0_n_19\,
      \grant_r_reg[0]_2\ => \bank_cntrl[3].bank0_n_24\,
      \grant_r_reg[0]_3\ => \bank_cntrl[0].bank0_n_26\,
      \grant_r_reg[0]_4\ => \bank_cntrl[2].bank0_n_30\,
      \grant_r_reg[0]_5\ => \bank_cntrl[0].bank0_n_59\,
      \grant_r_reg[0]_6\ => \bank_cntrl[2].bank0_n_39\,
      \grant_r_reg[0]_7\ => \bank_cntrl[3].bank0_n_32\,
      \grant_r_reg[1]\ => arb_mux0_n_102,
      \grant_r_reg[1]_0\ => \bank_cntrl[1].bank0_n_23\,
      \grant_r_reg[1]_1\ => \bank_cntrl[0].bank0_n_20\,
      \grant_r_reg[1]_2\(0) => \bank_cntrl[0].bank0_n_57\,
      \grant_r_reg[2]\(1) => arb_mux0_n_88,
      \grant_r_reg[2]\(0) => arb_mux0_n_89,
      \grant_r_reg[2]_0\ => \bank_cntrl[1].bank0_n_19\,
      \grant_r_reg[2]_1\ => \bank_cntrl[1].bank0_n_39\,
      \grant_r_reg[2]_2\ => \bank_cntrl[1].bank0_n_21\,
      \grant_r_reg[2]_3\ => \bank_cntrl[1].bank0_n_40\,
      \grant_r_reg[3]\ => \grant_r_reg[3]\,
      \grant_r_reg[3]_0\(36 downto 0) => \grant_r_reg[3]_0\(36 downto 0),
      \grant_r_reg[3]_1\(8 downto 0) => \grant_r_reg[3]_1\(8 downto 0),
      \grant_r_reg[3]_10\ => \bank_cntrl[2].bank0_n_38\,
      \grant_r_reg[3]_2\(3 downto 0) => sending_row(3 downto 0),
      \grant_r_reg[3]_3\ => arb_mux0_n_90,
      \grant_r_reg[3]_4\(3 downto 0) => sending_pre(3 downto 0),
      \grant_r_reg[3]_5\ => \grant_r_reg[3]_2\,
      \grant_r_reg[3]_6\ => \grant_r_reg[3]_3\,
      \grant_r_reg[3]_7\ => arb_mux0_n_101,
      \grant_r_reg[3]_8\ => \bank_cntrl[0].bank0_n_58\,
      \grant_r_reg[3]_9\ => \bank_cntrl[3].bank0_n_31\,
      granted_col_r_reg => \^sent_col\,
      granted_col_r_reg_0 => granted_col_r_reg,
      granted_col_r_reg_1(1 downto 0) => granted_col_r_reg_0(1 downto 0),
      granted_col_r_reg_2 => \bank_cntrl[1].bank0_n_22\,
      granted_col_r_reg_3 => \bank_cntrl[0].bank0_n_60\,
      granted_col_r_reg_4 => \bank_cntrl[1].bank0_n_26\,
      granted_col_r_reg_5 => \bank_cntrl[2].bank0_n_28\,
      granted_col_r_reg_6 => \bank_cntrl[2].bank0_n_32\,
      granted_col_r_reg_7 => \bank_cntrl[2].bank0_n_55\,
      granted_row_r_reg => arb_mux0_n_82,
      granted_row_r_reg_0 => \bank_cntrl[2].bank0_n_53\,
      granted_row_r_reg_1 => \bank_cntrl[0].bank0_n_56\,
      inhbt_act_faw_r => inhbt_act_faw_r,
      insert_maint_r1_lcl_reg => insert_maint_r1,
      insert_maint_r1_lcl_reg_0 => \^insert_maint_r\,
      \last_master_r_reg[3]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\,
      maint_rank_r => maint_rank_r,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      mc_aux_out0_1 => mc_aux_out0_1,
      mc_cas_n_ns(2 downto 0) => mc_cas_n_ns(2 downto 0),
      mc_cs_n_ns(0) => mc_cs_n_ns(0),
      mc_odt_ns(0) => mc_odt_ns(0),
      mc_ras_n_ns(2 downto 0) => mc_ras_n_ns(2 downto 0),
      ofs_rdy_r => \bank_state0/ofs_rdy_r_11\,
      ofs_rdy_r_13 => \bank_state0/ofs_rdy_r_3\,
      ofs_rdy_r_14 => \bank_state0/ofs_rdy_r_17\,
      ofs_rdy_r_15 => \bank_state0/ofs_rdy_r\,
      override_demand_ns => \bank_state0/override_demand_ns\,
      override_demand_r => \bank_state0/override_demand_r\,
      \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \bank_cntrl[2].bank0_n_19\,
      rd_this_rank_r(3 downto 0) => rd_this_rank_r(3 downto 0),
      rd_wr_r(3 downto 0) => rd_wr_r(3 downto 0),
      rd_wr_r_lcl_reg => arb_mux0_n_10,
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg,
      rd_wr_r_lcl_reg_1 => arb_mux0_n_21,
      rd_wr_r_lcl_reg_2 => arb_mux0_n_22,
      req_data_buf_addr_r(15 downto 12) => req_data_buf_addr_r(18 downto 15),
      req_data_buf_addr_r(11 downto 8) => req_data_buf_addr_r(13 downto 10),
      req_data_buf_addr_r(7 downto 4) => req_data_buf_addr_r(8 downto 5),
      req_data_buf_addr_r(3 downto 0) => req_data_buf_addr_r(3 downto 0),
      req_periodic_rd_r(3 downto 0) => req_periodic_rd_r(3 downto 0),
      req_row_r(38 downto 27) => req_row_r(50 downto 39),
      req_row_r(26 downto 15) => req_row_r(37 downto 26),
      req_row_r(14 downto 3) => req_row_r(24 downto 13),
      req_row_r(2 downto 0) => req_row_r(11 downto 9),
      rnk_config_strobe_ns => \arb_row_col0/rnk_config_strobe_ns\,
      rnk_config_valid_ns => \arb_row_col0/rnk_config_valid_ns\,
      rnk_config_valid_r => rnk_config_valid_r,
      row_cmd_wr(3 downto 0) => row_cmd_wr(3 downto 0),
      \rstdiv0_sync_r1_reg_rep__11\ => arb_mux0_n_95,
      wr_this_rank_r(3 downto 0) => wr_this_rank_r(3 downto 0),
      \wr_this_rank_r_reg[0]\ => \wr_this_rank_r_reg[0]\
    );
\bank_cntrl[0].bank0\: entity work.mig_7series_0_mig_7series_v4_2_bank_cntrl
     port map (
      CLK => CLK,
      D(0) => \maint_controller.maint_hit_busies_ns\(0),
      Q(1) => sending_col(3),
      Q(0) => sending_col(0),
      S(2 downto 0) => S(2 downto 0),
      accept_internal_r => accept_internal_r,
      accept_internal_r_reg => periodic_rd_ack_r_lcl_reg_0,
      accept_internal_r_reg_0 => \^idle_r_lcl_reg_0\,
      accept_internal_r_reg_1 => \^idle_r_lcl_reg\,
      accept_internal_r_reg_2 => \^idle_r_lcl_reg_1\,
      act_this_rank_r(0) => act_this_rank_r(0),
      \act_wait_r_lcl_i_4__1\ => \bank_cntrl[2].bank0_n_37\,
      \act_wait_r_lcl_i_4__1_0\ => \bank_cntrl[1].bank0_n_37\,
      \act_wait_r_lcl_i_4__1_1\ => \bank_cntrl[3].bank0_n_29\,
      act_wait_r_lcl_reg => \bank_cntrl[0].bank0_n_22\,
      act_wait_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_42\,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_3,
      app_en_r2 => app_en_r2,
      auto_pre_r => auto_pre_r,
      auto_pre_r_lcl_reg => auto_pre_r_lcl_reg,
      bm_end_r1 => bm_end_r1,
      \cmd_pipe_plus.mc_address_reg[23]\ => arb_mux0_n_82,
      col_wait_r => \bank_state0/col_wait_r\,
      col_wait_r_reg => \bank_cntrl[0].bank0_n_19\,
      col_wait_r_reg_0 => col_wait_r_reg,
      col_wait_r_reg_1(0) => sending_row(0),
      \compute_tail.tail_r_lcl_reg\ => \bank_cntrl[1].bank0_n_38\,
      demand_act_priority_r => \bank_state0/demand_act_priority_r\,
      demand_priority_r => \bank_state0/demand_priority_r\,
      demand_priority_r_0 => \bank_state0/demand_priority_r_19\,
      demand_priority_r_2 => \bank_state0/demand_priority_r_5\,
      demand_priority_r_reg => \bank_cntrl[0].bank0_n_26\,
      demand_priority_r_reg_0 => \bank_cntrl[0].bank0_n_60\,
      demand_priority_r_reg_1 => \bank_cntrl[3].bank0_n_25\,
      demand_priority_r_reg_2 => \bank_cntrl[1].bank0_n_28\,
      demand_priority_r_reg_3 => \bank_cntrl[2].bank0_n_31\,
      demand_priority_r_reg_4 => \^sent_col\,
      demanded_prior_r => \bank_state0/demanded_prior_r\,
      demanded_prior_r_1 => \bank_state0/demanded_prior_r_18\,
      demanded_prior_r_reg => arb_mux0_n_102,
      \grant_r[3]_i_12\(0) => rb_hit_busies_r(4),
      \grant_r_reg[0]\ => \bank_cntrl[0].bank0_n_23\,
      \grant_r_reg[0]_0\ => \bank_cntrl[0].bank0_n_61\,
      \grant_r_reg[0]_1\ => arb_mux0_n_21,
      \grant_r_reg[1]\ => \bank_cntrl[1].bank0_n_40\,
      \grant_r_reg[1]_0\(1) => arb_mux0_n_88,
      \grant_r_reg[1]_0\(0) => arb_mux0_n_89,
      \grant_r_reg[1]_1\ => \bank_cntrl[3].bank0_n_32\,
      \grant_r_reg[1]_2\ => arb_mux0_n_95,
      \grant_r_reg[1]_3\ => arb_mux0_n_90,
      granted_col_r_i_3 => \bank_cntrl[3].bank0_n_48\,
      head_r_lcl_reg => \bank_cntrl[0].bank0_n_56\,
      head_r_lcl_reg_0(2 downto 0) => idle_r(3 downto 1),
      hi_priority => hi_priority,
      idle_r(0) => idle_r(0),
      idle_r_lcl_reg => \bank_cntrl[0].bank0_n_18\,
      idle_r_lcl_reg_0 => \^idle_r_lcl_reg_2\,
      idle_r_lcl_reg_1 => \bank_cntrl[0].bank0_n_37\,
      idle_r_lcl_reg_2 => \bank_cntrl[0].bank0_n_38\,
      idle_r_lcl_reg_3 => \bank_cntrl[0].bank0_n_39\,
      idle_r_lcl_reg_4 => \bank_cntrl[0].bank0_n_40\,
      \maint_controller.maint_hit_busies_r_reg[0]\ => \maint_controller.maint_hit_busies_r_reg[3]\,
      \maint_controller.maint_hit_busies_r_reg[0]_0\(0) => \maint_controller.maint_hit_busies_r\(0),
      maint_rank_r => maint_rank_r,
      maint_sre_r => maint_sre_r,
      maint_zq_r => maint_zq_r,
      ofs_rdy_r => \bank_state0/ofs_rdy_r\,
      ofs_rdy_r0 => \bank_state0/ofs_rdy_r0_9\,
      ofs_rdy_r_reg => periodic_rd_cntr_r_reg_0,
      \order_q_r_reg[0]\ => \bank_cntrl[0].bank0_n_24\,
      \order_q_r_reg[0]_0\ => \bank_cntrl[3].bank0_n_19\,
      \order_q_r_reg[1]\ => \bank_cntrl[3].bank0_n_21\,
      ordered_r(0) => ordered_r(0),
      override_demand_r => \bank_state0/override_demand_r\,
      p_106_out => p_106_out,
      p_130_out => p_130_out,
      p_13_out => p_13_out,
      p_145_out => p_145_out,
      p_28_out => p_28_out,
      p_67_out => p_67_out,
      p_9_in => p_9_in,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_lcl_reg,
      pass_open_bank_r_lcl_reg_0 => bank_common0_n_15,
      periodic_rd_insert => periodic_rd_insert,
      pre_bm_end_r_reg => \bank_cntrl[0].bank0_n_32\,
      pre_bm_end_r_reg_0 => \bank_cntrl[0].bank0_n_35\,
      pre_bm_end_r_reg_1 => \bank_cntrl[0].bank0_n_36\,
      pre_bm_end_r_reg_2(0) => sending_pre(0),
      pre_passing_open_bank_r_reg => \bank_cntrl[0].bank0_n_29\,
      pre_wait_r_reg => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\,
      q_entry_ns(0) => \bank_queue0/q_entry_ns\(1),
      q_entry_r(0) => q_entry_r(1),
      \q_entry_r_reg[0]\ => \bank_cntrl[0].bank0_n_20\,
      \q_entry_r_reg[0]_0\(2 downto 0) => rb_hit_busy_r(3 downto 1),
      \q_entry_r_reg[1]\ => \bank_cntrl[0].bank0_n_62\,
      \q_entry_r_reg[1]_0\ => \bank_cntrl[1].bank0_n_34\,
      \q_entry_r_reg[1]_1\ => \bank_cntrl[2].bank0_n_34\,
      \q_entry_r_reg[1]_2\ => \bank_cntrl[1].bank0_n_31\,
      \q_entry_r_reg[1]_3\ => bank_common0_n_8,
      \q_entry_r_reg[1]_4\ => \bank_cntrl[2].bank0_n_35\,
      q_has_priority_r_reg => bank_common0_n_16,
      q_has_rd_r_reg => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \bank_cntrl[1].bank0_n_24\,
      \ras_timer_r_reg[0]_0\ => \bank_cntrl[2].bank0_n_23\,
      \ras_timer_r_reg[0]_1\ => \bank_cntrl[3].bank0_n_17\,
      \ras_timer_r_reg[1]\ => \bank_cntrl[0].bank0_n_21\,
      \ras_timer_r_reg[1]_0\ => \bank_cntrl[1].bank0_n_25\,
      \ras_timer_r_reg[1]_1\ => \bank_cntrl[2].bank0_n_27\,
      \ras_timer_r_reg[1]_2\ => \bank_cntrl[3].bank0_n_18\,
      ras_timer_zero_r_reg(0) => \bank_cntrl[0].bank0_n_57\,
      ras_timer_zero_r_reg_0 => \bank_cntrl[0].bank0_n_58\,
      ras_timer_zero_r_reg_1 => \bank_cntrl[0].bank0_n_59\,
      ras_timer_zero_r_reg_2 => ras_timer_zero_r_reg,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ => \bank_cntrl[1].bank0_n_17\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ => \bank_cntrl[2].bank0_n_18\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => \bank_cntrl[0].bank0_n_28\,
      rb_hit_busy_r(0) => rb_hit_busy_r(0),
      rb_hit_busy_r_reg => \bank_cntrl[0].bank0_n_33\,
      rb_hit_busy_r_reg_0 => \bank_cntrl[0].bank0_n_41\,
      rd_this_rank_r(0) => rd_this_rank_r(0),
      rd_wr_r(0) => rd_wr_r(0),
      rd_wr_r_lcl_reg => rd_wr_r_lcl_reg_0,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0),
      req_bank_rdy_r_reg => \bank_cntrl[3].bank0_n_20\,
      \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r\(9 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_data_buf_addr_r_reg[3]\(3 downto 0) => req_data_buf_addr_r(3 downto 0),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      \req_row_r_lcl_reg[12]\(12) => \^req_row_r_lcl_reg[12]\(9),
      \req_row_r_lcl_reg[12]\(11 downto 9) => req_row_r(11 downto 9),
      \req_row_r_lcl_reg[12]\(8 downto 0) => \^req_row_r_lcl_reg[12]\(8 downto 0),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg => \bank_cntrl[0].bank0_n_27\,
      \rnk_config_strobe_r_reg[0]\ => arb_mux0_n_104,
      \rnk_config_strobe_r_reg[0]_0\ => arb_mux0_n_105,
      row(12 downto 0) => row(12 downto 0),
      row_cmd_wr(0) => row_cmd_wr(0),
      row_hit_r_reg(0) => row_hit_r_reg(0),
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      wait_for_maint_r_lcl_reg => bank_common0_n_11,
      wait_for_maint_r_lcl_reg_0 => \^periodic_rd_ack_r_lcl_reg\,
      wait_for_maint_r_lcl_reg_1 => was_priority_reg,
      was_priority => was_priority,
      was_wr => was_wr,
      wr_this_rank_r(0) => wr_this_rank_r(0)
    );
\bank_cntrl[1].bank0\: entity work.\mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized0\
     port map (
      CLK => CLK,
      D(0) => \maint_controller.maint_hit_busies_ns\(1),
      Q(0) => sending_col(1),
      accept_internal_r => accept_internal_r,
      accept_ns => \^accept_ns\,
      act_this_rank_r(0) => act_this_rank_r(1),
      act_wait_r_lcl_reg => act_wait_r_lcl_reg_1,
      app_en_r2 => app_en_r2,
      auto_pre_r => auto_pre_r_1,
      auto_pre_r_lcl_reg => auto_pre_r_lcl_reg,
      bm_end_r1_0 => bm_end_r1_0,
      col_wait_r => \bank_state0/col_wait_r_2\,
      col_wait_r_0 => \bank_state0/col_wait_r\,
      col_wait_r_reg => \bank_cntrl[1].bank0_n_21\,
      col_wait_r_reg_0 => \bank_cntrl[1].bank0_n_23\,
      col_wait_r_reg_1 => col_wait_r_reg,
      \compute_tail.tail_r_lcl_reg\ => \bank_cntrl[3].bank0_n_26\,
      demand_act_priority_r => \bank_state0/demand_act_priority_r_6\,
      demand_act_priority_r_1 => \bank_state0/demand_act_priority_r_14\,
      demand_act_priority_r_reg => \bank_cntrl[1].bank0_n_39\,
      demand_priority_r => \bank_state0/demand_priority_r_5\,
      demand_priority_r_reg => \bank_cntrl[1].bank0_n_19\,
      demand_priority_r_reg_0 => \bank_cntrl[1].bank0_n_54\,
      demand_priority_r_reg_1 => \bank_cntrl[0].bank0_n_27\,
      demand_priority_r_reg_2 => \bank_cntrl[3].bank0_n_25\,
      demand_priority_r_reg_3 => \bank_cntrl[2].bank0_n_31\,
      demand_priority_r_reg_4 => \^sent_col\,
      demanded_prior_r => \bank_state0/demanded_prior_r_4\,
      demanded_prior_r_reg => \bank_cntrl[2].bank0_n_54\,
      demanded_prior_r_reg_0 => \bank_cntrl[3].bank0_n_49\,
      demanded_prior_r_reg_1 => \bank_cntrl[0].bank0_n_61\,
      \grant_r[3]_i_12\(0) => rb_hit_busies_r(5),
      \grant_r_reg[1]\ => arb_mux0_n_10,
      \grant_r_reg[2]\ => \bank_cntrl[0].bank0_n_20\,
      \grant_r_reg[2]_0\ => arb_mux0_n_21,
      \grant_r_reg[2]_1\(1 downto 0) => sending_row(2 downto 1),
      \grant_r_reg[2]_2\ => bank_common0_n_17,
      \grant_r_reg[2]_3\ => arb_mux0_n_101,
      granted_col_r_i_2 => \bank_cntrl[0].bank0_n_29\,
      granted_col_r_i_2_0 => \bank_cntrl[2].bank0_n_37\,
      granted_col_r_i_2_1 => \bank_cntrl[3].bank0_n_29\,
      head_r_lcl_reg => \bank_cntrl[0].bank0_n_33\,
      head_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_18\,
      hi_priority => hi_priority,
      idle_r(2 downto 1) => idle_r(3 downto 2),
      idle_r(0) => idle_r(0),
      idle_r_lcl_reg(0) => idle_r(1),
      idle_r_lcl_reg_0 => \^idle_r_lcl_reg_1\,
      idle_r_lcl_reg_1 => \bank_cntrl[1].bank0_n_31\,
      \maint_controller.maint_hit_busies_r_reg[1]\ => \maint_controller.maint_hit_busies_r_reg[3]\,
      \maint_controller.maint_hit_busies_r_reg[1]_0\(0) => \maint_controller.maint_hit_busies_r\(1),
      maint_rank_r => maint_rank_r,
      maint_sre_r => maint_sre_r,
      maint_zq_r => maint_zq_r,
      ofs_rdy_r => \bank_state0/ofs_rdy_r_3\,
      ofs_rdy_r0 => \bank_state0/ofs_rdy_r0_8\,
      ofs_rdy_r_reg => periodic_rd_cntr_r_reg_0,
      \order_q_r_reg[0]\ => \bank_cntrl[1].bank0_n_26\,
      \order_q_r_reg[0]_0\ => \bank_cntrl[3].bank0_n_19\,
      \order_q_r_reg[1]\ => \bank_cntrl[3].bank0_n_21\,
      ordered_r(0) => ordered_r(1),
      ordered_r_lcl_reg => \^periodic_rd_ack_r_lcl_reg\,
      ordered_r_lcl_reg_0 => was_priority_reg,
      p_106_out => p_106_out,
      p_130_out => p_130_out,
      p_13_out => p_13_out,
      p_145_out => p_145_out,
      p_28_out => p_28_out,
      p_67_out => p_67_out,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_lcl_reg_0,
      pass_open_bank_r_lcl_reg_0 => \bank_cntrl[1].bank0_n_33\,
      pass_open_bank_r_lcl_reg_1 => bank_common0_n_14,
      periodic_rd_ack_ns => periodic_rd_ack_ns,
      periodic_rd_ack_r_lcl_reg => \^idle_r_lcl_reg\,
      periodic_rd_ack_r_lcl_reg_0 => \^idle_r_lcl_reg_0\,
      periodic_rd_ack_r_lcl_reg_1 => \^idle_r_lcl_reg_2\,
      periodic_rd_ack_r_lcl_reg_2 => periodic_rd_ack_r_lcl_reg_0,
      periodic_rd_insert => periodic_rd_insert,
      pre_bm_end_r_reg => \bank_cntrl[1].bank0_n_17\,
      pre_bm_end_r_reg_0 => \bank_cntrl[1].bank0_n_32\,
      pre_bm_end_r_reg_1 => \bank_cntrl[1].bank0_n_38\,
      pre_bm_end_r_reg_2(0) => sending_pre(1),
      pre_passing_open_bank_r_reg => \bank_cntrl[1].bank0_n_37\,
      \q_entry_r[1]_i_2__1\ => \bank_cntrl[0].bank0_n_41\,
      \q_entry_r_reg[0]\ => \bank_cntrl[1].bank0_n_22\,
      \q_entry_r_reg[0]_0\ => \bank_cntrl[0].bank0_n_40\,
      \q_entry_r_reg[1]\ => \bank_cntrl[1].bank0_n_34\,
      \q_entry_r_reg[1]_0\(0) => \bank_queue0/q_entry_ns\(1),
      q_has_priority_r_reg => bank_common0_n_16,
      q_has_rd_r_reg => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \bank_cntrl[2].bank0_n_23\,
      \ras_timer_r_reg[0]_0\ => \bank_cntrl[3].bank0_n_17\,
      \ras_timer_r_reg[0]_1\ => \bank_cntrl[0].bank0_n_21\,
      \ras_timer_r_reg[1]\ => \bank_cntrl[1].bank0_n_24\,
      \ras_timer_r_reg[1]_0\ => \bank_cntrl[2].bank0_n_27\,
      \ras_timer_r_reg[1]_1\ => \bank_cntrl[3].bank0_n_18\,
      \ras_timer_r_reg[1]_2\ => \bank_cntrl[0].bank0_n_23\,
      ras_timer_zero_r_reg => \bank_cntrl[1].bank0_n_40\,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_0,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ => \bank_cntrl[2].bank0_n_18\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \bank_cntrl[1].bank0_n_36\,
      rb_hit_busy_r(2 downto 1) => rb_hit_busy_r(3 downto 2),
      rb_hit_busy_r(0) => rb_hit_busy_r(0),
      rb_hit_busy_r_reg(0) => rb_hit_busy_r(1),
      rd_this_rank_r(0) => rd_this_rank_r(1),
      rd_wr_r(0) => rd_wr_r(1),
      rd_wr_r_lcl_reg => \bank_cntrl[1].bank0_n_25\,
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg_0,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]_2\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0),
      req_bank_rdy_r_reg => \bank_cntrl[3].bank0_n_20\,
      \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r_0\(9 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_data_buf_addr_r_reg[3]\(3 downto 0) => req_data_buf_addr_r(8 downto 5),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(1),
      \req_row_r_lcl_reg[12]\(12) => \^req_row_r_lcl_reg[12]\(10),
      \req_row_r_lcl_reg[12]\(11 downto 0) => req_row_r(24 downto 13),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg => \bank_cntrl[1].bank0_n_28\,
      rnk_config_strobe_ns => \arb_row_col0/rnk_config_strobe_ns\,
      \rnk_config_strobe_r_reg[0]\ => \bank_cntrl[2].bank0_n_30\,
      \rnk_config_strobe_r_reg[0]_0\ => \bank_cntrl[3].bank0_n_24\,
      \rnk_config_strobe_r_reg[0]_1\ => \bank_cntrl[0].bank0_n_26\,
      \rnk_config_strobe_r_reg[0]_2\ => arb_mux0_n_105,
      rnk_config_valid_ns => \arb_row_col0/rnk_config_valid_ns\,
      rnk_config_valid_r => rnk_config_valid_r,
      rnk_config_valid_r_lcl_reg => rnk_config_valid_r_lcl_reg,
      row(12 downto 0) => row(12 downto 0),
      row_cmd_wr(0) => row_cmd_wr(1),
      row_hit_r_reg(0) => row_hit_r_reg_0(0),
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      wait_for_maint_r_lcl_reg => bank_common0_n_11,
      was_priority => was_priority,
      was_wr => was_wr,
      wr_this_rank_r(0) => wr_this_rank_r(1)
    );
\bank_cntrl[2].bank0\: entity work.\mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized1\
     port map (
      CLK => CLK,
      D(0) => \maint_controller.maint_hit_busies_ns\(2),
      Q(2 downto 0) => rb_hit_busies_r(5 downto 3),
      accept_internal_r => accept_internal_r,
      act_this_rank_r(0) => act_this_rank_r(2),
      act_wait_r_lcl_reg => \bank_cntrl[2].bank0_n_53\,
      act_wait_r_lcl_reg_0(0) => sending_row(2),
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_2,
      app_en_r2 => app_en_r2,
      auto_pre_r => auto_pre_r_10,
      auto_pre_r_lcl_reg => auto_pre_r_lcl_reg,
      bm_end_r1_2 => bm_end_r1_2,
      col_wait_r_reg => col_wait_r_reg,
      \compute_tail.tail_r_lcl_reg\ => \bank_cntrl[1].bank0_n_32\,
      demand_act_priority_r => \bank_state0/demand_act_priority_r_14\,
      demand_priority_r => \bank_state0/demand_priority_r_13\,
      demand_priority_r_2 => \bank_state0/demand_priority_r\,
      demand_priority_r_reg => \bank_cntrl[2].bank0_n_30\,
      demand_priority_r_reg_0 => \bank_cntrl[2].bank0_n_54\,
      demand_priority_r_reg_1 => \bank_cntrl[2].bank0_n_55\,
      demand_priority_r_reg_2 => \bank_cntrl[0].bank0_n_27\,
      demand_priority_r_reg_3 => \bank_cntrl[3].bank0_n_25\,
      demand_priority_r_reg_4 => \bank_cntrl[1].bank0_n_28\,
      demanded_prior_r => \bank_state0/demanded_prior_r_12\,
      demanded_prior_r_3 => \bank_state0/demanded_prior_r\,
      demanded_prior_r_reg => \bank_cntrl[1].bank0_n_54\,
      demanded_prior_r_reg_0 => \bank_cntrl[3].bank0_n_49\,
      demanded_prior_r_reg_1 => \bank_cntrl[0].bank0_n_61\,
      \grant_r[3]_i_5\ => \bank_cntrl[3].bank0_n_28\,
      \grant_r[3]_i_5_0\ => \bank_cntrl[3].bank0_n_47\,
      head_r_lcl_reg => \bank_cntrl[2].bank0_n_38\,
      head_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_33\,
      head_r_lcl_reg_1 => \bank_cntrl[0].bank0_n_18\,
      head_r_lcl_reg_2 => \bank_cntrl[1].bank0_n_33\,
      hi_priority => hi_priority,
      idle_r(0) => idle_r(2),
      idle_r_lcl_reg => \^idle_r_lcl_reg_0\,
      idle_r_lcl_reg_0 => \bank_cntrl[2].bank0_n_32\,
      idle_r_lcl_reg_1 => \bank_cntrl[2].bank0_n_35\,
      \maint_controller.maint_hit_busies_r_reg[2]\ => \maint_controller.maint_hit_busies_r_reg[3]\,
      \maint_controller.maint_hit_busies_r_reg[2]_0\(0) => \maint_controller.maint_hit_busies_r\(2),
      maint_rank_r => maint_rank_r,
      maint_sre_r => maint_sre_r,
      maint_zq_r => maint_zq_r,
      ofs_rdy_r => \bank_state0/ofs_rdy_r_11\,
      ofs_rdy_r0 => \bank_state0/ofs_rdy_r0_9\,
      ofs_rdy_r0_0 => \bank_state0/ofs_rdy_r0_8\,
      ofs_rdy_r0_1 => \bank_state0/ofs_rdy_r0\,
      ofs_rdy_r_reg(2) => rd_wr_r(3),
      ofs_rdy_r_reg(1 downto 0) => rd_wr_r(1 downto 0),
      \order_q_r_reg[0]\ => \bank_cntrl[2].bank0_n_28\,
      \order_q_r_reg[0]_0\ => \bank_cntrl[3].bank0_n_19\,
      \order_q_r_reg[1]\ => \bank_cntrl[3].bank0_n_21\,
      ordered_r(0) => ordered_r(2),
      ordered_r_lcl_reg => \^periodic_rd_ack_r_lcl_reg\,
      ordered_r_lcl_reg_0 => was_priority_reg,
      override_demand_ns => \bank_state0/override_demand_ns\,
      override_demand_r => \bank_state0/override_demand_r\,
      p_106_out => p_106_out,
      p_130_out => p_130_out,
      p_13_out => p_13_out,
      p_145_out => p_145_out,
      p_28_out => p_28_out,
      p_67_out => p_67_out,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_lcl_reg_1,
      pass_open_bank_r_lcl_reg_0 => bank_common0_n_13,
      periodic_rd_insert => periodic_rd_insert,
      phy_mc_cmd_full => phy_mc_cmd_full,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_ctl_full_r_reg => periodic_rd_cntr_r_reg_0,
      phy_mc_data_full => phy_mc_data_full,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \bank_cntrl[1].bank0_n_40\,
      \pre_4_1_1T_arb.granted_pre_r_reg_0\(0) => sending_pre(2),
      \pre_4_1_1T_arb.granted_pre_r_reg_1\ => \bank_cntrl[3].bank0_n_30\,
      pre_bm_end_r_reg => \bank_cntrl[2].bank0_n_18\,
      pre_bm_end_r_reg_0 => \bank_cntrl[2].bank0_n_33\,
      pre_passing_open_bank_r_reg => \bank_cntrl[2].bank0_n_37\,
      \q_entry_r[1]_i_2__2\ => \bank_cntrl[0].bank0_n_41\,
      \q_entry_r_reg[0]\ => \bank_cntrl[2].bank0_n_34\,
      \q_entry_r_reg[0]_0\(2) => rb_hit_busy_r(3),
      \q_entry_r_reg[0]_0\(1 downto 0) => rb_hit_busy_r(1 downto 0),
      \q_entry_r_reg[0]_1\ => \bank_cntrl[0].bank0_n_39\,
      \q_entry_r_reg[1]\(0) => q_entry_r(1),
      \q_entry_r_reg[1]_0\ => \bank_cntrl[0].bank0_n_62\,
      q_has_priority_r_reg => bank_common0_n_16,
      q_has_rd_r_reg => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \bank_cntrl[3].bank0_n_17\,
      \ras_timer_r_reg[0]_0\ => \bank_cntrl[0].bank0_n_21\,
      \ras_timer_r_reg[0]_1\ => \bank_cntrl[1].bank0_n_24\,
      \ras_timer_r_reg[0]_2\ => \bank_cntrl[1].bank0_n_36\,
      \ras_timer_r_reg[0]_3\ => \bank_cntrl[0].bank0_n_28\,
      \ras_timer_r_reg[0]_4\ => \bank_cntrl[3].bank0_n_29\,
      \ras_timer_r_reg[1]\ => \bank_cntrl[2].bank0_n_23\,
      \ras_timer_r_reg[1]_0\ => \bank_cntrl[3].bank0_n_18\,
      \ras_timer_r_reg[1]_1\ => \bank_cntrl[0].bank0_n_23\,
      \ras_timer_r_reg[1]_2\ => \bank_cntrl[1].bank0_n_25\,
      ras_timer_zero_r_reg => \bank_cntrl[2].bank0_n_19\,
      ras_timer_zero_r_reg_0 => \bank_cntrl[2].bank0_n_39\,
      ras_timer_zero_r_reg_1(1) => sending_col(2),
      ras_timer_zero_r_reg_1(0) => sending_col(0),
      ras_timer_zero_r_reg_2 => ras_timer_zero_r_reg_1,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \bank_cntrl[1].bank0_n_17\,
      rb_hit_busy_r(0) => rb_hit_busy_r(2),
      rd_this_rank_r(0) => rd_this_rank_r(2),
      rd_wr_r(0) => rd_wr_r(2),
      rd_wr_r_lcl_reg => \bank_cntrl[2].bank0_n_27\,
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg_0,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]_1\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0),
      req_bank_rdy_r_reg => \bank_cntrl[3].bank0_n_20\,
      \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r_7\(9 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_data_buf_addr_r_reg[3]\(3 downto 0) => req_data_buf_addr_r(13 downto 10),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(2),
      \req_row_r_lcl_reg[12]\(12) => \^req_row_r_lcl_reg[12]\(11),
      \req_row_r_lcl_reg[12]\(11 downto 0) => req_row_r(37 downto 26),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg => \bank_cntrl[2].bank0_n_31\,
      \rnk_config_strobe_r_reg[0]\ => arb_mux0_n_105,
      row(12 downto 0) => row(12 downto 0),
      row_cmd_wr(0) => row_cmd_wr(2),
      row_hit_r_reg(0) => row_hit_r_reg_1(0),
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      \starve_limit_cntr_r_reg[0]\ => \^sent_col\,
      wait_for_maint_r_lcl_reg => bank_common0_n_11,
      was_priority => was_priority,
      was_wr => was_wr,
      wr_this_rank_r(0) => wr_this_rank_r(2)
    );
\bank_cntrl[3].bank0\: entity work.\mig_7series_0_mig_7series_v4_2_bank_cntrl__parameterized2\
     port map (
      CLK => CLK,
      D(0) => \maint_controller.maint_hit_busies_ns\(3),
      Q(3 downto 0) => sending_col(3 downto 0),
      accept_internal_r => accept_internal_r,
      act_this_rank_r(0) => act_this_rank_r(3),
      act_wait_r_lcl_i_4 => \bank_cntrl[1].bank0_n_37\,
      act_wait_r_lcl_i_4_0 => \bank_cntrl[2].bank0_n_37\,
      act_wait_r_lcl_i_4_1 => \bank_cntrl[0].bank0_n_29\,
      act_wait_r_lcl_reg => \bank_cntrl[3].bank0_n_46\,
      act_wait_r_lcl_reg_0(0) => sending_row(3),
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_0,
      app_en_r2 => app_en_r2,
      auto_pre_r => auto_pre_r_16,
      auto_pre_r_lcl_reg => auto_pre_r_lcl_reg,
      bm_end_r1_4 => bm_end_r1_4,
      col_wait_r_reg => \bank_cntrl[3].bank0_n_16\,
      col_wait_r_reg_0 => col_wait_r_reg,
      demand_act_priority_r => \bank_state0/demand_act_priority_r_20\,
      demand_priority_r => \bank_state0/demand_priority_r_19\,
      demand_priority_r_0 => \bank_state0/demand_priority_r\,
      demand_priority_r_3 => \bank_state0/demand_priority_r_5\,
      demand_priority_r_5 => \bank_state0/demand_priority_r_13\,
      demand_priority_r_reg => \bank_cntrl[3].bank0_n_24\,
      demand_priority_r_reg_0 => \bank_cntrl[0].bank0_n_27\,
      demand_priority_r_reg_1 => \bank_cntrl[1].bank0_n_28\,
      demand_priority_r_reg_2 => \bank_cntrl[2].bank0_n_31\,
      demand_priority_r_reg_3 => \^sent_col\,
      demanded_prior_r => \bank_state0/demanded_prior_r_18\,
      demanded_prior_r_1 => \bank_state0/demanded_prior_r\,
      demanded_prior_r_2 => \bank_state0/demanded_prior_r_4\,
      demanded_prior_r_4 => \bank_state0/demanded_prior_r_12\,
      demanded_prior_r_reg => \bank_cntrl[3].bank0_n_47\,
      demanded_prior_r_reg_0 => \bank_cntrl[3].bank0_n_48\,
      demanded_prior_r_reg_1 => arb_mux0_n_102,
      \grant_r[3]_i_12\(0) => rb_hit_busies_r(3),
      \grant_r_reg[0]\ => arb_mux0_n_22,
      \grant_r_reg[3]\ => \bank_cntrl[3].bank0_n_30\,
      \grant_r_reg[3]_0\ => \bank_cntrl[3].bank0_n_49\,
      head_r_lcl_reg => \bank_cntrl[3].bank0_n_31\,
      head_r_lcl_reg_0 => \bank_cntrl[2].bank0_n_33\,
      head_r_lcl_reg_1 => \bank_cntrl[0].bank0_n_18\,
      head_r_lcl_reg_2 => \bank_cntrl[0].bank0_n_33\,
      hi_priority => hi_priority,
      idle_r(0) => idle_r(3),
      idle_r_lcl_reg => \^idle_r_lcl_reg\,
      \maint_controller.maint_hit_busies_r_reg[3]\ => \maint_controller.maint_hit_busies_r_reg[3]\,
      \maint_controller.maint_hit_busies_r_reg[3]_0\(0) => \maint_controller.maint_hit_busies_r\(3),
      maint_rank_r => maint_rank_r,
      maint_sre_r => maint_sre_r,
      maint_zq_r => maint_zq_r,
      ofs_rdy_r => \bank_state0/ofs_rdy_r_17\,
      ofs_rdy_r0 => \bank_state0/ofs_rdy_r0\,
      ofs_rdy_r_reg => periodic_rd_cntr_r_reg_0,
      \order_q_r_reg[0]\ => \bank_cntrl[3].bank0_n_22\,
      \order_q_r_reg[0]_0\(2 downto 0) => ordered_r(2 downto 0),
      ordered_r_lcl_reg => \bank_cntrl[3].bank0_n_19\,
      ordered_r_lcl_reg_0 => \bank_cntrl[3].bank0_n_21\,
      ordered_r_lcl_reg_1 => \^periodic_rd_ack_r_lcl_reg\,
      ordered_r_lcl_reg_2 => was_priority_reg,
      p_106_out => p_106_out,
      p_130_out => p_130_out,
      p_13_out => p_13_out,
      p_145_out => p_145_out,
      p_28_out => p_28_out,
      p_67_out => p_67_out,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_lcl_reg_2,
      pass_open_bank_r_lcl_reg_0 => bank_common0_n_12,
      periodic_rd_insert => periodic_rd_insert,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \bank_cntrl[0].bank0_n_59\,
      pre_bm_end_r_reg => \bank_cntrl[3].bank0_n_26\,
      pre_bm_end_r_reg_0(0) => sending_pre(3),
      pre_passing_open_bank_r_reg => \bank_cntrl[3].bank0_n_29\,
      \q_entry_r_reg[0]\ => \bank_cntrl[0].bank0_n_37\,
      \q_entry_r_reg[1]\ => \bank_cntrl[0].bank0_n_35\,
      \q_entry_r_reg[1]_0\ => \bank_cntrl[0].bank0_n_32\,
      \q_entry_r_reg[1]_1\ => \bank_cntrl[0].bank0_n_36\,
      \q_entry_r_reg[1]_2\ => \bank_cntrl[0].bank0_n_38\,
      \q_entry_r_reg[1]_3\ => bank_common0_n_9,
      q_has_priority_r_reg => bank_common0_n_16,
      q_has_rd_r_reg => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \bank_cntrl[0].bank0_n_21\,
      \ras_timer_r_reg[0]_0\ => \bank_cntrl[1].bank0_n_24\,
      \ras_timer_r_reg[0]_1\ => \bank_cntrl[2].bank0_n_23\,
      \ras_timer_r_reg[0]_2\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\,
      \ras_timer_r_reg[1]\ => \bank_cntrl[3].bank0_n_17\,
      \ras_timer_r_reg[1]_0\ => \bank_cntrl[0].bank0_n_23\,
      \ras_timer_r_reg[1]_1\ => \bank_cntrl[1].bank0_n_25\,
      \ras_timer_r_reg[1]_2\ => \bank_cntrl[2].bank0_n_27\,
      ras_timer_zero_r_reg => \bank_cntrl[3].bank0_n_32\,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_2,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ => \bank_cntrl[3].bank0_n_28\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \bank_cntrl[1].bank0_n_17\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ => \bank_cntrl[2].bank0_n_18\,
      rb_hit_busy_r(2 downto 0) => rb_hit_busy_r(2 downto 0),
      rb_hit_busy_r_reg(0) => rb_hit_busy_r(3),
      rd_this_rank_r(0) => rd_this_rank_r(3),
      rd_wr_r_lcl_reg(0) => rd_wr_r(3),
      rd_wr_r_lcl_reg_0 => \bank_cntrl[3].bank0_n_18\,
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_0,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0),
      \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r_15\(9 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_data_buf_addr_r_reg[3]\(3 downto 0) => req_data_buf_addr_r(18 downto 15),
      \req_data_buf_addr_r_reg[3]_0\(3 downto 0) => \req_data_buf_addr_r_reg[3]\(3 downto 0),
      req_periodic_rd_r(0) => req_periodic_rd_r(3),
      \req_row_r_lcl_reg[12]\(12) => \^req_row_r_lcl_reg[12]\(12),
      \req_row_r_lcl_reg[12]\(11 downto 0) => req_row_r(50 downto 39),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg => \bank_cntrl[3].bank0_n_20\,
      req_wr_r_lcl_reg_0 => \bank_cntrl[3].bank0_n_25\,
      \rnk_config_strobe_r_reg[0]\ => arb_mux0_n_103,
      \rnk_config_strobe_r_reg[0]_0\ => arb_mux0_n_105,
      row(12 downto 0) => row(12 downto 0),
      row_cmd_wr(0) => row_cmd_wr(3),
      row_hit_r_reg(0) => row_hit_r_reg_2(0),
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      wait_for_maint_r_lcl_reg => bank_common0_n_11,
      was_priority => was_priority,
      was_wr => was_wr,
      wr_this_rank_r(0) => wr_this_rank_r(3)
    );
bank_common0: entity work.mig_7series_0_mig_7series_v4_2_bank_common
     port map (
      CLK => CLK,
      D(3 downto 0) => \maint_controller.maint_hit_busies_ns\(3 downto 0),
      Q(3 downto 0) => \maint_controller.maint_hit_busies_r\(3 downto 0),
      accept_internal_r => accept_internal_r,
      accept_ns => \^accept_ns\,
      accept_r_reg_0 => bank_common0_n_16,
      app_en_r2 => app_en_r2,
      \generate_maint_cmds.insert_maint_r_lcl_reg_0\ => \^insert_maint_r\,
      \generate_maint_cmds.insert_maint_r_lcl_reg_1\ => bank_common0_n_17,
      \grant_r[3]_i_2__1\ => \bank_cntrl[3].bank0_n_46\,
      \grant_r[3]_i_2__1_0\ => \bank_cntrl[2].bank0_n_53\,
      \grant_r[3]_i_2__1_1\(0) => sending_row(1),
      \grant_r[3]_i_2__1_2\ => \bank_cntrl[0].bank0_n_22\,
      hi_priority => hi_priority,
      inhbt_act_faw_r => inhbt_act_faw_r,
      \maint_controller.maint_wip_r_lcl_reg_0\ => bank_common0_n_11,
      \maint_controller.maint_wip_r_lcl_reg_1\ => \rtp_timer_r_reg[0]\,
      maint_req_r => maint_req_r,
      maint_srx_r => maint_srx_r,
      maint_wip_r => maint_wip_r,
      maint_zq_r => maint_zq_r,
      p_13_out => p_13_out,
      p_9_in => p_9_in,
      periodic_rd_ack_ns => periodic_rd_ack_ns,
      periodic_rd_ack_r_lcl_reg_0 => \^periodic_rd_ack_r_lcl_reg\,
      periodic_rd_ack_r_lcl_reg_1 => bank_common0_n_8,
      periodic_rd_ack_r_lcl_reg_2 => bank_common0_n_9,
      periodic_rd_ack_r_lcl_reg_3 => bank_common0_n_12,
      periodic_rd_ack_r_lcl_reg_4 => bank_common0_n_15,
      periodic_rd_cntr_r_reg_0 => periodic_rd_cntr_r_reg,
      periodic_rd_cntr_r_reg_1 => periodic_rd_cntr_r_reg_0,
      periodic_rd_insert => periodic_rd_insert,
      \q_entry_r_reg[1]\ => \bank_cntrl[2].bank0_n_18\,
      rb_hit_busy_r(3 downto 0) => rb_hit_busy_r(3 downto 0),
      rb_hit_busy_r_reg => bank_common0_n_13,
      rb_hit_busy_r_reg_0 => bank_common0_n_14,
      req_periodic_rd_r_lcl_reg => req_periodic_rd_r_lcl_reg,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\(0) => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\(0),
      \rstdiv0_sync_r1_reg_rep__12\ => \rstdiv0_sync_r1_reg_rep__12\,
      was_priority => was_priority,
      was_priority_reg_0 => was_priority_reg,
      was_wr => was_wr,
      was_wr0 => was_wr0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_mc_phy is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mem_dqs_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mem_dqs_ts : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg : out STD_LOGIC;
    A_rst_primitives_reg_0 : out STD_LOGIC;
    out_dq_2 : out STD_LOGIC;
    mem_dq_ts : out STD_LOGIC_VECTOR ( 17 downto 0 );
    out_dm_0 : out STD_LOGIC;
    out_dq_0 : out STD_LOGIC;
    out_dq_6 : out STD_LOGIC;
    out_dq_3 : out STD_LOGIC;
    out_dq_1 : out STD_LOGIC;
    out_dq_4 : out STD_LOGIC;
    out_dq_7 : out STD_LOGIC;
    out_dq_5 : out STD_LOGIC;
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rd_ptr_reg[0]\ : out STD_LOGIC;
    \rd_ptr_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[2]\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC;
    \rd_ptr_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    \rd_ptr_reg[2]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg_1 : out STD_LOGIC;
    out_dq_13 : out STD_LOGIC;
    out_dq_8 : out STD_LOGIC;
    out_dq_15 : out STD_LOGIC;
    out_dq_12 : out STD_LOGIC;
    out_dq_10 : out STD_LOGIC;
    out_dq_9 : out STD_LOGIC;
    out_dq_11 : out STD_LOGIC;
    out_dq_14 : out STD_LOGIC;
    out_dm_1 : out STD_LOGIC;
    \rd_ptr_reg[0]_1\ : out STD_LOGIC;
    \rd_ptr_reg[1]_1\ : out STD_LOGIC;
    \rd_ptr_reg[2]_1\ : out STD_LOGIC;
    \rd_ptr_reg[3]_1\ : out STD_LOGIC;
    phy_mc_ctl_full : out STD_LOGIC;
    ref_dll_lock : out STD_LOGIC;
    idelay_ld_rst : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_empty_reg[1]\ : out STD_LOGIC;
    init_complete_r1_timing_reg : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    \my_empty_reg[1]_2\ : out STD_LOGIC;
    \FSM_onehot_cal1_state_r_reg[13]\ : out STD_LOGIC;
    \pi_counter_read_val_reg[5]\ : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    \my_empty_reg[0]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 65 downto 0 );
    app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ : out STD_LOGIC;
    \pi_counter_read_val_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_rddata_en : out STD_LOGIC;
    p_128_in : out STD_LOGIC;
    \mcGo_r_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    in0 : out STD_LOGIC;
    phy_mc_data_full : out STD_LOGIC;
    wr_en_2 : out STD_LOGIC;
    wr_en_3 : out STD_LOGIC;
    phy_mc_cmd_full : out STD_LOGIC;
    wr_en_4 : out STD_LOGIC;
    \wr_ptr_reg[0]\ : out STD_LOGIC;
    \wr_ptr_reg[1]\ : out STD_LOGIC;
    \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \wr_ptr_reg[0]_0\ : out STD_LOGIC;
    \wr_ptr_reg[1]_0\ : out STD_LOGIC;
    \wr_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    A_rst_primitives_reg_2 : out STD_LOGIC_VECTOR ( 9 downto 0 );
    mem_out : out STD_LOGIC_VECTOR ( 30 downto 0 );
    wr_en : out STD_LOGIC;
    p_1_in : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_61\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_62\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[0]_3\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \slave_ts.oserdes_slave_ts\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_0\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_1\ : in STD_LOGIC;
    D1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D9 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ififo_rst_reg0 : in STD_LOGIC;
    ofifo_rst_reg0 : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC;
    out_fifo_2 : in STD_LOGIC;
    \my_empty_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \my_empty_reg[6]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[6]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[6]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \input_[8].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    LD0_0 : in STD_LOGIC;
    CLKB0_5 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_2\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_3\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_4\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \slave_ts.oserdes_slave_ts_2\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_3\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_4\ : in STD_LOGIC;
    D0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ififo_rst_reg0_1 : in STD_LOGIC;
    ofifo_rst_reg0_2 : in STD_LOGIC;
    phy_ctl_wr_i2 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
    RST0 : in STD_LOGIC;
    rst_out_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_reg[3]_6\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \rd_ptr_reg[3]_7\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_reg[3]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_9\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_ptr_timing_reg[0]\ : in STD_LOGIC;
    calib_cmd_wren : in STD_LOGIC;
    app_rd_data_valid_0 : in STD_LOGIC;
    mux_wrdata_en : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC;
    calib_wrdata_en : in STD_LOGIC;
    out_fifo_3 : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_1\ : in STD_LOGIC;
    out_fifo_4 : in STD_LOGIC_VECTOR ( 32 downto 0 );
    \cnt_idel_dec_cpt_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    out_fifo_5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    app_rd_data_valid_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.tail_r_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    cnt_pwron_cke_done_r : in STD_LOGIC;
    mux_cmd_wren : in STD_LOGIC;
    out_fifo_7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \mcGo_r_reg[0]_0\ : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \app_rd_data[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    calib_sel : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_mc_phy : entity is "mig_7series_v4_2_ddr_mc_phy";
end mig_7series_0_mig_7series_v4_2_ddr_mc_phy;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_mc_phy is
  signal \^mcgo_r_reg[15]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mcGo_w : STD_LOGIC_VECTOR ( 0 to 0 );
  signal p_0_in : STD_LOGIC_VECTOR ( 15 downto 1 );
begin
  \mcGo_r_reg[15]_0\(0) <= \^mcgo_r_reg[15]_0\(0);
calib_ctl_wren_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^mcgo_r_reg[15]_0\(0),
      I1 => cnt_pwron_cke_done_r,
      O => p_128_in
    );
\ddr_phy_4lanes_0.u_ddr_phy_4lanes\: entity work.mig_7series_0_mig_7series_v4_2_ddr_phy_4lanes
     port map (
      A_rst_primitives_reg_0 => A_rst_primitives_reg,
      A_rst_primitives_reg_1 => A_rst_primitives_reg_0,
      A_rst_primitives_reg_2 => A_rst_primitives_reg_1,
      A_rst_primitives_reg_3(9 downto 0) => A_rst_primitives_reg_2(9 downto 0),
      CLK => CLK,
      CLKB0 => CLKB0,
      CLKB0_5 => CLKB0_5,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      D(0) => mcGo_w(0),
      D0(7 downto 0) => D0(7 downto 0),
      D1(7 downto 0) => D1(7 downto 0),
      D2(7 downto 0) => D2(7 downto 0),
      D3(7 downto 0) => D3(7 downto 0),
      D4(7 downto 0) => D4(7 downto 0),
      D5(7 downto 0) => D5(7 downto 0),
      D6(7 downto 0) => D6(7 downto 0),
      D7(7 downto 0) => D7(7 downto 0),
      D8(7 downto 0) => D8(7 downto 0),
      D9(7 downto 0) => D9(7 downto 0),
      \FSM_onehot_cal1_state_r_reg[13]\ => \FSM_onehot_cal1_state_r_reg[13]\,
      LD0 => LD0,
      LD0_0 => LD0_0,
      Q(10 downto 0) => Q(10 downto 0),
      RST0 => RST0,
      SR(0) => SR(0),
      app_rd_data(127 downto 0) => app_rd_data(127 downto 0),
      \app_rd_data[117]\(63 downto 0) => \app_rd_data[117]\(63 downto 0),
      app_rd_data_valid => app_rd_data_valid,
      app_rd_data_valid_0 => app_rd_data_valid_0,
      app_rd_data_valid_1(0) => app_rd_data_valid_1(0),
      calib_cmd_wren => calib_cmd_wren,
      calib_sel(0) => calib_sel(0),
      calib_wrdata_en => calib_wrdata_en,
      \cnt_idel_dec_cpt_r_reg[0]\(0) => \cnt_idel_dec_cpt_r_reg[0]\(0),
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0) => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0),
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      idelay_inc => idelay_inc,
      idelay_ld_rst => idelay_ld_rst,
      ififo_rst_reg0 => ififo_rst_reg0,
      ififo_rst_reg0_1 => ififo_rst_reg0_1,
      in0 => in0,
      init_complete_r1_timing_reg => init_complete_r1_timing_reg,
      \input_[8].iserdes_dq_.iserdesdq\ => \input_[8].iserdes_dq_.iserdesdq\,
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq\,
      mc_cas_n(1 downto 0) => mc_cas_n(1 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(0) => mc_ras_n(0),
      mc_wrdata_en => mc_wrdata_en,
      mem_dq_in(15 downto 0) => mem_dq_in(15 downto 0),
      mem_dq_out(11 downto 0) => mem_dq_out(11 downto 0),
      mem_dq_ts(17 downto 0) => mem_dq_ts(17 downto 0),
      mem_dqs_in(1 downto 0) => mem_dqs_in(1 downto 0),
      mem_dqs_out(1 downto 0) => mem_dqs_out(1 downto 0),
      mem_dqs_ts(1 downto 0) => mem_dqs_ts(1 downto 0),
      mem_out(30 downto 0) => mem_out(30 downto 0),
      mem_refclk => mem_refclk,
      mux_cmd_wren => mux_cmd_wren,
      mux_wrdata_en => mux_wrdata_en,
      \my_empty_reg[0]\ => \my_empty_reg[0]\,
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]_1\,
      \my_empty_reg[1]_2\ => \my_empty_reg[1]_2\,
      \my_empty_reg[6]\(3 downto 0) => \my_empty_reg[6]\(3 downto 0),
      \my_empty_reg[6]_0\(3 downto 0) => \my_empty_reg[6]_0\(3 downto 0),
      \my_empty_reg[6]_1\(3 downto 0) => \my_empty_reg[6]_1\(3 downto 0),
      \my_empty_reg[6]_2\(3 downto 0) => \my_empty_reg[6]_2\(3 downto 0),
      \my_empty_reg[6]_3\(2 downto 0) => \my_empty_reg[6]_3\(2 downto 0),
      \my_empty_reg[6]_4\(7 downto 0) => \my_empty_reg[6]_4\(7 downto 0),
      \my_empty_reg[6]_5\(7 downto 0) => \my_empty_reg[6]_5\(7 downto 0),
      \my_empty_reg[6]_6\(3 downto 0) => \my_empty_reg[6]_6\(3 downto 0),
      \my_empty_reg[6]_7\(3 downto 0) => \my_empty_reg[6]_7\(3 downto 0),
      \my_empty_reg[6]_8\(3 downto 0) => \my_empty_reg[6]_8\(3 downto 0),
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      ofifo_rst_reg0 => ofifo_rst_reg0,
      ofifo_rst_reg0_2 => ofifo_rst_reg0_2,
      \out\(1 downto 0) => \out\(1 downto 0),
      out_dm_0 => out_dm_0,
      out_dm_1 => out_dm_1,
      out_dq_0 => out_dq_0,
      out_dq_1 => out_dq_1,
      out_dq_10 => out_dq_10,
      out_dq_11 => out_dq_11,
      out_dq_12 => out_dq_12,
      out_dq_13 => out_dq_13,
      out_dq_14 => out_dq_14,
      out_dq_15 => out_dq_15,
      out_dq_2 => out_dq_2,
      out_dq_3 => out_dq_3,
      out_dq_4 => out_dq_4,
      out_dq_5 => out_dq_5,
      out_dq_6 => out_dq_6,
      out_dq_7 => out_dq_7,
      out_dq_8 => out_dq_8,
      out_dq_9 => out_dq_9,
      out_fifo => out_fifo,
      out_fifo_0 => out_fifo_0,
      out_fifo_1 => out_fifo_1,
      out_fifo_2 => out_fifo_2,
      out_fifo_3 => out_fifo_3,
      out_fifo_4(32 downto 0) => out_fifo_4(32 downto 0),
      out_fifo_5(7 downto 0) => out_fifo_5(7 downto 0),
      out_fifo_6(7 downto 0) => out_fifo_6(7 downto 0),
      out_fifo_7(1 downto 0) => out_fifo_7(1 downto 0),
      p_1_in => p_1_in,
      phy_ctl_wr_i2 => phy_ctl_wr_i2,
      phy_dout(31 downto 0) => phy_dout(31 downto 0),
      phy_mc_cmd_full => phy_mc_cmd_full,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      phy_rddata_en => phy_rddata_en,
      phy_read_calib => phy_read_calib,
      \pi_counter_read_val_reg[5]_0\ => \pi_counter_read_val_reg[5]\,
      \pi_counter_read_val_reg[5]_1\(5 downto 0) => \pi_counter_read_val_reg[5]_0\(5 downto 0),
      pi_dqs_found_lanes(1 downto 0) => pi_dqs_found_lanes(1 downto 0),
      \pi_dqs_found_lanes_r1_reg[0]\ => \pi_dqs_found_lanes_r1_reg[0]\,
      \pi_dqs_found_lanes_r1_reg[0]_0\ => \pi_dqs_found_lanes_r1_reg[0]_0\,
      \pi_dqs_found_lanes_r1_reg[0]_1\ => \pi_dqs_found_lanes_r1_reg[0]_1\,
      \pi_dqs_found_lanes_r1_reg[0]_2\ => \pi_dqs_found_lanes_r1_reg[0]_2\,
      \pi_dqs_found_lanes_r1_reg[0]_3\ => \pi_dqs_found_lanes_r1_reg[0]_3\,
      \pi_dqs_found_lanes_r1_reg[2]\ => \pi_dqs_found_lanes_r1_reg[2]\,
      \pi_dqs_found_lanes_r1_reg[2]_0\ => \pi_dqs_found_lanes_r1_reg[2]_0\,
      \pi_dqs_found_lanes_r1_reg[2]_1\ => \pi_dqs_found_lanes_r1_reg[2]_1\,
      \pi_dqs_found_lanes_r1_reg[2]_2\ => \pi_dqs_found_lanes_r1_reg[2]_2\,
      \pi_dqs_found_lanes_r1_reg[2]_3\ => \pi_dqs_found_lanes_r1_reg[2]_3\,
      \pi_dqs_found_lanes_r1_reg[2]_4\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[2]_4\(5 downto 0),
      pll_locked => pll_locked,
      \po_stg2_wrcal_cnt_reg[0]\ => \po_stg2_wrcal_cnt_reg[0]\,
      \po_stg2_wrcal_cnt_reg[0]_0\ => \po_stg2_wrcal_cnt_reg[0]_0\,
      \po_stg2_wrcal_cnt_reg[0]_1\ => \po_stg2_wrcal_cnt_reg[0]_1\,
      \po_stg2_wrcal_cnt_reg[0]_10\ => \po_stg2_wrcal_cnt_reg[0]_10\,
      \po_stg2_wrcal_cnt_reg[0]_11\ => \po_stg2_wrcal_cnt_reg[0]_11\,
      \po_stg2_wrcal_cnt_reg[0]_12\ => \po_stg2_wrcal_cnt_reg[0]_12\,
      \po_stg2_wrcal_cnt_reg[0]_13\ => \po_stg2_wrcal_cnt_reg[0]_13\,
      \po_stg2_wrcal_cnt_reg[0]_14\ => \po_stg2_wrcal_cnt_reg[0]_14\,
      \po_stg2_wrcal_cnt_reg[0]_15\ => \po_stg2_wrcal_cnt_reg[0]_15\,
      \po_stg2_wrcal_cnt_reg[0]_16\ => \po_stg2_wrcal_cnt_reg[0]_16\,
      \po_stg2_wrcal_cnt_reg[0]_17\ => \po_stg2_wrcal_cnt_reg[0]_17\,
      \po_stg2_wrcal_cnt_reg[0]_18\ => \po_stg2_wrcal_cnt_reg[0]_18\,
      \po_stg2_wrcal_cnt_reg[0]_19\ => \po_stg2_wrcal_cnt_reg[0]_19\,
      \po_stg2_wrcal_cnt_reg[0]_2\ => \po_stg2_wrcal_cnt_reg[0]_2\,
      \po_stg2_wrcal_cnt_reg[0]_20\ => \po_stg2_wrcal_cnt_reg[0]_20\,
      \po_stg2_wrcal_cnt_reg[0]_21\ => \po_stg2_wrcal_cnt_reg[0]_21\,
      \po_stg2_wrcal_cnt_reg[0]_22\ => \po_stg2_wrcal_cnt_reg[0]_22\,
      \po_stg2_wrcal_cnt_reg[0]_23\ => \po_stg2_wrcal_cnt_reg[0]_23\,
      \po_stg2_wrcal_cnt_reg[0]_24\ => \po_stg2_wrcal_cnt_reg[0]_24\,
      \po_stg2_wrcal_cnt_reg[0]_25\ => \po_stg2_wrcal_cnt_reg[0]_25\,
      \po_stg2_wrcal_cnt_reg[0]_26\ => \po_stg2_wrcal_cnt_reg[0]_26\,
      \po_stg2_wrcal_cnt_reg[0]_27\ => \po_stg2_wrcal_cnt_reg[0]_27\,
      \po_stg2_wrcal_cnt_reg[0]_28\ => \po_stg2_wrcal_cnt_reg[0]_28\,
      \po_stg2_wrcal_cnt_reg[0]_29\ => \po_stg2_wrcal_cnt_reg[0]_29\,
      \po_stg2_wrcal_cnt_reg[0]_3\ => \po_stg2_wrcal_cnt_reg[0]_3\,
      \po_stg2_wrcal_cnt_reg[0]_30\ => \po_stg2_wrcal_cnt_reg[0]_30\,
      \po_stg2_wrcal_cnt_reg[0]_31\ => \po_stg2_wrcal_cnt_reg[0]_31\,
      \po_stg2_wrcal_cnt_reg[0]_32\ => \po_stg2_wrcal_cnt_reg[0]_32\,
      \po_stg2_wrcal_cnt_reg[0]_33\ => \po_stg2_wrcal_cnt_reg[0]_33\,
      \po_stg2_wrcal_cnt_reg[0]_34\ => \po_stg2_wrcal_cnt_reg[0]_34\,
      \po_stg2_wrcal_cnt_reg[0]_35\ => \po_stg2_wrcal_cnt_reg[0]_35\,
      \po_stg2_wrcal_cnt_reg[0]_36\ => \po_stg2_wrcal_cnt_reg[0]_36\,
      \po_stg2_wrcal_cnt_reg[0]_37\ => \po_stg2_wrcal_cnt_reg[0]_37\,
      \po_stg2_wrcal_cnt_reg[0]_38\ => \po_stg2_wrcal_cnt_reg[0]_38\,
      \po_stg2_wrcal_cnt_reg[0]_39\ => \po_stg2_wrcal_cnt_reg[0]_39\,
      \po_stg2_wrcal_cnt_reg[0]_4\ => \po_stg2_wrcal_cnt_reg[0]_4\,
      \po_stg2_wrcal_cnt_reg[0]_40\ => \po_stg2_wrcal_cnt_reg[0]_40\,
      \po_stg2_wrcal_cnt_reg[0]_41\ => \po_stg2_wrcal_cnt_reg[0]_41\,
      \po_stg2_wrcal_cnt_reg[0]_42\ => \po_stg2_wrcal_cnt_reg[0]_42\,
      \po_stg2_wrcal_cnt_reg[0]_43\ => \po_stg2_wrcal_cnt_reg[0]_43\,
      \po_stg2_wrcal_cnt_reg[0]_44\ => \po_stg2_wrcal_cnt_reg[0]_44\,
      \po_stg2_wrcal_cnt_reg[0]_45\ => \po_stg2_wrcal_cnt_reg[0]_45\,
      \po_stg2_wrcal_cnt_reg[0]_46\ => \po_stg2_wrcal_cnt_reg[0]_46\,
      \po_stg2_wrcal_cnt_reg[0]_47\ => \po_stg2_wrcal_cnt_reg[0]_47\,
      \po_stg2_wrcal_cnt_reg[0]_48\ => \po_stg2_wrcal_cnt_reg[0]_48\,
      \po_stg2_wrcal_cnt_reg[0]_49\ => \po_stg2_wrcal_cnt_reg[0]_49\,
      \po_stg2_wrcal_cnt_reg[0]_5\ => \po_stg2_wrcal_cnt_reg[0]_5\,
      \po_stg2_wrcal_cnt_reg[0]_50\ => \po_stg2_wrcal_cnt_reg[0]_50\,
      \po_stg2_wrcal_cnt_reg[0]_51\ => \po_stg2_wrcal_cnt_reg[0]_51\,
      \po_stg2_wrcal_cnt_reg[0]_52\ => \po_stg2_wrcal_cnt_reg[0]_52\,
      \po_stg2_wrcal_cnt_reg[0]_53\ => \po_stg2_wrcal_cnt_reg[0]_53\,
      \po_stg2_wrcal_cnt_reg[0]_54\ => \po_stg2_wrcal_cnt_reg[0]_54\,
      \po_stg2_wrcal_cnt_reg[0]_55\ => \po_stg2_wrcal_cnt_reg[0]_55\,
      \po_stg2_wrcal_cnt_reg[0]_56\ => \po_stg2_wrcal_cnt_reg[0]_56\,
      \po_stg2_wrcal_cnt_reg[0]_57\ => \po_stg2_wrcal_cnt_reg[0]_57\,
      \po_stg2_wrcal_cnt_reg[0]_58\ => \po_stg2_wrcal_cnt_reg[0]_58\,
      \po_stg2_wrcal_cnt_reg[0]_59\ => \po_stg2_wrcal_cnt_reg[0]_59\,
      \po_stg2_wrcal_cnt_reg[0]_6\ => \po_stg2_wrcal_cnt_reg[0]_6\,
      \po_stg2_wrcal_cnt_reg[0]_60\ => \po_stg2_wrcal_cnt_reg[0]_60\,
      \po_stg2_wrcal_cnt_reg[0]_61\ => \po_stg2_wrcal_cnt_reg[0]_61\,
      \po_stg2_wrcal_cnt_reg[0]_62\ => \po_stg2_wrcal_cnt_reg[0]_62\,
      \po_stg2_wrcal_cnt_reg[0]_7\ => \po_stg2_wrcal_cnt_reg[0]_7\,
      \po_stg2_wrcal_cnt_reg[0]_8\ => \po_stg2_wrcal_cnt_reg[0]_8\,
      \po_stg2_wrcal_cnt_reg[0]_9\ => \po_stg2_wrcal_cnt_reg[0]_9\,
      \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\,
      \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]_0\,
      \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_1\,
      \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\,
      \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]_0\,
      \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_1\,
      \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\,
      \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]_0\,
      \rd_ptr_reg[2]_1\ => \rd_ptr_reg[2]_1\,
      \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\,
      \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]_0\,
      \rd_ptr_reg[3]_1\ => \rd_ptr_reg[3]_1\,
      \rd_ptr_reg[3]_2\(3 downto 0) => \rd_ptr_reg[3]_2\(3 downto 0),
      \rd_ptr_reg[3]_3\(3 downto 0) => \rd_ptr_reg[3]_3\(3 downto 0),
      \rd_ptr_reg[3]_4\(3 downto 0) => \rd_ptr_reg[3]_4\(3 downto 0),
      \rd_ptr_reg[3]_5\(7 downto 0) => \rd_ptr_reg[3]_5\(7 downto 0),
      \rd_ptr_reg[3]_6\(4 downto 0) => \rd_ptr_reg[3]_6\(4 downto 0),
      \rd_ptr_reg[3]_7\(0) => \rd_ptr_reg[3]_7\(0),
      \rd_ptr_reg[3]_8\(3 downto 0) => \rd_ptr_reg[3]_8\(3 downto 0),
      \rd_ptr_reg[3]_9\(0) => \rd_ptr_reg[3]_9\(0),
      \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0),
      \read_fifo.tail_r_reg[4]\(0) => \read_fifo.tail_r_reg[4]\(0),
      ref_dll_lock => ref_dll_lock,
      rst_out_reg_0(0) => rst_out_reg(0),
      \slave_ts.oserdes_slave_ts\ => \slave_ts.oserdes_slave_ts\,
      \slave_ts.oserdes_slave_ts_0\ => \slave_ts.oserdes_slave_ts_0\,
      \slave_ts.oserdes_slave_ts_1\ => \slave_ts.oserdes_slave_ts_1\,
      \slave_ts.oserdes_slave_ts_2\ => \slave_ts.oserdes_slave_ts_2\,
      \slave_ts.oserdes_slave_ts_3\ => \slave_ts.oserdes_slave_ts_3\,
      \slave_ts.oserdes_slave_ts_4\ => \slave_ts.oserdes_slave_ts_4\,
      sync_pulse => sync_pulse,
      wr_en => wr_en,
      wr_en_2 => wr_en_2,
      wr_en_3 => wr_en_3,
      wr_en_4 => wr_en_4,
      \wr_ptr_reg[0]\ => \wr_ptr_reg[0]\,
      \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]_0\,
      \wr_ptr_reg[1]\ => \wr_ptr_reg[1]\,
      \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]_0\,
      \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0),
      \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0),
      \wr_ptr_reg[3]_1\(3 downto 0) => \wr_ptr_reg[3]_1\(3 downto 0),
      \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]\,
      \wr_ptr_timing_reg[0]_0\ => \wr_ptr_timing_reg[0]_0\,
      \wr_ptr_timing_reg[0]_1\ => \wr_ptr_timing_reg[0]_1\
    );
\mcGo_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_w(0),
      Q => p_0_in(1),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(10),
      Q => p_0_in(11),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(11),
      Q => p_0_in(12),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(12),
      Q => p_0_in(13),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(13),
      Q => p_0_in(14),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(14),
      Q => p_0_in(15),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(15),
      Q => \^mcgo_r_reg[15]_0\(0),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(1),
      Q => p_0_in(2),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(2),
      Q => p_0_in(3),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(3),
      Q => p_0_in(4),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(4),
      Q => p_0_in(5),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(5),
      Q => p_0_in(6),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(6),
      Q => p_0_in(7),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(7),
      Q => p_0_in(8),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(8),
      Q => p_0_in(9),
      R => \mcGo_r_reg[0]_0\
    );
\mcGo_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in(9),
      Q => p_0_in(10),
      R => \mcGo_r_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_mc_phy_wrapper is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives : out STD_LOGIC;
    A_rst_primitives_reg : out STD_LOGIC;
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rd_ptr_reg[0]\ : out STD_LOGIC;
    \rd_ptr_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[2]\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC;
    \rd_ptr_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    \rd_ptr_reg[2]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC;
    \rd_ptr_reg[0]_1\ : out STD_LOGIC;
    \rd_ptr_reg[1]_1\ : out STD_LOGIC;
    \rd_ptr_reg[2]_1\ : out STD_LOGIC;
    \rd_ptr_reg[3]_1\ : out STD_LOGIC;
    phy_mc_ctl_full : out STD_LOGIC;
    ref_dll_lock : out STD_LOGIC;
    idelay_ld_rst : out STD_LOGIC;
    ddr2_cas_n : out STD_LOGIC;
    ddr2_ras_n : out STD_LOGIC;
    ddr2_we_n : out STD_LOGIC;
    ddr2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
    ddr2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_empty_reg[1]\ : out STD_LOGIC;
    mem_out : out STD_LOGIC_VECTOR ( 30 downto 0 );
    init_complete_r1_timing_reg : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    \my_empty_reg[1]_2\ : out STD_LOGIC;
    \FSM_onehot_cal1_state_r_reg[13]\ : out STD_LOGIC;
    \pi_counter_read_val_reg[5]\ : out STD_LOGIC;
    \my_empty_reg[5]\ : out STD_LOGIC;
    \my_empty_reg[3]\ : out STD_LOGIC;
    \my_empty_reg[5]_0\ : out STD_LOGIC;
    \my_empty_reg[3]_0\ : out STD_LOGIC;
    \my_empty_reg[5]_1\ : out STD_LOGIC;
    \my_empty_reg[3]_1\ : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    \my_empty_reg[0]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 65 downto 0 );
    app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_rddata_en : out STD_LOGIC;
    p_128_in : out STD_LOGIC;
    \mcGo_r_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    in0 : out STD_LOGIC;
    phy_mc_data_full : out STD_LOGIC;
    wr_en_2 : out STD_LOGIC;
    wr_en_3 : out STD_LOGIC;
    phy_mc_cmd_full : out STD_LOGIC;
    wr_en_4 : out STD_LOGIC;
    \wr_ptr_reg[0]\ : out STD_LOGIC;
    \wr_ptr_reg[1]\ : out STD_LOGIC;
    \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \wr_ptr_reg[0]_0\ : out STD_LOGIC;
    \wr_ptr_reg[1]_0\ : out STD_LOGIC;
    \wr_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    wr_en : out STD_LOGIC;
    p_1_in : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_0\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_1\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_2\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_3\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_4\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_5\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_6\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_7\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_8\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_9\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_10\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_11\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_12\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_13\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_14\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_15\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_16\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_17\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_18\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_19\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_20\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_21\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_22\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_23\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_24\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_25\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_26\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_27\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_28\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_29\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_30\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_31\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_32\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_33\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_34\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_35\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_36\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_37\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_38\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_39\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_40\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_41\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_42\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_43\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_44\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_45\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_46\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_47\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_48\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_49\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_50\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_51\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_52\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_53\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_54\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_55\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_56\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_57\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_58\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_59\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_60\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_61\ : out STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_62\ : out STD_LOGIC;
    ddr2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
    ddr2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    CLK : in STD_LOGIC;
    \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_2\ : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_3\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \slave_ts.oserdes_slave_ts\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_0\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_1\ : in STD_LOGIC;
    D1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D9 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ififo_rst_reg0 : in STD_LOGIC;
    ofifo_rst_reg0 : in STD_LOGIC;
    out_fifo : in STD_LOGIC;
    out_fifo_0 : in STD_LOGIC;
    out_fifo_1 : in STD_LOGIC;
    out_fifo_2 : in STD_LOGIC;
    \my_empty_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \my_empty_reg[6]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[6]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[6]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[6]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \input_[8].iserdes_dq_.iserdesdq\ : in STD_LOGIC;
    LD0_0 : in STD_LOGIC;
    CLKB0_5 : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_1\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_2\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_3\ : in STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_4\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \slave_ts.oserdes_slave_ts_2\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_3\ : in STD_LOGIC;
    \slave_ts.oserdes_slave_ts_4\ : in STD_LOGIC;
    D0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ififo_rst_reg0_1 : in STD_LOGIC;
    ofifo_rst_reg0_2 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST0 : in STD_LOGIC;
    rst_out_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle : in STD_LOGIC;
    UNCONN_IN : in STD_LOGIC;
    UNCONN_IN_0 : in STD_LOGIC;
    UNCONN_IN_1 : in STD_LOGIC;
    phy_ctl_wr_i1_reg_0 : in STD_LOGIC;
    \rd_ptr_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_reg[3]_6\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \rd_ptr_reg[3]_7\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_reg[3]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_reg[3]_9\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_ptr_timing_reg[0]\ : in STD_LOGIC;
    calib_cmd_wren : in STD_LOGIC;
    app_rd_data_valid_0 : in STD_LOGIC;
    mux_wrdata_en : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC;
    calib_wrdata_en : in STD_LOGIC;
    out_fifo_3 : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_1\ : in STD_LOGIC;
    out_fifo_4 : in STD_LOGIC_VECTOR ( 32 downto 0 );
    \cnt_idel_dec_cpt_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    out_fifo_5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_fifo_6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    mux_cmd_wren : in STD_LOGIC;
    \my_full_reg[0]\ : in STD_LOGIC;
    app_rd_data_valid_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.tail_r_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : in STD_LOGIC;
    cnt_pwron_cke_done_r : in STD_LOGIC;
    out_fifo_7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \mcGo_r_reg[0]\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_ptr_timing_reg[0]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_timing_reg[2]\ : in STD_LOGIC;
    \wr_ptr_timing_reg[0]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 10 downto 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \app_rd_data[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    calib_sel : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_mc_phy_wrapper : entity is "mig_7series_v4_2_ddr_mc_phy_wrapper";
end mig_7series_0_mig_7series_v4_2_ddr_mc_phy_wrapper;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_mc_phy_wrapper is
  signal mem_dq_in : STD_LOGIC_VECTOR ( 28 downto 1 );
  signal mem_dq_ts : STD_LOGIC_VECTOR ( 33 downto 1 );
  signal mem_dqs_in : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mem_dqs_out : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mem_dqs_ts : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal out_addr_0 : STD_LOGIC;
  signal out_addr_1 : STD_LOGIC;
  signal out_addr_10 : STD_LOGIC;
  signal out_addr_11 : STD_LOGIC;
  signal out_addr_12 : STD_LOGIC;
  signal out_addr_2 : STD_LOGIC;
  signal out_addr_3 : STD_LOGIC;
  signal out_addr_4 : STD_LOGIC;
  signal out_addr_5 : STD_LOGIC;
  signal out_addr_6 : STD_LOGIC;
  signal out_addr_7 : STD_LOGIC;
  signal out_addr_8 : STD_LOGIC;
  signal out_addr_9 : STD_LOGIC;
  signal out_ba_0 : STD_LOGIC;
  signal out_ba_1 : STD_LOGIC;
  signal out_ba_2 : STD_LOGIC;
  signal out_cas_n : STD_LOGIC;
  signal out_cke : STD_LOGIC;
  signal out_cs_n : STD_LOGIC;
  signal out_dm_0 : STD_LOGIC;
  signal out_dm_1 : STD_LOGIC;
  signal out_dq_0 : STD_LOGIC;
  signal out_dq_1 : STD_LOGIC;
  signal out_dq_10 : STD_LOGIC;
  signal out_dq_11 : STD_LOGIC;
  signal out_dq_12 : STD_LOGIC;
  signal out_dq_13 : STD_LOGIC;
  signal out_dq_14 : STD_LOGIC;
  signal out_dq_15 : STD_LOGIC;
  signal out_dq_2 : STD_LOGIC;
  signal out_dq_3 : STD_LOGIC;
  signal out_dq_4 : STD_LOGIC;
  signal out_dq_5 : STD_LOGIC;
  signal out_dq_6 : STD_LOGIC;
  signal out_dq_7 : STD_LOGIC;
  signal out_dq_8 : STD_LOGIC;
  signal out_dq_9 : STD_LOGIC;
  signal out_odt : STD_LOGIC;
  signal out_ras_n : STD_LOGIC;
  signal out_we_n : STD_LOGIC;
  signal phy_ctl_wd_i1 : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal phy_ctl_wd_i2 : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal phy_ctl_wr_i1 : STD_LOGIC;
  signal phy_ctl_wr_i2 : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE : string;
  attribute CAPACITANCE of \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[0].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[0].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[10].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[10].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[11].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[11].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[12].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[12].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[1].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[1].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[2].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[2].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[3].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[3].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[4].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[4].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[5].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[5].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[6].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[6].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[7].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[7].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[8].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[8].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[9].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[9].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_bank_obuf[0].u_bank_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_bank_obuf[0].u_bank_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_bank_obuf[1].u_bank_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_bank_obuf[1].u_bank_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_bank_obuf[2].u_bank_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_bank_obuf[2].u_bank_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[0].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[0].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[1].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[1].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[11].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[14].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[15].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[1].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[4].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[7].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[8].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of u_cas_n_obuf : label is "PRIMITIVE";
  attribute CAPACITANCE of u_cas_n_obuf : label is "DONT_CARE";
  attribute BOX_TYPE of u_ras_n_obuf : label is "PRIMITIVE";
  attribute CAPACITANCE of u_ras_n_obuf : label is "DONT_CARE";
  attribute BOX_TYPE of u_we_n_obuf : label is "PRIMITIVE";
  attribute CAPACITANCE of u_we_n_obuf : label is "DONT_CARE";
begin
\cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_cke,
      O => ddr2_cke(0)
    );
\cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_odt,
      O => ddr2_odt(0)
    );
\gen_addr_obuf[0].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_0,
      O => ddr2_addr(0)
    );
\gen_addr_obuf[10].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_10,
      O => ddr2_addr(10)
    );
\gen_addr_obuf[11].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_11,
      O => ddr2_addr(11)
    );
\gen_addr_obuf[12].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_12,
      O => ddr2_addr(12)
    );
\gen_addr_obuf[1].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_1,
      O => ddr2_addr(1)
    );
\gen_addr_obuf[2].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_2,
      O => ddr2_addr(2)
    );
\gen_addr_obuf[3].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_3,
      O => ddr2_addr(3)
    );
\gen_addr_obuf[4].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_4,
      O => ddr2_addr(4)
    );
\gen_addr_obuf[5].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_5,
      O => ddr2_addr(5)
    );
\gen_addr_obuf[6].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_6,
      O => ddr2_addr(6)
    );
\gen_addr_obuf[7].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_7,
      O => ddr2_addr(7)
    );
\gen_addr_obuf[8].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_8,
      O => ddr2_addr(8)
    );
\gen_addr_obuf[9].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_addr_9,
      O => ddr2_addr(9)
    );
\gen_bank_obuf[0].u_bank_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_ba_0,
      O => ddr2_ba(0)
    );
\gen_bank_obuf[1].u_bank_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_ba_1,
      O => ddr2_ba(1)
    );
\gen_bank_obuf[2].u_bank_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_ba_2,
      O => ddr2_ba(2)
    );
\gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_cs_n,
      O => ddr2_cs_n(0)
    );
\gen_dm_obuf.loop_dm[0].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_dm_0,
      O => ddr2_dm(0),
      T => mem_dq_ts(2)
    );
\gen_dm_obuf.loop_dm[1].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_dm_1,
      O => ddr2_dm(1),
      T => mem_dq_ts(33)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_0,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(0),
      O => mem_dq_in(3),
      T => mem_dq_ts(3)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_10,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(10),
      O => mem_dq_in(25),
      T => mem_dq_ts(29)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[11].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_11,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(11),
      O => mem_dq_in(27),
      T => mem_dq_ts(31)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_12,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(12),
      O => mem_dq_in(24),
      T => mem_dq_ts(28)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_13,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(13),
      O => mem_dq_in(20),
      T => mem_dq_ts(24)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[14].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_14,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(14),
      O => mem_dq_in(28),
      T => mem_dq_ts(32)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[15].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_15,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(15),
      O => mem_dq_in(22),
      T => mem_dq_ts(26)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[1].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_1,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(1),
      O => mem_dq_in(6),
      T => mem_dq_ts(6)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_2,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(2),
      O => mem_dq_in(1),
      T => mem_dq_ts(1)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_3,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(3),
      O => mem_dq_in(5),
      T => mem_dq_ts(5)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[4].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_4,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(4),
      O => mem_dq_in(7),
      T => mem_dq_ts(7)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_5,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(5),
      O => mem_dq_in(9),
      T => mem_dq_ts(9)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_6,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(6),
      O => mem_dq_in(4),
      T => mem_dq_ts(4)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[7].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_7,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(7),
      O => mem_dq_in(8),
      T => mem_dq_ts(8)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[8].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_8,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(8),
      O => mem_dq_in(21),
      T => mem_dq_ts(25)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dq_9,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dq(9),
      O => mem_dq_in(26),
      T => mem_dq_ts(30)
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dqs_out(0),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dqs_p(0),
      IOB => ddr2_dqs_n(0),
      O => mem_dqs_in(0),
      T => mem_dqs_ts(0)
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dqs_out(2),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr2_dqs_p(1),
      IOB => ddr2_dqs_n(1),
      O => mem_dqs_in(2),
      T => mem_dqs_ts(2)
    );
\genblk24.phy_ctl_pre_fifo_0\: entity work.mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo
     port map (
      CLK => CLK,
      E(0) => E(0),
      UNCONN_IN => UNCONN_IN,
      mux_cmd_wren => mux_cmd_wren,
      \my_empty_reg[3]_0\ => \my_empty_reg[3]\,
      \my_empty_reg[5]_0\ => \my_empty_reg[5]\,
      \my_full_reg[0]_0\ => \my_full_reg[0]\,
      \wr_ptr_timing_reg[0]_0\(0) => rst_out_reg(0)
    );
\genblk24.phy_ctl_pre_fifo_1\: entity work.\mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\
     port map (
      CLK => CLK,
      UNCONN_IN => UNCONN_IN_0,
      mux_cmd_wren => mux_cmd_wren,
      \my_empty_reg[3]_0\ => \my_empty_reg[3]_0\,
      \my_empty_reg[5]_0\ => \my_empty_reg[5]_0\,
      \my_empty_reg[8]_0\ => \rd_ptr_timing_reg[2]\,
      \my_full_reg[0]_0\ => \my_full_reg[0]\,
      \rd_ptr_timing_reg[0]_0\(0) => rst_out_reg(0),
      \wr_ptr_timing_reg[0]_0\(0) => \wr_ptr_timing_reg[0]_2\(0)
    );
\genblk24.phy_ctl_pre_fifo_2\: entity work.\mig_7series_0_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_6\
     port map (
      CLK => CLK,
      UNCONN_IN => UNCONN_IN_1,
      mux_cmd_wren => mux_cmd_wren,
      \my_empty_reg[3]_0\ => \my_empty_reg[3]_1\,
      \my_empty_reg[5]_0\ => \my_empty_reg[5]_1\,
      \my_full_reg[0]_0\ => \my_full_reg[0]\,
      \rd_ptr_timing_reg[2]_0\ => \rd_ptr_timing_reg[2]\,
      \wr_ptr_timing_reg[0]_0\(0) => rst_out_reg(0),
      \wr_ptr_timing_reg[0]_1\(0) => \wr_ptr_timing_reg[0]_3\(0)
    );
\phy_ctl_wd_i1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => phy_ctl_wd_i1(0),
      R => '0'
    );
\phy_ctl_wd_i1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(3),
      Q => phy_ctl_wd_i1(17),
      R => '0'
    );
\phy_ctl_wd_i1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(4),
      Q => phy_ctl_wd_i1(18),
      R => '0'
    );
\phy_ctl_wd_i1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(5),
      Q => phy_ctl_wd_i1(19),
      R => '0'
    );
\phy_ctl_wd_i1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => phy_ctl_wd_i1(1),
      R => '0'
    );
\phy_ctl_wd_i1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(6),
      Q => phy_ctl_wd_i1(20),
      R => '0'
    );
\phy_ctl_wd_i1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(7),
      Q => phy_ctl_wd_i1(21),
      R => '0'
    );
\phy_ctl_wd_i1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(8),
      Q => phy_ctl_wd_i1(22),
      R => '0'
    );
\phy_ctl_wd_i1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(9),
      Q => phy_ctl_wd_i1(23),
      R => '0'
    );
\phy_ctl_wd_i1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(10),
      Q => phy_ctl_wd_i1(24),
      R => '0'
    );
\phy_ctl_wd_i1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(2),
      Q => phy_ctl_wd_i1(2),
      R => '0'
    );
\phy_ctl_wd_i2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(0),
      Q => phy_ctl_wd_i2(0),
      R => '0'
    );
\phy_ctl_wd_i2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(17),
      Q => phy_ctl_wd_i2(17),
      R => '0'
    );
\phy_ctl_wd_i2_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(18),
      Q => phy_ctl_wd_i2(18),
      R => '0'
    );
\phy_ctl_wd_i2_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(19),
      Q => phy_ctl_wd_i2(19),
      R => '0'
    );
\phy_ctl_wd_i2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(1),
      Q => phy_ctl_wd_i2(1),
      R => '0'
    );
\phy_ctl_wd_i2_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(20),
      Q => phy_ctl_wd_i2(20),
      R => '0'
    );
\phy_ctl_wd_i2_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(21),
      Q => phy_ctl_wd_i2(21),
      R => '0'
    );
\phy_ctl_wd_i2_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(22),
      Q => phy_ctl_wd_i2(22),
      R => '0'
    );
\phy_ctl_wd_i2_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(23),
      Q => phy_ctl_wd_i2(23),
      R => '0'
    );
\phy_ctl_wd_i2_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(24),
      Q => phy_ctl_wd_i2(24),
      R => '0'
    );
\phy_ctl_wd_i2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(2),
      Q => phy_ctl_wd_i2(2),
      R => '0'
    );
phy_ctl_wr_i1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wr_i1_reg_0,
      Q => phy_ctl_wr_i1,
      R => '0'
    );
phy_ctl_wr_i2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wr_i1,
      Q => phy_ctl_wr_i2,
      R => '0'
    );
u_cas_n_obuf: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_cas_n,
      O => ddr2_cas_n
    );
u_ddr_mc_phy: entity work.mig_7series_0_mig_7series_v4_2_ddr_mc_phy
     port map (
      A_rst_primitives_reg => A_rst_primitives,
      A_rst_primitives_reg_0 => A_rst_primitives_reg,
      A_rst_primitives_reg_1 => A_rst_primitives_reg_0,
      A_rst_primitives_reg_2(9) => out_we_n,
      A_rst_primitives_reg_2(8) => out_addr_7,
      A_rst_primitives_reg_2(7) => out_cas_n,
      A_rst_primitives_reg_2(6) => out_cke,
      A_rst_primitives_reg_2(5) => out_cs_n,
      A_rst_primitives_reg_2(4) => out_addr_4,
      A_rst_primitives_reg_2(3) => out_odt,
      A_rst_primitives_reg_2(2) => out_addr_6,
      A_rst_primitives_reg_2(1) => out_addr_11,
      A_rst_primitives_reg_2(0) => out_addr_8,
      CLK => CLK,
      CLKB0 => CLKB0,
      CLKB0_5 => CLKB0_5,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      D0(7 downto 0) => D0(7 downto 0),
      D1(7 downto 0) => D1(7 downto 0),
      D2(7 downto 0) => D2(7 downto 0),
      D3(7 downto 0) => D3(7 downto 0),
      D4(7 downto 0) => D4(7 downto 0),
      D5(7 downto 0) => D5(7 downto 0),
      D6(7 downto 0) => D6(7 downto 0),
      D7(7 downto 0) => D7(7 downto 0),
      D8(7 downto 0) => D8(7 downto 0),
      D9(7 downto 0) => D9(7 downto 0),
      \FSM_onehot_cal1_state_r_reg[13]\ => \FSM_onehot_cal1_state_r_reg[13]\,
      LD0 => LD0,
      LD0_0 => LD0_0,
      Q(10 downto 3) => phy_ctl_wd_i2(24 downto 17),
      Q(2 downto 0) => phy_ctl_wd_i2(2 downto 0),
      RST0 => RST0,
      SR(0) => SR(0),
      app_rd_data(127 downto 0) => app_rd_data(127 downto 0),
      \app_rd_data[117]\(63 downto 0) => \app_rd_data[117]\(63 downto 0),
      app_rd_data_valid => app_rd_data_valid,
      app_rd_data_valid_0 => app_rd_data_valid_0,
      app_rd_data_valid_1(0) => app_rd_data_valid_1(0),
      calib_cmd_wren => calib_cmd_wren,
      calib_sel(0) => calib_sel(0),
      calib_wrdata_en => calib_wrdata_en,
      \cnt_idel_dec_cpt_r_reg[0]\(0) => \cnt_idel_dec_cpt_r_reg[0]\(0),
      cnt_pwron_cke_done_r => cnt_pwron_cke_done_r,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0) => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0),
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0),
      idelay_inc => idelay_inc,
      idelay_ld_rst => idelay_ld_rst,
      ififo_rst_reg0 => ififo_rst_reg0,
      ififo_rst_reg0_1 => ififo_rst_reg0_1,
      in0 => in0,
      init_complete_r1_timing_reg => init_complete_r1_timing_reg,
      \input_[8].iserdes_dq_.iserdesdq\ => \input_[8].iserdes_dq_.iserdesdq\,
      \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq\,
      \mcGo_r_reg[0]_0\ => \mcGo_r_reg[0]\,
      \mcGo_r_reg[15]_0\(0) => \mcGo_r_reg[15]\(0),
      mc_cas_n(1 downto 0) => mc_cas_n(1 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(0) => mc_ras_n(0),
      mc_wrdata_en => mc_wrdata_en,
      mem_dq_in(15 downto 11) => mem_dq_in(28 downto 24),
      mem_dq_in(10 downto 8) => mem_dq_in(22 downto 20),
      mem_dq_in(7 downto 1) => mem_dq_in(9 downto 3),
      mem_dq_in(0) => mem_dq_in(1),
      mem_dq_out(11) => out_ba_0,
      mem_dq_out(10) => out_addr_10,
      mem_dq_out(9) => out_addr_9,
      mem_dq_out(8) => out_addr_5,
      mem_dq_out(7) => out_addr_1,
      mem_dq_out(6) => out_ba_1,
      mem_dq_out(5) => out_addr_0,
      mem_dq_out(4) => out_ras_n,
      mem_dq_out(3) => out_ba_2,
      mem_dq_out(2) => out_addr_3,
      mem_dq_out(1) => out_addr_2,
      mem_dq_out(0) => out_addr_12,
      mem_dq_ts(17 downto 12) => mem_dq_ts(33 downto 28),
      mem_dq_ts(11 downto 9) => mem_dq_ts(26 downto 24),
      mem_dq_ts(8 downto 0) => mem_dq_ts(9 downto 1),
      mem_dqs_in(1) => mem_dqs_in(2),
      mem_dqs_in(0) => mem_dqs_in(0),
      mem_dqs_out(1) => mem_dqs_out(2),
      mem_dqs_out(0) => mem_dqs_out(0),
      mem_dqs_ts(1) => mem_dqs_ts(2),
      mem_dqs_ts(0) => mem_dqs_ts(0),
      mem_out(30 downto 0) => mem_out(30 downto 0),
      mem_refclk => mem_refclk,
      mux_cmd_wren => mux_cmd_wren,
      mux_wrdata_en => mux_wrdata_en,
      \my_empty_reg[0]\ => \my_empty_reg[0]\,
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]_1\,
      \my_empty_reg[1]_2\ => \my_empty_reg[1]_2\,
      \my_empty_reg[6]\(3 downto 0) => \my_empty_reg[6]\(3 downto 0),
      \my_empty_reg[6]_0\(3 downto 0) => \my_empty_reg[6]_0\(3 downto 0),
      \my_empty_reg[6]_1\(3 downto 0) => \my_empty_reg[6]_1\(3 downto 0),
      \my_empty_reg[6]_2\(3 downto 0) => \my_empty_reg[6]_2\(3 downto 0),
      \my_empty_reg[6]_3\(2 downto 0) => \my_empty_reg[6]_3\(2 downto 0),
      \my_empty_reg[6]_4\(7 downto 0) => \my_empty_reg[6]_4\(7 downto 0),
      \my_empty_reg[6]_5\(7 downto 0) => \my_empty_reg[6]_5\(7 downto 0),
      \my_empty_reg[6]_6\(3 downto 0) => \my_empty_reg[6]_6\(3 downto 0),
      \my_empty_reg[6]_7\(3 downto 0) => \my_empty_reg[6]_7\(3 downto 0),
      \my_empty_reg[6]_8\(3 downto 0) => \my_empty_reg[6]_8\(3 downto 0),
      \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0),
      ofifo_rst_reg0 => ofifo_rst_reg0,
      ofifo_rst_reg0_2 => ofifo_rst_reg0_2,
      \out\(1 downto 0) => \out\(1 downto 0),
      out_dm_0 => out_dm_0,
      out_dm_1 => out_dm_1,
      out_dq_0 => out_dq_0,
      out_dq_1 => out_dq_1,
      out_dq_10 => out_dq_10,
      out_dq_11 => out_dq_11,
      out_dq_12 => out_dq_12,
      out_dq_13 => out_dq_13,
      out_dq_14 => out_dq_14,
      out_dq_15 => out_dq_15,
      out_dq_2 => out_dq_2,
      out_dq_3 => out_dq_3,
      out_dq_4 => out_dq_4,
      out_dq_5 => out_dq_5,
      out_dq_6 => out_dq_6,
      out_dq_7 => out_dq_7,
      out_dq_8 => out_dq_8,
      out_dq_9 => out_dq_9,
      out_fifo => out_fifo,
      out_fifo_0 => out_fifo_0,
      out_fifo_1 => out_fifo_1,
      out_fifo_2 => out_fifo_2,
      out_fifo_3 => out_fifo_3,
      out_fifo_4(32 downto 0) => out_fifo_4(32 downto 0),
      out_fifo_5(7 downto 0) => out_fifo_5(7 downto 0),
      out_fifo_6(7 downto 0) => out_fifo_6(7 downto 0),
      out_fifo_7(1 downto 0) => out_fifo_7(1 downto 0),
      p_128_in => p_128_in,
      p_1_in => p_1_in,
      phy_ctl_wr_i2 => phy_ctl_wr_i2,
      phy_dout(31 downto 0) => phy_dout(31 downto 0),
      phy_mc_cmd_full => phy_mc_cmd_full,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      phy_rddata_en => phy_rddata_en,
      phy_read_calib => phy_read_calib,
      \pi_counter_read_val_reg[5]\ => \pi_counter_read_val_reg[5]\,
      \pi_counter_read_val_reg[5]_0\(5 downto 0) => Q(5 downto 0),
      pi_dqs_found_lanes(1 downto 0) => pi_dqs_found_lanes(1 downto 0),
      \pi_dqs_found_lanes_r1_reg[0]\ => \pi_dqs_found_lanes_r1_reg[0]\,
      \pi_dqs_found_lanes_r1_reg[0]_0\ => \pi_dqs_found_lanes_r1_reg[0]_0\,
      \pi_dqs_found_lanes_r1_reg[0]_1\ => \pi_dqs_found_lanes_r1_reg[0]_1\,
      \pi_dqs_found_lanes_r1_reg[0]_2\ => \pi_dqs_found_lanes_r1_reg[0]_2\,
      \pi_dqs_found_lanes_r1_reg[0]_3\ => \pi_dqs_found_lanes_r1_reg[0]_3\,
      \pi_dqs_found_lanes_r1_reg[2]\ => \pi_dqs_found_lanes_r1_reg[2]\,
      \pi_dqs_found_lanes_r1_reg[2]_0\ => \pi_dqs_found_lanes_r1_reg[2]_0\,
      \pi_dqs_found_lanes_r1_reg[2]_1\ => \pi_dqs_found_lanes_r1_reg[2]_1\,
      \pi_dqs_found_lanes_r1_reg[2]_2\ => \pi_dqs_found_lanes_r1_reg[2]_2\,
      \pi_dqs_found_lanes_r1_reg[2]_3\ => \pi_dqs_found_lanes_r1_reg[2]_3\,
      \pi_dqs_found_lanes_r1_reg[2]_4\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[2]_4\(5 downto 0),
      pll_locked => pll_locked,
      \po_stg2_wrcal_cnt_reg[0]\ => \po_stg2_wrcal_cnt_reg[0]\,
      \po_stg2_wrcal_cnt_reg[0]_0\ => \po_stg2_wrcal_cnt_reg[0]_0\,
      \po_stg2_wrcal_cnt_reg[0]_1\ => \po_stg2_wrcal_cnt_reg[0]_1\,
      \po_stg2_wrcal_cnt_reg[0]_10\ => \po_stg2_wrcal_cnt_reg[0]_10\,
      \po_stg2_wrcal_cnt_reg[0]_11\ => \po_stg2_wrcal_cnt_reg[0]_11\,
      \po_stg2_wrcal_cnt_reg[0]_12\ => \po_stg2_wrcal_cnt_reg[0]_12\,
      \po_stg2_wrcal_cnt_reg[0]_13\ => \po_stg2_wrcal_cnt_reg[0]_13\,
      \po_stg2_wrcal_cnt_reg[0]_14\ => \po_stg2_wrcal_cnt_reg[0]_14\,
      \po_stg2_wrcal_cnt_reg[0]_15\ => \po_stg2_wrcal_cnt_reg[0]_15\,
      \po_stg2_wrcal_cnt_reg[0]_16\ => \po_stg2_wrcal_cnt_reg[0]_16\,
      \po_stg2_wrcal_cnt_reg[0]_17\ => \po_stg2_wrcal_cnt_reg[0]_17\,
      \po_stg2_wrcal_cnt_reg[0]_18\ => \po_stg2_wrcal_cnt_reg[0]_18\,
      \po_stg2_wrcal_cnt_reg[0]_19\ => \po_stg2_wrcal_cnt_reg[0]_19\,
      \po_stg2_wrcal_cnt_reg[0]_2\ => \po_stg2_wrcal_cnt_reg[0]_2\,
      \po_stg2_wrcal_cnt_reg[0]_20\ => \po_stg2_wrcal_cnt_reg[0]_20\,
      \po_stg2_wrcal_cnt_reg[0]_21\ => \po_stg2_wrcal_cnt_reg[0]_21\,
      \po_stg2_wrcal_cnt_reg[0]_22\ => \po_stg2_wrcal_cnt_reg[0]_22\,
      \po_stg2_wrcal_cnt_reg[0]_23\ => \po_stg2_wrcal_cnt_reg[0]_23\,
      \po_stg2_wrcal_cnt_reg[0]_24\ => \po_stg2_wrcal_cnt_reg[0]_24\,
      \po_stg2_wrcal_cnt_reg[0]_25\ => \po_stg2_wrcal_cnt_reg[0]_25\,
      \po_stg2_wrcal_cnt_reg[0]_26\ => \po_stg2_wrcal_cnt_reg[0]_26\,
      \po_stg2_wrcal_cnt_reg[0]_27\ => \po_stg2_wrcal_cnt_reg[0]_27\,
      \po_stg2_wrcal_cnt_reg[0]_28\ => \po_stg2_wrcal_cnt_reg[0]_28\,
      \po_stg2_wrcal_cnt_reg[0]_29\ => \po_stg2_wrcal_cnt_reg[0]_29\,
      \po_stg2_wrcal_cnt_reg[0]_3\ => \po_stg2_wrcal_cnt_reg[0]_3\,
      \po_stg2_wrcal_cnt_reg[0]_30\ => \po_stg2_wrcal_cnt_reg[0]_30\,
      \po_stg2_wrcal_cnt_reg[0]_31\ => \po_stg2_wrcal_cnt_reg[0]_31\,
      \po_stg2_wrcal_cnt_reg[0]_32\ => \po_stg2_wrcal_cnt_reg[0]_32\,
      \po_stg2_wrcal_cnt_reg[0]_33\ => \po_stg2_wrcal_cnt_reg[0]_33\,
      \po_stg2_wrcal_cnt_reg[0]_34\ => \po_stg2_wrcal_cnt_reg[0]_34\,
      \po_stg2_wrcal_cnt_reg[0]_35\ => \po_stg2_wrcal_cnt_reg[0]_35\,
      \po_stg2_wrcal_cnt_reg[0]_36\ => \po_stg2_wrcal_cnt_reg[0]_36\,
      \po_stg2_wrcal_cnt_reg[0]_37\ => \po_stg2_wrcal_cnt_reg[0]_37\,
      \po_stg2_wrcal_cnt_reg[0]_38\ => \po_stg2_wrcal_cnt_reg[0]_38\,
      \po_stg2_wrcal_cnt_reg[0]_39\ => \po_stg2_wrcal_cnt_reg[0]_39\,
      \po_stg2_wrcal_cnt_reg[0]_4\ => \po_stg2_wrcal_cnt_reg[0]_4\,
      \po_stg2_wrcal_cnt_reg[0]_40\ => \po_stg2_wrcal_cnt_reg[0]_40\,
      \po_stg2_wrcal_cnt_reg[0]_41\ => \po_stg2_wrcal_cnt_reg[0]_41\,
      \po_stg2_wrcal_cnt_reg[0]_42\ => \po_stg2_wrcal_cnt_reg[0]_42\,
      \po_stg2_wrcal_cnt_reg[0]_43\ => \po_stg2_wrcal_cnt_reg[0]_43\,
      \po_stg2_wrcal_cnt_reg[0]_44\ => \po_stg2_wrcal_cnt_reg[0]_44\,
      \po_stg2_wrcal_cnt_reg[0]_45\ => \po_stg2_wrcal_cnt_reg[0]_45\,
      \po_stg2_wrcal_cnt_reg[0]_46\ => \po_stg2_wrcal_cnt_reg[0]_46\,
      \po_stg2_wrcal_cnt_reg[0]_47\ => \po_stg2_wrcal_cnt_reg[0]_47\,
      \po_stg2_wrcal_cnt_reg[0]_48\ => \po_stg2_wrcal_cnt_reg[0]_48\,
      \po_stg2_wrcal_cnt_reg[0]_49\ => \po_stg2_wrcal_cnt_reg[0]_49\,
      \po_stg2_wrcal_cnt_reg[0]_5\ => \po_stg2_wrcal_cnt_reg[0]_5\,
      \po_stg2_wrcal_cnt_reg[0]_50\ => \po_stg2_wrcal_cnt_reg[0]_50\,
      \po_stg2_wrcal_cnt_reg[0]_51\ => \po_stg2_wrcal_cnt_reg[0]_51\,
      \po_stg2_wrcal_cnt_reg[0]_52\ => \po_stg2_wrcal_cnt_reg[0]_52\,
      \po_stg2_wrcal_cnt_reg[0]_53\ => \po_stg2_wrcal_cnt_reg[0]_53\,
      \po_stg2_wrcal_cnt_reg[0]_54\ => \po_stg2_wrcal_cnt_reg[0]_54\,
      \po_stg2_wrcal_cnt_reg[0]_55\ => \po_stg2_wrcal_cnt_reg[0]_55\,
      \po_stg2_wrcal_cnt_reg[0]_56\ => \po_stg2_wrcal_cnt_reg[0]_56\,
      \po_stg2_wrcal_cnt_reg[0]_57\ => \po_stg2_wrcal_cnt_reg[0]_57\,
      \po_stg2_wrcal_cnt_reg[0]_58\ => \po_stg2_wrcal_cnt_reg[0]_58\,
      \po_stg2_wrcal_cnt_reg[0]_59\ => \po_stg2_wrcal_cnt_reg[0]_59\,
      \po_stg2_wrcal_cnt_reg[0]_6\ => \po_stg2_wrcal_cnt_reg[0]_6\,
      \po_stg2_wrcal_cnt_reg[0]_60\ => \po_stg2_wrcal_cnt_reg[0]_60\,
      \po_stg2_wrcal_cnt_reg[0]_61\ => \po_stg2_wrcal_cnt_reg[0]_61\,
      \po_stg2_wrcal_cnt_reg[0]_62\ => \po_stg2_wrcal_cnt_reg[0]_62\,
      \po_stg2_wrcal_cnt_reg[0]_7\ => \po_stg2_wrcal_cnt_reg[0]_7\,
      \po_stg2_wrcal_cnt_reg[0]_8\ => \po_stg2_wrcal_cnt_reg[0]_8\,
      \po_stg2_wrcal_cnt_reg[0]_9\ => \po_stg2_wrcal_cnt_reg[0]_9\,
      \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\,
      \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]_0\,
      \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_1\,
      \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\,
      \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]_0\,
      \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_1\,
      \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\,
      \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]_0\,
      \rd_ptr_reg[2]_1\ => \rd_ptr_reg[2]_1\,
      \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\,
      \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]_0\,
      \rd_ptr_reg[3]_1\ => \rd_ptr_reg[3]_1\,
      \rd_ptr_reg[3]_2\(3 downto 0) => \rd_ptr_reg[3]_2\(3 downto 0),
      \rd_ptr_reg[3]_3\(3 downto 0) => \rd_ptr_reg[3]_3\(3 downto 0),
      \rd_ptr_reg[3]_4\(3 downto 0) => \rd_ptr_reg[3]_4\(3 downto 0),
      \rd_ptr_reg[3]_5\(7 downto 0) => \rd_ptr_reg[3]_5\(7 downto 0),
      \rd_ptr_reg[3]_6\(4 downto 0) => \rd_ptr_reg[3]_6\(4 downto 0),
      \rd_ptr_reg[3]_7\(0) => \rd_ptr_reg[3]_7\(0),
      \rd_ptr_reg[3]_8\(3 downto 0) => \rd_ptr_reg[3]_8\(3 downto 0),
      \rd_ptr_reg[3]_9\(0) => \rd_ptr_reg[3]_9\(0),
      \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0),
      \read_fifo.tail_r_reg[4]\(0) => \read_fifo.tail_r_reg[4]\(0),
      ref_dll_lock => ref_dll_lock,
      rst_out_reg(0) => rst_out_reg(0),
      \slave_ts.oserdes_slave_ts\ => \slave_ts.oserdes_slave_ts\,
      \slave_ts.oserdes_slave_ts_0\ => \slave_ts.oserdes_slave_ts_0\,
      \slave_ts.oserdes_slave_ts_1\ => \slave_ts.oserdes_slave_ts_1\,
      \slave_ts.oserdes_slave_ts_2\ => \slave_ts.oserdes_slave_ts_2\,
      \slave_ts.oserdes_slave_ts_3\ => \slave_ts.oserdes_slave_ts_3\,
      \slave_ts.oserdes_slave_ts_4\ => \slave_ts.oserdes_slave_ts_4\,
      sync_pulse => sync_pulse,
      wr_en => wr_en,
      wr_en_2 => wr_en_2,
      wr_en_3 => wr_en_3,
      wr_en_4 => wr_en_4,
      \wr_ptr_reg[0]\ => \wr_ptr_reg[0]\,
      \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]_0\,
      \wr_ptr_reg[1]\ => \wr_ptr_reg[1]\,
      \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]_0\,
      \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0),
      \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0),
      \wr_ptr_reg[3]_1\(3 downto 0) => \wr_ptr_reg[3]_1\(3 downto 0),
      \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]\,
      \wr_ptr_timing_reg[0]_0\ => \wr_ptr_timing_reg[0]_0\,
      \wr_ptr_timing_reg[0]_1\ => \wr_ptr_timing_reg[0]_1\
    );
u_ras_n_obuf: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_ras_n,
      O => ddr2_ras_n
    );
u_we_n_obuf: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => out_we_n,
      O => ddr2_we_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_mc is
  port (
    periodic_rd_ack_r_lcl_reg : out STD_LOGIC;
    accept_ns : out STD_LOGIC;
    bm_end_r1 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    bm_end_r1_2 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : out STD_LOGIC;
    bm_end_r1_4 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : out STD_LOGIC;
    \periodic_read_request.periodic_rd_r_lcl_reg\ : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    mc_cmd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    idle : out STD_LOGIC;
    tempmon_sample_en : out STD_LOGIC;
    mc_ras_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_wrdata_en : out STD_LOGIC;
    mc_cas_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    periodic_rd_cntr_r_reg : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    \cmd_pipe_plus.mc_cas_n_reg[2]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_dout : out STD_LOGIC_VECTOR ( 0 to 0 );
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    idle_r_lcl_reg : out STD_LOGIC;
    idle_r_lcl_reg_0 : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    idle_r_lcl_reg_2 : out STD_LOGIC;
    \req_row_r_lcl_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \read_fifo.tail_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \pointer_ram.pointer_we\ : out STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[7]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.wr_data_addr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_address_reg[38]_0\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \cmd_pipe_plus.mc_cke_reg[3]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_data_offset_reg[2]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_data_offset_reg[5]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[4]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[3]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[0]_0\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    was_wr0 : in STD_LOGIC;
    maint_ref_zq_wip_r_reg : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    p_145_out : in STD_LOGIC;
    p_106_out : in STD_LOGIC;
    p_67_out : in STD_LOGIC;
    p_28_out : in STD_LOGIC;
    phy_mc_cmd_full : in STD_LOGIC;
    phy_mc_ctl_full : in STD_LOGIC;
    app_zq_ns : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 2 downto 0 );
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[0]\ : in STD_LOGIC;
    \last_master_r_reg[2]\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]\ : in STD_LOGIC;
    mem_reg_0_15_54_59 : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[5]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \inhbt_act_faw.faw_cnt_r_reg[0]\ : in STD_LOGIC;
    phy_mc_data_full : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    ras_timer_zero_r_reg : in STD_LOGIC;
    act_wait_r_lcl_reg : in STD_LOGIC;
    act_wait_r_lcl_reg_0 : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    was_priority_reg : in STD_LOGIC;
    app_en_r2 : in STD_LOGIC;
    row : in STD_LOGIC_VECTOR ( 12 downto 0 );
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    ras_timer_zero_r_reg_2 : in STD_LOGIC;
    \read_fifo.tail_r_reg[0]_0\ : in STD_LOGIC;
    \read_fifo.tail_r_reg[4]\ : in STD_LOGIC;
    ram_init_done_r : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_mc : entity is "mig_7series_v4_2_mc";
end mig_7series_0_mig_7series_v4_2_mc;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_mc is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \arb_mux0/arb_select0/cke_r\ : STD_LOGIC;
  signal \arb_mux0/arb_select0/mc_aux_out0_1\ : STD_LOGIC;
  signal \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal bank_mach0_n_116 : STD_LOGIC;
  signal bank_mach0_n_117 : STD_LOGIC;
  signal bank_mach0_n_118 : STD_LOGIC;
  signal bank_mach0_n_120 : STD_LOGIC;
  signal bank_mach0_n_121 : STD_LOGIC;
  signal bank_mach0_n_18 : STD_LOGIC;
  signal bank_mach0_n_23 : STD_LOGIC;
  signal bank_mach0_n_27 : STD_LOGIC;
  signal \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1]\ : STD_LOGIC;
  signal col_periodic_rd : STD_LOGIC;
  signal col_rd_wr : STD_LOGIC;
  signal col_wr_data_buf_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal inhbt_act_faw_r : STD_LOGIC;
  signal insert_maint_r : STD_LOGIC;
  signal insert_maint_r1 : STD_LOGIC;
  signal maint_rank_r : STD_LOGIC;
  signal maint_ref_zq_wip : STD_LOGIC;
  signal maint_req_r : STD_LOGIC;
  signal maint_sre_r : STD_LOGIC;
  signal maint_srx_r : STD_LOGIC;
  signal maint_wip_r : STD_LOGIC;
  signal maint_zq_r : STD_LOGIC;
  signal mc_address_ns : STD_LOGIC_VECTOR ( 38 downto 0 );
  signal mc_bank_ns : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \^mc_cas_n\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_cas_n_ns : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_cke_ns : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^mc_cmd\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal mc_cmd_ns : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^mc_cs_n\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mc_cs_n_ns : STD_LOGIC_VECTOR ( 1 to 1 );
  signal mc_data_offset_ns : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal mc_odt_ns : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^mc_ras_n\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_ras_n_ns : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_read_idle_ns : STD_LOGIC;
  signal mc_ref_zq_wip_ns : STD_LOGIC;
  signal mc_we_n_ns : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_wrdata_en_ns : STD_LOGIC;
  signal \^periodic_rd_ack_r_lcl_reg\ : STD_LOGIC;
  signal \^periodic_rd_cntr_r_reg\ : STD_LOGIC;
  signal \^periodic_read_request.periodic_rd_r_lcl_reg\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/act_this_rank\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank\ : STD_LOGIC;
  signal rank_mach0_n_14 : STD_LOGIC;
  signal rank_mach0_n_15 : STD_LOGIC;
  signal rank_mach0_n_16 : STD_LOGIC;
  signal rank_mach0_n_17 : STD_LOGIC;
  signal \rtw_timer.rtw_cnt_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal sent_col : STD_LOGIC;
  signal wr_data_en_ns : STD_LOGIC;
  signal \wtr_timer.wtr_cnt_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
  attribute syn_maxfan : string;
  attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[0]\ : label is "30";
  attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[1]\ : label is "30";
  attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[2]\ : label is "30";
  attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[3]\ : label is "30";
begin
  E(0) <= \^e\(0);
  Q(2 downto 0) <= \^q\(2 downto 0);
  mc_cas_n(2 downto 0) <= \^mc_cas_n\(2 downto 0);
  mc_cmd(1 downto 0) <= \^mc_cmd\(1 downto 0);
  mc_cs_n(0) <= \^mc_cs_n\(0);
  mc_ras_n(2 downto 0) <= \^mc_ras_n\(2 downto 0);
  periodic_rd_ack_r_lcl_reg <= \^periodic_rd_ack_r_lcl_reg\;
  periodic_rd_cntr_r_reg <= \^periodic_rd_cntr_r_reg\;
  \periodic_read_request.periodic_rd_r_lcl_reg\ <= \^periodic_read_request.periodic_rd_r_lcl_reg\;
bank_mach0: entity work.mig_7series_0_mig_7series_v4_2_bank_mach
     port map (
      CLK => CLK,
      D(0) => \arb_mux0/arb_select0/cke_r\,
      DIC(0) => col_periodic_rd,
      E(0) => mc_cmd_ns(1),
      Q(0) => \rtw_timer.rtw_cnt_r\(1),
      S(2 downto 0) => S(2 downto 0),
      accept_ns => accept_ns,
      act_this_rank => \rank_cntrl[0].rank_cntrl0/act_this_rank\,
      act_wait_r_lcl_reg(2 downto 0) => mc_we_n_ns(2 downto 0),
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_0,
      act_wait_r_lcl_reg_2 => act_wait_r_lcl_reg_1,
      act_wait_r_lcl_reg_3 => act_wait_r_lcl_reg_2,
      app_en_r2 => app_en_r2,
      auto_pre_r_lcl_reg => rank_mach0_n_16,
      bm_end_r1 => bm_end_r1,
      bm_end_r1_0 => bm_end_r1_0,
      bm_end_r1_2 => bm_end_r1_2,
      bm_end_r1_4 => bm_end_r1_4,
      cke_r_reg(0) => mc_cke_ns(1),
      \cmd_pipe_plus.mc_data_offset_reg[2]\(1 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]_1\(2 downto 1),
      \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1]\,
      col_rd_wr => col_rd_wr,
      col_wait_r_reg => col_wait_r_reg,
      col_wr_data_buf_addr(3 downto 0) => col_wr_data_buf_addr(3 downto 0),
      \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\(3 downto 0),
      \grant_r[3]_i_5\(0) => \wtr_timer.wtr_cnt_r\(1),
      \grant_r_reg[0]\ => bank_mach0_n_118,
      \grant_r_reg[3]\ => bank_mach0_n_23,
      \grant_r_reg[3]_0\(36 downto 11) => mc_address_ns(38 downto 13),
      \grant_r_reg[3]_0\(10 downto 0) => mc_address_ns(10 downto 0),
      \grant_r_reg[3]_1\(8 downto 0) => mc_bank_ns(8 downto 0),
      \grant_r_reg[3]_2\ => bank_mach0_n_116,
      \grant_r_reg[3]_3\ => bank_mach0_n_120,
      granted_col_r_reg => bank_mach0_n_18,
      granted_col_r_reg_0(1 downto 0) => mc_data_offset_ns(2 downto 1),
      idle_r_lcl_reg => idle_r_lcl_reg,
      idle_r_lcl_reg_0 => idle_r_lcl_reg_0,
      idle_r_lcl_reg_1 => idle_r_lcl_reg_1,
      idle_r_lcl_reg_2 => idle_r_lcl_reg_2,
      inhbt_act_faw_r => inhbt_act_faw_r,
      insert_maint_r => insert_maint_r,
      insert_maint_r1 => insert_maint_r1,
      \maint_controller.maint_hit_busies_r_reg[3]\ => rank_mach0_n_17,
      maint_rank_r => maint_rank_r,
      maint_req_r => maint_req_r,
      maint_sre_r => maint_sre_r,
      maint_srx_r => maint_srx_r,
      maint_wip_r => maint_wip_r,
      maint_zq_r => maint_zq_r,
      mc_aux_out0_1 => \arb_mux0/arb_select0/mc_aux_out0_1\,
      mc_cas_n_ns(2 downto 0) => mc_cas_n_ns(2 downto 0),
      mc_cs_n_ns(0) => mc_cs_n_ns(1),
      mc_odt_ns(0) => mc_odt_ns(0),
      mc_ras_n_ns(2 downto 0) => mc_ras_n_ns(2 downto 0),
      p_106_out => p_106_out,
      p_145_out => p_145_out,
      p_28_out => p_28_out,
      p_67_out => p_67_out,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_lcl_reg,
      pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_lcl_reg_0,
      pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg_1,
      pass_open_bank_r_lcl_reg_2 => pass_open_bank_r_lcl_reg_2,
      periodic_rd_ack_r_lcl_reg => \^periodic_rd_ack_r_lcl_reg\,
      periodic_rd_ack_r_lcl_reg_0 => \grant_r_reg[0]\,
      periodic_rd_cntr_r_reg => \^periodic_rd_cntr_r_reg\,
      periodic_rd_cntr_r_reg_0 => maint_ref_zq_wip_r_reg,
      \periodic_rd_generation.read_this_rank\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank\,
      phy_mc_cmd_full => phy_mc_cmd_full,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      q_has_rd_r_reg => rank_mach0_n_15,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_0,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_1,
      ras_timer_zero_r_reg_2 => ras_timer_zero_r_reg_2,
      rd_wr_r_lcl_reg => bank_mach0_n_27,
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_1\(2 downto 0),
      \req_bank_r_lcl_reg[2]_2\(2 downto 0) => \req_bank_r_lcl_reg[2]_2\(2 downto 0),
      \req_bank_r_lcl_reg[2]_3\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0),
      \req_col_r_reg[9]\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_data_buf_addr_r_reg[3]\(3 downto 0) => D(3 downto 0),
      req_periodic_rd_r_lcl_reg => \^periodic_read_request.periodic_rd_r_lcl_reg\,
      \req_row_r_lcl_reg[12]\(12 downto 0) => \req_row_r_lcl_reg[12]\(12 downto 0),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ => \wtr_timer.wtr_cnt_r_reg[0]\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\ => \last_master_r_reg[2]\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\ => rank_mach0_n_14,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\(0) => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(7),
      rnk_config_valid_r_lcl_reg => \inhbt_act_faw.faw_cnt_r_reg[0]\,
      row(12 downto 0) => row(12 downto 0),
      row_hit_r_reg(0) => row_hit_r_reg(0),
      row_hit_r_reg_0(0) => row_hit_r_reg_0(0),
      row_hit_r_reg_1(0) => row_hit_r_reg_1(0),
      row_hit_r_reg_2(0) => row_hit_r_reg_2(0),
      \rstdiv0_sync_r1_reg_rep__12\ => bank_mach0_n_121,
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      sent_col => sent_col,
      was_priority_reg => was_priority_reg,
      was_wr0 => was_wr0,
      \wr_this_rank_r_reg[0]\ => bank_mach0_n_117
    );
\cmd_pipe_plus.mc_address_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(0),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(10),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(10),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(13),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(11),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(14),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(12),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(15),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(13),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(16),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(14),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(17),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(15),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(18),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(16),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(19),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(17),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(1),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(20),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(18),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(21),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(19),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(22),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(20),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(23),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(21),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(24),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(22),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(25),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(23),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(26),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(24),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(27),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(25),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(28),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(26),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(29),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(27),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(2),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(30),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(28),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(31),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(29),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(32),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(30),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(33),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(31),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(34),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(32),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(35),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(33),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(36),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(34),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(37),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(35),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(38),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(36),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(3),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(3),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(4),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(4),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(5),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(5),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(6),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(6),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(7),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(7),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(8),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(8),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(9),
      Q => \cmd_pipe_plus.mc_address_reg[38]_0\(9),
      R => '0'
    );
\cmd_pipe_plus.mc_aux_out0_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \arb_mux0/arb_select0/mc_aux_out0_1\,
      Q => \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1]\,
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(0),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(1),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(2),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(3),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(3),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(4),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(4),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(5),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(5),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(6),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(6),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(7),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(7),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(8),
      Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(8),
      R => '0'
    );
\cmd_pipe_plus.mc_cas_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cas_n_ns(0),
      Q => \^mc_cas_n\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_cas_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cas_n_ns(1),
      Q => \^mc_cas_n\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_cas_n_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cas_n_ns(2),
      Q => \^mc_cas_n\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_cke_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \arb_mux0/arb_select0/cke_r\,
      Q => \cmd_pipe_plus.mc_cke_reg[3]_0\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_cke_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cke_ns(1),
      Q => \cmd_pipe_plus.mc_cke_reg[3]_0\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_cmd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sent_col,
      Q => \^mc_cmd\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_cmd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cmd_ns(1),
      Q => \^mc_cmd\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_cs_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cs_n_ns(1),
      Q => \^mc_cs_n\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_data_offset_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_reg[5]_1\(0),
      Q => \cmd_pipe_plus.mc_data_offset_reg[0]_0\,
      R => bank_mach0_n_18
    );
\cmd_pipe_plus.mc_data_offset_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_data_offset_ns(1),
      Q => \cmd_pipe_plus.mc_data_offset_reg[2]_0\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_data_offset_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_data_offset_ns(2),
      Q => \cmd_pipe_plus.mc_data_offset_reg[2]_0\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_data_offset_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_reg[5]_1\(3),
      Q => \cmd_pipe_plus.mc_data_offset_reg[3]_0\,
      R => bank_mach0_n_18
    );
\cmd_pipe_plus.mc_data_offset_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_reg[5]_1\(4),
      Q => \cmd_pipe_plus.mc_data_offset_reg[4]_0\,
      R => bank_mach0_n_18
    );
\cmd_pipe_plus.mc_data_offset_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_reg[5]_1\(5),
      Q => \cmd_pipe_plus.mc_data_offset_reg[5]_0\,
      R => bank_mach0_n_18
    );
\cmd_pipe_plus.mc_odt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_odt_ns(0),
      Q => mc_odt(0),
      R => '0'
    );
\cmd_pipe_plus.mc_ras_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_ras_n_ns(0),
      Q => \^mc_ras_n\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_ras_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_ras_n_ns(1),
      Q => \^mc_ras_n\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_ras_n_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_ras_n_ns(2),
      Q => \^mc_ras_n\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_we_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_we_n_ns(0),
      Q => \^q\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_we_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_we_n_ns(1),
      Q => \^q\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_we_n_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_we_n_ns(2),
      Q => \^q\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_wrdata_en_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_wrdata_en_ns,
      Q => mc_wrdata_en,
      R => '0'
    );
\cmd_pipe_plus.wr_data_addr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\(0),
      Q => \cmd_pipe_plus.wr_data_addr_reg[3]_0\(0),
      R => '0'
    );
\cmd_pipe_plus.wr_data_addr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\(1),
      Q => \cmd_pipe_plus.wr_data_addr_reg[3]_0\(1),
      R => '0'
    );
\cmd_pipe_plus.wr_data_addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\(2),
      Q => \cmd_pipe_plus.wr_data_addr_reg[3]_0\(2),
      R => '0'
    );
\cmd_pipe_plus.wr_data_addr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\(3),
      Q => \cmd_pipe_plus.wr_data_addr_reg[3]_0\(3),
      R => '0'
    );
\cmd_pipe_plus.wr_data_en_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_data_en_ns,
      Q => \^e\(0),
      R => '0'
    );
col_mach0: entity work.mig_7series_0_mig_7series_v4_2_col_mach
     port map (
      CLK => CLK,
      D(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\(3 downto 0),
      DIC(0) => col_periodic_rd,
      E(0) => mc_cmd_ns(1),
      Q(0) => \read_fifo.tail_r_reg[0]\(0),
      col_rd_wr => col_rd_wr,
      col_wr_data_buf_addr(3 downto 0) => col_wr_data_buf_addr(3 downto 0),
      maint_ref_zq_wip => maint_ref_zq_wip,
      mc_cmd(0) => \^mc_cmd\(0),
      mc_read_idle_ns => mc_read_idle_ns,
      mc_read_idle_r_reg => \grant_r_reg[0]\,
      mc_ref_zq_wip_ns => mc_ref_zq_wip_ns,
      mc_wrdata_en_ns => mc_wrdata_en_ns,
      \read_fifo.fifo_out_data_r_reg[7]_0\(1 downto 0) => \read_fifo.fifo_out_data_r_reg[7]\(1 downto 0),
      \read_fifo.head_r_reg[0]_0\ => maint_ref_zq_wip_r_reg,
      \read_fifo.tail_r_reg[0]_0\ => \read_fifo.tail_r_reg[0]_0\,
      \read_fifo.tail_r_reg[0]_1\ => \wtr_timer.wtr_cnt_r_reg[0]\,
      \read_fifo.tail_r_reg[4]_0\ => \read_fifo.tail_r_reg[4]\,
      wr_data_en_ns => wr_data_en_ns
    );
mc_read_idle_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_read_idle_ns,
      Q => idle,
      R => '0'
    );
mc_ref_zq_wip_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_ref_zq_wip_ns,
      Q => tempmon_sample_en,
      R => '0'
    );
\mem_reg_0_15_30_35_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_ras_n\(1),
      I1 => mem_reg_0_15_54_59,
      O => phy_dout(0)
    );
\mem_reg_0_15_48_53_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(1),
      I1 => mem_reg_0_15_54_59,
      O => \cmd_pipe_plus.mc_cas_n_reg[2]_0\(0)
    );
\mem_reg_0_15_54_59_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(2),
      I1 => mem_reg_0_15_54_59,
      O => \cmd_pipe_plus.mc_cas_n_reg[2]_0\(1)
    );
\mem_reg_0_15_54_59_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_cs_n\(0),
      I1 => mem_reg_0_15_54_59,
      O => \cmd_pipe_plus.mc_cas_n_reg[2]_0\(2)
    );
\mem_reg_0_15_54_59_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_ras_n\(2),
      I1 => mem_reg_0_15_54_59,
      O => \cmd_pipe_plus.mc_cas_n_reg[2]_0\(3)
    );
\mem_reg_0_15_72_77_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_cas_n\(1),
      I1 => mem_reg_0_15_54_59,
      O => \cmd_pipe_plus.mc_cas_n_reg[2]_0\(4)
    );
\mem_reg_0_15_72_77_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_cas_n\(2),
      I1 => mem_reg_0_15_54_59,
      O => \cmd_pipe_plus.mc_cas_n_reg[2]_0\(5)
    );
\pointer_ram.rams[0].RAM32M0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^e\(0),
      I1 => ram_init_done_r,
      O => \pointer_ram.pointer_we\
    );
rank_mach0: entity work.mig_7series_0_mig_7series_v4_2_rank_mach
     port map (
      CLK => CLK,
      D(0) => mc_cke_ns(1),
      Q(0) => \rtw_timer.rtw_cnt_r\(1),
      act_this_rank => \rank_cntrl[0].rank_cntrl0/act_this_rank\,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_zq_ack => app_zq_ack,
      app_zq_ns => app_zq_ns,
      cke_r_reg(0) => \arb_mux0/arb_select0/cke_r\,
      \grant_r_reg[0]\ => \grant_r_reg[0]\,
      \inhbt_act_faw.faw_cnt_r_reg[0]\ => bank_mach0_n_120,
      \inhbt_act_faw.faw_cnt_r_reg[0]_0\ => \inhbt_act_faw.faw_cnt_r_reg[0]\,
      inhbt_act_faw_r => inhbt_act_faw_r,
      insert_maint_r => insert_maint_r,
      insert_maint_r1 => insert_maint_r1,
      \last_master_r_reg[2]\ => \last_master_r_reg[2]\,
      \maint_controller.maint_hit_busies_r_reg[3]\ => \^periodic_rd_cntr_r_reg\,
      \maint_controller.maint_wip_r_lcl_reg\ => rank_mach0_n_17,
      maint_rank_r => maint_rank_r,
      maint_ref_zq_wip => maint_ref_zq_wip,
      maint_ref_zq_wip_r_reg => maint_ref_zq_wip_r_reg,
      maint_req_r => maint_req_r,
      maint_sre_r => maint_sre_r,
      maint_srx_r => maint_srx_r,
      maint_wip_r => maint_wip_r,
      maint_zq_r => maint_zq_r,
      \maintenance_request.maint_sre_r_lcl_reg\(0) => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(7),
      \maintenance_request.maint_sre_r_lcl_reg_0\ => rank_mach0_n_15,
      \maintenance_request.maint_sre_r_lcl_reg_1\ => rank_mach0_n_16,
      \maintenance_request.maint_srx_r_lcl_reg\ => rank_mach0_n_14,
      \periodic_rd_generation.periodic_rd_cntr1_r_reg\ => \^periodic_rd_ack_r_lcl_reg\,
      \periodic_rd_generation.periodic_rd_request_r_reg\ => bank_mach0_n_23,
      \periodic_rd_generation.read_this_rank\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank\,
      \periodic_read_request.periodic_rd_r_lcl_reg\ => \^periodic_read_request.periodic_rd_r_lcl_reg\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ => bank_mach0_n_121,
      \rtw_timer.rtw_cnt_r_reg[1]\ => bank_mach0_n_27,
      \wtr_timer.wtr_cnt_r_reg[0]\ => \wtr_timer.wtr_cnt_r_reg[0]\,
      \wtr_timer.wtr_cnt_r_reg[0]_0\ => bank_mach0_n_117,
      \wtr_timer.wtr_cnt_r_reg[0]_1\ => bank_mach0_n_118,
      \wtr_timer.wtr_cnt_r_reg[1]\(0) => \wtr_timer.wtr_cnt_r\(1),
      \wtr_timer.wtr_cnt_r_reg[1]_0\ => bank_mach0_n_116
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_ddr_phy_top is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg : out STD_LOGIC;
    \rd_ptr_reg[0]\ : out STD_LOGIC;
    \rd_ptr_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[2]\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC;
    \rd_ptr_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    \rd_ptr_reg[2]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC;
    \rd_ptr_reg[0]_1\ : out STD_LOGIC;
    \rd_ptr_reg[1]_1\ : out STD_LOGIC;
    \rd_ptr_reg[2]_1\ : out STD_LOGIC;
    \rd_ptr_reg[3]_1\ : out STD_LOGIC;
    phy_mc_ctl_full : out STD_LOGIC;
    ref_dll_lock : out STD_LOGIC;
    ddr2_cas_n : out STD_LOGIC;
    ddr2_ras_n : out STD_LOGIC;
    ddr2_we_n : out STD_LOGIC;
    ddr2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
    ddr2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
    new_cnt_cpt_r_reg : out STD_LOGIC;
    rdlvl_stg1_start_reg : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    pi_cnt_dec_reg : out STD_LOGIC;
    prbs_rdlvl_done_pulse_reg : out STD_LOGIC;
    phy_dout : out STD_LOGIC_VECTOR ( 44 downto 0 );
    init_calib_complete_reg_rep : out STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__9\ : out STD_LOGIC;
    init_complete_r1_timing_reg : out STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[117]\ : out STD_LOGIC_VECTOR ( 59 downto 0 );
    init_calib_complete_reg_rep_0 : out STD_LOGIC_VECTOR ( 59 downto 0 );
    app_zq_ns : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    \my_empty_reg[0]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 65 downto 0 );
    app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 );
    \wr_ptr_reg[0]\ : out STD_LOGIC;
    \wr_ptr_reg[1]\ : out STD_LOGIC;
    \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \wr_ptr_reg[0]_0\ : out STD_LOGIC;
    \wr_ptr_reg[1]_0\ : out STD_LOGIC;
    \wr_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    wr_en : out STD_LOGIC;
    p_1_in : out STD_LOGIC;
    phy_mc_data_full : out STD_LOGIC;
    wr_en_2 : out STD_LOGIC;
    wr_en_3 : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    wr_en_4 : out STD_LOGIC;
    phy_mc_cmd_full : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
    ddr2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    CLK : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    CLKB0_5 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST0 : in STD_LOGIC;
    rst_out_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle : in STD_LOGIC;
    \complex_address_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \lane_cnt_po_r_reg[0]\ : in STD_LOGIC;
    \samp_edge_cnt1_r_reg[0]\ : in STD_LOGIC;
    \rd_ptr_timing_reg[2]\ : in STD_LOGIC;
    rdlvl_stg1_start_reg_0 : in STD_LOGIC;
    init_complete_r_timing_reg : in STD_LOGIC;
    \one_inc_min_limit_reg[2]\ : in STD_LOGIC;
    tempmon_sample_en : in STD_LOGIC;
    \init_state_r1_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    wrcal_done_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \mcGo_r_reg[0]\ : in STD_LOGIC;
    \my_full_reg[0]\ : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    mem_out : in STD_LOGIC_VECTOR ( 79 downto 0 );
    delay_done_reg : in STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][1][4]\ : in STD_LOGIC;
    out_fifo : in STD_LOGIC_VECTOR ( 79 downto 0 );
    out_fifo_0 : in STD_LOGIC_VECTOR ( 79 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 143 downto 0 );
    app_zq_req : in STD_LOGIC;
    app_rd_data_valid_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.tail_r_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \complex_num_writes_reg[4]\ : in STD_LOGIC;
    mc_cas_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_ras_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_odt : in STD_LOGIC_VECTOR ( 0 to 0 );
    out_fifo_1 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_shift_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \device_temp_101_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
    \app_rd_data[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    mem_reg_0_15_60_65 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \phy_ctl_wd_i1_reg[17]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \phy_ctl_wd_i1_reg[20]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[21]\ : in STD_LOGIC;
    \phy_ctl_wd_i1_reg[22]\ : in STD_LOGIC;
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : in STD_LOGIC_VECTOR ( 36 downto 0 );
    out_fifo_2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \out_fifo_i_69__1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_ddr_phy_top : entity is "mig_7series_v4_2_ddr_phy_top";
end mig_7series_0_mig_7series_v4_2_ddr_phy_top;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_ddr_phy_top is
  signal calib_cmd_wren : STD_LOGIC;
  signal calib_complete : STD_LOGIC;
  signal calib_in_common : STD_LOGIC;
  signal calib_sel : STD_LOGIC_VECTOR ( 1 to 1 );
  signal calib_sel0 : STD_LOGIC;
  signal \calib_sel[1]_i_1_n_0\ : STD_LOGIC;
  signal calib_wrdata_en : STD_LOGIC;
  signal \calib_zero_ctrl[0]_i_1_n_0\ : STD_LOGIC;
  signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/p_27_in\ : STD_LOGIC;
  signal dqs_po_dec_done : STD_LOGIC;
  signal \gen_byte_sel_div2.calib_in_common_i_1_n_0\ : STD_LOGIC;
  signal \genblk24.phy_ctl_pre_fifo_0/wr_en\ : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of \genblk24.phy_ctl_pre_fifo_0/wr_en\ : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of \genblk24.phy_ctl_pre_fifo_0/wr_en\ : signal is "found";
  signal \genblk24.phy_ctl_pre_fifo_1/wr_en\ : STD_LOGIC;
  attribute MAX_FANOUT of \genblk24.phy_ctl_pre_fifo_1/wr_en\ : signal is "50";
  attribute RTL_MAX_FANOUT of \genblk24.phy_ctl_pre_fifo_1/wr_en\ : signal is "found";
  signal \genblk24.phy_ctl_pre_fifo_2/wr_en\ : STD_LOGIC;
  attribute MAX_FANOUT of \genblk24.phy_ctl_pre_fifo_2/wr_en\ : signal is "50";
  attribute RTL_MAX_FANOUT of \genblk24.phy_ctl_pre_fifo_2/wr_en\ : signal is "found";
  signal idelay_inc : STD_LOGIC;
  signal \^init_calib_complete_reg_rep__9\ : STD_LOGIC;
  signal mux_address : STD_LOGIC_VECTOR ( 37 downto 4 );
  signal mux_cas_n : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mux_cke : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal mux_cmd_wren : STD_LOGIC;
  signal mux_cs_n : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mux_odt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mux_we_n : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mux_wrdata_en : STD_LOGIC;
  signal p_1_out : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal phy_mc_go : STD_LOGIC;
  signal phy_rddata_en : STD_LOGIC;
  signal phy_read_calib : STD_LOGIC;
  signal pi_fine_dly_dec_done : STD_LOGIC;
  signal po_ck_addr_cmd_delay_done : STD_LOGIC;
  signal po_stg2_wrcal_cnt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rd_data_offset_cal_done : STD_LOGIC;
  signal tempmon_pi_f_dec : STD_LOGIC;
  signal tempmon_pi_f_inc : STD_LOGIC;
  signal tempmon_sel_pi_incdec : STD_LOGIC;
  signal u_ddr_calib_top_n_100 : STD_LOGIC;
  signal u_ddr_calib_top_n_104 : STD_LOGIC;
  signal u_ddr_calib_top_n_109 : STD_LOGIC;
  signal u_ddr_calib_top_n_113 : STD_LOGIC;
  signal u_ddr_calib_top_n_117 : STD_LOGIC;
  signal u_ddr_calib_top_n_121 : STD_LOGIC;
  signal u_ddr_calib_top_n_122 : STD_LOGIC;
  signal u_ddr_calib_top_n_2 : STD_LOGIC;
  signal u_ddr_calib_top_n_243 : STD_LOGIC;
  signal u_ddr_calib_top_n_245 : STD_LOGIC;
  signal u_ddr_calib_top_n_247 : STD_LOGIC;
  signal u_ddr_calib_top_n_446 : STD_LOGIC;
  signal u_ddr_calib_top_n_447 : STD_LOGIC;
  signal u_ddr_calib_top_n_448 : STD_LOGIC;
  signal u_ddr_calib_top_n_462 : STD_LOGIC;
  signal u_ddr_calib_top_n_70 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_70 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_70 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of u_ddr_calib_top_n_70 : signal is "10";
  signal u_ddr_calib_top_n_71 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_71 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_71 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_71 : signal is "10";
  signal u_ddr_calib_top_n_72 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_72 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_72 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_72 : signal is "10";
  signal u_ddr_calib_top_n_74 : STD_LOGIC;
  signal u_ddr_calib_top_n_75 : STD_LOGIC;
  signal u_ddr_calib_top_n_76 : STD_LOGIC;
  signal u_ddr_calib_top_n_77 : STD_LOGIC;
  signal u_ddr_calib_top_n_78 : STD_LOGIC;
  signal u_ddr_calib_top_n_79 : STD_LOGIC;
  signal u_ddr_calib_top_n_8 : STD_LOGIC;
  signal u_ddr_calib_top_n_80 : STD_LOGIC;
  signal u_ddr_calib_top_n_81 : STD_LOGIC;
  signal u_ddr_calib_top_n_82 : STD_LOGIC;
  signal u_ddr_calib_top_n_83 : STD_LOGIC;
  signal u_ddr_calib_top_n_84 : STD_LOGIC;
  signal u_ddr_calib_top_n_85 : STD_LOGIC;
  signal u_ddr_calib_top_n_86 : STD_LOGIC;
  signal u_ddr_calib_top_n_87 : STD_LOGIC;
  signal u_ddr_calib_top_n_88 : STD_LOGIC;
  signal u_ddr_calib_top_n_89 : STD_LOGIC;
  signal u_ddr_calib_top_n_9 : STD_LOGIC;
  signal u_ddr_calib_top_n_90 : STD_LOGIC;
  signal u_ddr_calib_top_n_91 : STD_LOGIC;
  signal u_ddr_calib_top_n_92 : STD_LOGIC;
  signal u_ddr_calib_top_n_93 : STD_LOGIC;
  signal u_ddr_calib_top_n_94 : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_counter_load_val\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_rst_primitives\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ififo_rst_reg0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d8\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst_reg0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_rst_reg0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst_reg0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\ : STD_LOGIC_VECTOR ( 72 downto 16 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \u_ddr_mc_phy/pi_counter_read_val_w[0]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal u_ddr_mc_phy_wrapper_n_291 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_292 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_293 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_294 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_295 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_296 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_297 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_298 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_299 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_300 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_301 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_302 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_303 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_304 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_305 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_306 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_307 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_308 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_309 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_310 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_311 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_312 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_313 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_314 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_315 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_316 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_317 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_318 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_319 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_320 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_321 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_322 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_323 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_324 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_325 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_326 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_327 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_328 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_329 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_330 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_331 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_332 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_333 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_334 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_335 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_336 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_337 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_338 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_339 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_340 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_341 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_342 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_343 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_344 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_345 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_346 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_347 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_348 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_349 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_350 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_351 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_352 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_353 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_363 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_4 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_455 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_456 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_457 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_458 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_459 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_460 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_461 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_462 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_463 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_464 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_465 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_466 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_467 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_468 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_469 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_470 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_471 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_472 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_473 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_474 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_475 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_476 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_477 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_478 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_479 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_480 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_481 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_482 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_483 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_484 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_485 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_486 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_487 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_488 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_489 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_490 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_491 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_492 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_493 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_494 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_495 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_496 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_497 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_498 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_499 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_5 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_50 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_500 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_501 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_502 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_503 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_504 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_505 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_506 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_507 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_508 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_509 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_510 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_511 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_512 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_513 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_514 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_515 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_516 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_517 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_518 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_83 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_84 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_85 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_86 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_87 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_88 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_89 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_90 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_91 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_92 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_93 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_96 : STD_LOGIC;
  signal \u_ddr_phy_init/cnt_pwron_cke_done_r\ : STD_LOGIC;
  signal \u_ddr_phy_init/p_128_in\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.calib_in_common_i_1\ : label is "soft_lutpair524";
  attribute SOFT_HLUTNM of tempmon_pi_f_en_r_i_1 : label is "soft_lutpair524";
begin
  \init_calib_complete_reg_rep__9\ <= \^init_calib_complete_reg_rep__9\;
\calib_sel[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404040404040004"
    )
        port map (
      I0 => u_ddr_calib_top_n_446,
      I1 => u_ddr_calib_top_n_448,
      I2 => \my_full_reg[0]\,
      I3 => calib_complete,
      I4 => tempmon_pi_f_dec,
      I5 => tempmon_pi_f_inc,
      O => \calib_sel[1]_i_1_n_0\
    );
\calib_zero_ctrl[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF8AAAAAAA"
    )
        port map (
      I0 => dqs_po_dec_done,
      I1 => u_ddr_calib_top_n_462,
      I2 => po_ck_addr_cmd_delay_done,
      I3 => pi_fine_dly_dec_done,
      I4 => rd_data_offset_cal_done,
      I5 => calib_sel0,
      O => \calib_zero_ctrl[0]_i_1_n_0\
    );
\gen_byte_sel_div2.calib_in_common_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF0FEF0"
    )
        port map (
      I0 => tempmon_pi_f_inc,
      I1 => tempmon_pi_f_dec,
      I2 => u_ddr_calib_top_n_447,
      I3 => u_ddr_calib_top_n_8,
      I4 => calib_in_common,
      O => \gen_byte_sel_div2.calib_in_common_i_1_n_0\
    );
tempmon_pi_f_en_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tempmon_pi_f_inc,
      I1 => tempmon_pi_f_dec,
      O => tempmon_sel_pi_incdec
    );
u_ddr_calib_top: entity work.mig_7series_0_mig_7series_v4_2_ddr_calib_top
     port map (
      A_rst_primitives => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_rst_primitives\,
      CLK => CLK,
      COUNTERLOADVAL(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_counter_load_val\(5 downto 0),
      D(10 downto 3) => p_1_out(24 downto 17),
      D(2 downto 0) => p_1_out(2 downto 0),
      D0(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d0\(7 downto 0),
      D1(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(7 downto 0),
      D2(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(7 downto 0),
      D3(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(7 downto 0),
      D4(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(7 downto 0),
      D5(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(7 downto 0),
      D6(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(7 downto 0),
      D7(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(7 downto 0),
      D8(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d8\(7 downto 0),
      D9(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9\(7 downto 0),
      E(0) => u_ddr_calib_top_n_243,
      \FSM_onehot_cal1_state_r_reg[13]\(0) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/p_27_in\,
      LD0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\,
      LD0_0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\,
      Q(0) => phy_mc_go,
      SR(0) => SR(0),
      SS(0) => SS(0),
      app_zq_ns => app_zq_ns,
      app_zq_req => app_zq_req,
      calib_cmd_wren => calib_cmd_wren,
      calib_complete => calib_complete,
      calib_ctl_wren_reg => u_ddr_calib_top_n_74,
      calib_in_common => calib_in_common,
      calib_sel(0) => calib_sel(1),
      calib_sel0 => calib_sel0,
      \calib_sel_reg[1]_0\ => u_ddr_calib_top_n_75,
      \calib_sel_reg[1]_1\ => u_ddr_calib_top_n_79,
      \calib_sel_reg[1]_10\ => \calib_sel[1]_i_1_n_0\,
      \calib_sel_reg[1]_2\ => u_ddr_calib_top_n_80,
      \calib_sel_reg[1]_3\ => u_ddr_calib_top_n_81,
      \calib_sel_reg[1]_4\ => u_ddr_calib_top_n_82,
      \calib_sel_reg[1]_5\ => u_ddr_calib_top_n_83,
      \calib_sel_reg[1]_6\ => u_ddr_calib_top_n_84,
      \calib_sel_reg[1]_7\ => u_ddr_calib_top_n_85,
      \calib_sel_reg[1]_8\ => u_ddr_calib_top_n_86,
      \calib_sel_reg[1]_9\ => u_ddr_calib_top_n_122,
      calib_wrdata_en => calib_wrdata_en,
      \calib_zero_ctrl_reg[0]_0\ => u_ddr_calib_top_n_121,
      \calib_zero_ctrl_reg[0]_1\ => \calib_zero_ctrl[0]_i_1_n_0\,
      ck_po_stg2_f_en_reg => u_ddr_calib_top_n_77,
      ck_po_stg2_f_indec_reg => u_ddr_calib_top_n_78,
      ck_po_stg2_f_indec_reg_0 => u_ddr_calib_top_n_90,
      \cmd_pipe_plus.mc_cas_n_reg[0]\(25) => mux_cas_n(0),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(24) => mux_cke(3),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(23) => mux_cke(0),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(22) => mux_cs_n(0),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(21) => mux_we_n(0),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(20) => u_ddr_calib_top_n_100,
      \cmd_pipe_plus.mc_cas_n_reg[0]\(19) => mux_address(30),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(18) => mux_address(17),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(17) => mux_address(4),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(16) => u_ddr_calib_top_n_104,
      \cmd_pipe_plus.mc_cas_n_reg[0]\(15) => mux_address(33),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(14) => mux_address(20),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(13) => mux_address(7),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(12) => mux_odt(0),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(11) => u_ddr_calib_top_n_109,
      \cmd_pipe_plus.mc_cas_n_reg[0]\(10) => mux_address(32),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(9) => mux_address(19),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(8) => mux_address(6),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(7) => u_ddr_calib_top_n_113,
      \cmd_pipe_plus.mc_cas_n_reg[0]\(6) => mux_address(37),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(5) => mux_address(24),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(4) => mux_address(11),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(3) => u_ddr_calib_top_n_117,
      \cmd_pipe_plus.mc_cas_n_reg[0]\(2) => mux_address(34),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(1) => mux_address(21),
      \cmd_pipe_plus.mc_cas_n_reg[0]\(0) => mux_address(8),
      \cmd_pipe_plus.mc_cas_n_reg[0]_0\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(0),
      \cmd_pipe_plus.mc_cas_n_reg[0]_1\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\(0),
      \cmd_pipe_plus.mc_cke_reg[3]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\(3 downto 0),
      \cmd_pipe_plus.mc_ras_n_reg[2]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(2 downto 0),
      \cmd_pipe_plus.mc_we_n_reg[0]\(4 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(4 downto 0),
      \cnt_idel_dec_cpt_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_86,
      \cnt_idel_dec_cpt_r_reg[5]\(5 downto 0) => \u_ddr_mc_phy/pi_counter_read_val_w[0]_0\(5 downto 0),
      cnt_pwron_cke_done_r => \u_ddr_phy_init/cnt_pwron_cke_done_r\,
      \cnt_pwron_r_reg[0]\ => \mcGo_r_reg[0]\,
      \cnt_shift_r_reg[0]\(0) => \cnt_shift_r_reg[0]\(0),
      \complex_address_reg[9]\(1 downto 0) => \complex_address_reg[9]\(1 downto 0),
      \complex_num_writes_reg[4]\ => \complex_num_writes_reg[4]\,
      \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(36 downto 0) => \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(36 downto 0),
      \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\(143 downto 0) => Q(143 downto 0),
      delay_done_reg => delay_done_reg,
      \device_temp_101_reg[11]\(11 downto 0) => \device_temp_101_reg[11]\(11 downto 0),
      dqs_po_dec_done => dqs_po_dec_done,
      fine_adjust_done_r_reg => u_ddr_calib_top_n_462,
      first_fail_detect_reg => \rd_ptr_timing_reg[2]\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ => u_ddr_calib_top_n_448,
      \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ => u_ddr_calib_top_n_446,
      \gen_byte_sel_div2.calib_in_common_reg_0\ => \gen_byte_sel_div2.calib_in_common_i_1_n_0\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_299,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_301,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_303,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_305,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_298,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_300,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_302,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_304,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_323,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_325,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_327,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_329,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_322,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_324,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_326,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_328,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_291,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_293,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_295,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_297,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_96,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_292,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_294,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_296,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_315,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_317,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_319,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_321,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_314,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_316,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_318,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_320,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_331,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_333,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_335,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_337,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_330,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_332,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_334,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_336,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_347,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_349,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_351,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_353,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_346,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_348,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_350,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_352,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_307,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_309,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_311,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_313,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_306,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_308,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_310,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_312,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_339,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_341,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_343,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_345,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_338,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_340,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_342,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_344,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_471,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_511,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_487,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_463,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_503,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_455,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_495,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_472,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_512,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_488,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_464,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_504,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_456,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_480,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_496,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_473,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_513,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_489,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_465,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_505,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_457,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_481,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_497,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_474,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_514,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_490,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_466,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_506,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_458,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_482,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_475,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_515,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_491,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_467,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_507,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_459,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_499,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_476,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_516,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_492,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_468,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_508,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_460,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_484,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_500,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_477,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_517,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_493,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_469,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_509,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_461,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_485,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_501,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_478,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_518,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_494,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_470,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_510,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_462,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_486,
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(7 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[11]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d0\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(7 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\(3 downto 0),
      \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(7 downto 0),
      \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_479,
      \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_498,
      \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_483,
      \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_502,
      idelay_ce_r2_reg_0 => u_ddr_calib_top_n_87,
      idelay_inc => idelay_inc,
      idelay_ld_rst => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\,
      \idelay_tap_cnt_r_reg[0][1][4]\ => \idelay_tap_cnt_r_reg[0][1][4]\,
      ififo_rst_reg0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ififo_rst_reg0\,
      ififo_rst_reg0_1 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_rst_reg0\,
      in0 => u_ddr_mc_phy_wrapper_n_363,
      init_calib_complete_reg_rep_0 => init_calib_complete_reg_rep,
      init_calib_complete_reg_rep_1(59 downto 0) => init_calib_complete_reg_rep_0(59 downto 0),
      \init_calib_complete_reg_rep__0_0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1_0\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__2_0\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__4_0\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(3 downto 0),
      \init_calib_complete_reg_rep__5_0\ => u_ddr_calib_top_n_70,
      \init_calib_complete_reg_rep__5_1\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\(7 downto 0),
      \init_calib_complete_reg_rep__6_0\ => u_ddr_calib_top_n_71,
      \init_calib_complete_reg_rep__8_0\ => u_ddr_calib_top_n_72,
      \init_calib_complete_reg_rep__9_0\ => \^init_calib_complete_reg_rep__9\,
      init_complete_r_timing_reg => init_complete_r_timing_reg,
      init_dqsfound_done_r_reg => u_ddr_calib_top_n_447,
      \init_state_r1_reg[0]\(0) => \init_state_r1_reg[0]\(0),
      \lane_cnt_po_r_reg[0]\ => \lane_cnt_po_r_reg[0]\,
      mc_cas_n(0) => mc_cas_n(0),
      mc_cmd(1 downto 0) => mc_cmd(1 downto 0),
      mc_odt(0) => mc_odt(0),
      mc_ras_n(2 downto 0) => mc_ras_n(2 downto 0),
      mc_wrdata_en => mc_wrdata_en,
      mem_out(30) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(72),
      mem_out(29 downto 26) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(67 downto 64),
      mem_out(25) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(56),
      mem_out(24 downto 12) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(52 downto 40),
      mem_out(11 downto 8) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(35 downto 32),
      mem_out(7 downto 4) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(27 downto 24),
      mem_out(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(19 downto 16),
      mem_reg_0_15_48_53(0) => out_fifo_1(0),
      mem_reg_0_15_60_65(1 downto 0) => mem_reg_0_15_60_65(1 downto 0),
      mux_cmd_wren => mux_cmd_wren,
      mux_wrdata_en => mux_wrdata_en,
      \my_empty_reg[3]\ => \genblk24.phy_ctl_pre_fifo_0/wr_en\,
      \my_empty_reg[3]_0\ => \genblk24.phy_ctl_pre_fifo_1/wr_en\,
      \my_empty_reg[3]_1\ => \genblk24.phy_ctl_pre_fifo_2/wr_en\,
      \my_empty_reg[5]\(0) => u_ddr_calib_top_n_245,
      \my_empty_reg[5]_0\(0) => u_ddr_calib_top_n_247,
      new_cnt_cpt_r_reg => new_cnt_cpt_r_reg,
      \not_empty_wait_cnt_reg[4]\ => \my_full_reg[0]\,
      ofifo_rst_reg0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst_reg0\,
      ofifo_rst_reg0_2 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst_reg0\,
      \one_inc_min_limit_reg[2]\ => \one_inc_min_limit_reg[2]\,
      \out\ => u_ddr_calib_top_n_9,
      out_fifo(71 downto 0) => out_fifo(79 downto 8),
      out_fifo_0 => u_ddr_mc_phy_wrapper_n_83,
      out_fifo_1(71 downto 24) => out_fifo_0(79 downto 32),
      out_fifo_1(23 downto 0) => out_fifo_0(23 downto 0),
      out_fifo_2 => u_ddr_mc_phy_wrapper_n_84,
      out_fifo_3 => u_ddr_mc_phy_wrapper_n_50,
      out_fifo_4(8 downto 0) => out_fifo_2(8 downto 0),
      out_fifo_5(46 downto 43) => mem_out(75 downto 72),
      out_fifo_5(42 downto 39) => mem_out(67 downto 64),
      out_fifo_5(38 downto 19) => mem_out(59 downto 40),
      out_fifo_5(18 downto 16) => mem_out(34 downto 32),
      out_fifo_5(15 downto 12) => mem_out(27 downto 24),
      out_fifo_5(11 downto 8) => mem_out(19 downto 16),
      out_fifo_5(7 downto 4) => mem_out(11 downto 8),
      out_fifo_5(3 downto 0) => mem_out(3 downto 0),
      out_fifo_6 => u_ddr_mc_phy_wrapper_n_85,
      p_128_in => \u_ddr_phy_init/p_128_in\,
      \phy_ctl_wd_i1_reg[17]\ => \phy_ctl_wd_i1_reg[17]\,
      \phy_ctl_wd_i1_reg[19]\(1 downto 0) => \phy_ctl_wd_i1_reg[19]\(1 downto 0),
      \phy_ctl_wd_i1_reg[20]\ => \phy_ctl_wd_i1_reg[20]\,
      \phy_ctl_wd_i1_reg[21]\ => \phy_ctl_wd_i1_reg[21]\,
      \phy_ctl_wd_i1_reg[22]\ => \phy_ctl_wd_i1_reg[22]\,
      phy_dout(44 downto 0) => phy_dout(44 downto 0),
      phy_rddata_en => phy_rddata_en,
      phy_read_calib => phy_read_calib,
      pi_cnt_dec_reg => pi_cnt_dec_reg,
      pi_dqs_found_lanes(1) => u_ddr_mc_phy_wrapper_n_4,
      pi_dqs_found_lanes(0) => u_ddr_mc_phy_wrapper_n_5,
      pi_fine_dly_dec_done => pi_fine_dly_dec_done,
      \pi_rst_stg1_cal_reg[0]\ => u_ddr_calib_top_n_91,
      pi_stg2_load_reg => u_ddr_calib_top_n_94,
      \pi_stg2_reg_l_reg[5]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val\(5 downto 0),
      po_ck_addr_cmd_delay_done => po_ck_addr_cmd_delay_done,
      po_en_s2_c_reg => u_ddr_calib_top_n_76,
      po_en_s2_c_reg_0 => u_ddr_calib_top_n_89,
      po_en_s2_f_reg => u_ddr_calib_top_n_88,
      \po_stg2_wrcal_cnt_reg[0]\(0) => po_stg2_wrcal_cnt(0),
      prbs_rdlvl_done_pulse_reg => prbs_rdlvl_done_pulse_reg,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5 downto 0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5 downto 0),
      rd_data_offset_cal_done => rd_data_offset_cal_done,
      \rd_mux_sel_r_reg[0]\ => u_ddr_calib_top_n_2,
      rdlvl_stg1_done_int_reg => u_ddr_calib_top_n_8,
      rdlvl_stg1_start_reg => rdlvl_stg1_start_reg,
      rdlvl_stg1_start_reg_0 => rdlvl_stg1_start_reg_0,
      samp_edge_cnt0_en_r => samp_edge_cnt0_en_r,
      \samp_edge_cnt1_r_reg[0]\ => \samp_edge_cnt1_r_reg[0]\,
      store_sr_req_r_reg => u_ddr_mc_phy_wrapper_n_87,
      \tap_cnt_cpt_r_reg[5]\(0) => \tap_cnt_cpt_r_reg[5]\(0),
      tempmon_pi_f_dec => tempmon_pi_f_dec,
      tempmon_pi_f_en_r_reg_0 => u_ddr_calib_top_n_92,
      tempmon_pi_f_inc => tempmon_pi_f_inc,
      tempmon_pi_f_inc_r_reg_0 => u_ddr_calib_top_n_93,
      tempmon_sample_en => tempmon_sample_en,
      tempmon_sel_pi_incdec => tempmon_sel_pi_incdec,
      \wr_en_inferred__0_i_1\ => u_ddr_mc_phy_wrapper_n_89,
      \wr_en_inferred__0_i_1__0\ => u_ddr_mc_phy_wrapper_n_91,
      \wr_en_inferred__0_i_1__1\ => u_ddr_mc_phy_wrapper_n_93,
      \wr_ptr_timing_reg[0]\ => u_ddr_mc_phy_wrapper_n_88,
      \wr_ptr_timing_reg[0]_0\ => u_ddr_mc_phy_wrapper_n_90,
      \wr_ptr_timing_reg[0]_1\ => u_ddr_mc_phy_wrapper_n_92,
      wrcal_done_reg(0) => wrcal_done_reg(0),
      \wrcal_dqs_cnt_r_reg[1]\(0) => rst_out_reg(0),
      \write_buffer.wr_buf_out_data_reg[117]\(59 downto 0) => \write_buffer.wr_buf_out_data_reg[117]\(59 downto 0),
      \write_buffer.wr_buf_out_data_reg[120]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[121]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[122]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[123]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[124]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[126]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(7 downto 0),
      \write_buffer.wr_buf_out_data_reg[127]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(7 downto 0)
    );
u_ddr_mc_phy_wrapper: entity work.mig_7series_0_mig_7series_v4_2_ddr_mc_phy_wrapper
     port map (
      A_rst_primitives => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_rst_primitives\,
      A_rst_primitives_reg => A_rst_primitives_reg,
      A_rst_primitives_reg_0 => A_rst_primitives_reg_0,
      CLK => CLK,
      CLKB0 => CLKB0,
      CLKB0_5 => CLKB0_5,
      COUNTERLOADVAL(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_counter_load_val\(5 downto 0),
      D(10 downto 3) => p_1_out(24 downto 17),
      D(2 downto 0) => p_1_out(2 downto 0),
      D0(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d0\(7 downto 0),
      D1(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(7 downto 0),
      D2(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(7 downto 0),
      D3(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(7 downto 0),
      D4(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(7 downto 0),
      D5(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(7 downto 0),
      D6(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(7 downto 0),
      D7(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(7 downto 0),
      D8(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d8\(7 downto 0),
      D9(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9\(7 downto 0),
      E(0) => u_ddr_calib_top_n_243,
      \FSM_onehot_cal1_state_r_reg[13]\ => u_ddr_mc_phy_wrapper_n_86,
      LD0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\,
      LD0_0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\,
      Q(5 downto 0) => \u_ddr_mc_phy/pi_counter_read_val_w[0]_0\(5 downto 0),
      RST0 => RST0,
      SR(0) => SR(0),
      UNCONN_IN => \genblk24.phy_ctl_pre_fifo_0/wr_en\,
      UNCONN_IN_0 => \genblk24.phy_ctl_pre_fifo_1/wr_en\,
      UNCONN_IN_1 => \genblk24.phy_ctl_pre_fifo_2/wr_en\,
      app_rd_data(127 downto 0) => app_rd_data(127 downto 0),
      \app_rd_data[117]\(63 downto 0) => \app_rd_data[117]\(63 downto 0),
      app_rd_data_valid => app_rd_data_valid,
      app_rd_data_valid_0 => u_ddr_calib_top_n_9,
      app_rd_data_valid_1(0) => app_rd_data_valid_0(0),
      calib_cmd_wren => calib_cmd_wren,
      calib_sel(0) => calib_sel(1),
      calib_wrdata_en => calib_wrdata_en,
      \cnt_idel_dec_cpt_r_reg[0]\(0) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/p_27_in\,
      cnt_pwron_cke_done_r => \u_ddr_phy_init/cnt_pwron_cke_done_r\,
      ddr2_addr(12 downto 0) => ddr2_addr(12 downto 0),
      ddr2_ba(2 downto 0) => ddr2_ba(2 downto 0),
      ddr2_cas_n => ddr2_cas_n,
      ddr2_cke(0) => ddr2_cke(0),
      ddr2_cs_n(0) => ddr2_cs_n(0),
      ddr2_dm(1 downto 0) => ddr2_dm(1 downto 0),
      ddr2_dq(15 downto 0) => ddr2_dq(15 downto 0),
      ddr2_dqs_n(1 downto 0) => ddr2_dqs_n(1 downto 0),
      ddr2_dqs_p(1 downto 0) => ddr2_dqs_p(1 downto 0),
      ddr2_odt(0) => ddr2_odt(0),
      ddr2_ras_n => ddr2_ras_n,
      ddr2_we_n => ddr2_we_n,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_346,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => u_ddr_mc_phy_wrapper_n_300,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => u_ddr_mc_phy_wrapper_n_301,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => u_ddr_mc_phy_wrapper_n_302,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => u_ddr_mc_phy_wrapper_n_303,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => u_ddr_mc_phy_wrapper_n_304,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => u_ddr_mc_phy_wrapper_n_305,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => u_ddr_mc_phy_wrapper_n_338,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => u_ddr_mc_phy_wrapper_n_339,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => u_ddr_mc_phy_wrapper_n_340,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => u_ddr_mc_phy_wrapper_n_341,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_347,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => u_ddr_mc_phy_wrapper_n_342,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => u_ddr_mc_phy_wrapper_n_343,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => u_ddr_mc_phy_wrapper_n_344,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => u_ddr_mc_phy_wrapper_n_345,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_348,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => u_ddr_mc_phy_wrapper_n_330,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => u_ddr_mc_phy_wrapper_n_331,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => u_ddr_mc_phy_wrapper_n_332,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => u_ddr_mc_phy_wrapper_n_333,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => u_ddr_mc_phy_wrapper_n_334,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => u_ddr_mc_phy_wrapper_n_335,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => u_ddr_mc_phy_wrapper_n_336,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => u_ddr_mc_phy_wrapper_n_337,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_349,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => u_ddr_mc_phy_wrapper_n_96,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => u_ddr_mc_phy_wrapper_n_291,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => u_ddr_mc_phy_wrapper_n_292,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => u_ddr_mc_phy_wrapper_n_293,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => u_ddr_mc_phy_wrapper_n_294,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => u_ddr_mc_phy_wrapper_n_295,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => u_ddr_mc_phy_wrapper_n_296,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => u_ddr_mc_phy_wrapper_n_297,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => u_ddr_mc_phy_wrapper_n_322,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => u_ddr_mc_phy_wrapper_n_323,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_350,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => u_ddr_mc_phy_wrapper_n_324,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => u_ddr_mc_phy_wrapper_n_325,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => u_ddr_mc_phy_wrapper_n_326,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => u_ddr_mc_phy_wrapper_n_327,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => u_ddr_mc_phy_wrapper_n_328,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => u_ddr_mc_phy_wrapper_n_329,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => u_ddr_mc_phy_wrapper_n_314,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => u_ddr_mc_phy_wrapper_n_315,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => u_ddr_mc_phy_wrapper_n_316,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => u_ddr_mc_phy_wrapper_n_317,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_351,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => u_ddr_mc_phy_wrapper_n_318,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => u_ddr_mc_phy_wrapper_n_319,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => u_ddr_mc_phy_wrapper_n_320,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => u_ddr_mc_phy_wrapper_n_321,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => u_ddr_mc_phy_wrapper_n_306,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => u_ddr_mc_phy_wrapper_n_307,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => u_ddr_mc_phy_wrapper_n_308,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => u_ddr_mc_phy_wrapper_n_309,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => u_ddr_mc_phy_wrapper_n_310,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => u_ddr_mc_phy_wrapper_n_311,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_352,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => u_ddr_mc_phy_wrapper_n_312,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => u_ddr_mc_phy_wrapper_n_313,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_353,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => u_ddr_mc_phy_wrapper_n_298,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => u_ddr_mc_phy_wrapper_n_299,
      freq_refclk => freq_refclk,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => u_ddr_calib_top_n_2,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0) => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0),
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0) => po_stg2_wrcal_cnt(0),
      idelay_inc => idelay_inc,
      idelay_ld_rst => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\,
      idle => idle,
      ififo_rst_reg0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ififo_rst_reg0\,
      ififo_rst_reg0_1 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_rst_reg0\,
      in0 => u_ddr_mc_phy_wrapper_n_363,
      init_complete_r1_timing_reg => init_complete_r1_timing_reg,
      \input_[8].iserdes_dq_.iserdesdq\ => u_ddr_calib_top_n_87,
      \input_[9].iserdes_dq_.iserdesdq\ => u_ddr_calib_top_n_79,
      \mcGo_r_reg[0]\ => \mcGo_r_reg[0]\,
      \mcGo_r_reg[15]\(0) => phy_mc_go,
      mc_cas_n(1 downto 0) => mc_cas_n(2 downto 1),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(0) => mc_ras_n(2),
      mc_wrdata_en => mc_wrdata_en,
      mem_out(30) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(72),
      mem_out(29 downto 26) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(67 downto 64),
      mem_out(25) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(56),
      mem_out(24 downto 12) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(52 downto 40),
      mem_out(11 downto 8) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(35 downto 32),
      mem_out(7 downto 4) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(27 downto 24),
      mem_out(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(19 downto 16),
      mem_refclk => mem_refclk,
      mux_cmd_wren => mux_cmd_wren,
      mux_wrdata_en => mux_wrdata_en,
      \my_empty_reg[0]\ => \my_empty_reg[0]\,
      \my_empty_reg[1]\ => u_ddr_mc_phy_wrapper_n_50,
      \my_empty_reg[1]_0\ => u_ddr_mc_phy_wrapper_n_83,
      \my_empty_reg[1]_1\ => u_ddr_mc_phy_wrapper_n_84,
      \my_empty_reg[1]_2\ => u_ddr_mc_phy_wrapper_n_85,
      \my_empty_reg[3]\ => u_ddr_mc_phy_wrapper_n_89,
      \my_empty_reg[3]_0\ => u_ddr_mc_phy_wrapper_n_91,
      \my_empty_reg[3]_1\ => u_ddr_mc_phy_wrapper_n_93,
      \my_empty_reg[5]\ => u_ddr_mc_phy_wrapper_n_88,
      \my_empty_reg[5]_0\ => u_ddr_mc_phy_wrapper_n_90,
      \my_empty_reg[5]_1\ => u_ddr_mc_phy_wrapper_n_92,
      \my_empty_reg[6]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d0\(3 downto 0),
      \my_empty_reg[6]_0\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(3 downto 0),
      \my_empty_reg[6]_1\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(3 downto 0),
      \my_empty_reg[6]_2\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(3 downto 0),
      \my_empty_reg[6]_3\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(2 downto 0),
      \my_empty_reg[6]_4\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(7 downto 0),
      \my_empty_reg[6]_5\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(7 downto 0),
      \my_empty_reg[6]_6\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(3 downto 0),
      \my_empty_reg[6]_7\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(3 downto 0),
      \my_empty_reg[6]_8\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\(3 downto 0),
      \my_empty_reg[7]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(7 downto 0),
      \my_empty_reg[7]_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(7 downto 0),
      \my_empty_reg[7]_1\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(7 downto 0),
      \my_empty_reg[7]_2\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 0),
      \my_empty_reg[7]_3\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 0),
      \my_empty_reg[7]_4\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(7 downto 0),
      \my_empty_reg[7]_5\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(7 downto 0),
      \my_empty_reg[7]_6\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\(7 downto 0),
      \my_full_reg[0]\ => \my_full_reg[0]\,
      ofifo_rst_reg0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst_reg0\,
      ofifo_rst_reg0_2 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst_reg0\,
      \out\(1 downto 0) => \out\(1 downto 0),
      out_fifo => u_ddr_calib_top_n_76,
      out_fifo_0 => u_ddr_calib_top_n_121,
      out_fifo_1 => u_ddr_calib_top_n_77,
      out_fifo_2 => u_ddr_calib_top_n_78,
      out_fifo_3 => u_ddr_calib_top_n_71,
      out_fifo_4(32 downto 29) => mem_out(79 downto 76),
      out_fifo_4(28 downto 25) => mem_out(71 downto 68),
      out_fifo_4(24 downto 21) => mem_out(63 downto 60),
      out_fifo_4(20 downto 16) => mem_out(39 downto 35),
      out_fifo_4(15 downto 12) => mem_out(31 downto 28),
      out_fifo_4(11 downto 8) => mem_out(23 downto 20),
      out_fifo_4(7 downto 4) => mem_out(15 downto 12),
      out_fifo_4(3 downto 0) => mem_out(7 downto 4),
      out_fifo_5(7 downto 0) => out_fifo(7 downto 0),
      out_fifo_6(7 downto 0) => out_fifo_0(31 downto 24),
      out_fifo_7(1 downto 0) => out_fifo_1(2 downto 1),
      p_128_in => \u_ddr_phy_init/p_128_in\,
      p_1_in => p_1_in,
      phy_ctl_wr_i1_reg_0 => u_ddr_calib_top_n_74,
      phy_dout(31 downto 30) => \out_fifo_i_69__1\(5 downto 4),
      phy_dout(29) => mux_cas_n(0),
      phy_dout(28) => mux_cke(3),
      phy_dout(27) => mux_cke(0),
      phy_dout(26 downto 25) => \out_fifo_i_69__1\(3 downto 2),
      phy_dout(24) => mux_cs_n(0),
      phy_dout(23 downto 22) => \out_fifo_i_69__1\(1 downto 0),
      phy_dout(21) => mux_we_n(0),
      phy_dout(20) => u_ddr_calib_top_n_100,
      phy_dout(19) => mux_address(30),
      phy_dout(18) => mux_address(17),
      phy_dout(17) => mux_address(4),
      phy_dout(16) => u_ddr_calib_top_n_104,
      phy_dout(15) => mux_address(33),
      phy_dout(14) => mux_address(20),
      phy_dout(13) => mux_address(7),
      phy_dout(12) => mux_odt(0),
      phy_dout(11) => u_ddr_calib_top_n_109,
      phy_dout(10) => mux_address(32),
      phy_dout(9) => mux_address(19),
      phy_dout(8) => mux_address(6),
      phy_dout(7) => u_ddr_calib_top_n_113,
      phy_dout(6) => mux_address(37),
      phy_dout(5) => mux_address(24),
      phy_dout(4) => mux_address(11),
      phy_dout(3) => u_ddr_calib_top_n_117,
      phy_dout(2) => mux_address(34),
      phy_dout(1) => mux_address(21),
      phy_dout(0) => mux_address(8),
      phy_mc_cmd_full => phy_mc_cmd_full,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      phy_rddata_en => phy_rddata_en,
      phy_read_calib => phy_read_calib,
      \pi_counter_read_val_reg[5]\ => u_ddr_mc_phy_wrapper_n_87,
      pi_dqs_found_lanes(1) => u_ddr_mc_phy_wrapper_n_4,
      pi_dqs_found_lanes(0) => u_ddr_mc_phy_wrapper_n_5,
      \pi_dqs_found_lanes_r1_reg[0]\ => u_ddr_calib_top_n_86,
      \pi_dqs_found_lanes_r1_reg[0]_0\ => u_ddr_calib_top_n_122,
      \pi_dqs_found_lanes_r1_reg[0]_1\ => u_ddr_calib_top_n_84,
      \pi_dqs_found_lanes_r1_reg[0]_2\ => u_ddr_calib_top_n_85,
      \pi_dqs_found_lanes_r1_reg[0]_3\ => u_ddr_calib_top_n_83,
      \pi_dqs_found_lanes_r1_reg[2]\ => u_ddr_calib_top_n_94,
      \pi_dqs_found_lanes_r1_reg[2]_0\ => u_ddr_calib_top_n_75,
      \pi_dqs_found_lanes_r1_reg[2]_1\ => u_ddr_calib_top_n_92,
      \pi_dqs_found_lanes_r1_reg[2]_2\ => u_ddr_calib_top_n_93,
      \pi_dqs_found_lanes_r1_reg[2]_3\ => u_ddr_calib_top_n_91,
      \pi_dqs_found_lanes_r1_reg[2]_4\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val\(5 downto 0),
      pll_locked => pll_locked,
      \po_stg2_wrcal_cnt_reg[0]\ => u_ddr_mc_phy_wrapper_n_455,
      \po_stg2_wrcal_cnt_reg[0]_0\ => u_ddr_mc_phy_wrapper_n_456,
      \po_stg2_wrcal_cnt_reg[0]_1\ => u_ddr_mc_phy_wrapper_n_457,
      \po_stg2_wrcal_cnt_reg[0]_10\ => u_ddr_mc_phy_wrapper_n_466,
      \po_stg2_wrcal_cnt_reg[0]_11\ => u_ddr_mc_phy_wrapper_n_467,
      \po_stg2_wrcal_cnt_reg[0]_12\ => u_ddr_mc_phy_wrapper_n_468,
      \po_stg2_wrcal_cnt_reg[0]_13\ => u_ddr_mc_phy_wrapper_n_469,
      \po_stg2_wrcal_cnt_reg[0]_14\ => u_ddr_mc_phy_wrapper_n_470,
      \po_stg2_wrcal_cnt_reg[0]_15\ => u_ddr_mc_phy_wrapper_n_471,
      \po_stg2_wrcal_cnt_reg[0]_16\ => u_ddr_mc_phy_wrapper_n_472,
      \po_stg2_wrcal_cnt_reg[0]_17\ => u_ddr_mc_phy_wrapper_n_473,
      \po_stg2_wrcal_cnt_reg[0]_18\ => u_ddr_mc_phy_wrapper_n_474,
      \po_stg2_wrcal_cnt_reg[0]_19\ => u_ddr_mc_phy_wrapper_n_475,
      \po_stg2_wrcal_cnt_reg[0]_2\ => u_ddr_mc_phy_wrapper_n_458,
      \po_stg2_wrcal_cnt_reg[0]_20\ => u_ddr_mc_phy_wrapper_n_476,
      \po_stg2_wrcal_cnt_reg[0]_21\ => u_ddr_mc_phy_wrapper_n_477,
      \po_stg2_wrcal_cnt_reg[0]_22\ => u_ddr_mc_phy_wrapper_n_478,
      \po_stg2_wrcal_cnt_reg[0]_23\ => u_ddr_mc_phy_wrapper_n_479,
      \po_stg2_wrcal_cnt_reg[0]_24\ => u_ddr_mc_phy_wrapper_n_480,
      \po_stg2_wrcal_cnt_reg[0]_25\ => u_ddr_mc_phy_wrapper_n_481,
      \po_stg2_wrcal_cnt_reg[0]_26\ => u_ddr_mc_phy_wrapper_n_482,
      \po_stg2_wrcal_cnt_reg[0]_27\ => u_ddr_mc_phy_wrapper_n_483,
      \po_stg2_wrcal_cnt_reg[0]_28\ => u_ddr_mc_phy_wrapper_n_484,
      \po_stg2_wrcal_cnt_reg[0]_29\ => u_ddr_mc_phy_wrapper_n_485,
      \po_stg2_wrcal_cnt_reg[0]_3\ => u_ddr_mc_phy_wrapper_n_459,
      \po_stg2_wrcal_cnt_reg[0]_30\ => u_ddr_mc_phy_wrapper_n_486,
      \po_stg2_wrcal_cnt_reg[0]_31\ => u_ddr_mc_phy_wrapper_n_487,
      \po_stg2_wrcal_cnt_reg[0]_32\ => u_ddr_mc_phy_wrapper_n_488,
      \po_stg2_wrcal_cnt_reg[0]_33\ => u_ddr_mc_phy_wrapper_n_489,
      \po_stg2_wrcal_cnt_reg[0]_34\ => u_ddr_mc_phy_wrapper_n_490,
      \po_stg2_wrcal_cnt_reg[0]_35\ => u_ddr_mc_phy_wrapper_n_491,
      \po_stg2_wrcal_cnt_reg[0]_36\ => u_ddr_mc_phy_wrapper_n_492,
      \po_stg2_wrcal_cnt_reg[0]_37\ => u_ddr_mc_phy_wrapper_n_493,
      \po_stg2_wrcal_cnt_reg[0]_38\ => u_ddr_mc_phy_wrapper_n_494,
      \po_stg2_wrcal_cnt_reg[0]_39\ => u_ddr_mc_phy_wrapper_n_495,
      \po_stg2_wrcal_cnt_reg[0]_4\ => u_ddr_mc_phy_wrapper_n_460,
      \po_stg2_wrcal_cnt_reg[0]_40\ => u_ddr_mc_phy_wrapper_n_496,
      \po_stg2_wrcal_cnt_reg[0]_41\ => u_ddr_mc_phy_wrapper_n_497,
      \po_stg2_wrcal_cnt_reg[0]_42\ => u_ddr_mc_phy_wrapper_n_498,
      \po_stg2_wrcal_cnt_reg[0]_43\ => u_ddr_mc_phy_wrapper_n_499,
      \po_stg2_wrcal_cnt_reg[0]_44\ => u_ddr_mc_phy_wrapper_n_500,
      \po_stg2_wrcal_cnt_reg[0]_45\ => u_ddr_mc_phy_wrapper_n_501,
      \po_stg2_wrcal_cnt_reg[0]_46\ => u_ddr_mc_phy_wrapper_n_502,
      \po_stg2_wrcal_cnt_reg[0]_47\ => u_ddr_mc_phy_wrapper_n_503,
      \po_stg2_wrcal_cnt_reg[0]_48\ => u_ddr_mc_phy_wrapper_n_504,
      \po_stg2_wrcal_cnt_reg[0]_49\ => u_ddr_mc_phy_wrapper_n_505,
      \po_stg2_wrcal_cnt_reg[0]_5\ => u_ddr_mc_phy_wrapper_n_461,
      \po_stg2_wrcal_cnt_reg[0]_50\ => u_ddr_mc_phy_wrapper_n_506,
      \po_stg2_wrcal_cnt_reg[0]_51\ => u_ddr_mc_phy_wrapper_n_507,
      \po_stg2_wrcal_cnt_reg[0]_52\ => u_ddr_mc_phy_wrapper_n_508,
      \po_stg2_wrcal_cnt_reg[0]_53\ => u_ddr_mc_phy_wrapper_n_509,
      \po_stg2_wrcal_cnt_reg[0]_54\ => u_ddr_mc_phy_wrapper_n_510,
      \po_stg2_wrcal_cnt_reg[0]_55\ => u_ddr_mc_phy_wrapper_n_511,
      \po_stg2_wrcal_cnt_reg[0]_56\ => u_ddr_mc_phy_wrapper_n_512,
      \po_stg2_wrcal_cnt_reg[0]_57\ => u_ddr_mc_phy_wrapper_n_513,
      \po_stg2_wrcal_cnt_reg[0]_58\ => u_ddr_mc_phy_wrapper_n_514,
      \po_stg2_wrcal_cnt_reg[0]_59\ => u_ddr_mc_phy_wrapper_n_515,
      \po_stg2_wrcal_cnt_reg[0]_6\ => u_ddr_mc_phy_wrapper_n_462,
      \po_stg2_wrcal_cnt_reg[0]_60\ => u_ddr_mc_phy_wrapper_n_516,
      \po_stg2_wrcal_cnt_reg[0]_61\ => u_ddr_mc_phy_wrapper_n_517,
      \po_stg2_wrcal_cnt_reg[0]_62\ => u_ddr_mc_phy_wrapper_n_518,
      \po_stg2_wrcal_cnt_reg[0]_7\ => u_ddr_mc_phy_wrapper_n_463,
      \po_stg2_wrcal_cnt_reg[0]_8\ => u_ddr_mc_phy_wrapper_n_464,
      \po_stg2_wrcal_cnt_reg[0]_9\ => u_ddr_mc_phy_wrapper_n_465,
      \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\,
      \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]_0\,
      \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_1\,
      \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\,
      \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]_0\,
      \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_1\,
      \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\,
      \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]_0\,
      \rd_ptr_reg[2]_1\ => \rd_ptr_reg[2]_1\,
      \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\,
      \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]_0\,
      \rd_ptr_reg[3]_1\ => \rd_ptr_reg[3]_1\,
      \rd_ptr_reg[3]_2\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(3 downto 0),
      \rd_ptr_reg[3]_3\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(3 downto 0),
      \rd_ptr_reg[3]_4\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\(3 downto 0),
      \rd_ptr_reg[3]_5\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(7 downto 0),
      \rd_ptr_reg[3]_6\(4 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(4 downto 0),
      \rd_ptr_reg[3]_7\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(0),
      \rd_ptr_reg[3]_8\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\(3 downto 0),
      \rd_ptr_reg[3]_9\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\(0),
      \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0),
      \rd_ptr_timing_reg[2]\ => \rd_ptr_timing_reg[2]\,
      \read_fifo.tail_r_reg[4]\(0) => \read_fifo.tail_r_reg[4]\(0),
      ref_dll_lock => ref_dll_lock,
      rst_out_reg(0) => rst_out_reg(0),
      \slave_ts.oserdes_slave_ts\ => u_ddr_calib_top_n_81,
      \slave_ts.oserdes_slave_ts_0\ => u_ddr_calib_top_n_80,
      \slave_ts.oserdes_slave_ts_1\ => u_ddr_calib_top_n_82,
      \slave_ts.oserdes_slave_ts_2\ => u_ddr_calib_top_n_89,
      \slave_ts.oserdes_slave_ts_3\ => u_ddr_calib_top_n_88,
      \slave_ts.oserdes_slave_ts_4\ => u_ddr_calib_top_n_90,
      sync_pulse => sync_pulse,
      wr_en => wr_en,
      wr_en_2 => wr_en_2,
      wr_en_3 => wr_en_3,
      wr_en_4 => wr_en_4,
      \wr_ptr_reg[0]\ => \wr_ptr_reg[0]\,
      \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]_0\,
      \wr_ptr_reg[1]\ => \wr_ptr_reg[1]\,
      \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]_0\,
      \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0),
      \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0),
      \wr_ptr_reg[3]_1\(3 downto 0) => \wr_ptr_reg[3]_1\(3 downto 0),
      \wr_ptr_timing_reg[0]\ => \^init_calib_complete_reg_rep__9\,
      \wr_ptr_timing_reg[0]_0\ => u_ddr_calib_top_n_72,
      \wr_ptr_timing_reg[0]_1\ => u_ddr_calib_top_n_70,
      \wr_ptr_timing_reg[0]_2\(0) => u_ddr_calib_top_n_245,
      \wr_ptr_timing_reg[0]_3\(0) => u_ddr_calib_top_n_247
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_mem_intfc is
  port (
    periodic_rd_ack_r : out STD_LOGIC;
    accept_ns : out STD_LOGIC;
    bm_end_r1 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    bm_end_r1_2 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : out STD_LOGIC;
    bm_end_r1_4 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : out STD_LOGIC;
    periodic_rd_r : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg : out STD_LOGIC;
    \rd_ptr_reg[0]\ : out STD_LOGIC;
    \rd_ptr_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[2]\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC;
    \rd_ptr_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    \rd_ptr_reg[2]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC;
    \rd_ptr_reg[0]_1\ : out STD_LOGIC;
    \rd_ptr_reg[1]_1\ : out STD_LOGIC;
    \rd_ptr_reg[2]_1\ : out STD_LOGIC;
    \rd_ptr_reg[3]_1\ : out STD_LOGIC;
    ref_dll_lock : out STD_LOGIC;
    ddr2_cas_n : out STD_LOGIC;
    ddr2_ras_n : out STD_LOGIC;
    ddr2_we_n : out STD_LOGIC;
    ddr2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
    ddr2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
    periodic_rd_cntr_r : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    new_cnt_cpt_r_reg : out STD_LOGIC;
    rdlvl_stg1_start_reg : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    pi_cnt_dec_reg : out STD_LOGIC;
    prbs_rdlvl_done_pulse_reg : out STD_LOGIC;
    phy_dout : out STD_LOGIC_VECTOR ( 46 downto 0 );
    \init_calib_complete_reg_rep__0\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : out STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : out STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[117]\ : out STD_LOGIC_VECTOR ( 59 downto 0 );
    init_calib_complete_reg_rep : out STD_LOGIC_VECTOR ( 59 downto 0 );
    req_bank_r : out STD_LOGIC_VECTOR ( 11 downto 0 );
    idle_r_lcl_reg : out STD_LOGIC;
    idle_r_lcl_reg_0 : out STD_LOGIC;
    idle_r_lcl_reg_1 : out STD_LOGIC;
    idle_r_lcl_reg_2 : out STD_LOGIC;
    \req_row_r_lcl_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    app_rd_data_valid : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 65 downto 0 );
    app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 );
    \pointer_ram.pointer_we\ : out STD_LOGIC;
    app_rd_data_end : out STD_LOGIC;
    \cmd_pipe_plus.wr_data_addr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \wr_ptr_reg[0]\ : out STD_LOGIC;
    \wr_ptr_reg[1]\ : out STD_LOGIC;
    \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \wr_ptr_reg[0]_0\ : out STD_LOGIC;
    \wr_ptr_reg[1]_0\ : out STD_LOGIC;
    \wr_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    wr_en : out STD_LOGIC;
    p_1_in : out STD_LOGIC;
    wr_en_2 : out STD_LOGIC;
    wr_en_3 : out STD_LOGIC;
    wr_en_4 : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
    ddr2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    CLK : in STD_LOGIC;
    was_wr0 : in STD_LOGIC;
    maint_ref_zq_wip_r_reg : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    p_145_out : in STD_LOGIC;
    p_106_out : in STD_LOGIC;
    p_67_out : in STD_LOGIC;
    p_28_out : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    CLKB0_5 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST0 : in STD_LOGIC;
    rst_out_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    col_wait_r_reg : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 2 downto 0 );
    row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \complex_address_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \lane_cnt_po_r_reg[0]\ : in STD_LOGIC;
    \samp_edge_cnt1_r_reg[0]\ : in STD_LOGIC;
    rdlvl_stg1_start_reg_0 : in STD_LOGIC;
    init_complete_r_timing_reg : in STD_LOGIC;
    \one_inc_min_limit_reg[2]\ : in STD_LOGIC;
    \init_state_r1_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    wrcal_done_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \inhbt_act_faw.faw_cnt_r_reg[0]\ : in STD_LOGIC;
    \last_master_r_reg[2]\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]\ : in STD_LOGIC;
    mem_out : in STD_LOGIC_VECTOR ( 79 downto 0 );
    \idelay_tap_cnt_r_reg[0][1][4]\ : in STD_LOGIC;
    out_fifo : in STD_LOGIC_VECTOR ( 79 downto 0 );
    out_fifo_0 : in STD_LOGIC_VECTOR ( 79 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 143 downto 0 );
    app_sr_req : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    app_zq_req : in STD_LOGIC;
    ras_timer_zero_r_reg : in STD_LOGIC;
    act_wait_r_lcl_reg : in STD_LOGIC;
    act_wait_r_lcl_reg_0 : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    was_priority_reg : in STD_LOGIC;
    app_en_r2 : in STD_LOGIC;
    row : in STD_LOGIC_VECTOR ( 12 downto 0 );
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    ras_timer_zero_r_reg_2 : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \complex_num_writes_reg[4]\ : in STD_LOGIC;
    ram_init_done_r : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_col_r_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_shift_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \device_temp_101_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
    \app_rd_data[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_mem_intfc : entity is "mig_7series_v4_2_mem_intfc";
end mig_7series_0_mig_7series_v4_2_mem_intfc;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_mem_intfc is
  signal \col_mach0/p_0_in\ : STD_LOGIC;
  signal ddr_phy_top0_n_222 : STD_LOGIC;
  signal ddr_phy_top0_n_506 : STD_LOGIC;
  signal ddr_phy_top0_n_507 : STD_LOGIC;
  signal ddr_phy_top0_n_508 : STD_LOGIC;
  signal ddr_phy_top0_n_509 : STD_LOGIC;
  signal ddr_phy_top0_n_510 : STD_LOGIC;
  signal ddr_phy_top0_n_511 : STD_LOGIC;
  signal ddr_phy_top0_n_94 : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of ddr_phy_top0_n_94 : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of ddr_phy_top0_n_94 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of ddr_phy_top0_n_94 : signal is "10";
  signal ddr_phy_top0_n_98 : STD_LOGIC;
  attribute MAX_FANOUT of ddr_phy_top0_n_98 : signal is "50";
  attribute RTL_MAX_FANOUT of ddr_phy_top0_n_98 : signal is "found";
  attribute syn_maxfan of ddr_phy_top0_n_98 : signal is "10";
  signal ddr_phy_top0_n_99 : STD_LOGIC;
  signal idle : STD_LOGIC;
  signal mc0_n_124 : STD_LOGIC;
  signal mc0_n_125 : STD_LOGIC;
  signal mc0_n_126 : STD_LOGIC;
  signal mc0_n_127 : STD_LOGIC;
  signal mc0_n_128 : STD_LOGIC;
  signal mc0_n_129 : STD_LOGIC;
  signal mc0_n_29 : STD_LOGIC;
  signal mc0_n_30 : STD_LOGIC;
  signal mc0_n_32 : STD_LOGIC;
  signal mc0_n_33 : STD_LOGIC;
  signal mc0_n_34 : STD_LOGIC;
  signal mc_address : STD_LOGIC_VECTOR ( 38 downto 0 );
  signal mc_bank : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal mc_cas_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_cke : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal mc_cmd : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal mc_cs_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal mc_odt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mc_ras_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_we_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_wrdata_en : STD_LOGIC;
  signal \^phy_dout\ : STD_LOGIC_VECTOR ( 46 downto 0 );
  signal phy_mc_cmd_full : STD_LOGIC;
  signal phy_mc_ctl_full : STD_LOGIC;
  signal phy_mc_data_full : STD_LOGIC;
  signal \rank_mach0/rank_common0/app_zq_ns\ : STD_LOGIC;
  signal \read_fifo.tail_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal tempmon_sample_en : STD_LOGIC;
begin
  phy_dout(46 downto 0) <= \^phy_dout\(46 downto 0);
ddr_phy_top0: entity work.mig_7series_0_mig_7series_v4_2_ddr_phy_top
     port map (
      A_rst_primitives_reg => A_rst_primitives_reg,
      A_rst_primitives_reg_0 => A_rst_primitives_reg_0,
      CLK => CLK,
      CLKB0 => CLKB0,
      CLKB0_5 => CLKB0_5,
      Q(143 downto 0) => Q(143 downto 0),
      RST0 => RST0,
      SR(0) => SR(0),
      SS(0) => SS(0),
      app_rd_data(127 downto 0) => app_rd_data(127 downto 0),
      \app_rd_data[117]\(63 downto 0) => \app_rd_data[117]\(63 downto 0),
      app_rd_data_valid => app_rd_data_valid,
      app_rd_data_valid_0(0) => \col_mach0/p_0_in\,
      app_zq_ns => \rank_mach0/rank_common0/app_zq_ns\,
      app_zq_req => app_zq_req,
      \cnt_shift_r_reg[0]\(0) => \cnt_shift_r_reg[0]\(0),
      \complex_address_reg[9]\(1 downto 0) => \complex_address_reg[9]\(1 downto 0),
      \complex_num_writes_reg[4]\ => \complex_num_writes_reg[4]\,
      ddr2_addr(12 downto 0) => ddr2_addr(12 downto 0),
      ddr2_ba(2 downto 0) => ddr2_ba(2 downto 0),
      ddr2_cas_n => ddr2_cas_n,
      ddr2_cke(0) => ddr2_cke(0),
      ddr2_cs_n(0) => ddr2_cs_n(0),
      ddr2_dm(1 downto 0) => ddr2_dm(1 downto 0),
      ddr2_dq(15 downto 0) => ddr2_dq(15 downto 0),
      ddr2_dqs_n(1 downto 0) => ddr2_dqs_n(1 downto 0),
      ddr2_dqs_p(1 downto 0) => ddr2_dqs_p(1 downto 0),
      ddr2_odt(0) => ddr2_odt(0),
      ddr2_ras_n => ddr2_ras_n,
      ddr2_we_n => ddr2_we_n,
      \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(36 downto 11) => mc_address(38 downto 13),
      \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\(10 downto 0) => mc_address(10 downto 0),
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      delay_done_reg => \wtr_timer.wtr_cnt_r_reg[0]\,
      \device_temp_101_reg[11]\(11 downto 0) => \device_temp_101_reg[11]\(11 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0),
      freq_refclk => freq_refclk,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0) => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0),
      \idelay_tap_cnt_r_reg[0][1][4]\ => \idelay_tap_cnt_r_reg[0][1][4]\,
      idle => idle,
      init_calib_complete_reg_rep => ddr_phy_top0_n_94,
      init_calib_complete_reg_rep_0(59 downto 0) => init_calib_complete_reg_rep(59 downto 0),
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__9\ => ddr_phy_top0_n_98,
      init_complete_r1_timing_reg => ddr_phy_top0_n_99,
      init_complete_r_timing_reg => init_complete_r_timing_reg,
      \init_state_r1_reg[0]\(0) => \init_state_r1_reg[0]\(0),
      \lane_cnt_po_r_reg[0]\ => \lane_cnt_po_r_reg[0]\,
      \mcGo_r_reg[0]\ => col_wait_r_reg,
      mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0),
      mc_cmd(1 downto 0) => mc_cmd(1 downto 0),
      mc_cs_n(0) => mc_cs_n(1),
      mc_odt(0) => mc_odt(0),
      mc_ras_n(2 downto 0) => mc_ras_n(2 downto 0),
      mc_wrdata_en => mc_wrdata_en,
      mem_out(79 downto 0) => mem_out(79 downto 0),
      mem_refclk => mem_refclk,
      mem_reg_0_15_60_65(1) => mc_cke(3),
      mem_reg_0_15_60_65(0) => mc_cke(0),
      \my_empty_reg[0]\ => ddr_phy_top0_n_222,
      \my_full_reg[0]\ => \inhbt_act_faw.faw_cnt_r_reg[0]\,
      new_cnt_cpt_r_reg => new_cnt_cpt_r_reg,
      \one_inc_min_limit_reg[2]\ => \one_inc_min_limit_reg[2]\,
      \out\(1 downto 0) => \out\(1 downto 0),
      out_fifo(79 downto 0) => out_fifo(79 downto 0),
      out_fifo_0(79 downto 0) => out_fifo_0(79 downto 0),
      out_fifo_1(2 downto 0) => mc_we_n(2 downto 0),
      out_fifo_2(8 downto 0) => mc_bank(8 downto 0),
      \out_fifo_i_69__1\(5) => mc0_n_29,
      \out_fifo_i_69__1\(4) => mc0_n_30,
      \out_fifo_i_69__1\(3) => \^phy_dout\(18),
      \out_fifo_i_69__1\(2) => mc0_n_32,
      \out_fifo_i_69__1\(1) => mc0_n_33,
      \out_fifo_i_69__1\(0) => mc0_n_34,
      p_1_in => p_1_in,
      \phy_ctl_wd_i1_reg[17]\ => mc0_n_129,
      \phy_ctl_wd_i1_reg[19]\(1) => mc0_n_124,
      \phy_ctl_wd_i1_reg[19]\(0) => mc0_n_125,
      \phy_ctl_wd_i1_reg[20]\ => mc0_n_128,
      \phy_ctl_wd_i1_reg[21]\ => mc0_n_127,
      \phy_ctl_wd_i1_reg[22]\ => mc0_n_126,
      phy_dout(44 downto 17) => \^phy_dout\(46 downto 19),
      phy_dout(16 downto 0) => \^phy_dout\(16 downto 0),
      phy_mc_cmd_full => phy_mc_cmd_full,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      pi_cnt_dec_reg => pi_cnt_dec_reg,
      pll_locked => pll_locked,
      prbs_rdlvl_done_pulse_reg => prbs_rdlvl_done_pulse_reg,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5) => ddr_phy_top0_n_506,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(4) => ddr_phy_top0_n_507,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3) => ddr_phy_top0_n_508,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(2) => ddr_phy_top0_n_509,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(1) => ddr_phy_top0_n_510,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(0) => ddr_phy_top0_n_511,
      \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\,
      \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]_0\,
      \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_1\,
      \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\,
      \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]_0\,
      \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_1\,
      \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\,
      \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]_0\,
      \rd_ptr_reg[2]_1\ => \rd_ptr_reg[2]_1\,
      \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\,
      \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]_0\,
      \rd_ptr_reg[3]_1\ => \rd_ptr_reg[3]_1\,
      \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0),
      \rd_ptr_timing_reg[2]\ => maint_ref_zq_wip_r_reg,
      rdlvl_stg1_start_reg => rdlvl_stg1_start_reg,
      rdlvl_stg1_start_reg_0 => rdlvl_stg1_start_reg_0,
      \read_fifo.tail_r_reg[4]\(0) => \read_fifo.tail_r\(0),
      ref_dll_lock => ref_dll_lock,
      rst_out_reg(0) => rst_out_reg(0),
      samp_edge_cnt0_en_r => samp_edge_cnt0_en_r,
      \samp_edge_cnt1_r_reg[0]\ => \samp_edge_cnt1_r_reg[0]\,
      sync_pulse => sync_pulse,
      \tap_cnt_cpt_r_reg[5]\(0) => \tap_cnt_cpt_r_reg[5]\(0),
      tempmon_sample_en => tempmon_sample_en,
      wr_en => wr_en,
      wr_en_2 => wr_en_2,
      wr_en_3 => wr_en_3,
      wr_en_4 => wr_en_4,
      \wr_ptr_reg[0]\ => \wr_ptr_reg[0]\,
      \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]_0\,
      \wr_ptr_reg[1]\ => \wr_ptr_reg[1]\,
      \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]_0\,
      \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0),
      \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0),
      \wr_ptr_reg[3]_1\(3 downto 0) => \wr_ptr_reg[3]_1\(3 downto 0),
      wrcal_done_reg(0) => wrcal_done_reg(0),
      \write_buffer.wr_buf_out_data_reg[117]\(59 downto 0) => \write_buffer.wr_buf_out_data_reg[117]\(59 downto 0)
    );
mc0: entity work.mig_7series_0_mig_7series_v4_2_mc
     port map (
      CLK => CLK,
      D(3 downto 0) => D(3 downto 0),
      E(0) => E(0),
      Q(2 downto 0) => mc_we_n(2 downto 0),
      S(2 downto 0) => S(2 downto 0),
      accept_ns => accept_ns,
      act_wait_r_lcl_reg => act_wait_r_lcl_reg,
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg_0,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_1,
      act_wait_r_lcl_reg_2 => act_wait_r_lcl_reg_2,
      app_en_r2 => app_en_r2,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_zq_ack => app_zq_ack,
      app_zq_ns => \rank_mach0/rank_common0/app_zq_ns\,
      bm_end_r1 => bm_end_r1,
      bm_end_r1_0 => bm_end_r1_0,
      bm_end_r1_2 => bm_end_r1_2,
      bm_end_r1_4 => bm_end_r1_4,
      \cmd_pipe_plus.mc_address_reg[38]_0\(36 downto 11) => mc_address(38 downto 13),
      \cmd_pipe_plus.mc_address_reg[38]_0\(10 downto 0) => mc_address(10 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]_0\(8 downto 0) => mc_bank(8 downto 0),
      \cmd_pipe_plus.mc_cas_n_reg[2]_0\(5) => mc0_n_29,
      \cmd_pipe_plus.mc_cas_n_reg[2]_0\(4) => mc0_n_30,
      \cmd_pipe_plus.mc_cas_n_reg[2]_0\(3) => \^phy_dout\(18),
      \cmd_pipe_plus.mc_cas_n_reg[2]_0\(2) => mc0_n_32,
      \cmd_pipe_plus.mc_cas_n_reg[2]_0\(1) => mc0_n_33,
      \cmd_pipe_plus.mc_cas_n_reg[2]_0\(0) => mc0_n_34,
      \cmd_pipe_plus.mc_cke_reg[3]_0\(1) => mc_cke(3),
      \cmd_pipe_plus.mc_cke_reg[3]_0\(0) => mc_cke(0),
      \cmd_pipe_plus.mc_data_offset_reg[0]_0\ => mc0_n_129,
      \cmd_pipe_plus.mc_data_offset_reg[2]_0\(1) => mc0_n_124,
      \cmd_pipe_plus.mc_data_offset_reg[2]_0\(0) => mc0_n_125,
      \cmd_pipe_plus.mc_data_offset_reg[3]_0\ => mc0_n_128,
      \cmd_pipe_plus.mc_data_offset_reg[4]_0\ => mc0_n_127,
      \cmd_pipe_plus.mc_data_offset_reg[5]_0\ => mc0_n_126,
      \cmd_pipe_plus.mc_data_offset_reg[5]_1\(5) => ddr_phy_top0_n_506,
      \cmd_pipe_plus.mc_data_offset_reg[5]_1\(4) => ddr_phy_top0_n_507,
      \cmd_pipe_plus.mc_data_offset_reg[5]_1\(3) => ddr_phy_top0_n_508,
      \cmd_pipe_plus.mc_data_offset_reg[5]_1\(2) => ddr_phy_top0_n_509,
      \cmd_pipe_plus.mc_data_offset_reg[5]_1\(1) => ddr_phy_top0_n_510,
      \cmd_pipe_plus.mc_data_offset_reg[5]_1\(0) => ddr_phy_top0_n_511,
      \cmd_pipe_plus.wr_data_addr_reg[3]_0\(3 downto 0) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      col_wait_r_reg => col_wait_r_reg,
      \grant_r_reg[0]\ => ddr_phy_top0_n_98,
      idle => idle,
      idle_r_lcl_reg => idle_r_lcl_reg,
      idle_r_lcl_reg_0 => idle_r_lcl_reg_0,
      idle_r_lcl_reg_1 => idle_r_lcl_reg_1,
      idle_r_lcl_reg_2 => idle_r_lcl_reg_2,
      \inhbt_act_faw.faw_cnt_r_reg[0]\ => \inhbt_act_faw.faw_cnt_r_reg[0]\,
      \last_master_r_reg[2]\ => \last_master_r_reg[2]\,
      maint_ref_zq_wip_r_reg => maint_ref_zq_wip_r_reg,
      mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0),
      mc_cmd(1 downto 0) => mc_cmd(1 downto 0),
      mc_cs_n(0) => mc_cs_n(1),
      mc_odt(0) => mc_odt(0),
      mc_ras_n(2 downto 0) => mc_ras_n(2 downto 0),
      mc_wrdata_en => mc_wrdata_en,
      mem_reg_0_15_54_59 => ddr_phy_top0_n_94,
      p_106_out => p_106_out,
      p_145_out => p_145_out,
      p_28_out => p_28_out,
      p_67_out => p_67_out,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_lcl_reg,
      pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_lcl_reg_0,
      pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg_1,
      pass_open_bank_r_lcl_reg_2 => pass_open_bank_r_lcl_reg_2,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r,
      periodic_rd_cntr_r_reg => periodic_rd_cntr_r,
      \periodic_read_request.periodic_rd_r_lcl_reg\ => periodic_rd_r,
      phy_dout(0) => \^phy_dout\(17),
      phy_mc_cmd_full => phy_mc_cmd_full,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      \pointer_ram.pointer_we\ => \pointer_ram.pointer_we\,
      ram_init_done_r => ram_init_done_r,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_0,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_1,
      ras_timer_zero_r_reg_2 => ras_timer_zero_r_reg_2,
      rd_wr_r_lcl_reg => rd_wr_r_lcl_reg,
      \read_fifo.fifo_out_data_r_reg[7]\(1) => app_rd_data_end,
      \read_fifo.fifo_out_data_r_reg[7]\(0) => \col_mach0/p_0_in\,
      \read_fifo.tail_r_reg[0]\(0) => \read_fifo.tail_r\(0),
      \read_fifo.tail_r_reg[0]_0\ => ddr_phy_top0_n_99,
      \read_fifo.tail_r_reg[4]\ => ddr_phy_top0_n_222,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => req_bank_r(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => req_bank_r(11 downto 9),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => req_bank_r(8 downto 6),
      \req_bank_r_lcl_reg[2]_2\(2 downto 0) => req_bank_r(5 downto 3),
      \req_bank_r_lcl_reg[2]_3\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_col_r_reg[9]\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_row_r_lcl_reg[12]\(12 downto 0) => \req_row_r_lcl_reg[12]\(12 downto 0),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      row(12 downto 0) => row(12 downto 0),
      row_hit_r_reg(0) => row_hit_r_reg(0),
      row_hit_r_reg_0(0) => row_hit_r_reg_0(0),
      row_hit_r_reg_1(0) => row_hit_r_reg_1(0),
      row_hit_r_reg_2(0) => row_hit_r_reg_2(0),
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      tempmon_sample_en => tempmon_sample_en,
      was_priority_reg => was_priority_reg,
      was_wr0 => was_wr0,
      \wtr_timer.wtr_cnt_r_reg[0]\ => \wtr_timer.wtr_cnt_r_reg[0]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v4_2_memc_ui_top_std is
  port (
    bm_end_r1 : out STD_LOGIC;
    pass_open_bank_r : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    pass_open_bank_r_1 : out STD_LOGIC;
    bm_end_r1_2 : out STD_LOGIC;
    pass_open_bank_r_3 : out STD_LOGIC;
    bm_end_r1_4 : out STD_LOGIC;
    pass_open_bank_r_5 : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg : out STD_LOGIC;
    \rd_ptr_reg[0]\ : out STD_LOGIC;
    \rd_ptr_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[2]\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC;
    \rd_ptr_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    \rd_ptr_reg[2]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg_0 : out STD_LOGIC;
    \rd_ptr_reg[0]_1\ : out STD_LOGIC;
    \rd_ptr_reg[1]_1\ : out STD_LOGIC;
    \rd_ptr_reg[2]_1\ : out STD_LOGIC;
    \rd_ptr_reg[3]_1\ : out STD_LOGIC;
    ref_dll_lock : out STD_LOGIC;
    ddr2_cas_n : out STD_LOGIC;
    ddr2_ras_n : out STD_LOGIC;
    ddr2_we_n : out STD_LOGIC;
    ddr2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
    ddr2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
    app_sr_active : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    app_wdf_rdy : out STD_LOGIC;
    new_cnt_cpt_r_reg : out STD_LOGIC;
    rdlvl_stg1_start_reg : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    pi_cnt_dec : out STD_LOGIC;
    prbs_rdlvl_done_pulse : out STD_LOGIC;
    phy_dout : out STD_LOGIC_VECTOR ( 46 downto 0 );
    \write_buffer.wr_buf_out_data_reg[117]\ : out STD_LOGIC_VECTOR ( 71 downto 0 );
    init_calib_complete_reg_rep : out STD_LOGIC_VECTOR ( 71 downto 0 );
    app_rd_data_valid : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 65 downto 0 );
    app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 );
    app_rd_data_end : out STD_LOGIC;
    \wr_ptr_reg[0]\ : out STD_LOGIC;
    \wr_ptr_reg[1]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \wr_ptr_reg[0]_0\ : out STD_LOGIC;
    \wr_ptr_reg[1]_0\ : out STD_LOGIC;
    \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    wr_en : out STD_LOGIC;
    p_1_in : out STD_LOGIC;
    wr_en_2 : out STD_LOGIC;
    wr_en_3 : out STD_LOGIC;
    wr_en_4 : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
    ddr2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    CLK : in STD_LOGIC;
    maint_ref_zq_wip_r_reg : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    CLKB0_5 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST0 : in STD_LOGIC;
    rst_out_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    col_wait_r_reg : in STD_LOGIC;
    reset_reg_0 : in STD_LOGIC;
    \complex_address_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \lane_cnt_po_r_reg[0]\ : in STD_LOGIC;
    \samp_edge_cnt1_r_reg[0]\ : in STD_LOGIC;
    rdlvl_stg1_start_reg_0 : in STD_LOGIC;
    init_complete_r_timing_reg : in STD_LOGIC;
    \one_inc_min_limit_reg[2]\ : in STD_LOGIC;
    \init_state_r1_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    wrcal_done_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \last_master_r_reg[2]\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]\ : in STD_LOGIC;
    mem_out : in STD_LOGIC_VECTOR ( 79 downto 0 );
    \idelay_tap_cnt_r_reg[0][1][4]\ : in STD_LOGIC;
    out_fifo : in STD_LOGIC_VECTOR ( 79 downto 0 );
    out_fifo_0 : in STD_LOGIC_VECTOR ( 79 downto 0 );
    app_sr_req : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    app_zq_req : in STD_LOGIC;
    ras_timer_zero_r_reg : in STD_LOGIC;
    act_wait_r_lcl_reg : in STD_LOGIC;
    act_wait_r_lcl_reg_0 : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    \rtp_timer_r_reg[0]\ : in STD_LOGIC;
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    ras_timer_zero_r_reg_2 : in STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \complex_num_writes_reg[4]\ : in STD_LOGIC;
    app_addr : in STD_LOGIC_VECTOR ( 25 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    app_wdf_data : in STD_LOGIC_VECTOR ( 127 downto 0 );
    app_wdf_mask : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_shift_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 11 downto 0 );
    \app_rd_data[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    app_en : in STD_LOGIC;
    app_wdf_wren : in STD_LOGIC;
    app_wdf_end : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v4_2_memc_ui_top_std : entity is "mig_7series_v4_2_memc_ui_top_std";
end mig_7series_0_mig_7series_v4_2_memc_ui_top_std;

architecture STRUCTURE of mig_7series_0_mig_7series_v4_2_memc_ui_top_std is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal accept_ns : STD_LOGIC;
  signal bank : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal col : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal data_buf_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \mc0/bank_mach0/bank_cntrl[1].bank0/bank_compare0/req_wr_r_lcl0\ : STD_LOGIC;
  signal \mc0/bank_mach0/bank_common0/periodic_rd_cntr_r\ : STD_LOGIC;
  signal \mc0/bank_mach0/bank_common0/was_wr0\ : STD_LOGIC;
  signal \mc0/bank_mach0/p_106_out\ : STD_LOGIC;
  signal \mc0/bank_mach0/p_145_out\ : STD_LOGIC;
  signal \mc0/bank_mach0/p_28_out\ : STD_LOGIC;
  signal \mc0/bank_mach0/p_67_out\ : STD_LOGIC;
  signal \mc0/bank_mach0/req_bank_r\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \mc0/bank_mach0/req_row_r\ : STD_LOGIC_VECTOR ( 51 downto 0 );
  signal \mc0/periodic_rd_ack_r\ : STD_LOGIC;
  signal \mc0/periodic_rd_r\ : STD_LOGIC;
  signal mem_intfc0_n_111 : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of mem_intfc0_n_111 : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of mem_intfc0_n_111 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of mem_intfc0_n_111 : signal is "10";
  signal mem_intfc0_n_112 : STD_LOGIC;
  attribute MAX_FANOUT of mem_intfc0_n_112 : signal is "50";
  attribute RTL_MAX_FANOUT of mem_intfc0_n_112 : signal is "found";
  attribute syn_maxfan of mem_intfc0_n_112 : signal is "10";
  signal mem_intfc0_n_113 : STD_LOGIC;
  attribute MAX_FANOUT of mem_intfc0_n_113 : signal is "50";
  attribute RTL_MAX_FANOUT of mem_intfc0_n_113 : signal is "found";
  attribute syn_maxfan of mem_intfc0_n_113 : signal is "10";
  signal mem_intfc0_n_246 : STD_LOGIC;
  signal mem_intfc0_n_247 : STD_LOGIC;
  signal mem_intfc0_n_248 : STD_LOGIC;
  signal mem_intfc0_n_249 : STD_LOGIC;
  signal ram_init_done_r : STD_LOGIC;
  signal reset_reg_n_0 : STD_LOGIC;
  signal row : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal u_ui_top_n_12 : STD_LOGIC;
  signal u_ui_top_n_14 : STD_LOGIC;
  signal u_ui_top_n_15 : STD_LOGIC;
  signal u_ui_top_n_16 : STD_LOGIC;
  signal u_ui_top_n_4 : STD_LOGIC;
  signal u_ui_top_n_5 : STD_LOGIC;
  signal u_ui_top_n_6 : STD_LOGIC;
  signal u_ui_top_n_7 : STD_LOGIC;
  signal \ui_cmd0/app_en_r2\ : STD_LOGIC;
  signal \ui_wr_data0/pointer_ram.pointer_we\ : STD_LOGIC;
  signal wr_data : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal wr_data_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_data_en : STD_LOGIC;
  signal wr_data_mask : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute syn_maxfan of reset_reg : label is "10";
begin
  E(0) <= \^e\(0);
mem_intfc0: entity work.mig_7series_0_mig_7series_v4_2_mem_intfc
     port map (
      A_rst_primitives_reg => A_rst_primitives_reg,
      A_rst_primitives_reg_0 => A_rst_primitives_reg_0,
      CLK => CLK,
      CLKB0 => CLKB0,
      CLKB0_5 => CLKB0_5,
      D(3 downto 0) => data_buf_addr(3 downto 0),
      E(0) => wr_data_en,
      Q(143 downto 128) => wr_data_mask(15 downto 0),
      Q(127 downto 0) => wr_data(127 downto 0),
      RST0 => RST0,
      S(2) => u_ui_top_n_14,
      S(1) => u_ui_top_n_15,
      S(0) => u_ui_top_n_16,
      SR(0) => SR(0),
      SS(0) => SS(0),
      accept_ns => accept_ns,
      act_wait_r_lcl_reg => act_wait_r_lcl_reg,
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg_0,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_1,
      act_wait_r_lcl_reg_2 => act_wait_r_lcl_reg_2,
      app_en_r2 => \ui_cmd0/app_en_r2\,
      app_rd_data(127 downto 0) => app_rd_data(127 downto 0),
      \app_rd_data[117]\(63 downto 0) => \app_rd_data[117]\(63 downto 0),
      app_rd_data_end => app_rd_data_end,
      app_rd_data_valid => app_rd_data_valid,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_zq_ack => app_zq_ack,
      app_zq_req => app_zq_req,
      bm_end_r1 => bm_end_r1,
      bm_end_r1_0 => bm_end_r1_0,
      bm_end_r1_2 => bm_end_r1_2,
      bm_end_r1_4 => bm_end_r1_4,
      \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0) => wr_data_addr(3 downto 0),
      \cnt_shift_r_reg[0]\(0) => \cnt_shift_r_reg[0]\(0),
      col_wait_r_reg => col_wait_r_reg,
      \complex_address_reg[9]\(1 downto 0) => \complex_address_reg[9]\(1 downto 0),
      \complex_num_writes_reg[4]\ => \complex_num_writes_reg[4]\,
      ddr2_addr(12 downto 0) => ddr2_addr(12 downto 0),
      ddr2_ba(2 downto 0) => ddr2_ba(2 downto 0),
      ddr2_cas_n => ddr2_cas_n,
      ddr2_cke(0) => ddr2_cke(0),
      ddr2_cs_n(0) => ddr2_cs_n(0),
      ddr2_dm(1 downto 0) => ddr2_dm(1 downto 0),
      ddr2_dq(15 downto 0) => ddr2_dq(15 downto 0),
      ddr2_dqs_n(1 downto 0) => ddr2_dqs_n(1 downto 0),
      ddr2_dqs_p(1 downto 0) => ddr2_dqs_p(1 downto 0),
      ddr2_odt(0) => ddr2_odt(0),
      ddr2_ras_n => ddr2_ras_n,
      ddr2_we_n => ddr2_we_n,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \device_temp_101_reg[11]\(11 downto 0) => D(11 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0),
      freq_refclk => freq_refclk,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0) => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0),
      \idelay_tap_cnt_r_reg[0][1][4]\ => \idelay_tap_cnt_r_reg[0][1][4]\,
      idle_r_lcl_reg => mem_intfc0_n_246,
      idle_r_lcl_reg_0 => mem_intfc0_n_247,
      idle_r_lcl_reg_1 => mem_intfc0_n_248,
      idle_r_lcl_reg_2 => mem_intfc0_n_249,
      \inhbt_act_faw.faw_cnt_r_reg[0]\ => reset_reg_0,
      init_calib_complete_reg_rep(59 downto 49) => init_calib_complete_reg_rep(71 downto 61),
      init_calib_complete_reg_rep(48 downto 44) => init_calib_complete_reg_rep(58 downto 54),
      init_calib_complete_reg_rep(43 downto 40) => init_calib_complete_reg_rep(52 downto 49),
      init_calib_complete_reg_rep(39 downto 35) => init_calib_complete_reg_rep(47 downto 43),
      init_calib_complete_reg_rep(34 downto 30) => init_calib_complete_reg_rep(41 downto 37),
      init_calib_complete_reg_rep(29 downto 20) => init_calib_complete_reg_rep(34 downto 25),
      init_calib_complete_reg_rep(19 downto 18) => init_calib_complete_reg_rep(23 downto 22),
      init_calib_complete_reg_rep(17 downto 14) => init_calib_complete_reg_rep(20 downto 17),
      init_calib_complete_reg_rep(13 downto 7) => init_calib_complete_reg_rep(15 downto 9),
      init_calib_complete_reg_rep(6 downto 2) => init_calib_complete_reg_rep(7 downto 3),
      init_calib_complete_reg_rep(1 downto 0) => init_calib_complete_reg_rep(1 downto 0),
      \init_calib_complete_reg_rep__0\ => mem_intfc0_n_111,
      \init_calib_complete_reg_rep__1\ => mem_intfc0_n_112,
      \init_calib_complete_reg_rep__2\ => mem_intfc0_n_113,
      init_complete_r_timing_reg => init_complete_r_timing_reg,
      \init_state_r1_reg[0]\(0) => \init_state_r1_reg[0]\(0),
      \lane_cnt_po_r_reg[0]\ => \lane_cnt_po_r_reg[0]\,
      \last_master_r_reg[2]\ => \last_master_r_reg[2]\,
      maint_ref_zq_wip_r_reg => maint_ref_zq_wip_r_reg,
      mem_out(79 downto 0) => mem_out(79 downto 0),
      mem_refclk => mem_refclk,
      new_cnt_cpt_r_reg => new_cnt_cpt_r_reg,
      \one_inc_min_limit_reg[2]\ => \one_inc_min_limit_reg[2]\,
      \out\(1 downto 0) => \out\(1 downto 0),
      out_fifo(79 downto 0) => out_fifo(79 downto 0),
      out_fifo_0(79 downto 0) => out_fifo_0(79 downto 0),
      p_106_out => \mc0/bank_mach0/p_106_out\,
      p_145_out => \mc0/bank_mach0/p_145_out\,
      p_1_in => p_1_in,
      p_28_out => \mc0/bank_mach0/p_28_out\,
      p_67_out => \mc0/bank_mach0/p_67_out\,
      pass_open_bank_r_lcl_reg => pass_open_bank_r,
      pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_1,
      pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_3,
      pass_open_bank_r_lcl_reg_2 => pass_open_bank_r_5,
      periodic_rd_ack_r => \mc0/periodic_rd_ack_r\,
      periodic_rd_cntr_r => \mc0/bank_mach0/bank_common0/periodic_rd_cntr_r\,
      periodic_rd_r => \mc0/periodic_rd_r\,
      phy_dout(46 downto 0) => phy_dout(46 downto 0),
      pi_cnt_dec_reg => pi_cnt_dec,
      pll_locked => pll_locked,
      \pointer_ram.pointer_we\ => \ui_wr_data0/pointer_ram.pointer_we\,
      prbs_rdlvl_done_pulse_reg => prbs_rdlvl_done_pulse,
      ram_init_done_r => ram_init_done_r,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_0,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_1,
      ras_timer_zero_r_reg_2 => ras_timer_zero_r_reg_2,
      \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\,
      \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]_0\,
      \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_1\,
      \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\,
      \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]_0\,
      \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_1\,
      \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\,
      \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]_0\,
      \rd_ptr_reg[2]_1\ => \rd_ptr_reg[2]_1\,
      \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\,
      \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]_0\,
      \rd_ptr_reg[3]_1\ => \rd_ptr_reg[3]_1\,
      \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0),
      rd_wr_r_lcl_reg => u_ui_top_n_12,
      rdlvl_stg1_start_reg => rdlvl_stg1_start_reg,
      rdlvl_stg1_start_reg_0 => rdlvl_stg1_start_reg_0,
      ref_dll_lock => ref_dll_lock,
      req_bank_r(11 downto 0) => \mc0/bank_mach0/req_bank_r\(11 downto 0),
      \req_bank_r_lcl_reg[2]\(2 downto 0) => bank(2 downto 0),
      \req_col_r_reg[9]\(9 downto 0) => col(9 downto 0),
      \req_row_r_lcl_reg[12]\(12) => \mc0/bank_mach0/req_row_r\(51),
      \req_row_r_lcl_reg[12]\(11) => \mc0/bank_mach0/req_row_r\(38),
      \req_row_r_lcl_reg[12]\(10) => \mc0/bank_mach0/req_row_r\(25),
      \req_row_r_lcl_reg[12]\(9) => \mc0/bank_mach0/req_row_r\(12),
      \req_row_r_lcl_reg[12]\(8 downto 0) => \mc0/bank_mach0/req_row_r\(8 downto 0),
      req_wr_r_lcl0 => \mc0/bank_mach0/bank_cntrl[1].bank0/bank_compare0/req_wr_r_lcl0\,
      row(12 downto 0) => row(12 downto 0),
      row_hit_r_reg(0) => u_ui_top_n_6,
      row_hit_r_reg_0(0) => u_ui_top_n_7,
      row_hit_r_reg_1(0) => u_ui_top_n_5,
      row_hit_r_reg_2(0) => u_ui_top_n_4,
      rst_out_reg(0) => rst_out_reg(0),
      \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\,
      samp_edge_cnt0_en_r => samp_edge_cnt0_en_r,
      \samp_edge_cnt1_r_reg[0]\ => \samp_edge_cnt1_r_reg[0]\,
      sync_pulse => sync_pulse,
      \tap_cnt_cpt_r_reg[5]\(0) => \tap_cnt_cpt_r_reg[5]\(0),
      was_priority_reg => \^e\(0),
      was_wr0 => \mc0/bank_mach0/bank_common0/was_wr0\,
      wr_en => wr_en,
      wr_en_2 => wr_en_2,
      wr_en_3 => wr_en_3,
      wr_en_4 => wr_en_4,
      \wr_ptr_reg[0]\ => \wr_ptr_reg[0]\,
      \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]_0\,
      \wr_ptr_reg[1]\ => \wr_ptr_reg[1]\,
      \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]_0\,
      \wr_ptr_reg[3]\(3 downto 0) => Q(3 downto 0),
      \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0),
      \wr_ptr_reg[3]_1\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0),
      wrcal_done_reg(0) => wrcal_done_reg(0),
      \write_buffer.wr_buf_out_data_reg[117]\(59 downto 55) => \write_buffer.wr_buf_out_data_reg[117]\(71 downto 67),
      \write_buffer.wr_buf_out_data_reg[117]\(54 downto 51) => \write_buffer.wr_buf_out_data_reg[117]\(65 downto 62),
      \write_buffer.wr_buf_out_data_reg[117]\(50 downto 47) => \write_buffer.wr_buf_out_data_reg[117]\(60 downto 57),
      \write_buffer.wr_buf_out_data_reg[117]\(46 downto 40) => \write_buffer.wr_buf_out_data_reg[117]\(55 downto 49),
      \write_buffer.wr_buf_out_data_reg[117]\(39 downto 35) => \write_buffer.wr_buf_out_data_reg[117]\(47 downto 43),
      \write_buffer.wr_buf_out_data_reg[117]\(34 downto 31) => \write_buffer.wr_buf_out_data_reg[117]\(41 downto 38),
      \write_buffer.wr_buf_out_data_reg[117]\(30 downto 27) => \write_buffer.wr_buf_out_data_reg[117]\(36 downto 33),
      \write_buffer.wr_buf_out_data_reg[117]\(26 downto 24) => \write_buffer.wr_buf_out_data_reg[117]\(31 downto 29),
      \write_buffer.wr_buf_out_data_reg[117]\(23 downto 14) => \write_buffer.wr_buf_out_data_reg[117]\(26 downto 17),
      \write_buffer.wr_buf_out_data_reg[117]\(13 downto 3) => \write_buffer.wr_buf_out_data_reg[117]\(15 downto 5),
      \write_buffer.wr_buf_out_data_reg[117]\(2 downto 0) => \write_buffer.wr_buf_out_data_reg[117]\(2 downto 0),
      \wtr_timer.wtr_cnt_r_reg[0]\ => \wtr_timer.wtr_cnt_r_reg[0]\
    );
reset_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => reset_reg_0,
      Q => reset_reg_n_0,
      R => '0'
    );
u_ui_top: entity work.mig_7series_0_mig_7series_v4_2_ui_top
     port map (
      CLK => CLK,
      D(3 downto 0) => data_buf_addr(3 downto 0),
      E(0) => wr_data_en,
      Q(143 downto 128) => wr_data_mask(15 downto 0),
      Q(127 downto 0) => wr_data(127 downto 0),
      S(2) => u_ui_top_n_14,
      S(1) => u_ui_top_n_15,
      S(0) => u_ui_top_n_16,
      accept_ns => accept_ns,
      app_addr(25 downto 0) => app_addr(25 downto 0),
      \app_addr_r1_reg[25]\(2 downto 0) => bank(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => col(9 downto 0),
      \app_addr_r2_reg[22]\(0) => u_ui_top_n_4,
      \app_addr_r2_reg[22]_0\(0) => u_ui_top_n_5,
      \app_addr_r2_reg[22]_1\(0) => u_ui_top_n_6,
      \app_addr_r2_reg[22]_2\(0) => u_ui_top_n_7,
      app_cmd(1 downto 0) => app_cmd(1 downto 0),
      \app_cmd_r2_reg[0]\ => u_ui_top_n_12,
      app_en => app_en,
      app_en_r2 => \ui_cmd0/app_en_r2\,
      app_rdy_r_reg => \^e\(0),
      app_wdf_data(127 downto 0) => app_wdf_data(127 downto 0),
      app_wdf_end => app_wdf_end,
      app_wdf_mask(15 downto 0) => app_wdf_mask(15 downto 0),
      app_wdf_rdy => app_wdf_rdy,
      app_wdf_wren => app_wdf_wren,
      \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ => mem_intfc0_n_113,
      \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ => mem_intfc0_n_111,
      \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ => mem_intfc0_n_112,
      p_106_out => \mc0/bank_mach0/p_106_out\,
      p_145_out => \mc0/bank_mach0/p_145_out\,
      p_28_out => \mc0/bank_mach0/p_28_out\,
      p_67_out => \mc0/bank_mach0/p_67_out\,
      periodic_rd_ack_r => \mc0/periodic_rd_ack_r\,
      periodic_rd_cntr_r => \mc0/bank_mach0/bank_common0/periodic_rd_cntr_r\,
      periodic_rd_r => \mc0/periodic_rd_r\,
      \pointer_ram.pointer_we\ => \ui_wr_data0/pointer_ram.pointer_we\,
      ram_init_done_r => ram_init_done_r,
      rb_hit_busy_r_reg => mem_intfc0_n_249,
      rb_hit_busy_r_reg_0 => mem_intfc0_n_246,
      rb_hit_busy_r_reg_1 => mem_intfc0_n_247,
      rb_hit_busy_r_reg_2 => mem_intfc0_n_248,
      req_bank_r(11 downto 0) => \mc0/bank_mach0/req_bank_r\(11 downto 0),
      req_wr_r_lcl0 => \mc0/bank_mach0/bank_cntrl[1].bank0/bank_compare0/req_wr_r_lcl0\,
      row(12 downto 0) => row(12 downto 0),
      row_hit_r_reg(12) => \mc0/bank_mach0/req_row_r\(51),
      row_hit_r_reg(11) => \mc0/bank_mach0/req_row_r\(38),
      row_hit_r_reg(10) => \mc0/bank_mach0/req_row_r\(25),
      row_hit_r_reg(9) => \mc0/bank_mach0/req_row_r\(12),
      row_hit_r_reg(8 downto 0) => \mc0/bank_mach0/req_row_r\(8 downto 0),
      was_wr0 => \mc0/bank_mach0/bank_common0/was_wr0\,
      \wr_req_counter.wr_req_cnt_r_reg[0]\ => reset_reg_n_0,
      \write_buffer.wr_buf_out_data_reg[37]\(11) => \write_buffer.wr_buf_out_data_reg[117]\(66),
      \write_buffer.wr_buf_out_data_reg[37]\(10) => \write_buffer.wr_buf_out_data_reg[117]\(61),
      \write_buffer.wr_buf_out_data_reg[37]\(9) => \write_buffer.wr_buf_out_data_reg[117]\(56),
      \write_buffer.wr_buf_out_data_reg[37]\(8) => \write_buffer.wr_buf_out_data_reg[117]\(48),
      \write_buffer.wr_buf_out_data_reg[37]\(7) => \write_buffer.wr_buf_out_data_reg[117]\(42),
      \write_buffer.wr_buf_out_data_reg[37]\(6) => \write_buffer.wr_buf_out_data_reg[117]\(37),
      \write_buffer.wr_buf_out_data_reg[37]\(5) => \write_buffer.wr_buf_out_data_reg[117]\(32),
      \write_buffer.wr_buf_out_data_reg[37]\(4 downto 3) => \write_buffer.wr_buf_out_data_reg[117]\(28 downto 27),
      \write_buffer.wr_buf_out_data_reg[37]\(2) => \write_buffer.wr_buf_out_data_reg[117]\(16),
      \write_buffer.wr_buf_out_data_reg[37]\(1 downto 0) => \write_buffer.wr_buf_out_data_reg[117]\(4 downto 3),
      \write_buffer.wr_buf_out_data_reg[5]\(3 downto 0) => wr_data_addr(3 downto 0),
      \write_buffer.wr_buf_out_data_reg[78]\(11 downto 10) => init_calib_complete_reg_rep(60 downto 59),
      \write_buffer.wr_buf_out_data_reg[78]\(9) => init_calib_complete_reg_rep(53),
      \write_buffer.wr_buf_out_data_reg[78]\(8) => init_calib_complete_reg_rep(48),
      \write_buffer.wr_buf_out_data_reg[78]\(7) => init_calib_complete_reg_rep(42),
      \write_buffer.wr_buf_out_data_reg[78]\(6 downto 5) => init_calib_complete_reg_rep(36 downto 35),
      \write_buffer.wr_buf_out_data_reg[78]\(4) => init_calib_complete_reg_rep(24),
      \write_buffer.wr_buf_out_data_reg[78]\(3) => init_calib_complete_reg_rep(21),
      \write_buffer.wr_buf_out_data_reg[78]\(2) => init_calib_complete_reg_rep(16),
      \write_buffer.wr_buf_out_data_reg[78]\(1) => init_calib_complete_reg_rep(8),
      \write_buffer.wr_buf_out_data_reg[78]\(0) => init_calib_complete_reg_rep(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_0_mig is
  port (
    \gen_mmcm.mmcm_i\ : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    iserdes_clk : out STD_LOGIC;
    \rd_ptr_reg[0]\ : out STD_LOGIC;
    \rd_ptr_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[2]\ : out STD_LOGIC;
    \rd_ptr_reg[3]\ : out STD_LOGIC;
    rd_ptr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    iserdes_clk_0 : out STD_LOGIC;
    \rd_ptr_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    \rd_ptr_reg[2]_0\ : out STD_LOGIC;
    \rd_ptr_reg[3]_0\ : out STD_LOGIC;
    ddr2_cas_n : out STD_LOGIC;
    ddr2_ras_n : out STD_LOGIC;
    ddr2_we_n : out STD_LOGIC;
    ddr2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
    ddr2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
    app_sr_active : out STD_LOGIC;
    app_rdy_r_reg : out STD_LOGIC;
    app_wdf_rdy : out STD_LOGIC;
    ui_clk_sync_rst : out STD_LOGIC;
    phy_dout : out STD_LOGIC_VECTOR ( 46 downto 0 );
    \write_buffer.wr_buf_out_data_reg[117]\ : out STD_LOGIC_VECTOR ( 71 downto 0 );
    init_calib_complete_reg_rep : out STD_LOGIC_VECTOR ( 71 downto 0 );
    app_rd_data_end : out STD_LOGIC;
    wr_ptr : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    wr_ptr_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 65 downto 0 );
    app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 );
    wr_en : out STD_LOGIC;
    p_1_in : out STD_LOGIC;
    wr_en_2 : out STD_LOGIC;
    wr_en_3 : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    wr_en_4 : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
    ddr2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    CLKB0 : in STD_LOGIC;
    CLKB0_5 : in STD_LOGIC;
    device_temp_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
    sys_rst : in STD_LOGIC;
    mem_out : in STD_LOGIC_VECTOR ( 79 downto 0 );
    out_fifo : in STD_LOGIC_VECTOR ( 79 downto 0 );
    out_fifo_0 : in STD_LOGIC_VECTOR ( 79 downto 0 );
    app_addr : in STD_LOGIC_VECTOR ( 25 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    app_wdf_data : in STD_LOGIC_VECTOR ( 127 downto 0 );
    app_wdf_mask : in STD_LOGIC_VECTOR ( 15 downto 0 );
    sys_clk_i : in STD_LOGIC;
    \app_rd_data[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    app_en : in STD_LOGIC;
    app_wdf_wren : in STD_LOGIC;
    app_wdf_end : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    app_zq_req : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_0_mig : entity is "mig_7series_0_mig";
end mig_7series_0_mig_7series_0_mig;

architecture STRUCTURE of mig_7series_0_mig_7series_0_mig is
  signal device_temp_sync_r4_neq_r3 : STD_LOGIC;
  signal freq_refclk : STD_LOGIC;
  signal \^gen_mmcm.mmcm_i\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/RST0\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/pass_open_bank_r\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/pass_open_bank_r\ : STD_LOGIC;
  signal mem_refclk : STD_LOGIC;
  signal pll_locked : STD_LOGIC;
  signal ref_dll_lock : STD_LOGIC;
  signal rst_tmp : STD_LOGIC;
  signal rstdiv0_sync_r1 : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rstdiv0_sync_r1 : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rstdiv0_sync_r1 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rstdiv0_sync_r1 : signal is "50";
  signal sync_pulse : STD_LOGIC;
  signal sys_rst_act_hi : STD_LOGIC;
  signal u_ddr2_clk_ibuf_n_0 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_0 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_10 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_10 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_10 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_10 : signal is "50";
  signal u_ddr2_infrastructure_n_11 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_11 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_11 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_11 : signal is "50";
  signal u_ddr2_infrastructure_n_12 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_12 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_12 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_12 : signal is "50";
  signal u_ddr2_infrastructure_n_13 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_13 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_13 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_13 : signal is "50";
  signal u_ddr2_infrastructure_n_14 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_14 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_14 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_14 : signal is "50";
  signal u_ddr2_infrastructure_n_15 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_15 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_15 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_15 : signal is "50";
  signal u_ddr2_infrastructure_n_16 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_16 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_16 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_16 : signal is "50";
  signal u_ddr2_infrastructure_n_17 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_17 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_17 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_17 : signal is "50";
  signal u_ddr2_infrastructure_n_18 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_18 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_18 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_18 : signal is "50";
  signal u_ddr2_infrastructure_n_19 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_19 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_19 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_19 : signal is "50";
  signal u_ddr2_infrastructure_n_20 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_20 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_20 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_20 : signal is "50";
  signal u_ddr2_infrastructure_n_21 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_21 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_21 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_21 : signal is "50";
  signal u_ddr2_infrastructure_n_22 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_22 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_22 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_22 : signal is "50";
  signal u_ddr2_infrastructure_n_24 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_26 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_27 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_28 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_29 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_30 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_31 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_32 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_33 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_36 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_37 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_38 : STD_LOGIC;
  signal u_ddr2_infrastructure_n_7 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_7 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_7 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_7 : signal is "50";
  signal u_ddr2_infrastructure_n_8 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_8 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_8 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_8 : signal is "50";
  signal u_ddr2_infrastructure_n_9 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr2_infrastructure_n_9 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr2_infrastructure_n_9 : signal is "found";
  attribute syn_maxfan of u_ddr2_infrastructure_n_9 : signal is "50";
  signal u_memc_ui_top_std_n_56 : STD_LOGIC;
  signal u_memc_ui_top_std_n_57 : STD_LOGIC;
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of u_memc_ui_top_std : label is "mig_7series_v4_2_ddr2_7Series, mig_7series_0, 2018.3";
begin
  \gen_mmcm.mmcm_i\ <= \^gen_mmcm.mmcm_i\;
\temp_mon_enabled.u_tempmon\: entity work.mig_7series_0_mig_7series_v4_2_tempmon
     port map (
      D(11 downto 0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100\(11 downto 0),
      SR(0) => u_ddr2_infrastructure_n_24,
      device_temp_i(11 downto 0) => device_temp_i(11 downto 0),
      device_temp_sync_r4_neq_r3 => device_temp_sync_r4_neq_r3,
      \device_temp_sync_r5_reg[11]_0\ => \^gen_mmcm.mmcm_i\
    );
u_ddr2_clk_ibuf: entity work.mig_7series_0_mig_7series_v4_2_clk_ibuf
     port map (
      mmcm_clk => u_ddr2_clk_ibuf_n_0,
      sys_clk_i => sys_clk_i
    );
u_ddr2_infrastructure: entity work.mig_7series_0_mig_7series_v4_2_infrastructure
     port map (
      AS(0) => sys_rst_act_hi,
      CLK => \^gen_mmcm.mmcm_i\,
      RST0 => \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/RST0\,
      SR(0) => rstdiv0_sync_r1,
      SS(0) => u_ddr2_infrastructure_n_37,
      bm_end_r1 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_0 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_2 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_4 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1\,
      \cnt_shift_r_reg[0]\ => u_memc_ui_top_std_n_57,
      device_temp_sync_r4_neq_r3 => device_temp_sync_r4_neq_r3,
      freq_refclk => freq_refclk,
      \gen_mmcm.mmcm_i_i_1_0\ => u_ddr2_infrastructure_n_0,
      mem_refclk => mem_refclk,
      mmcm_clk => u_ddr2_clk_ibuf_n_0,
      pass_open_bank_r => \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r\,
      pass_open_bank_r_1 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r\,
      pass_open_bank_r_3 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/pass_open_bank_r\,
      pass_open_bank_r_5 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/pass_open_bank_r\,
      pi_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec\,
      pll_locked => pll_locked,
      prbs_rdlvl_done_pulse => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse\,
      rst_tmp => rst_tmp,
      rstdiv0_sync_r1_reg_rep_0 => u_ddr2_infrastructure_n_7,
      \rstdiv0_sync_r1_reg_rep__0_0\ => u_ddr2_infrastructure_n_8,
      \rstdiv0_sync_r1_reg_rep__10_0\ => u_ddr2_infrastructure_n_18,
      \rstdiv0_sync_r1_reg_rep__11_0\ => u_ddr2_infrastructure_n_19,
      \rstdiv0_sync_r1_reg_rep__11_1\ => u_ddr2_infrastructure_n_26,
      \rstdiv0_sync_r1_reg_rep__11_2\ => u_ddr2_infrastructure_n_27,
      \rstdiv0_sync_r1_reg_rep__11_3\ => u_ddr2_infrastructure_n_28,
      \rstdiv0_sync_r1_reg_rep__11_4\ => u_ddr2_infrastructure_n_29,
      \rstdiv0_sync_r1_reg_rep__11_5\ => u_ddr2_infrastructure_n_30,
      \rstdiv0_sync_r1_reg_rep__11_6\ => u_ddr2_infrastructure_n_31,
      \rstdiv0_sync_r1_reg_rep__12_0\ => u_ddr2_infrastructure_n_20,
      \rstdiv0_sync_r1_reg_rep__12_1\ => u_ddr2_infrastructure_n_32,
      \rstdiv0_sync_r1_reg_rep__12_2\ => u_ddr2_infrastructure_n_33,
      \rstdiv0_sync_r1_reg_rep__13_0\ => u_ddr2_infrastructure_n_21,
      \rstdiv0_sync_r1_reg_rep__13_1\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0\,
      \rstdiv0_sync_r1_reg_rep__13_2\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0\,
      \rstdiv0_sync_r1_reg_rep__13_3\ => u_ddr2_infrastructure_n_36,
      \rstdiv0_sync_r1_reg_rep__14_0\ => u_ddr2_infrastructure_n_22,
      \rstdiv0_sync_r1_reg_rep__14_1\(0) => u_ddr2_infrastructure_n_24,
      \rstdiv0_sync_r1_reg_rep__14_2\ => u_ddr2_infrastructure_n_38,
      \rstdiv0_sync_r1_reg_rep__1_0\(0) => u_ddr2_infrastructure_n_9,
      \rstdiv0_sync_r1_reg_rep__2_0\ => u_ddr2_infrastructure_n_10,
      \rstdiv0_sync_r1_reg_rep__4_0\(1) => u_ddr2_infrastructure_n_11,
      \rstdiv0_sync_r1_reg_rep__4_0\(0) => u_ddr2_infrastructure_n_12,
      \rstdiv0_sync_r1_reg_rep__5_0\ => u_ddr2_infrastructure_n_13,
      \rstdiv0_sync_r1_reg_rep__6_0\(0) => u_ddr2_infrastructure_n_14,
      \rstdiv0_sync_r1_reg_rep__7_0\(0) => u_ddr2_infrastructure_n_15,
      \rstdiv0_sync_r1_reg_rep__8_0\ => u_ddr2_infrastructure_n_16,
      \rstdiv0_sync_r1_reg_rep__9_0\ => u_ddr2_infrastructure_n_17,
      samp_edge_cnt0_en_r => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r\,
      sync_pulse => sync_pulse,
      \tap_cnt_cpt_r_reg[5]\ => u_memc_ui_top_std_n_56,
      ui_clk_sync_rst => ui_clk_sync_rst
    );
u_iodelay_ctrl: entity work.mig_7series_0_mig_7series_v4_2_iodelay_ctrl
     port map (
      AS(0) => sys_rst_act_hi,
      mmcm_clk => u_ddr2_clk_ibuf_n_0,
      ref_dll_lock => ref_dll_lock,
      rst_tmp => rst_tmp,
      \rstdiv2_sync_r_reg[11]\ => u_ddr2_infrastructure_n_0,
      sys_rst => sys_rst
    );
u_memc_ui_top_std: entity work.mig_7series_0_mig_7series_v4_2_memc_ui_top_std
     port map (
      A_rst_primitives_reg => iserdes_clk,
      A_rst_primitives_reg_0 => iserdes_clk_0,
      CLK => \^gen_mmcm.mmcm_i\,
      CLKB0 => CLKB0,
      CLKB0_5 => CLKB0_5,
      D(11 downto 0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100\(11 downto 0),
      E(0) => app_rdy_r_reg,
      Q(3 downto 0) => Q(3 downto 0),
      RST0 => \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/RST0\,
      SR(0) => rstdiv0_sync_r1,
      SS(0) => u_ddr2_infrastructure_n_37,
      act_wait_r_lcl_reg => u_ddr2_infrastructure_n_33,
      act_wait_r_lcl_reg_0 => u_ddr2_infrastructure_n_29,
      act_wait_r_lcl_reg_1 => u_ddr2_infrastructure_n_31,
      act_wait_r_lcl_reg_2 => u_ddr2_infrastructure_n_27,
      app_addr(25 downto 0) => app_addr(25 downto 0),
      app_cmd(1 downto 0) => app_cmd(1 downto 0),
      app_en => app_en,
      app_rd_data(127 downto 0) => app_rd_data(127 downto 0),
      \app_rd_data[117]\(63 downto 0) => \app_rd_data[117]\(63 downto 0),
      app_rd_data_end => app_rd_data_end,
      app_rd_data_valid => app_rd_data_valid,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_wdf_data(127 downto 0) => app_wdf_data(127 downto 0),
      app_wdf_end => app_wdf_end,
      app_wdf_mask(15 downto 0) => app_wdf_mask(15 downto 0),
      app_wdf_rdy => app_wdf_rdy,
      app_wdf_wren => app_wdf_wren,
      app_zq_ack => app_zq_ack,
      app_zq_req => app_zq_req,
      bm_end_r1 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_0 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_2 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_4 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1\,
      \cnt_shift_r_reg[0]\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0\,
      col_wait_r_reg => u_ddr2_infrastructure_n_17,
      \complex_address_reg[9]\(1) => u_ddr2_infrastructure_n_11,
      \complex_address_reg[9]\(0) => u_ddr2_infrastructure_n_12,
      \complex_num_writes_reg[4]\ => u_ddr2_infrastructure_n_38,
      ddr2_addr(12 downto 0) => ddr2_addr(12 downto 0),
      ddr2_ba(2 downto 0) => ddr2_ba(2 downto 0),
      ddr2_cas_n => ddr2_cas_n,
      ddr2_cke(0) => ddr2_cke(0),
      ddr2_cs_n(0) => ddr2_cs_n(0),
      ddr2_dm(1 downto 0) => ddr2_dm(1 downto 0),
      ddr2_dq(15 downto 0) => ddr2_dq(15 downto 0),
      ddr2_dqs_n(1 downto 0) => ddr2_dqs_n(1 downto 0),
      ddr2_dqs_p(1 downto 0) => ddr2_dqs_p(1 downto 0),
      ddr2_odt(0) => ddr2_odt(0),
      ddr2_ras_n => ddr2_ras_n,
      ddr2_we_n => ddr2_we_n,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 0),
      freq_refclk => freq_refclk,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0) => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 0),
      \idelay_tap_cnt_r_reg[0][1][4]\ => u_ddr2_infrastructure_n_21,
      init_calib_complete_reg_rep(71 downto 0) => init_calib_complete_reg_rep(71 downto 0),
      init_complete_r_timing_reg => u_ddr2_infrastructure_n_8,
      \init_state_r1_reg[0]\(0) => u_ddr2_infrastructure_n_9,
      \lane_cnt_po_r_reg[0]\ => u_ddr2_infrastructure_n_13,
      \last_master_r_reg[2]\ => u_ddr2_infrastructure_n_18,
      maint_ref_zq_wip_r_reg => u_ddr2_infrastructure_n_16,
      mem_out(79 downto 0) => mem_out(79 downto 0),
      mem_refclk => mem_refclk,
      new_cnt_cpt_r_reg => u_memc_ui_top_std_n_56,
      \one_inc_min_limit_reg[2]\ => u_ddr2_infrastructure_n_7,
      \out\(1 downto 0) => \out\(1 downto 0),
      out_fifo(79 downto 0) => out_fifo(79 downto 0),
      out_fifo_0(79 downto 0) => out_fifo_0(79 downto 0),
      p_1_in => p_1_in,
      pass_open_bank_r => \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r\,
      pass_open_bank_r_1 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r\,
      pass_open_bank_r_3 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/pass_open_bank_r\,
      pass_open_bank_r_5 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/pass_open_bank_r\,
      phy_dout(46 downto 0) => phy_dout(46 downto 0),
      pi_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec\,
      pll_locked => pll_locked,
      prbs_rdlvl_done_pulse => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse\,
      ras_timer_zero_r_reg => u_ddr2_infrastructure_n_26,
      ras_timer_zero_r_reg_0 => u_ddr2_infrastructure_n_28,
      ras_timer_zero_r_reg_1 => u_ddr2_infrastructure_n_30,
      ras_timer_zero_r_reg_2 => u_ddr2_infrastructure_n_32,
      \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\,
      \rd_ptr_reg[0]_0\ => rd_ptr(0),
      \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_0\,
      \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\,
      \rd_ptr_reg[1]_0\ => rd_ptr(1),
      \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_0\,
      \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\,
      \rd_ptr_reg[2]_0\ => rd_ptr(2),
      \rd_ptr_reg[2]_1\ => \rd_ptr_reg[2]_0\,
      \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\,
      \rd_ptr_reg[3]_0\ => rd_ptr(3),
      \rd_ptr_reg[3]_1\ => \rd_ptr_reg[3]_0\,
      \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0),
      rdlvl_stg1_start_reg => u_memc_ui_top_std_n_57,
      rdlvl_stg1_start_reg_0 => u_ddr2_infrastructure_n_10,
      ref_dll_lock => ref_dll_lock,
      reset_reg_0 => u_ddr2_infrastructure_n_22,
      rst_out_reg(0) => u_ddr2_infrastructure_n_15,
      \rtp_timer_r_reg[0]\ => u_ddr2_infrastructure_n_19,
      samp_edge_cnt0_en_r => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r\,
      \samp_edge_cnt1_r_reg[0]\ => u_ddr2_infrastructure_n_36,
      sync_pulse => sync_pulse,
      \tap_cnt_cpt_r_reg[5]\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0\,
      wr_en => wr_en,
      wr_en_2 => wr_en_2,
      wr_en_3 => wr_en_3,
      wr_en_4 => wr_en_4,
      \wr_ptr_reg[0]\ => wr_ptr(0),
      \wr_ptr_reg[0]_0\ => wr_ptr_1(0),
      \wr_ptr_reg[1]\ => wr_ptr(1),
      \wr_ptr_reg[1]_0\ => wr_ptr_1(1),
      \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0),
      \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0),
      wrcal_done_reg(0) => u_ddr2_infrastructure_n_14,
      \write_buffer.wr_buf_out_data_reg[117]\(71 downto 0) => \write_buffer.wr_buf_out_data_reg[117]\(71 downto 0),
      \wtr_timer.wtr_cnt_r_reg[0]\ => u_ddr2_infrastructure_n_20
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0 is
  port (
    ddr2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
    ddr2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
    ddr2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr2_ras_n : out STD_LOGIC;
    ddr2_cas_n : out STD_LOGIC;
    ddr2_we_n : out STD_LOGIC;
    ddr2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    sys_clk_i : in STD_LOGIC;
    app_addr : in STD_LOGIC_VECTOR ( 26 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 2 downto 0 );
    app_en : in STD_LOGIC;
    app_wdf_data : in STD_LOGIC_VECTOR ( 127 downto 0 );
    app_wdf_end : in STD_LOGIC;
    app_wdf_mask : in STD_LOGIC_VECTOR ( 15 downto 0 );
    app_wdf_wren : in STD_LOGIC;
    app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 );
    app_rd_data_end : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    app_rdy : out STD_LOGIC;
    app_wdf_rdy : out STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    app_zq_req : in STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    ui_clk : out STD_LOGIC;
    ui_clk_sync_rst : out STD_LOGIC;
    init_calib_complete : out STD_LOGIC;
    device_temp_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
    sys_rst : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of mig_7series_0 : entity is true;
end mig_7series_0;

architecture STRUCTURE of mig_7series_0 is
  signal \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1\ : STD_LOGIC;
  signal \^init_calib_complete\ : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of init_calib_complete : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of init_calib_complete : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of init_calib_complete : signal is "10";
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\ : STD_LOGIC_VECTOR ( 38 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_ras_n\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\ : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : STD_LOGIC;
  attribute MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : signal is "40";
  attribute RTL_MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : signal is "found";
  attribute syn_maxfan of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : signal is "10";
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\ : STD_LOGIC_VECTOR ( 79 downto 8 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : STD_LOGIC;
  attribute MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : signal is "50";
  attribute RTL_MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : signal is "found";
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\ : STD_LOGIC_VECTOR ( 79 downto 6 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\ : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : STD_LOGIC;
  attribute MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : signal is "50";
  attribute RTL_MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : signal is "found";
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : STD_LOGIC;
  attribute MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : signal is "40";
  attribute RTL_MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : signal is "found";
  attribute syn_maxfan of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : signal is "10";
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\ : STD_LOGIC_VECTOR ( 71 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : STD_LOGIC;
  attribute MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : signal is "50";
  attribute RTL_MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : signal is "found";
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\ : STD_LOGIC_VECTOR ( 71 downto 0 );
  signal u_mig_7series_0_mig_n_152 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_153 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_154 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_155 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_156 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_157 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_158 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_159 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_168 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_169 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_17 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_170 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_171 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_172 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_173 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_174 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_175 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_18 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_19 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_20 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_49 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_53 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_57 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_6 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_61 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_65 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_69 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_7 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_73 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_77 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_78 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_8 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_84 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_88 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_9 : STD_LOGIC;
  signal u_mig_7series_0_mig_n_92 : STD_LOGIC;
  signal \^ui_clk\ : STD_LOGIC;
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 320;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 12;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 17;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is 24;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is 29;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 30;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 36;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 41;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 42;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 47;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 48;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 53;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 54;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 59;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 60;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 65;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 66;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 71;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 6;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 11;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 72;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 77;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 78;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 79;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 5;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 12;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 17;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 18;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 23;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 24;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 29;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 30;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 36;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 41;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 42;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 47;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 48;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 53;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 54;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 59;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 60;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 65;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 66;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 71;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 6;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 11;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 72;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 77;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is "ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 78;
  attribute ram_slice_end of \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 79;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 5;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 12;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 17;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 18;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 23;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 24;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 29;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 30;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 36;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 41;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 42;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 47;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 48;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 53;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 54;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 59;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 60;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 65;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 66;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 71;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 6;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 11;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 72;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 77;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 78;
  attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 79;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is 0;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is 5;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 12;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 17;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 18;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 23;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 30;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 36;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 41;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 42;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 47;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 48;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 53;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 54;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 59;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 60;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 65;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 66;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 71;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 320;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 3;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 6;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 11;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 5;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 12;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 17;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 18;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 23;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 24;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 29;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 30;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 36;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 41;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 42;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 47;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 48;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 53;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 54;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 59;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 60;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 65;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 66;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 71;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 6;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 11;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 72;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 77;
  attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is "";
  attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 720;
  attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem";
  attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 0;
  attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 8;
  attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 0;
  attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 78;
  attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 79;
begin
  init_calib_complete <= \^init_calib_complete\;
  ui_clk <= \^ui_clk\;
\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(13 downto 12),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(15 downto 14),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(13 downto 12),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(15 downto 14),
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(25 downto 24),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(27 downto 26),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(25 downto 24),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(27 downto 26),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(29 downto 28),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(31 downto 30),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(33 downto 32),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(31 downto 30),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(33 downto 32),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(35 downto 34),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(37 downto 36),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(39 downto 38),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(37 downto 36),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(39 downto 38),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(41 downto 40),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(43 downto 42),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(45 downto 44),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(43 downto 42),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(45 downto 44),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(47 downto 46),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(49 downto 48),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(51 downto 50),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(49 downto 48),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(51 downto 50),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(53 downto 52),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(55 downto 54),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(57 downto 56),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(55 downto 54),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(57 downto 56),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(59 downto 58),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(61 downto 60),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(63 downto 62),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(61 downto 60),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(63 downto 62),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(65 downto 64),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(67 downto 66),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(69 downto 68),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(71 downto 70),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(67 downto 66),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(69 downto 68),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(71 downto 70),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(7 downto 6),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(9 downto 8),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_1\,
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(9 downto 8),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(11 downto 10),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(73 downto 72),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(75 downto 74),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(77 downto 76),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(73 downto 72),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(75 downto 74),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(77 downto 76),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(79 downto 78),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(79 downto 78),
      DOB(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOB_UNCONNECTED\(1 downto 0),
      DOC(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOC_UNCONNECTED\(1 downto 0),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(82),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(66),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(114),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(98),
      DIC(1) => u_mig_7series_0_mig_n_158,
      DIC(0) => u_mig_7series_0_mig_n_159,
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => u_mig_7series_0_mig_n_156,
      DIA(0) => u_mig_7series_0_mig_n_157,
      DIB(1) => u_mig_7series_0_mig_n_154,
      DIB(0) => u_mig_7series_0_mig_n_155,
      DIC(1) => u_mig_7series_0_mig_n_152,
      DIC(0) => u_mig_7series_0_mig_n_153,
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(16),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(0),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(48),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(32),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(80),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(64),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(112),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(96),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(22),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(6),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(54),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(38),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(86),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(70),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(118),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(102),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(19),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(3),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(51),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(35),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(83),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(67),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(115),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(99),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(17),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(1),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(49),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(33),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(81),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(65),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(113),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(97),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(20),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(4),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(52),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(36),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(84),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(68),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(116),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(100),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(23),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(7),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(55),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(39),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(87),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(71),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(119),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(103),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(18),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(2),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(50),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(34),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(21),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(5),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(53),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(37),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(85),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(69),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1\,
      DOB(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2\,
      DOB(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3\,
      DOC(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4\,
      DOC(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_9,
      ADDRA(2) => u_mig_7series_0_mig_n_8,
      ADDRA(1) => u_mig_7series_0_mig_n_7,
      ADDRA(0) => u_mig_7series_0_mig_n_6,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_9,
      ADDRB(2) => u_mig_7series_0_mig_n_8,
      ADDRB(1) => u_mig_7series_0_mig_n_7,
      ADDRB(0) => u_mig_7series_0_mig_n_6,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_9,
      ADDRC(2) => u_mig_7series_0_mig_n_8,
      ADDRC(1) => u_mig_7series_0_mig_n_7,
      ADDRC(0) => u_mig_7series_0_mig_n_6,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(117),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(101),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0\,
      DOA(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1\,
      DOB(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED\(1 downto 0),
      DOC(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED\(1 downto 0),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(25),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(12),
      DIB(1) => u_mig_7series_0_mig_n_92,
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(38),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(1 downto 0),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(3 downto 2),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(5 downto 4),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(16),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(3),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(13 downto 12),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(15 downto 14),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(17 downto 16),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => u_mig_7series_0_mig_n_84,
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(29),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(19 downto 18),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(21 downto 20),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(23 downto 22),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(5),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(2),
      DIB(1) => \^init_calib_complete\,
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(8),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(25 downto 24),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(27 downto 26),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(29 downto 28),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1) => u_mig_7series_0_mig_n_78,
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_ras_n\(0),
      DIC(1) => '1',
      DIC(0) => u_mig_7series_0_mig_n_77,
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(31 downto 30),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(33 downto 32),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(35 downto 34),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(13),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(37 downto 36),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(39 downto 38),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(41 downto 40),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => u_mig_7series_0_mig_n_73,
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(26),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(23),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(10),
      DIC(1) => u_mig_7series_0_mig_n_69,
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(36),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(43 downto 42),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(45 downto 44),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(47 downto 46),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(4),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(1),
      DIB(1) => u_mig_7series_0_mig_n_65,
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(7),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(3),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(49 downto 48),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(51 downto 50),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(53 downto 52),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => u_mig_7series_0_mig_n_61,
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(6),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(14),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(1),
      DIC(1) => u_mig_7series_0_mig_n_57,
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(27),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(55 downto 54),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(57 downto 56),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(59 downto 58),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(18),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(5),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(61 downto 60),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(63 downto 62),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(65 downto 64),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => u_mig_7series_0_mig_n_53,
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(31),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(67 downto 66),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(69 downto 68),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(71 downto 70),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(15),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(2),
      DIC(1) => u_mig_7series_0_mig_n_88,
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(7 downto 6),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(9 downto 8),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(11 downto 10),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(22),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(9),
      DIB(1) => u_mig_7series_0_mig_n_49,
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(35),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(73 downto 72),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(75 downto 74),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(77 downto 76),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(79 downto 78),
      DOB(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED\(1 downto 0),
      DOC(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED\(1 downto 0),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(1 downto 0),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(3 downto 2),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(1 downto 0),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(3 downto 2),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(5 downto 4),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(13 downto 12),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(15 downto 14),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(13 downto 12),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(15 downto 14),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(17 downto 16),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(19 downto 18),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(21 downto 20),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(19 downto 18),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(21 downto 20),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(23 downto 22),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(31 downto 30),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(33 downto 32),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_1\,
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(33 downto 32),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(35 downto 34),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(37 downto 36),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(39 downto 38),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(37 downto 36),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(39 downto 38),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(41 downto 40),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(43 downto 42),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(45 downto 44),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(43 downto 42),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(45 downto 44),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(47 downto 46),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(49 downto 48),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(51 downto 50),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(49 downto 48),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(51 downto 50),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(53 downto 52),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(55 downto 54),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(57 downto 56),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(55 downto 54),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(57 downto 56),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(59 downto 58),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(61 downto 60),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(63 downto 62),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(61 downto 60),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(63 downto 62),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(65 downto 64),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(67 downto 66),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(69 downto 68),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(71 downto 70),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(67 downto 66),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(69 downto 68),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(71 downto 70),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(7 downto 6),
      DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(9 downto 8),
      DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(7 downto 6),
      DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(9 downto 8),
      DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(11 downto 10),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(29),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(13),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(61),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(45),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(93),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(77),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(88),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(72),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(120),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(104),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(31),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(15),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(63),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(47),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(95),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(79),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(127),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(111),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(28),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(12),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(60),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(44),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(92),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(76),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(124),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(108),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(26),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(10),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(58),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(42),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(90),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(74),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(122),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(106),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(25),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(9),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(57),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(41),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(89),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(73),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(121),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(105),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(27),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(11),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(59),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(43),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(91),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(75),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(123),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(107),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(30),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(14),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(62),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(46),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(94),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(78),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(126),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(110),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(125),
      DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(109),
      DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(24),
      DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(8),
      DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(56),
      DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(40),
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => u_mig_7series_0_mig_n_174,
      DIA(0) => u_mig_7series_0_mig_n_175,
      DIB(1) => u_mig_7series_0_mig_n_172,
      DIB(0) => u_mig_7series_0_mig_n_173,
      DIC(1) => u_mig_7series_0_mig_n_170,
      DIC(0) => u_mig_7series_0_mig_n_171,
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1\,
      DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2\,
      DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3\,
      DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4\,
      DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5\,
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => u_mig_7series_0_mig_n_20,
      ADDRA(2) => u_mig_7series_0_mig_n_19,
      ADDRA(1) => u_mig_7series_0_mig_n_18,
      ADDRA(0) => u_mig_7series_0_mig_n_17,
      ADDRB(4) => '0',
      ADDRB(3) => u_mig_7series_0_mig_n_20,
      ADDRB(2) => u_mig_7series_0_mig_n_19,
      ADDRB(1) => u_mig_7series_0_mig_n_18,
      ADDRB(0) => u_mig_7series_0_mig_n_17,
      ADDRC(4) => '0',
      ADDRC(3) => u_mig_7series_0_mig_n_20,
      ADDRC(2) => u_mig_7series_0_mig_n_19,
      ADDRC(1) => u_mig_7series_0_mig_n_18,
      ADDRC(0) => u_mig_7series_0_mig_n_17,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      DIA(1) => u_mig_7series_0_mig_n_168,
      DIA(0) => u_mig_7series_0_mig_n_169,
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0\,
      DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1\,
      DOB(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED\(1 downto 0),
      DOC(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED\(1 downto 0),
      DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED\(1 downto 0),
      WCLK => \^ui_clk\,
      WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\
    );
u_mig_7series_0_mig: entity work.mig_7series_0_mig_7series_0_mig
     port map (
      CLKB0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\,
      CLKB0_5 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\,
      Q(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      app_addr(25 downto 0) => app_addr(25 downto 0),
      app_cmd(1 downto 0) => app_cmd(1 downto 0),
      app_en => app_en,
      app_rd_data(127 downto 0) => app_rd_data(127 downto 0),
      \app_rd_data[117]\(63 downto 8) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(79 downto 24),
      \app_rd_data[117]\(7 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(15 downto 8),
      app_rd_data_end => app_rd_data_end,
      app_rd_data_valid => app_rd_data_valid,
      app_rdy_r_reg => app_rdy,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_wdf_data(127 downto 0) => app_wdf_data(127 downto 0),
      app_wdf_end => app_wdf_end,
      app_wdf_mask(15 downto 0) => app_wdf_mask(15 downto 0),
      app_wdf_rdy => app_wdf_rdy,
      app_wdf_wren => app_wdf_wren,
      app_zq_ack => app_zq_ack,
      app_zq_req => app_zq_req,
      ddr2_addr(12 downto 0) => ddr2_addr(12 downto 0),
      ddr2_ba(2 downto 0) => ddr2_ba(2 downto 0),
      ddr2_cas_n => ddr2_cas_n,
      ddr2_cke(0) => ddr2_cke(0),
      ddr2_cs_n(0) => ddr2_cs_n(0),
      ddr2_dm(1 downto 0) => ddr2_dm(1 downto 0),
      ddr2_dq(15 downto 0) => ddr2_dq(15 downto 0),
      ddr2_dqs_n(1 downto 0) => ddr2_dqs_n(1 downto 0),
      ddr2_dqs_p(1 downto 0) => ddr2_dqs_p(1 downto 0),
      ddr2_odt(0) => ddr2_odt(0),
      ddr2_ras_n => ddr2_ras_n,
      ddr2_we_n => ddr2_we_n,
      ddr_ck_out(1) => ddr2_ck_n(0),
      ddr_ck_out(0) => ddr2_ck_p(0),
      device_temp_i(11 downto 0) => device_temp_i(11 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 24) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(71 downto 30),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(23 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(23 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 12) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(79 downto 24),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(11 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r\(17 downto 6),
      \gen_mmcm.mmcm_i\ => \^ui_clk\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(63 downto 24) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(71 downto 32),
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\(23 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(23 downto 0),
      init_calib_complete_reg_rep(71) => u_mig_7series_0_mig_n_168,
      init_calib_complete_reg_rep(70) => u_mig_7series_0_mig_n_169,
      init_calib_complete_reg_rep(69) => u_mig_7series_0_mig_n_170,
      init_calib_complete_reg_rep(68) => u_mig_7series_0_mig_n_171,
      init_calib_complete_reg_rep(67) => u_mig_7series_0_mig_n_172,
      init_calib_complete_reg_rep(66) => u_mig_7series_0_mig_n_173,
      init_calib_complete_reg_rep(65) => u_mig_7series_0_mig_n_174,
      init_calib_complete_reg_rep(64) => u_mig_7series_0_mig_n_175,
      init_calib_complete_reg_rep(63) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(126),
      init_calib_complete_reg_rep(62) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(110),
      init_calib_complete_reg_rep(61) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(94),
      init_calib_complete_reg_rep(60) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(78),
      init_calib_complete_reg_rep(59) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(62),
      init_calib_complete_reg_rep(58) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(46),
      init_calib_complete_reg_rep(57) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(30),
      init_calib_complete_reg_rep(56) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(14),
      init_calib_complete_reg_rep(55) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(123),
      init_calib_complete_reg_rep(54) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(107),
      init_calib_complete_reg_rep(53) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(91),
      init_calib_complete_reg_rep(52) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(75),
      init_calib_complete_reg_rep(51) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(59),
      init_calib_complete_reg_rep(50) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(43),
      init_calib_complete_reg_rep(49) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(27),
      init_calib_complete_reg_rep(48) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(11),
      init_calib_complete_reg_rep(47) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(121),
      init_calib_complete_reg_rep(46) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(105),
      init_calib_complete_reg_rep(45) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(89),
      init_calib_complete_reg_rep(44) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(73),
      init_calib_complete_reg_rep(43) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(57),
      init_calib_complete_reg_rep(42) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(41),
      init_calib_complete_reg_rep(41) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(25),
      init_calib_complete_reg_rep(40) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(9),
      init_calib_complete_reg_rep(39) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(122),
      init_calib_complete_reg_rep(38) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(106),
      init_calib_complete_reg_rep(37) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(90),
      init_calib_complete_reg_rep(36) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(74),
      init_calib_complete_reg_rep(35) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(58),
      init_calib_complete_reg_rep(34) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(42),
      init_calib_complete_reg_rep(33) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(26),
      init_calib_complete_reg_rep(32) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(10),
      init_calib_complete_reg_rep(31) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(124),
      init_calib_complete_reg_rep(30) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(108),
      init_calib_complete_reg_rep(29) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(92),
      init_calib_complete_reg_rep(28) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(76),
      init_calib_complete_reg_rep(27) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(60),
      init_calib_complete_reg_rep(26) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(44),
      init_calib_complete_reg_rep(25) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(28),
      init_calib_complete_reg_rep(24) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(12),
      init_calib_complete_reg_rep(23) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(127),
      init_calib_complete_reg_rep(22) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(111),
      init_calib_complete_reg_rep(21) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(95),
      init_calib_complete_reg_rep(20) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(79),
      init_calib_complete_reg_rep(19) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(63),
      init_calib_complete_reg_rep(18) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(47),
      init_calib_complete_reg_rep(17) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(31),
      init_calib_complete_reg_rep(16) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(15),
      init_calib_complete_reg_rep(15) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(120),
      init_calib_complete_reg_rep(14) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(104),
      init_calib_complete_reg_rep(13) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(88),
      init_calib_complete_reg_rep(12) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(72),
      init_calib_complete_reg_rep(11) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(56),
      init_calib_complete_reg_rep(10) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(40),
      init_calib_complete_reg_rep(9) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(24),
      init_calib_complete_reg_rep(8) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(8),
      init_calib_complete_reg_rep(7) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(125),
      init_calib_complete_reg_rep(6) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(109),
      init_calib_complete_reg_rep(5) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(93),
      init_calib_complete_reg_rep(4) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(77),
      init_calib_complete_reg_rep(3) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(61),
      init_calib_complete_reg_rep(2) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(45),
      init_calib_complete_reg_rep(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(29),
      init_calib_complete_reg_rep(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(13),
      iserdes_clk => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\,
      iserdes_clk_0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\,
      mem_out(79 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(79 downto 0),
      \out\(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      out_fifo(79) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0\,
      out_fifo(78) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1\,
      out_fifo(77) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4\,
      out_fifo(76) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5\,
      out_fifo(75) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2\,
      out_fifo(74) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3\,
      out_fifo(73) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0\,
      out_fifo(72) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1\,
      out_fifo(71) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4\,
      out_fifo(70) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5\,
      out_fifo(69) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2\,
      out_fifo(68) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3\,
      out_fifo(67) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0\,
      out_fifo(66) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1\,
      out_fifo(65) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4\,
      out_fifo(64) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5\,
      out_fifo(63) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2\,
      out_fifo(62) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3\,
      out_fifo(61) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0\,
      out_fifo(60) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1\,
      out_fifo(59) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4\,
      out_fifo(58) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5\,
      out_fifo(57) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2\,
      out_fifo(56) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3\,
      out_fifo(55) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0\,
      out_fifo(54) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1\,
      out_fifo(53) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4\,
      out_fifo(52) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5\,
      out_fifo(51) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2\,
      out_fifo(50) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3\,
      out_fifo(49) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0\,
      out_fifo(48) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1\,
      out_fifo(47) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4\,
      out_fifo(46) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5\,
      out_fifo(45) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2\,
      out_fifo(44) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3\,
      out_fifo(43) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0\,
      out_fifo(42) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1\,
      out_fifo(41) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4\,
      out_fifo(40) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5\,
      out_fifo(39) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2\,
      out_fifo(38) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3\,
      out_fifo(37) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0\,
      out_fifo(36) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1\,
      out_fifo(35) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4\,
      out_fifo(34) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5\,
      out_fifo(33) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2\,
      out_fifo(32) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3\,
      out_fifo(31) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0\,
      out_fifo(30) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1\,
      out_fifo(29) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4\,
      out_fifo(28) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5\,
      out_fifo(27) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2\,
      out_fifo(26) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3\,
      out_fifo(25) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0\,
      out_fifo(24) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1\,
      out_fifo(23) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4\,
      out_fifo(22) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5\,
      out_fifo(21) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2\,
      out_fifo(20) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3\,
      out_fifo(19) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0\,
      out_fifo(18) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1\,
      out_fifo(17) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4\,
      out_fifo(16) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5\,
      out_fifo(15) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2\,
      out_fifo(14) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3\,
      out_fifo(13) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0\,
      out_fifo(12) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1\,
      out_fifo(11) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4\,
      out_fifo(10) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5\,
      out_fifo(9) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2\,
      out_fifo(8) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3\,
      out_fifo(7) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0\,
      out_fifo(6) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1\,
      out_fifo(5) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4\,
      out_fifo(4) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5\,
      out_fifo(3) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2\,
      out_fifo(2) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3\,
      out_fifo(1) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0\,
      out_fifo(0) => \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1\,
      out_fifo_0(79) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0\,
      out_fifo_0(78) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1\,
      out_fifo_0(77) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4\,
      out_fifo_0(76) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5\,
      out_fifo_0(75) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2\,
      out_fifo_0(74) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3\,
      out_fifo_0(73) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0\,
      out_fifo_0(72) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1\,
      out_fifo_0(71) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4\,
      out_fifo_0(70) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5\,
      out_fifo_0(69) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2\,
      out_fifo_0(68) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3\,
      out_fifo_0(67) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0\,
      out_fifo_0(66) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1\,
      out_fifo_0(65) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4\,
      out_fifo_0(64) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5\,
      out_fifo_0(63) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2\,
      out_fifo_0(62) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3\,
      out_fifo_0(61) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0\,
      out_fifo_0(60) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1\,
      out_fifo_0(59) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4\,
      out_fifo_0(58) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5\,
      out_fifo_0(57) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2\,
      out_fifo_0(56) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3\,
      out_fifo_0(55) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0\,
      out_fifo_0(54) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1\,
      out_fifo_0(53) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4\,
      out_fifo_0(52) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5\,
      out_fifo_0(51) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2\,
      out_fifo_0(50) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3\,
      out_fifo_0(49) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0\,
      out_fifo_0(48) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1\,
      out_fifo_0(47) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4\,
      out_fifo_0(46) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5\,
      out_fifo_0(45) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2\,
      out_fifo_0(44) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3\,
      out_fifo_0(43) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0\,
      out_fifo_0(42) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1\,
      out_fifo_0(41) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4\,
      out_fifo_0(40) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5\,
      out_fifo_0(39) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2\,
      out_fifo_0(38) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3\,
      out_fifo_0(37) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0\,
      out_fifo_0(36) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1\,
      out_fifo_0(35) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4\,
      out_fifo_0(34) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5\,
      out_fifo_0(33) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2\,
      out_fifo_0(32) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3\,
      out_fifo_0(31) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0\,
      out_fifo_0(30) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1\,
      out_fifo_0(29) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4\,
      out_fifo_0(28) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5\,
      out_fifo_0(27) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2\,
      out_fifo_0(26) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3\,
      out_fifo_0(25) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0\,
      out_fifo_0(24) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1\,
      out_fifo_0(23) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4\,
      out_fifo_0(22) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5\,
      out_fifo_0(21) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2\,
      out_fifo_0(20) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3\,
      out_fifo_0(19) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0\,
      out_fifo_0(18) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1\,
      out_fifo_0(17) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4\,
      out_fifo_0(16) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5\,
      out_fifo_0(15) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2\,
      out_fifo_0(14) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3\,
      out_fifo_0(13) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0\,
      out_fifo_0(12) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1\,
      out_fifo_0(11) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4\,
      out_fifo_0(10) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5\,
      out_fifo_0(9) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2\,
      out_fifo_0(8) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3\,
      out_fifo_0(7) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0\,
      out_fifo_0(6) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1\,
      out_fifo_0(5) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4\,
      out_fifo_0(4) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5\,
      out_fifo_0(3) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2\,
      out_fifo_0(2) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3\,
      out_fifo_0(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0\,
      out_fifo_0(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1\,
      p_1_in => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\,
      phy_dout(46) => u_mig_7series_0_mig_n_49,
      phy_dout(45) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(35),
      phy_dout(44) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(22),
      phy_dout(43) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(9),
      phy_dout(42) => u_mig_7series_0_mig_n_53,
      phy_dout(41) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(31),
      phy_dout(40) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(18),
      phy_dout(39) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(5),
      phy_dout(38) => u_mig_7series_0_mig_n_57,
      phy_dout(37) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(27),
      phy_dout(36) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(14),
      phy_dout(35) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(1),
      phy_dout(34) => u_mig_7series_0_mig_n_61,
      phy_dout(33) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(6),
      phy_dout(32) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(3),
      phy_dout(31) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(0),
      phy_dout(30) => u_mig_7series_0_mig_n_65,
      phy_dout(29) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(7),
      phy_dout(28) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(4),
      phy_dout(27) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(1),
      phy_dout(26) => u_mig_7series_0_mig_n_69,
      phy_dout(25) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(36),
      phy_dout(24) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(23),
      phy_dout(23) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(10),
      phy_dout(22) => u_mig_7series_0_mig_n_73,
      phy_dout(21) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(26),
      phy_dout(20) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(13),
      phy_dout(19) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(0),
      phy_dout(18) => u_mig_7series_0_mig_n_77,
      phy_dout(17) => u_mig_7series_0_mig_n_78,
      phy_dout(16) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_ras_n\(0),
      phy_dout(15) => \^init_calib_complete\,
      phy_dout(14) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(8),
      phy_dout(13) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(5),
      phy_dout(12) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(2),
      phy_dout(11) => u_mig_7series_0_mig_n_84,
      phy_dout(10) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(29),
      phy_dout(9) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(16),
      phy_dout(8) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(3),
      phy_dout(7) => u_mig_7series_0_mig_n_88,
      phy_dout(6) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(28),
      phy_dout(5) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(15),
      phy_dout(4) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(2),
      phy_dout(3) => u_mig_7series_0_mig_n_92,
      phy_dout(2) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(38),
      phy_dout(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(25),
      phy_dout(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(12),
      rd_ptr(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0),
      \rd_ptr_reg[0]\ => u_mig_7series_0_mig_n_6,
      \rd_ptr_reg[0]_0\ => u_mig_7series_0_mig_n_17,
      \rd_ptr_reg[1]\ => u_mig_7series_0_mig_n_7,
      \rd_ptr_reg[1]_0\ => u_mig_7series_0_mig_n_18,
      \rd_ptr_reg[2]\ => u_mig_7series_0_mig_n_8,
      \rd_ptr_reg[2]_0\ => u_mig_7series_0_mig_n_19,
      \rd_ptr_reg[3]\ => u_mig_7series_0_mig_n_9,
      \rd_ptr_reg[3]_0\ => u_mig_7series_0_mig_n_20,
      \rd_ptr_timing_reg[1]\(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0),
      sys_clk_i => sys_clk_i,
      sys_rst => sys_rst,
      ui_clk_sync_rst => ui_clk_sync_rst,
      wr_en => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\,
      wr_en_2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\,
      wr_en_3 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\,
      wr_en_4 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\,
      wr_ptr(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      wr_ptr_1(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0),
      \wr_ptr_reg[3]\(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      \wr_ptr_reg[3]_0\(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0),
      \write_buffer.wr_buf_out_data_reg[117]\(71) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(117),
      \write_buffer.wr_buf_out_data_reg[117]\(70) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(101),
      \write_buffer.wr_buf_out_data_reg[117]\(69) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(85),
      \write_buffer.wr_buf_out_data_reg[117]\(68) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(69),
      \write_buffer.wr_buf_out_data_reg[117]\(67) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(53),
      \write_buffer.wr_buf_out_data_reg[117]\(66) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(37),
      \write_buffer.wr_buf_out_data_reg[117]\(65) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(21),
      \write_buffer.wr_buf_out_data_reg[117]\(64) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(5),
      \write_buffer.wr_buf_out_data_reg[117]\(63) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(119),
      \write_buffer.wr_buf_out_data_reg[117]\(62) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(103),
      \write_buffer.wr_buf_out_data_reg[117]\(61) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(87),
      \write_buffer.wr_buf_out_data_reg[117]\(60) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(71),
      \write_buffer.wr_buf_out_data_reg[117]\(59) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(55),
      \write_buffer.wr_buf_out_data_reg[117]\(58) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(39),
      \write_buffer.wr_buf_out_data_reg[117]\(57) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(23),
      \write_buffer.wr_buf_out_data_reg[117]\(56) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(7),
      \write_buffer.wr_buf_out_data_reg[117]\(55) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(116),
      \write_buffer.wr_buf_out_data_reg[117]\(54) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(100),
      \write_buffer.wr_buf_out_data_reg[117]\(53) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(84),
      \write_buffer.wr_buf_out_data_reg[117]\(52) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(68),
      \write_buffer.wr_buf_out_data_reg[117]\(51) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(52),
      \write_buffer.wr_buf_out_data_reg[117]\(50) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(36),
      \write_buffer.wr_buf_out_data_reg[117]\(49) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(20),
      \write_buffer.wr_buf_out_data_reg[117]\(48) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(4),
      \write_buffer.wr_buf_out_data_reg[117]\(47) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(113),
      \write_buffer.wr_buf_out_data_reg[117]\(46) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(97),
      \write_buffer.wr_buf_out_data_reg[117]\(45) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(81),
      \write_buffer.wr_buf_out_data_reg[117]\(44) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(65),
      \write_buffer.wr_buf_out_data_reg[117]\(43) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(49),
      \write_buffer.wr_buf_out_data_reg[117]\(42) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(33),
      \write_buffer.wr_buf_out_data_reg[117]\(41) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(17),
      \write_buffer.wr_buf_out_data_reg[117]\(40) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(1),
      \write_buffer.wr_buf_out_data_reg[117]\(39) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(115),
      \write_buffer.wr_buf_out_data_reg[117]\(38) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(99),
      \write_buffer.wr_buf_out_data_reg[117]\(37) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(83),
      \write_buffer.wr_buf_out_data_reg[117]\(36) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(67),
      \write_buffer.wr_buf_out_data_reg[117]\(35) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(51),
      \write_buffer.wr_buf_out_data_reg[117]\(34) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(35),
      \write_buffer.wr_buf_out_data_reg[117]\(33) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(19),
      \write_buffer.wr_buf_out_data_reg[117]\(32) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(3),
      \write_buffer.wr_buf_out_data_reg[117]\(31) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(118),
      \write_buffer.wr_buf_out_data_reg[117]\(30) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(102),
      \write_buffer.wr_buf_out_data_reg[117]\(29) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(86),
      \write_buffer.wr_buf_out_data_reg[117]\(28) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(70),
      \write_buffer.wr_buf_out_data_reg[117]\(27) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(54),
      \write_buffer.wr_buf_out_data_reg[117]\(26) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(38),
      \write_buffer.wr_buf_out_data_reg[117]\(25) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(22),
      \write_buffer.wr_buf_out_data_reg[117]\(24) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(6),
      \write_buffer.wr_buf_out_data_reg[117]\(23) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(112),
      \write_buffer.wr_buf_out_data_reg[117]\(22) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(96),
      \write_buffer.wr_buf_out_data_reg[117]\(21) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(80),
      \write_buffer.wr_buf_out_data_reg[117]\(20) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(64),
      \write_buffer.wr_buf_out_data_reg[117]\(19) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(48),
      \write_buffer.wr_buf_out_data_reg[117]\(18) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(32),
      \write_buffer.wr_buf_out_data_reg[117]\(17) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(16),
      \write_buffer.wr_buf_out_data_reg[117]\(16) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(0),
      \write_buffer.wr_buf_out_data_reg[117]\(15) => u_mig_7series_0_mig_n_152,
      \write_buffer.wr_buf_out_data_reg[117]\(14) => u_mig_7series_0_mig_n_153,
      \write_buffer.wr_buf_out_data_reg[117]\(13) => u_mig_7series_0_mig_n_154,
      \write_buffer.wr_buf_out_data_reg[117]\(12) => u_mig_7series_0_mig_n_155,
      \write_buffer.wr_buf_out_data_reg[117]\(11) => u_mig_7series_0_mig_n_156,
      \write_buffer.wr_buf_out_data_reg[117]\(10) => u_mig_7series_0_mig_n_157,
      \write_buffer.wr_buf_out_data_reg[117]\(9) => u_mig_7series_0_mig_n_158,
      \write_buffer.wr_buf_out_data_reg[117]\(8) => u_mig_7series_0_mig_n_159,
      \write_buffer.wr_buf_out_data_reg[117]\(7) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(114),
      \write_buffer.wr_buf_out_data_reg[117]\(6) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(98),
      \write_buffer.wr_buf_out_data_reg[117]\(5) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(82),
      \write_buffer.wr_buf_out_data_reg[117]\(4) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(66),
      \write_buffer.wr_buf_out_data_reg[117]\(3) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(50),
      \write_buffer.wr_buf_out_data_reg[117]\(2) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(34),
      \write_buffer.wr_buf_out_data_reg[117]\(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(18),
      \write_buffer.wr_buf_out_data_reg[117]\(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(2)
    );
end STRUCTURE;
