`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Engineer: GPH // // Description: Display temperature from ADT7420. // Output is 13 bits in twos complement. // Each bit is 0.0625 deg C. Actual temperature = bits * 0.0625 // For the user, the left four digits is the 13 bit value in hex. // The right 4 digits is the temmperature in degrees Fahrenheiht. // // ////////////////////////////////////////////////////////////////////////////////// module labkit( input clk_100mhz, input[15:0] sw, input btnc, btnu, btnl, btnr, btnd, input [7:0] jb, // output logic[3:0] vga_r, // output logic[3:0] vga_b, // output logic[3:0] vga_g, // output logic vga_hs, // output logic vga_vs, output logic led16_b, led16_g, led16_r, output logic led17_b, led17_g, led17_r, output logic [15:0] led, output logic ca, cb, cc, cd, ce, cf, cg, dp, // segments a-g, dp output logic[7:0] an, // Display location 0-7 inout tmp_scl, inout tmp_sda ); // ------------------------------------------------------------------------------------- // // This section read in the temperature from the Analog Device ADT7420 temperature sensor. // wire [12:0] temp_o; reg [12:0] temp_valid; always @(posedge clk_100mhz) temp_valid <= rdy_o ? temp_o : temp_valid; // each bit is 0.0625 deg centigrade TempSensorCtl temp_sense( .TMP_SCL (tmp_scl), .TMP_SDA (tmp_sda), .TEMP_O (temp_o), // 13bit msb = sign .RDY_O (rdy_o), // data valid .ERR_O (err_o), .CLK_I (clk_100mhz), .SRST_I (1'b0) ); // tmp_scl tmp_sda tmp_int tmp_ct // TMP_SCL : inout STD_LOGIC; // TMP_SDA : inout STD_LOGIC; //-- TMP_INT : in STD_LOGIC; -- Interrupt line from the ADT7420, not used in this project //-- TMP_CT : in STD_LOGIC; -- Critical Temperature interrupt line from ADT7420, not used in this project // TEMP_O : out STD_LOGIC_VECTOR(12 downto 0); --12-bit two's complement temperature with sign bit // RDY_O : out STD_LOGIC; --'1' when there is a valid temperature reading on TEMP_O // ERR_O : out STD_LOGIC; --'1' if communication error // CLK_I : in STD_LOGIC; // SRST_I : in STD_LOGIC // //---------------------------------------------------------------------------------------------------------------------- logic [31:0] data; // instantiate 7-segment display; display (8) 4-bit hex logic [6:0] segments; logic dp; assign {cg, cf, ce, cd, cc, cb, ca} = segments[6:0]; display_8hex_temp display(.clk_in(clk_100mhz),.data_in(data), .seg_out(segments), .strobe_out(an), .dp(dp)); //assign seg[6:0] = segments; // assign dp = 1'b1; // turn off the period assign led = sw; // turn leds on //assign data = {28'h0123456, sw[3:0]}; // display 0123456 + sw[3:0] //------------------------------------------------------------------- // // bcd to decimal trick: high lentency - not recommended but ok for displaying // logic [12:0] temp_real = ((temp_valid*18)/16) + 320; assign data[3:0] = temp_real % 10; assign data[7:4] = (temp_real/10) % 10; assign data[11:8] = (temp_real/100) % 10; assign data[15:12] = temp_real/1000 ; assign data[31:16] = {3'b0,temp_valid}; // //--------------------------------------------------------------------- assign led16_r = btnl; // left button -> red led assign led16_g = btnc; // center button -> green led assign led16_b = btnr; // right button -> blue led assign led17_r = btnl; assign led17_g = btnc; assign led17_b = btnr; // btnc button is user reset logic reset; debounce db1(.reset_in(reset),.clock_in(clk_100mhz),.noisy_in(btnc),.clean_out(reset)); // UP and DOWN buttons for pong paddle logic up,down; debounce db2(.reset_in(reset),.clock_in(clk_100mhz),.noisy_in(btnu),.clean_out(up)); debounce db3(.reset_in(reset),.clock_in(clk_100mhz),.noisy_in(btnd),.clean_out(down)); endmodule module synchronize #(parameter NSYNC = 3) // number of sync flops. must be >= 2 (input clk,in, output logic out); logic [NSYNC-2:0] sync; always_ff @ (posedge clk) begin {out,sync} <= {sync[NSYNC-2:0],in}; end endmodule /////////////////////////////////////////////////////////////////////////////// // // Pushbutton Debounce Module (video version - 24 bits) // /////////////////////////////////////////////////////////////////////////////// module debounce (input reset_in, clock_in, noisy_in, output logic clean_out); logic [19:0] count; logic new_input; always_ff @(posedge clock_in) if (reset_in) begin new_input <= noisy_in; clean_out <= noisy_in; count <= 0; end else if (noisy_in != new_input) begin new_input<=noisy_in; count <= 0; end else if (count == 1000000) clean_out <= new_input; else count <= count+1; endmodule ////////////////////////////////////////////////////////////////////////////////// // Engineer: g.p.hom // // Create Date: 18:18:59 04/21/2013 // Module Name: display_8hex // Description: Display 8 hex numbers on 7 segment display // ////////////////////////////////////////////////////////////////////////////////// module display_8hex_temp( input clk_in, // system clock input [31:0] data_in, // 8 hex numbers, msb first output logic [6:0] seg_out, // seven segment display output output logic [7:0] strobe_out, // digit strobe output logic dp ); localparam bits = 13; logic [bits:0] counter = 0; // clear on power up logic [6:0] segments[15:0]; // 16 7 bit memorys assign segments[0] = 7'b100_0000; // inverted logic assign segments[1] = 7'b111_1001; // gfedcba assign segments[2] = 7'b010_0100; assign segments[3] = 7'b011_0000; assign segments[4] = 7'b001_1001; assign segments[5] = 7'b001_0010; assign segments[6] = 7'b000_0010; assign segments[7] = 7'b111_1000; assign segments[8] = 7'b000_0000; assign segments[9] = 7'b001_1000; assign segments[10] = 7'b000_1000; assign segments[11] = 7'b000_0011; assign segments[12] = 7'b010_0111; assign segments[13] = 7'b010_0001; assign segments[14] = 7'b000_0110; assign segments[15] = 7'b000_1110; always_ff @(posedge clk_in) begin // Here I am using a counter and select 3 bits which provides // a reasonable refresh rate starting the left most digit // and moving left. counter <= counter + 1; dp <= !(counter[bits:bits-2]==6); // turn on dp on the second digit case (counter[bits:bits-2]) 3'b000: begin // use the MSB 4 bits seg_out <= segments[data_in[31:28]]; strobe_out <= 8'b0111_1111 ; end 3'b001: begin seg_out <= segments[data_in[27:24]]; strobe_out <= 8'b1011_1111 ; end 3'b010: begin seg_out <= segments[data_in[23:20]]; strobe_out <= 8'b1101_1111 ; end 3'b011: begin seg_out <= segments[data_in[19:16]]; strobe_out <= 8'b1110_1111; end 3'b100: begin seg_out <= (data_in[15:12] == 0) ? 7'b111_1111 : segments[data_in[15:12]]; strobe_out <= 8'b1111_0111; end 3'b101: begin seg_out <= segments[data_in[11:8]]; strobe_out <= 8'b1111_1011; end 3'b110: begin seg_out <= segments[data_in[7:4]]; strobe_out <= 8'b1111_1101; end 3'b111: begin seg_out <= segments[data_in[3:0]]; strobe_out <= 8'b1111_1110; end endcase end endmodule