# 
# Synthesis run script generated by Vivado
# 

set TIME_start [clock seconds] 
proc create_report { reportName command } {
  set status "."
  append status $reportName ".fail"
  if { [file exists $status] } {
    eval file delete [glob $status]
  }
  send_msg_id runtcl-4 info "Executing : $command"
  set retval [eval catch { $command } msg]
  if { $retval != 0 } {
    set fp [open $status w]
    close $fp
    send_msg_id runtcl-5 warning "$msg"
  }
}
set_param chipscope.maxJobs 1
create_project -in_memory -part xc7a100tcsg324-3

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir D:/a-junk_d/imu/lab5_font/lab5_font.cache/wt [current_project]
set_property parent.project_path D:/a-junk_d/imu/lab5_font/lab5_font.xpr [current_project]
set_property XPM_LIBRARIES XPM_MEMORY [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_cache_permissions disable [current_project]
add_files d:/f2020_6111/font_rom.coe
read_verilog -library xil_defaultlib {
  D:/a-junk_d/imu/lab5_font/lab5_font.srcs/sources_1/imports/f2018/ball.v
  D:/a-junk_d/imu/lab5_font/lab5_font.srcs/sources_1/imports/f2018/clk_wiz_0_clk_wiz.v
  D:/a-junk_d/imu/lab5_font/lab5_font.srcs/sources_1/imports/f2018/clock16x.v
  D:/a-junk_d/imu/lab5_font/lab5_font.srcs/sources_1/imports/fonts/cstringdisp.v
  D:/a-junk_d/imu/lab5_font/lab5_font.srcs/sources_1/imports/f2018/display_8hex.v
  D:/a-junk_d/imu/lab5_font/lab5_font.srcs/sources_1/imports/f2018/serialin.v
  D:/a-junk_d/imu/lab5_font/lab5_font.srcs/sources_1/imports/f2018/xvga.v
  D:/a-junk_d/imu/lab5_font/lab5_font.srcs/sources_1/imports/f2018/labkit_lab5c.v
}
read_ip -quiet D:/a-junk_d/imu/lab5_font/lab5_font.srcs/sources_1/ip/font_rom/font_rom.xci
set_property used_in_implementation false [get_files -all d:/a-junk_d/imu/lab5_font/lab5_font.srcs/sources_1/ip/font_rom/font_rom_ooc.xdc]

# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  set_property used_in_implementation false $dcp
}
read_xdc D:/a-junk_d/imu/lab5_font/lab5_font.srcs/constrs_1/imports/f2018/Nexys4DDR_Master_lab5c.xdc
set_property used_in_implementation false [get_files D:/a-junk_d/imu/lab5_font/lab5_font.srcs/constrs_1/imports/f2018/Nexys4DDR_Master_lab5c.xdc]

set_param ips.enableIPCacheLiteLoad 1
close [open __synthesis_is_running__ w]

synth_design -top labkit -part xc7a100tcsg324-3


# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef labkit.dcp
create_report "synth_1_synth_report_utilization_0" "report_utilization -file labkit_utilization_synth.rpt -pb labkit_utilization_synth.pb"
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]
