
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 08/09/2018 03:17:03 PM
// Design Name: 
// Module Name: clock16x
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module clock16x(
    input clk,
    output enable
    );
    
    reg [8:0] counter;
    
    always @(posedge clk)
        counter <= (counter == 422) ? 0 : counter +1;
        
    assign enable = counter==0;
           
    
endmodule
