### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 2708876
date_generated | Mon Oct 5 16:09:17 2020 | os_platform | WIN64
product_version | Vivado v2019.2 (64-bit) | project_id | 613a8cf9e9704bb8a708bc53d3db915b
project_iteration | 27 | random_id | 42b91d4f280e5a11bba65fe876ca0105
registration_id | 42b91d4f280e5a11bba65fe876ca0105 | route_design | TRUE
target_device | xc7a100t | target_family | artix7
target_package | csg324 | target_speed | -3
tool_flow | Vivado

user_environment
cpu_name | Intel(R) Core(TM) i5-2320 CPU @ 3.00GHz | cpu_speed | 2993 MHz
os_name | Windows Server 2016 or Windows 10 | os_release | major release (build 9200)
system_ram | 17.000 GB | total_processors | 1

vivado_usage

gui_handlers
basedialog_cancel=1 | basedialog_ok=15 | basedialog_yes=1 | cmdmsgdialog_ok=2
customizeerrordialog_ok=1 | filesetpanel_file_set_panel_tree=43 | flownavigatortreepanel_flow_navigator_tree=5 | gettingstartedview_open_project=1
hacgccoefilewidget_browse=1 | hpopuptitle_close=1 | ipstatussectionpanel_upgrade_selected=1 | ipstatustablepanel_ip_status_table=1
ipstatustablepanel_more_info=3 | pacommandnames_run_bitgen=1 | rdicommands_delete=1 | reportipstatusinfodialog_report_ip_status=1
simpleoutputproductdialog_generate_output_products_immediately=2 | upgradeip_convert_ip_to_core_container_and_set=1

java_command_handlers
addsources=2 | autoconnecttarget=4 | coreview=6 | customizecore=4
editdelete=2 | exportbitfile=2 | fileexit=1 | launchprogramfpga=24
newproject=2 | openfile=2 | openhardwaremanager=30 | openproject=4
openrecenttarget=7 | programdevice=27 | projectsettingscmdhandler=6 | recustomizecore=5
reportipstatus=1 | runbitgen=30 | runimplementation=3 | runsynthesis=1
showview=2 | upgradeip=1 | viewtaskimplementation=1 | viewtaskprojectmanager=20

other_data
guimode=7

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=3 | export_simulation_ies=3
export_simulation_modelsim=3 | export_simulation_questa=3 | export_simulation_riviera=3 | export_simulation_vcs=3
export_simulation_xsim=3 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=0 | simulator_language=Mixed | srcsetcount=9 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=2 | totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
bufg=2 | carry4=110 | dsp48e1=5 | fdre=306
fdse=8 | gnd=17 | ibuf=13 | lut1=66
lut2=163 | lut3=185 | lut4=84 | lut5=88
lut6=156 | mmcme2_adv=1 | muxf7=2 | obuf=52
ramb18e1=1 | srl16e=3 | vcc=14
pre_unisim_transformation
bufg=2 | carry4=110 | dsp48e1=5 | fdre=306
fdse=8 | gnd=17 | ibuf=13 | lut1=66
lut2=163 | lut3=185 | lut4=84 | lut5=88
lut6=156 | mmcme2_adv=1 | muxf7=2 | obuf=52
ramb18e1=1 | srl16e=3 | vcc=14

power_opt_design
command_line_options_spo
-cell_types=default::all | -clocks=default::[not_specified] | -exclude_cells=default::[not_specified] | -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 | bram_ports_newly_gated=0 | bram_ports_total=2 | flow_state=default
slice_registers_augmented=0 | slice_registers_newly_gated=0 | slice_registers_total=328 | srls_augmented=0
srls_newly_gated=0 | srls_total=3

ip_statistics
blk_mem_gen_v8_4_4/1
c_addra_width=11 | c_addrb_width=11 | c_algorithm=1 | c_axi_id_width=4
c_axi_slave_type=0 | c_axi_type=1 | c_byte_size=9 | c_common_clk=0
c_count_18k_bram=1 | c_count_36k_bram=0 | c_ctrl_ecc_algo=NONE | c_default_data=0
c_disable_warn_bhv_coll=0 | c_disable_warn_bhv_range=0 | c_elaboration_dir=./ | c_en_deepsleep_pin=0
c_en_ecc_pipe=0 | c_en_rdaddra_chg=0 | c_en_rdaddrb_chg=0 | c_en_safety_ckt=0
c_en_shutdown_pin=0 | c_en_sleep_pin=0 | c_enable_32bit_address=0 | c_est_power_summary=Estimated Power for IP _ 1.2196 mW
c_family=artix7 | c_has_axi_id=0 | c_has_ena=1 | c_has_enb=0
c_has_injecterr=0 | c_has_mem_output_regs_a=1 | c_has_mem_output_regs_b=0 | c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 | c_has_regcea=0 | c_has_regceb=0 | c_has_rsta=0
c_has_rstb=0 | c_has_softecc_input_regs_a=0 | c_has_softecc_output_regs_b=0 | c_init_file=font_rom.mem
c_init_file_name=[user-defined] | c_inita_val=0 | c_initb_val=0 | c_interface_type=0
c_load_init_file=1 | c_mem_type=3 | c_mux_pipeline_stages=0 | c_prim_type=1
c_read_depth_a=1536 | c_read_depth_b=1536 | c_read_latency_a=1 | c_read_latency_b=1
c_read_width_a=8 | c_read_width_b=8 | c_rst_priority_a=CE | c_rst_priority_b=CE
c_rstram_a=0 | c_rstram_b=0 | c_sim_collision_check=ALL | c_use_bram_block=0
c_use_byte_wea=0 | c_use_byte_web=0 | c_use_default_data=0 | c_use_ecc=0
c_use_softecc=0 | c_use_uram=0 | c_wea_width=1 | c_web_width=1
c_write_depth_a=1536 | c_write_depth_b=1536 | c_write_mode_a=WRITE_FIRST | c_write_mode_b=WRITE_FIRST
c_write_width_a=8 | c_write_width_b=8 | c_xdevicefamily=artix7 | core_container=false
iptotal=1 | x_ipcorerevision=4 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=blk_mem_gen | x_ipproduct=Vivado 2019.2 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=8.4

report_drc
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -internal=default::[not_specified] | -internal_only=default::[not_specified] | -messages=default::[not_specified]
-name=default::[not_specified] | -no_waivers=default::[not_specified] | -return_string=default::[not_specified] | -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] | -waived=default::[not_specified]
results
cfgbvs-1=1 | dpip-1=8 | dpop-1=2 | dpop-2=1

report_utilization
clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=2 | bufgctrl_util_percentage=6.25
bufhce_available=96 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=24 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=12 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=24 | bufr_fixed=0 | bufr_used=0 | bufr_util_percentage=0.00
mmcme2_adv_available=6 | mmcme2_adv_fixed=0 | mmcme2_adv_used=1 | mmcme2_adv_util_percentage=16.67
plle2_adv_available=6 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00
dsp
dsp48e1_only_used=5 | dsps_available=240 | dsps_fixed=0 | dsps_used=5
dsps_util_percentage=2.08
io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_ii=0
diff_hstl_ii_18=0 | diff_hsul_12=0 | diff_mobile_ddr=0 | diff_sstl135=0
diff_sstl135_r=0 | diff_sstl15=0 | diff_sstl15_r=0 | diff_sstl18_i=0
diff_sstl18_ii=0 | hstl_i=0 | hstl_i_18=0 | hstl_ii=0
hstl_ii_18=0 | hsul_12=0 | lvcmos12=0 | lvcmos15=0
lvcmos18=1 | lvcmos25=0 | lvcmos33=1 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl135=0 | sstl135_r=0
sstl15=0 | sstl15_r=0 | sstl18_i=0 | sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=135 | block_ram_tile_fixed=0 | block_ram_tile_used=0.5 | block_ram_tile_util_percentage=0.37
ramb18_available=270 | ramb18_fixed=0 | ramb18_used=1 | ramb18_util_percentage=0.37
ramb18e1_only_used=1 | ramb36_fifo_available=135 | ramb36_fifo_fixed=0 | ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock | bufg_used=2 | carry4_functional_category=CarryLogic | carry4_used=110
dsp48e1_functional_category=Block Arithmetic | dsp48e1_used=5 | fdre_functional_category=Flop & Latch | fdre_used=320
fdse_functional_category=Flop & Latch | fdse_used=8 | ibuf_functional_category=IO | ibuf_used=13
lut1_functional_category=LUT | lut1_used=66 | lut2_functional_category=LUT | lut2_used=163
lut3_functional_category=LUT | lut3_used=185 | lut4_functional_category=LUT | lut4_used=84
lut5_functional_category=LUT | lut5_used=88 | lut6_functional_category=LUT | lut6_used=156
mmcme2_adv_functional_category=Clock | mmcme2_adv_used=1 | muxf7_functional_category=MuxFx | muxf7_used=2
obuf_functional_category=IO | obuf_used=52 | ramb18e1_functional_category=Block Memory | ramb18e1_used=1
srl16e_functional_category=Distributed Memory | srl16e_used=3
slice_logic
f7_muxes_available=31700 | f7_muxes_fixed=0 | f7_muxes_used=2 | f7_muxes_util_percentage=<0.01
f8_muxes_available=15850 | f8_muxes_fixed=0 | f8_muxes_used=0 | f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=0 | lut_as_logic_available=63400 | lut_as_logic_fixed=0
lut_as_logic_used=569 | lut_as_logic_util_percentage=0.90 | lut_as_memory_available=19000 | lut_as_memory_fixed=0
lut_as_memory_used=3 | lut_as_memory_util_percentage=0.02 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=3
register_as_flip_flop_available=126800 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=328 | register_as_flip_flop_util_percentage=0.26
register_as_latch_available=126800 | register_as_latch_fixed=0 | register_as_latch_used=0 | register_as_latch_util_percentage=0.00
slice_luts_available=63400 | slice_luts_fixed=0 | slice_luts_used=572 | slice_luts_util_percentage=0.90
slice_registers_available=126800 | slice_registers_fixed=0 | slice_registers_used=328 | slice_registers_util_percentage=0.26
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=0 | lut_as_logic_available=63400 | lut_as_logic_fixed=0
lut_as_logic_used=569 | lut_as_logic_util_percentage=0.90 | lut_as_memory_available=19000 | lut_as_memory_fixed=0
lut_as_memory_used=3 | lut_as_memory_util_percentage=0.02 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=3
lut_in_front_of_the_register_is_unused_fixed=3 | lut_in_front_of_the_register_is_unused_used=126 | lut_in_front_of_the_register_is_used_fixed=126 | lut_in_front_of_the_register_is_used_used=68
register_driven_from_outside_the_slice_fixed=68 | register_driven_from_outside_the_slice_used=194 | register_driven_from_within_the_slice_fixed=194 | register_driven_from_within_the_slice_used=134
slice_available=15850 | slice_fixed=0 | slice_registers_available=126800 | slice_registers_fixed=0
slice_registers_used=328 | slice_registers_util_percentage=0.26 | slice_used=245 | slice_util_percentage=1.55
slicel_fixed=0 | slicel_used=151 | slicem_fixed=0 | slicem_used=94
unique_control_sets_available=15850 | unique_control_sets_fixed=15850 | unique_control_sets_used=18 | unique_control_sets_util_percentage=0.11
using_o5_and_o6_fixed=0.11 | using_o5_and_o6_used=0 | using_o5_output_only_fixed=0 | using_o5_output_only_used=3
using_o6_output_only_fixed=3 | using_o6_output_only_used=0
specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=0 | bscane2_util_percentage=0.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=0 | dna_port_util_percentage=0.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
pcie_2_1_available=1 | pcie_2_1_fixed=0 | pcie_2_1_used=0 | pcie_2_1_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7a100tcsg324-3
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=labkit | -verilog_define=default::[not_specified]
usage
elapsed=00:01:03s | hls_ip=0 | memory_gain=796.969MB | memory_peak=1136.605MB