while (a != b) if (a > b) a = a - b; else b = b - a;The controller will be a state machine that takes 2 bits of input (Z and N) and produces control signals for the data paths (DRA, DRB, DRALU, LDA, LDB, FN). Draw a state diagram for the controller. Outputs from your FSM should depend only on the current state. Indicate which are the initial and final states of your FSM on the diagram.
Opcode | Phase | COND | = | ADR+ | ALU | CC | DRSEL | LDSEL | Comment |
******** | **** | * | = | 1 | 111111 | 11 | 001 | 000 | Opcode = uROM; ADR+ |
Opcode | Phase | COND | = | ADR+ | ALU | CC | DRSEL | LDSEL | Comment |
00001010 | 0000 | * | = | 1 | 111111 | 11 | 001 | 101 | MAR = uROM; ADR+ |
00001010 | 0001 | * | = | 0 | 111111 | 11 | 100 | 010 | A = SRAM |
00001010 | 0010 | * | = | 1 | 111111 | 11 | 001 | 101 | MAR = uROM; ADR+ |
00001010 | 0011 | * | = | 0 | 111111 | 11 | 100 | 011 | B = SRAM |
00001010 | 0100 | * | = | 1 | 111111 | 11 | 001 | 101 | MAR = uROM; ADR+ |
00001010 | 0101 | * | = | 0 | 100110 | 00 | 010 | 100 | SRAM = A + B; latch CCs |
00001010 | 0110 | * | = | 1 | 111111 | 11 | 001 | 000 | OP = uROM; ADR+ |
Opcode | Phase | COND | = | ADR+ | ALU | CC | DRSEL | LDSEL | Comment |
00001011 | 0000 | * | = | 1 | 111111 | 11 | 001 | 010 | A = uROM; ADR+ |
00001011 | 0001 | * | = | 1 | 111111 | 11 | 001 | 101 | MAR = uROM; ADR+ |
00001011 | 0010 | * | = | 0 | 111111 | 11 | 100 | 011 | B = SRAM |
00001011 | 0011 | * | = | 1 | 111111 | 11 | 001 | 101 | MAR = uROM; ADR+ |
00001011 | 0100 | * | = | 0 | 100110 | 00 | 010 | 100 | SRAM = A + B; latch CCs |
00001011 | 0101 | * | = | 1 | 111111 | 11 | 001 | 000 | OP = uROM; ADR+ |
Opcode | Phase | COND | = | ADR+ | ALU | CC | DRSEL | LDSEL | Comment |
00001100 | 0000 | * | = | 1 | 111111 | 11 | 001 | 010 | A = uROM; ADR+ |
00001100 | 0001 | * | = | 0 | 111111 | 11 | 001 | 001 | ADR = uROM |
00001100 | 0010 | * | = | 0 | 111111 | 11 | 010 | 001 | ADR = A |
00001100 | 0011 | * | = | 1 | 111111 | 11 | 001 | 000 | OP = uROM; ADR+ |
Opcode | Phase | COND | = | ADR+ | ALU | CC | DRSEL | LDSEL | Comment |
00010111 | 0000 | * | = | 1 | 111111 | 11 | 001 | 010 | A = uROM; ADR+ |
00010111 | 0001 | * | = | 0 | 111111 | 01 | 010 | 010 | Shift CC's |
00010111 | 0010 | 1 | = | 0 | 111111 | 11 | 001 | 001 | ADR = uROM |
00010111 | 0011 | 1 | = | 0 | 111111 | 11 | 010 | 001 | ADR = A |
00010111 | 0100 | 1 | = | 1 | 111111 | 11 | 001 | 000 | OP = uROM; ADR+ |
00010111 | 0010 | 0 | = | 1 | 111111 | 11 | 001 | 010 | A = uROM; ADR+ |
00010111 | 0011 | 0 | = | 1 | 111111 | 11 | 001 | 000 | OP = uROM; ADR+ |
Opcode | Phase | COND | = | ADR+ | ALU | CC | DRSEL | LDSEL | Comment |
00000011 | 0000 | * | = | 0 | 110011 | 11 | 010 | 101 | MAR = 11111111 |
00000011 | 0001 | * | = | 0 | 111111 | 11 | 100 | 010 | A = SRAM |
00000011 | 0010 | * | = | 0 | 111110 | 11 | 010 | 100 | SRAM = A - 1 |
00000011 | 0011 | * | = | 1 | 111111 | 11 | 001 | 101 | MAR = uROM; ADR+ |
00000011 | 0100 | * | = | 0 | 111111 | 11 | 100 | 011 | B = SRAM |
00000011 | 0101 | * | = | 0 | 111111 | 11 | 010 | 101 | MAR = A |
00000011 | 0110 | * | = | 0 | 101011 | 11 | 010 | 100 | SRAM = B |
00010111 | 0111 | * | = | 1 | 111111 | 11 | 001 | 000 | OP = uROM; ADR+ |