/////////////////////////////////////////////////////////////////////////////// // // 6.111 FPGA Labkit -- Audio/Video Test // // For Labkit Revision 004 // // // Created: November 3, 2004 // Author: Nathan Ickes // /////////////////////////////////////////////////////////////////////////////// `include "audio.v" `include "vga.v" `include "video.v" `include "display.v" module labkit (beep, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch, ac97_bit_clock, vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync, vga_out_vsync, tv_out_ycrcb, tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset, tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff, tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock, ram0_data, ram0_address, ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b, ram0_bwe_b, ram1_data, ram1_address, ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b, ram1_bwe_b, clock_feedback_out, clock_feedback_in, flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_sts, flash_byte_b, rs232_txd, rs232_rxd, rs232_rts, rs232_cts, mouse_clock, mouse_data, keyboard_clock, keyboard_data, clock_27mhz, clock1, clock2, disp_blank, disp_data_out, disp_clock, disp_rs, disp_ce_b, disp_reset_b, disp_data_in, button0, button1, button2, button3, button_enter, button_right, button_left, button_down, button_up, switch, led, user1, user2, user3, user4, daughtercard, systemace_data, systemace_address, systemace_ce_b, systemace_we_b, systemace_oe_b, systemace_irq, systemace_mpbrdy, analyzer1_data, analyzer1_clock, analyzer2_data, analyzer2_clock, analyzer3_data, analyzer3_clock, analyzer4_data, analyzer4_clock); output beep, audio_reset_b, ac97_synch, ac97_sdata_out; input ac97_bit_clock, ac97_sdata_in; output [7:0] vga_out_red, vga_out_green, vga_out_blue; output vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync, vga_out_vsync; output [9:0] tv_out_ycrcb; output tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset; input [19:0] tv_in_ycrcb; input tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff; output tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock; inout [35:0] ram0_data; output [20:0] ram0_address; output ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b; output [3:0] ram0_bwe_b; inout [35:0] ram1_data; output [20:0] ram1_address; output ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b; output [3:0] ram1_bwe_b; input clock_feedback_in; output clock_feedback_out; inout [15:0] flash_data; output [24:0] flash_address; output flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_byte_b; input flash_sts; output rs232_txd, rs232_rts; input rs232_rxd, rs232_cts; input mouse_clock, mouse_data, keyboard_clock, keyboard_data; input clock_27mhz, clock1, clock2; output disp_blank, disp_clock, disp_rs, disp_ce_b, disp_reset_b; output disp_data_out; input disp_data_in; input button0, button1, button2, button3, button_enter, button_right, button_left, button_down, button_up; input [7:0] switch; output [7:0] led; inout [31:0] user1, user2, user3, user4; inout [43:0] daughtercard; inout [15:0] systemace_data; output [6:0] systemace_address; output systemace_ce_b, systemace_we_b, systemace_oe_b; input systemace_irq, systemace_mpbrdy; output [15:0] analyzer1_data, analyzer2_data, analyzer3_data, analyzer4_data; output analyzer1_clock, analyzer2_clock, analyzer3_clock, analyzer4_clock; //////////////////////////////////////////////////////////////////////////// // // Reset Generation // // A shift register primitive is used to generate an active-high reset // signal that remains high for 16 clock cycles after configuration finishes // and the FPGA's internal clocks begin toggling. // //////////////////////////////////////////////////////////////////////////// wire reset; SRL16 reset_sr (.D(1'b0), .CLK(clock_27mhz), .Q(reset), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1)); defparam reset_sr.INIT = 16'hFFFF; //////////////////////////////////////////////////////////////////////////// // // Audio Input and Output // //////////////////////////////////////////////////////////////////////////// wire [3:0] vol; wire [39:0] vdisp; wire volume_up, volume_down; audio audio1 (reset, clock_27mhz, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch, ac97_bit_clock, switch[1:0], {vol, 1'b0}, switch[2]); beeper beep1 (reset, clock_27mhz, beep, ~button_enter); debounce vol_up (reset, clock_27mhz, button_up, volume_up); debounce vol_down (reset, clock_27mhz, button_down, volume_down); volume vol1 (reset, clock_27mhz, volume_up, volume_down, vol, vdisp); //////////////////////////////////////////////////////////////////////////// // // VGA Output // //////////////////////////////////////////////////////////////////////////// vga vga_test (reset, clock_27mhz, vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync, vga_out_vsync); //////////////////////////////////////////////////////////////////////////// // // Video I/O // //////////////////////////////////////////////////////////////////////////// wire [1:0] videomode; debounce vmode0 (reset, clock_27mhz, switch[3], videomode[0]); debounce vmode1 (reset, clock_27mhz, switch[4], videomode[1]); video video_test (reset, clock_27mhz, tv_out_ycrcb, tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset, tv_in_ycrcb[19:10], tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff, tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock, videomode); PULLUP pu_in (.O(tv_in_i2c_data)); PULLUP pu_out (.O(tv_out_i2c_data)); assign user1 = {6'b000000, tv_in_line_clock1, // 25 tv_in_i2c_clock, // 24 tv_in_i2c_data, // 23 tv_in_ycrcb[19:10], // 22-13 clock_27mhz, // 12 tv_out_i2c_clock, // 11 tv_out_i2c_data, // 10 tv_out_ycrcb}; // 9-0 assign analyzer1_clock = clock_27mhz; assign analyzer1_data = {tv_out_i2c_clock, tv_out_i2c_data, 4'h0, tv_out_ycrcb}; assign analyzer2_clock = tv_in_line_clock1; assign analyzer2_data = {tv_in_i2c_clock, tv_in_i2c_data, 4'h0, tv_in_ycrcb[19:10]}; //////////////////////////////////////////////////////////////////////////// // // Alphanumeric Displays // //////////////////////////////////////////////////////////////////////////// // // 7654321076543210 // V: 0 MIC CLRBARS // V:32 SIN COMPOSI // V: 0 SQR S-VIDEO // V: 0 SIL MITLOGO // V: 0 LIN reg [79:0] volume_dots; reg [119:0] audio_source_dots; reg [279:0] video_source_dots; always @(vol) case (vol) 5'd15: volume_dots <= {40'b00000000_01000010_01111111_01000000_00000000, //15 40'b00100111_01000101_01000101_01000101_00111001}; 5'd14: volume_dots <= {40'b00000000_01000010_01111111_01000000_00000000, //14 40'b00011000_00010100_00010010_01111111_00010000}; 5'd13: volume_dots <= {40'b00000000_01000010_01111111_01000000_00000000, //13 40'b00100010_01000001_01001001_01001001_00110110}; 5'd12: volume_dots <= {40'b00000000_01000010_01111111_01000000_00000000, //12 40'b01100010_01010001_01001001_01001001_01000110}; 5'd11: volume_dots <= {40'b00000000_01000010_01111111_01000000_00000000, //11 40'b00000000_01000010_01111111_01000000_00000000}; 5'd10: volume_dots <= {40'b00000000_01000010_01111111_01000000_00000000, //10 40'b00111110_01010001_01001001_01000101_00111110}; 5'd09: volume_dots <= {40'b00000000_00000000_00000000_00000000_00000000, //9 40'b00000110_01001001_01001001_00101001_00011110}; 5'd08: volume_dots <= {40'b00000000_00000000_00000000_00000000_00000000, //8 40'b00110110_01001001_01001001_01001001_00110110}; 5'd07: volume_dots <= {40'b00000000_00000000_00000000_00000000_00000000, //7 40'b00000001_01110001_00001001_00000101_00000011}; 5'd06: volume_dots <= {40'b00000000_00000000_00000000_00000000_00000000, //6 40'b00111100_01001010_01001001_01001001_00110000}; 5'd05: volume_dots <= {40'b00000000_00000000_00000000_00000000_00000000, //5 40'b00100111_01000101_01000101_01000101_00111001}; 5'd04: volume_dots <= {40'b00000000_00000000_00000000_00000000_00000000, //4 40'b00011000_00010100_00010010_01111111_00010000}; 5'd03: volume_dots <= {40'b00000000_00000000_00000000_00000000_00000000, //3 40'b00100010_01000001_01001001_01001001_00110110}; 5'd02: volume_dots <= {40'b00000000_00000000_00000000_00000000_00000000, //2 40'b01100010_01010001_01001001_01001001_01000110}; 5'd01: volume_dots <= {40'b00000000_00000000_00000000_00000000_00000000, //1 40'b00000000_01000010_01111111_01000000_00000000}; 5'd00: volume_dots <= {40'b00000000_00000000_00000000_00000000_00000000, //0 40'b00111110_01010001_01001001_01000101_00111110}; default: volume_dots <= {40'b00000000_00000000_00000000_00000000_00000000, //? 40'b00000010_00000001_01010001_00001001_00000110}; endcase always @(switch[2:0]) case (switch[1:0]) 2'b00: if (switch[2]) audio_source_dots <= {40'b01111111_00000010_00001100_00000010_01111111, 40'b00000000_01000001_01111111_01000001_00000000, 40'b00111110_01000001_01000001_01000001_00100010}; // MIC else audio_source_dots <= {40'b01111111_01000000_01000000_01000000_01000000, 40'b00000000_01000001_01111111_01000001_00000000, 40'b01111111_00000010_00000100_00001000_01111111}; // LIN 2'b01: audio_source_dots <= {40'b00100110_01001001_01001001_01001001_00110010, 40'b00000000_01000001_01111111_01000001_00000000, 40'b01111111_01000000_01000000_01000000_01000000}; // SIL 2'b10: audio_source_dots <= {40'b00100110_01001001_01001001_01001001_00110010, 40'b00000000_01000001_01111111_01000001_00000000, 40'b01111111_00000010_00000100_00001000_01111111}; // SIN 2'b11: audio_source_dots <= {40'b00100110_01001001_01001001_01001001_00110010, 40'b00111110_01000001_01010001_00100001_01011110, 40'b01111111_00001001_00011001_00101001_01000110}; // SQR endcase always @(videomode) case (videomode) 2'b00: video_source_dots <= {40'b00111110_01000001_01000001_01000001_00100010, // C 40'b01111111_01000000_01000000_01000000_01000000, // L 40'b01111111_00001001_00011001_00101001_01000110, // R 40'b01111111_01001001_01001001_01001001_00110110, // B 40'b01111110_00001001_00001001_00001001_01111110, // A 40'b01111111_00001001_00011001_00101001_01000110, // R 40'b00100110_01001001_01001001_01001001_00110010};// S 2'b01: video_source_dots <= {40'b01111111_00000010_00001100_00000010_01111111, // M 40'b00000000_01000001_01111111_01000001_00000000, // I 40'b00000001_00000001_01111111_00000001_00000001, // T 40'b01111111_01000000_01000000_01000000_01000000, // L 40'b00111110_01000001_01000001_01000001_00111110, // O 40'b00111110_01000001_01001001_01001001_00111010, // G 40'b00111110_01000001_01000001_01000001_00111110};// O 2'b10: video_source_dots <= {40'b00111110_01000001_01000001_01000001_00100010, // C 40'b00111110_01000001_01000001_01000001_00111110, // O 40'b01111111_00000010_00001100_00000010_01111111, // M 40'b01111111_00001001_00001001_00001001_00000110, // P 40'b00111110_01000001_01000001_01000001_00111110, // O 40'b00100110_01001001_01001001_01001001_00110010, // S 40'b00000000_01000001_01111111_01000001_00000000};// I 2'b11: video_source_dots <= {40'b00100110_01001001_01001001_01001001_00110010, // S 40'b00001000_00001000_00001000_00001000_00001000, // - 40'b00000111_00011000_01100000_00011000_00000111, // V 40'b00000000_01000001_01111111_01000001_00000000, // I 40'b01111111_01000001_01000001_01000001_00111110, // D 40'b01111111_01001001_01001001_01001001_01000001, // E 40'b00111110_01000001_01000001_01000001_00111110};// O endcase wire [639:0] dots; display disp (reset, clock_27mhz, disp_blank, disp_clock, disp_rs, disp_ce_b, disp_reset_b, disp_data_out, dots); assign dots = { 40'b00000111_00011000_01100000_00011000_00000111, // 'V' 40'b00000000_00110110_00110110_00000000_00000000, // ':' volume_dots, 40'b00000000_00000000_00000000_00000000_00000000, // ' ' audio_source_dots, 40'b00000000_00000000_00000000_00000000_00000000, // ' ' video_source_dots }; //////////////////////////////////////////////////////////////////////////// // // Default I/O Assignments // //////////////////////////////////////////////////////////////////////////// // SRAMs assign ram0_data = 36'hZ; assign ram0_address = 21'h0; assign ram0_adv_ld = 1'b0; assign ram0_clk = 1'b0; assign ram0_cen_b = 1'b1; assign ram0_ce_b = 1'b1; assign ram0_oe_b = 1'b1; assign ram0_we_b = 1'b1; assign ram0_bwe_b = 4'hF; assign ram1_data = 36'hZ; assign ram1_address = 21'h0; assign ram1_adv_ld = 1'b0; assign ram1_clk = 1'b0; assign ram1_cen_b = 1'b1; assign ram1_ce_b = 1'b1; assign ram1_oe_b = 1'b1; assign ram1_we_b = 1'b1; assign ram1_bwe_b = 4'hF; assign clock_feedback_out = 1'b0; // Flash ROM assign flash_data = 16'hZ; assign flash_address = 15'h0; assign flash_ce_b = 1'b1; assign flash_oe_b = 1'b1; assign flash_we_b = 1'b1; assign flash_reset_b = 1'b0; assign flash_byte_b = 1'b1; // RS-232 Interface assign rs232_txd = 1'b1; assign rs232_rts = 1'b1; // Buttons, Switches, and Individual LEDs assign led = 8'hFF; // User I/Os assign user2 = 32'hZ; assign user3 = 32'hZ; assign user4 = 32'hZ; // Daughtercard Connectors assign daughtercard = 44'hZ; // SystemACE Microprocessor Port assign systemace_data = 16'hZ; assign systemace_address = 7'h0; assign systemace_ce_b = 1'b1; assign systemace_we_b = 1'b1; assign systemace_oe_b = 1'b1; // Logic Analyzer assign analyzer3_data = 16'h0; assign analyzer3_clock = 1'b1; assign analyzer4_data = 16'h0; assign analyzer4_clock = 1'b1; endmodule /////////////////////////////////////////////////////////////////////////////// // // Switch Debounce Module // /////////////////////////////////////////////////////////////////////////////// module debounce (reset, clock, noisy, clean); input reset, clock, noisy; output clean; reg [18:0] count; reg new, clean; always @(posedge clock) if (reset) begin count <= 0; new <= noisy; clean <= noisy; end else if (noisy != new) begin new <= noisy; count <= 0; end else if (count == 270000) clean <= new; else count <= count+1; endmodule