module gpiolb (reset, clock, ain, aout, bin, bout, dir, pass, fail, index);

   parameter bank_width = 34;
   parameter index_width = 8;
   
   input reset, clock;
   input [bank_width-1:0] ain, bin;
   output [bank_width-1:0] aout, bout;
   output dir; // 0 = A drives B, 1 = B drives A
   output pass, fail;
   output [index_width-1:0] index;
   
   reg [1:0] state;
   reg [index_width-1:0] index;
   reg [bank_width-1:0] aout, bout;
   reg dir;
   reg pass, fail;

   parameter testab = 2'h0, testba = 2'h1, failed = 2'h2;
   
   always @(posedge clock)
     if (reset)
       begin
	  state <= testab;
	  index <= 0;
	  aout <= 1;
	  bout <= 'hX;
	  dir <= 0;
	  pass <= 0;
	  fail <= 0;
       end
     else
       case (state)
	 
	 testab: // Test bank A driving bank B
	   if (bin != aout)
	     state <= failed;
	   else if (aout[bank_width-1])
	     begin
		state <= testba;
		dir <= 1;
		aout <= 'hX;
		bout <= 1;
		index <= index+1;
	     end
	   else
	     begin
		aout <= aout<<1;
		bout <= 'hX;
		index <= index+1;
	     end
	 
	 testba: // Test bank B driving bank A
	   if (ain != bout)
	     state <= failed;
	   else if (bout[bank_width-1])
	     begin
		state <= testab;
		dir <= 0;
		aout <= 1;
		bout <= 'hX;
		index <= 0;
		pass <= 1;
	     end
	   else
	     begin
		aout <= 'hX;
		bout <= bout<<1;
		index <= index+1;
	     end

	 failed:
	   begin
	      pass <= 0;
	      fail <= 1;
	   end
       endcase

endmodule