Static Timing Analysis

Project : Example 1- I2C Simple Use
Build Time : 06/15/23 11:03:57
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyBUS_CLK(fixed-function) CyBUS_CLK(fixed-function) 24.000 MHz 24.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Clock To Output Section
+ CyBUS_CLK(fixed-function)
Source Destination Delay (ns)
\I2C_MASTER_1:I2C_FF\/scl_out SCL(0)_PAD:out 20.515
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_MASTER_1:I2C_FF\ \I2C_MASTER_1:I2C_FF\/clock \I2C_MASTER_1:I2C_FF\/scl_out 1.000
Route 1 \I2C_MASTER_1:Net_643_0\ \I2C_MASTER_1:I2C_FF\/scl_out SCL(0)/pin_input 2.900
iocell2 P12[4] 1 SCL(0) SCL(0)/pin_input SCL(0)/pad_out 16.615
Route 1 SCL(0)_PAD SCL(0)/pad_out SCL(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C_MASTER_1:I2C_FF\/sda_out SDA(0)_PAD:out 19.939
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_MASTER_1:I2C_FF\ \I2C_MASTER_1:I2C_FF\/clock \I2C_MASTER_1:I2C_FF\/sda_out 1.000
Route 1 \I2C_MASTER_1:sda_x_wire\ \I2C_MASTER_1:I2C_FF\/sda_out SDA(0)/pin_input 2.901
iocell1 P12[5] 1 SDA(0) SDA(0)/pin_input SDA(0)/pad_out 16.038
Route 1 SDA(0)_PAD SDA(0)/pad_out SDA(0)_PAD:out 0.000
Clock Clock path delay 0.000