Since IEEE-754 represents the mantissa with 52 bits, to exactly represent the three uniformly spaced intermediary values, , , and , would require two additional bits in the mantissa, as shown in Table 4.4. To represent the negative values and only the sign bit is changed from 0 to 1; the exponent and mantissa bit patterns remain the same. The rounding mode round to zero is not depicted in the table since it is not relevant to our application. Round to zero is equivalent to round to negative infinity for positive values, and to round to positive infinity for negative values.
| Actual | Round To Nearest | Round To | ||||
| Value | Mantissa | Rounded | Represented | Rounded | Represented | |
| 52 bits | +2 | Mantissa | Value | Mantissa | Value | |
| 00 | ||||||
| 01 | ||||||
| 10 | ||||||
| 11 | ||||||
| 00 | ||||||
| 00 | ||||||
| 01 | ||||||
| 10 | ||||||
| 11 | ||||||
| 00 | ||||||
| Actual | Round To | |||
| Value | Mantissa | Rounded | Represented | |
| 52 bits | +2 | Mantissa | Value | |
| 00 | ||||
| 01 | ||||
| 10 | ||||
| 11 | ||||
| 00 | ||||
| 00 | ||||
| 01 | ||||
| 10 | ||||
| 11 | ||||
| 00 | ||||
For a given unlimited precision floating- point value
, which
may not be exactly representable under IEEE-754 (i.e. it may require
more than 52 bits to represent the mantissa of
), we want to
construct the tightest possible interval
such that the
lower bound
is the largest possible representable number not
greater than
, and the upper bound
is the smallest possible
representable number not less than
: