" *********************************************************** " * * " * Copyright, (C) Honeywell Information Systems Inc., 1982 * " * * " * Copyright (c) 1972 by Massachusetts Institute of * " * Technology and Honeywell Information Systems, Inc. * " * * " *********************************************************** name mst_boot_label " " This program is copied by the tape_mult_ "boot_program" control order and written onto a " bootable MST when tape_mult_ is subsequently opened for writing. This program is put into " execution by a bootload sequence as follows: The system operator depresses initialize and " bootload (or equivalent) on the system console. Assuming an MST with this program written " on its label is mounted and ready on the selected tape drive, the IOM (or equivalant) " hardwired bootload program will read in the first record on the tape (the label record), " starting at location 30 (8) absolute. When the record has been completely read in, a " terminate interrupt is executed. The interrupt cell used for a terminate interrupt is a " function of the IOM number. For IOM #0, interrupt cell 12 is used, for IOM #1, 2, and 3, " interrupt cells 13, 14, and 15 respectively are used. The interrupt cell is used to form " the interrupt vector address. Since interrupt vectors a 2 locations long, the interrupt " cell is multiplied by 2. Therefore for IOM #0, the interrupt vector address would be 24 " (10) or 30 (8). IOM #s 1, 2, and 3 interrupt vector addresses would be 32, 34, and 36 (8) " respectively. When the processor senses the terminate interrupt (via an execute interrupt " present (xip) signal), a hardware XED instruction is forced to be executed to the " interrupt vector address formed in the SCU. Since this program is read in so that location " 0 is overlayed at location 30 (8) absolute, by the IOM bootload program, the XED is forced " to execute the transfer vector instructions (2) for the appropriate IOM # and control is " transferred to the label "begin" from the transfer vector. " " The function of this program is to read in the next 2 records on the tape and transfer " control to executable code located in the second record read in. An IO channel program is " set up using boot channel and mailbox information stored by the IOM bootload program (at " locations 0 - 4 absolute). The record following the tape label record is read in and the " status is ignored, since this will be an EOF mark. The second record is read in by first " building a DCW formed from the value located in the label "load_origin" (lower). It is " assumed that any tape that will be bootloaded was built by the generate_mst command. " Therefore 30 (8) is subtracted from the load_origin address. This address (in the upper " part of word) is concatinated to a word count of 4096 (LS 12 bits of word = to 0), to form " the DCW. The DCW is then stored in the appropriate DCW mailbox location. (The generate_mst " command will place a standard tape record header (8 words) and a segment header (16 " words), before any executable data is stored.) When the next record has been read in, and " the terminate interrupt has been received, the status is checked. If the status is " anything other than ready, the status will be displayed in the A register and this program " will die in an inhibited DIS instruction. If no status error is detected, control is " transferred to the "load_origin" address. The current value for "load_origin" is 10000 " (8). " " The fault vectors (locations 100 to 177 (8)) are overlayed by an SCU 200/DIS pair. " Therefore if this program dies in a DIS instruction, one can look at absolute location 200 " - 207 for the SCU data stored as the result of the fault. " " Written by J. A. Bush 12/80 " bool bootload_info,0 bool load_offset,30 offset of IOM load bool boot_pgm_offset,300 offset of boot prg in label record bool default_load,10000 bool flt_vector,100 bool scu_info,200 bool connect_channel,2 bool lockup,7 lockup fault # inhibit on <-><-><-><-><-><-><-><-><-><-><-><-> begin: eax1 7*64 set all controller masks fld 0,dl mask all interrupts sscr 2*8,1 .. eax1 -64,1 SSCR will do nothing for unassigned masks tpl -2,ic .. inhibit off <-><-><-><-><-><-><-><-><-><-><-><-> ldx5 bootload_info+2 Mailbox loc in X5 ldaq bootload_info Last PCW stq tape_pcw+1-*,ic Set up PCW for reading rest of program qrl 9-2 eax6 0,qu Tape channel number * 4 in X6. adlx6 bootload_info+2 Add in base of mailbox eaa tape_pcw-*,ic get address of tape PCW ora =o040000,dl insert no change bit sta connect_channel*4,5 and set connect channel LPW eaa tape_status-*,ic get address of status word sta 2,6 set SCW for tape channel ldaq ignore_pair-*,ic Ignore lockup faults. staq flt_vector+lockup*2 Ignore lockup faults. ldi =o4000,dl Mask overflow. lxl3 load_origin-*,ic get load address eaa 0,3 copy xfer address to A reg sbla =o30,du subtract record hdr and segment hdr sta data_dcw-*,ic and set up dcw tsx2 rd_tape-*,ic read eof record,and ignore status tsx2 rd_tape-*,ic read in first real record cana stat_mask-*,ic Examine error bits. tnz boot_die-*,ic display status in A reg and die on error tra 0,3 and enter the real program " " rd_tape - subroutine to issue connect to tape channel " and wait for status word to be stored rd_tape: eaa data_idcw-*,ic Absolute address of DCW list. sta 0,6 Set tape LPW. stz tape_status-*,ic Clear status word. cioc bootload_info+1 read next record cams 4 lda tape_status-*,ic tze -2,ic Wait for it to happen. tra 0,2 return to caller " even inhibit on <+><+><+><+><+><+><+><+><+><+><+><+> boot_die: dis *-begin stop the machine tra -1,ic I said stop! ignore_pair: scu scu_info rcu scu_info inhibit off <-><-><-><-><-><-><-><-><-><-><-><-> tape_pcw: vfd o6/40,6/0,6/0,3/7,3/2,6/2,6/1 Reset status. vfd o9/0 data_idcw:vfd o6/5,6/0,6/0,3/7,3/0,6/0,6/0 Read tape binary. data_dcw: vfd 18/0,18/0 IOTD load_origin-24,4096 even tape_status: bss ,2 load_origin: zero 0,default_load default load origin stat_mask: oct 370000770000 " " If this program is bootloaded from tape by the IOM bootload program, " the IOM mailbox will get overwritten with the contents of this " tape record. It is imperitive that the previous contents be restored. " It is the purpose of the following code to perform this restoration. bool imbx,1400 IOM mailbox base equ mbx_org,(imbx-128)-boot_pgm_offset-load_offset org mbx_org bss ,128 IMW area bss ,2 for status storage bss ,2 for system fault storage bss ,3 vfd 18/imbx+2,6/,12/2 system fault DCW vfd 18/0,o6/04,12/0 connect LPW bss ,3 bss ,20 dup 56 payload channel mailboxes vfd 18/3,o6/02,12/3 LPW bss ,1 LPWX vfd 18/imbx,6/,12/0 SCW bss ,1 DCW dupend end " " " ----------------------------------------------------------- " " " " Historical Background " " This edition of the Multics software materials and documentation is provided and donated " to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. " as a contribution to computer science knowledge. " This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, " Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull " and Bull HN Information Systems Inc. to the development of this operating system. " Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), " renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership " of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for " managing computer hardware properly and for executing programs. Many subsequent operating systems " incorporated Multics principles. " Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., " as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . " " ----------------------------------------------------------- " " Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without " fee is hereby granted,provided that the below copyright notice and historical background appear in all copies " and that both the copyright notice and historical background and this permission notice appear in supporting " documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining " to distribution of the programs without specific prior written permission. " Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. " Copyright 2006 by Bull HN Information Systems Inc. " Copyright 2006 by Bull SAS " All Rights Reserved " "