COIN Co-Processor Research
Introduction
In the past thirty years we have witnessed revolutionary advances in the performance, cost and size reduction of the traditional electronic microprocessor. However, it still remains a serial machine and there are several important signal-processing problems for which this machine architecture is not optimal. We are developing the Compact Opto-electronic Integrated Neural (COIN) as a complementary co-processor to assist with problems that are computationally cumbersome for traditional serial electronic processors. Examples are problems that require synthesis and processing of big, parallel data sets. The research goal is aimed the development and fabrication of a scalable optics-on-VLSI integrated-circuit version of the COIN coprocessor.
System Architecture
Architecturally, the COIN is a multi-layer sandwich with each layer consisting of 2-D arrays of photodetectors and thresholding circuits in silicon, in combination with arrays of light emitters and holographic optical interconnection elements sandwiched together into a brick. The optical elements, which transmit information from one layer of neurons to the next, are based on the Fresnel-Zone-plate technology, and are being fabricated in a standard lithographic process with minimal processing steps allowing large arrays of interconnect elements to be fabricated with a single exposure step. The COIN coprocessor is an implementation of a feed forward neural network which uses standard training algoritms in its operation.
Architecture of the COIN coprocessor
COIN optoelectronic bistable pixel architecture
Such a co-processor is expected to achieve the desired signal processing versatility by combining the parallel and longitudinal (inter-plane) free-space communication strengths of optics with the transverse (intra-plane) communication and computational strengths of digital electronics in an optimal manner. Regading additional features of the COIN architecture, it:
employs a modular and cascadable architecture
employs a bi-planar addressing system for cascadability
is a pre-aligned, compact, rugged and hermetically sealed structure
employs programmable and addressable optical interconnection elements
employs electronic weights stored in the microcontroller.
is electronically as well as optically programmable
implements supervised learning.
The electronic controller shown in the above Figure is used during training, depending on the device configuration and targeted application. When the processor is configured as a neural-type machine, the current program state (context) of each neuron is stored electronically in the weightswithin the microcontroller. The supervised training routine is performed once before deployment of the device and would only need to be repeated if the data set changes. Since the training is done off-line, the controller need not be exceedingly fast, but rather could be a simple microcontroller or FPGA with appropriate memory. Thus far, we have demonstrated that the COIN is capable of learning to perform real-world tasks. Simpkins (see doctoral theses under the Publications tab) has showed that the system could be trained to recognize different people even after facial changes and even after failure of some of the neurons in a 12x12x5 network.
Nearest neighbor Interconnection scheme
Fresnel zone based optical interconnection element
Training Algorithm
Applications
Applications of the COIN include:
Pattern recognition from noisy and fragmented input images
Image segmentation for medical applications
Fusion of multispectral-multipolarization images for contrast enhancement
Adaptive optical wavefront phase computation
Pattern recognition of human features from large quantities of parallel biometric data
Multisensor signal processing (e.g. for robotic guidance and control)
Simulation for DNA computation and modeling
Multimedia processing, symbolic processing, and encryption breaking
Probabilistic reasoning, estimation, extrapolation and interpolation.
COIN in the back-plane of a real-time imaging infrared sensor to identify image embedded in clutter
Discrete component version of the COIN
Undergraduates in the Group have been working on demonstations of discrete-component versions of the COIN. The goal of their work is to inform the design of the integrated version of the COIN, and therefore reduce the development risk of the integrated version. Here is a document that shows the circuit design work of recent of a recent Master's student.