Module std::simd [−] [src]

🔬 This is a nightly-only experimental API. (stdsimd)

Platform independent SIMD vector types and operations.

This is an unstable module for portable SIMD operations. This module has not yet gone through an RFC and is likely to change, but feedback is always welcome!

Structs

b8x2 [
Experimental
]

A 16-bit wide vector with 2 bool lanes.
b8x4 [
Experimental
]

A 32-bit wide vector with 4 bool lanes.
b8x8 [
Experimental
]

A 64-bit vector with 8 bool lanes.
b8x16 [
Experimental
]

A 128-bit vector with 16 bool lanes.
b8x32 [
Experimental
]

A 256-bit vector with 32 bool lanes.
b8x64 [
Experimental
]

A 512-bit vector with 64 bool lanes.
f32x2 [
Experimental
]

A 64-bit vector with 2 f32 lanes.
f32x4 [
Experimental
]

A 128-bit vector with 4 f32 lanes.
f32x8 [
Experimental
]

A 256-bit vector with 8 f32 lanes.
f32x16 [
Experimental
]

A 512-bit vector with 16 f32 lanes.
f64x2 [
Experimental
]

A 128-bit vector with 2 f64 lanes.
f64x4 [
Experimental
]

A 256-bit vector with 4 f64 lanes.
f64x8 [
Experimental
]

A 512-bit vector with 8 f64 lanes.
i16x2 [
Experimental
]

A 32-bit wide vector with 2 i16 lanes.
i16x4 [
Experimental
]

A 64-bit vector with 4 i16 lanes.
i16x8 [
Experimental
]

A 128-bit vector with 8 i16 lanes.
i16x16 [
Experimental
]

A 256-bit vector with 16 i16 lanes.
i16x32 [
Experimental
]

A 512-bit vector with 32 i16 lanes.
i32x2 [
Experimental
]

A 64-bit vector with 2 i32 lanes.
i32x4 [
Experimental
]

A 128-bit vector with 4 i32 lanes.
i32x8 [
Experimental
]

A 256-bit vector with 8 i32 lanes.
i32x16 [
Experimental
]

A 512-bit vector with 16 i32 lanes.
i64x2 [
Experimental
]

A 128-bit vector with 2 u64 lanes.
i64x4 [
Experimental
]

A 256-bit vector with 4 i64 lanes.
i64x8 [
Experimental
]

A 512-bit vector with 8 i64 lanes.
i8x2 [
Experimental
]

A 16-bit wide vector with 2 i8 lanes.
i8x4 [
Experimental
]

A 32-bit wide vector with 4 i8 lanes.
i8x8 [
Experimental
]

A 64-bit vector with 8 i8 lanes.
i8x16 [
Experimental
]

A 128-bit vector with 16 i8 lanes.
i8x32 [
Experimental
]

A 256-bit vector with 32 i8 lanes.
i8x64 [
Experimental
]

A 512-bit vector with 64 i8 lanes.
u16x2 [
Experimental
]

A 32-bit wide vector with 2 u16 lanes.
u16x4 [
Experimental
]

A 64-bit vector with 4 u16 lanes.
u16x8 [
Experimental
]

A 128-bit vector with 8 u16 lanes.
u16x16 [
Experimental
]

A 256-bit vector with 16 u16 lanes.
u16x32 [
Experimental
]

A 512-bit vector with 32 u16 lanes.
u32x2 [
Experimental
]

A 64-bit vector with 2 u32 lanes.
u32x4 [
Experimental
]

A 128-bit vector with 4 u32 lanes.
u32x8 [
Experimental
]

A 256-bit vector with 8 u32 lanes.
u32x16 [
Experimental
]

A 512-bit vector with 16 u32 lanes.
u64x2 [
Experimental
]

A 128-bit vector with 2 u64 lanes.
u64x4 [
Experimental
]

A 256-bit vector with 4 u64 lanes.
u64x8 [
Experimental
]

A 512-bit vector with 8 u64 lanes.
u8x2 [
Experimental
]

A 16-bit wide vector with 2 u8 lanes.
u8x4 [
Experimental
]

A 32-bit wide vector with 4 u8 lanes.
u8x8 [
Experimental
]

A 64-bit vector with 8 u8 lanes.
u8x16 [
Experimental
]

A 128-bit vector with 16 u8 lanes.
u8x32 [
Experimental
]

A 256-bit vector with 32 u8 lanes.
u8x64 [
Experimental
]

A 512-bit vector with 64 u8 lanes.

Traits

FromBits [
Experimental
]

Safe lossless bitwise conversion from T to Self.
IntoBits [
Experimental
]

Safe lossless bitwise conversion from Self to T.