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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file fir_filter.v when simulating
// the core, fir_filter. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps


module fir_filter(
	ND,
	RDY,
	CLK,
	RFD,
	LD_WE,
	COEF_LD,
	LD_DIN,
	DIN,
	DOUT);


input ND;
output RDY;
input CLK;
output RFD;
input LD_WE;
input COEF_LD;
input [7 : 0] LD_DIN;
input [19 : 0] DIN;
output [31 : 0] DOUT;

// synopsys translate_off

      C_DA_FIR_V9_0 #(
		1,	// c_baat
		1,	// c_channels
		0,	// c_coeff_type
		8,	// c_coeff_width
		0,	// c_data_type
		20,	// c_data_width
		0,	// c_enable_rlocs
		0,	// c_filter_type
		0,	// c_has_reset
		0,	// c_has_sel_i
		0,	// c_has_sel_o
		0,	// c_has_sin_f
		0,	// c_has_sin_r
		0,	// c_has_sout_f
		0,	// c_has_sout_r
		26,	// c_latency
		"fir_filter.mif",	// c_mem_init_file
		0,	// c_optimize
		1,	// c_polyphase_factor
		1,	// c_reg_output
		1,	// c_reload
		274,	// c_reload_delay
		1,	// c_reload_mem_type
		1,	// c_response
		32,	// c_result_width
		0,	// c_saturate
		0,	// c_shape
		15,	// c_taps
		0,	// c_use_model_func
		1)	// c_zpf
	inst (
		.ND(ND),
		.RDY(RDY),
		.CLK(CLK),
		.RFD(RFD),
		.LD_WE(LD_WE),
		.COEF_LD(COEF_LD),
		.LD_DIN(LD_DIN),
		.DIN(DIN),
		.DOUT(DOUT),
		.RST(),
		.DOUT_I(),
		.DOUT_Q(),
		.SEL_I(),
		.SEL_O());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of fir_filter is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of fir_filter is "black_box"

endmodule