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Hierarchy for filter_sample
filter_sample
BUFG
SRL16
audio
ac97
ac97commands
dds_20bit
BLKMEMDP_V6_0
C_ADDSUB_V7_0 x 7
C_COMPARE_V7_0 x 4
C_GATE_BIT_V7_0 x 3
C_REG_FD_V7_0 x 21
C_SHIFT_FD_V7_0 x 2
C_SHIFT_RAM_V7_0 x 9
C_TWOS_COMP_V7_0 x 2
FDE x 5
FDPE x 2
LUT4 x 16
MULT_GEN_V7_0 x 3
debounce
display_16hex
fir_filter
C_DA_FIR_V9_0
jtag2mem
BSCAN_VIRTEX2
user_updown3
debounce
x 2
Unconnected modules
tone750hz
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This page:
Created:
Sun Dec 11 13:11:05 2005
Verilog converted to html by
v2html 7.30
(written by
Costas Calamvokis
).
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